Solar cell and manufacturing method thereof

Abstract

SOLUTION: To provide a solar cell that includes a silicon substrate, a front electrode on a front surface of the silicon substrate, and a back electrode on a back surface of the silicon substrate, in which the back surface of the silicon substrate includes a gate line region and a non-gate line region, the back electrode is provided in the gate line region, the gate line region has a first passivation contact structure, and a tunnel layer, at least one first doped polysilicon layer, at least one partition layer, and a second doped polysilicon layer are sequentially stacked, and the film layers and their thicknesses in the gate line region and the non-gate line region are different.EFFECT: A gate line region has a large thickness and two doped polysilicon layers, which prevents gate line slurry from penetrating the doped polysilicon layer and destroying an underlying tunnel oxide layer during firing, ensuring a field passivation effect. The non-gate line region is significantly smaller in thickness than the gate line region, which reduces parasitic absorption of backside light and improves photoelectric efficiency.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] This application relates to the field of photovoltaics, and more particularly to solar cells and methods for their manufacture. [Background technology]

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells use a tunnel layer and a doped polysilicon layer on the backside to form a passivation contact structure, achieving a field passivation effect, reducing contact resistance, increasing the open circuit voltage and short circuit current of the cell, and improving the cell's conversion efficiency.

[0003] However, the thickness of the backside doped polysilicon layer is between 100 nm and 150 nm, which affects the absorption of backside light and further affects the cell efficiency.

[0004] In view of this, there is a definite need to provide an improved solar cell and a manufacturing method thereof so as to solve the above technical problems. Summary of the Invention [Problem to be solved by the invention]

[0005] The present application aims to provide a solar cell and a method for manufacturing the same that improve the passivation effect on the back surface of the cell, increase light utilization rate, and provide excellent cell efficiency, while being simple in process. [Means for solving the problem]

[0006] To achieve the above object, the present application provides a solar cell comprising: a silicon substrate having a front surface and a back surface; a passivation contact structure on the back surface of the silicon substrate; and a back electrode provided on the passivation contact structure. The passivation contact structure comprises a tunnel layer, a first doped polysilicon layer, a barrier layer, and a second doped polysilicon layer, which are sequentially provided on the back surface of the silicon substrate, wherein the barrier layer is discontinuous.

[0007] Optionally, the barrier layer is selected from one or more of a silicon oxide layer, a silicon oxynitride layer, or a silicon carbide layer.

[0008] Optionally, the tunnel layer has a thickness of 1 nm to 3 nm.

[0009] Optionally, the thickness of the barrier layer is between 0.5 nm and 3 nm.

[0010] Optionally, the thickness of the tunnel layer and the thickness of the barrier layer are each 1.5 nm to 2 nm.

[0011] Optionally, the thickness of the first doped polysilicon layer is less than or equal to the thickness of the second doped polysilicon layer.

[0012] Optionally, the doping type of the first doped polysilicon layer and the second doped polysilicon layer is similar to the doping type of the silicon substrate, and the doping concentration of the second doped polysilicon layer is greater than the doping concentration of the first doped polysilicon layer.

[0013] Optionally, the doping concentration of the first doped polysilicon layer is 1E+20 cm -3 ~9E+20cm -3 and the doping concentration of the second doped polysilicon layer is 2E+20 cm -3 ~3E+21cm -3 is.

[0014] Optionally, the solar cell further comprises a back surface passivation layer and a back surface anti-reflection layer sequentially provided on a back surface of the passivation contact structure away from the silicon substrate, and the back surface electrode passes through the back surface anti-reflection layer and the back surface passivation layer to contact the second doped polysilicon layer.

[0015] Optionally, the solar cell may further include a front diffusion layer, a front passivation layer, a front anti-reflection layer, and a front electrode, which are sequentially provided on the front surface of the silicon substrate, and the front electrode is in contact with the front diffusion layer through the front anti-reflection layer and the front passivation layer.

[0016] Another object of the present application is to provide a method for manufacturing a solar cell, the method comprising: Sequentially depositing a tunnel layer, a first doped amorphous silicon layer, a partition layer, and a second doped amorphous silicon layer on a rear surface of a silicon substrate; partially forming a mask on the second doped amorphous silicon layer; converting the first phosphorus-doped amorphous silicon layer into a first doped polysilicon layer and converting the second phosphorus-doped amorphous silicon layer into a second doped polysilicon layer; removing the second doped polysilicon layer in areas other than the mask; removing the mask and the partition layer to form a discontinuous partition layer. Optionally, the mask layer is formed by laser processing in an oxygen atmosphere.

[0017] A further object of the present application is to provide a method for manufacturing a solar cell, the method comprising: providing a silicon substrate having opposing first and second surfaces, the second surface including a first region and a second region; sequentially forming a tunnel layer, a first phosphorus-doped amorphous silicon layer, a barrier layer, and a second phosphorus-doped amorphous silicon layer on a second surface of the silicon substrate; converting the first phosphorus-doped amorphous silicon layer into a first doped polysilicon layer and converting the second phosphorus-doped amorphous silicon layer into a second doped polysilicon layer; forming a mask layer on a surface of the second doped polysilicon layer in the first region; removing the second doped polysilicon layer in at least a portion of the second region and the oxide layer in the first region, leaving the second doped polysilicon layer in the first region; and fabricating an electrode in the first region contacting the second doped polysilicon layer.

[0018] Optionally, the mask layer is an oxide layer. Optionally, the step of removing the second doped polysilicon layer in at least a portion of the second region and the mask layer in the first region and leaving the second doped polysilicon layer in the first region includes the step of removing all of the second doped polysilicon layer in the second region using an alkaline solution, and removing the outermost partition layer in the second region and the oxide layer in the first region using an acid solution.

[0019] Optionally, the step of removing the second doped polysilicon layer in at least a portion of the second region and the mask layer in the first region and leaving the second doped polysilicon layer in the first region includes the steps of removing the second doped polysilicon layer in a portion of the second region using an alkaline solution and removing the oxide layer in the first region using an acid solution.

[0020] Optionally, the tunnel layer is a silicon oxide layer, a silicon oxynitride layer, or a combination of two layers, and has a thickness of 1 nm to 3 nm.

[0021] Optionally, the barrier layer is one or a combination of a silicon oxide layer, a silicon oxynitride layer, and a silicon carbide layer, and has a thickness of 0.5 nm to 3 nm or 1.5 nm to 2 nm.

[0022] A further object of the present application is to provide a solar cell, the solar cell comprising a silicon substrate and an electrode. The silicon substrate has a first surface and a second surface provided opposite to each other, the second surface having a first region and a second region. The second surface has a tunnel layer, at least one first doped layer, at least one barrier layer, and a second doped layer sequentially provided in the first region, and the second surface has a tunnel layer and at least one first doped layer provided in the second region. The electrode is located in the first region and is in contact with the second doped layer.

[0023] Optionally, a tunnel layer, a first doped layer, a barrier layer, and a second doped layer are provided in the first region, and a tunnel layer and a first doped layer are provided in the second region. Optionally, a tunnel layer, one first doped layer, one partition layer, and a second doped layer are provided in the first region, and a tunnel layer, one first doped layer, one partition layer, and a second doped layer are provided in the second region, and the thickness of the second doped layer in the second region is smaller than the thickness of the second doped layer in the first region. Optionally, a tunnel layer, at least two first doped layers and at least two partition layers alternately stacked, and a second doped layer are provided in the first region, and a tunnel layer, at least two first doped layers and at least one partition layer alternately stacked in the second region. Optionally, a tunnel layer, at least two first doped layers and at least two partition layers alternately stacked, and a second doped layer are provided in the first region, and a tunnel layer, at least two first doped layers and at least two partition layers alternately stacked, and a second doped layer are provided in the second region, and the thickness of the second doped layer in the second region is smaller than the thickness of the second doped layer in the first region.

[0024] A further object of the present application is to provide a solar cell comprising: a silicon substrate having a first surface and a second surface including opposing metal and non-metal regions; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate and located on the metal regions, the metal regions having a first passivation contact structure, the first passivation contact structure including, sequentially on the second surface, a tunnel layer, at least one first doped polysilicon layer, at least one barrier layer, and a second doped polysilicon layer.

[0025] Optionally, a dimension of the orthogonal projection of the metal region on the silicon substrate along a plane direction of the silicon substrate is equal to or greater than a dimension of the orthogonal projection of the second electrode on the silicon substrate along a plane direction of the silicon substrate.

[0026] Optionally, the non-metal region comprises a second passivation contact structure. Optionally, the second passivation contact structure includes a tunnel layer and a first doped polysilicon layer sequentially disposed on the second surface. Optionally, the second passivation contact structure includes a tunnel layer, a first doped polysilicon layer, a barrier layer, and a second doped polysilicon layer sequentially disposed on the second surface. Optionally, the second passivation contact structure includes a tunnel layer and a second doped polysilicon layer sequentially disposed on the second surface. Optionally, the second passivation contact structure includes a tunnel layer, at least two first doped polysilicon layers, and at least one separator layer disposed sequentially on the second surface. Optionally, the second passivation contact structure includes a tunnel layer, at least two first doped polysilicon layers, at least two partition layers, and a second doped polysilicon layer, sequentially disposed on the second surface.

[0027] Optionally, the first passivation contact structure and the second passivation contact structure have a height difference relative to a back surface of the silicon substrate.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] The manufacturing process of the SE (Selective Emitter) structure on the back surface of the battery in the present invention is simple, and the oxidation of the first region (metal region) is completed by a laser process, which eliminates the mask manufacturing process in the polysilicon process and the front surface chain process before removing plating irregularities. In addition, the present invention completely or partially removes the second doped layer in the second region (non-metallic region) on the back surface of the battery, leaving the second doped layer in the first region (metallic region) unaffected. This allows for both passivation and reduction of parasitic absorption without changing the slurry, thereby improving the process window and significantly improving the cell efficiency and double-sidedness. By removing the barrier layer / barrier layer on the back side of the battery, it can effectively improve the doping concentration change of the doped layer during the laser process, avoid the destruction of the tunnel layer, and further improve the passivation effect. At the same time, the barrier layer / barrier layer has a certain barrier ability against the penetration of the back side slurry, which helps to reduce the total thickness of the back side doped layer and increase the open circuit voltage (Voc) of the battery. In other words, in the solar cell of the present invention, the passivation contact structure has different film layers and thicknesses in the gate line region and non-gate line region. The gate line region has a four-layer structure including a tunnel layer, a first doped polysilicon layer, a barrier layer and a second doped polysilicon layer, and is thicker and has two doped polysilicon layers, which prevents the doped polysilicon layer from penetrating and destroying the underlying tunnel oxide layer when the gate line slurry is fired, ensuring the field passivation effect. The non-gate line region only includes a tunnel layer and a first doped polysilicon layer, and is significantly thinner than the gate line region, reducing the parasitic absorption of backside light and improving photoelectric efficiency. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a schematic structural diagram of a solar cell of the present invention. [Figure 2] 1 is a flowchart of a method for manufacturing a passivation contact structure for a solar cell of the present invention. [Figure 3] 1 is a structural schematic diagram of a solar cell according to Example 1 of the present invention. [Figure 4] FIG. 4 is a partial structural schematic diagram of a portion A in FIG. 3. [Figure 5] 3 is a schematic plan view of a second surface of a silicon substrate in Example 1 of the present invention. FIG. [Figure 6] FIG. 3 is a plan view schematically illustrating a second surface and a second electrode according to the first embodiment of the present invention. [Figure 7a] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7b] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7c] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7d] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7e] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7f] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7g] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7h] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7i] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 7j] 1 is a schematic diagram showing a manufacturing process flow of a solar cell in Example 1 of the present invention. [Figure 8] FIG. 2 is a schematic diagram of a laser scanning pattern in a laser process in Example 1 of the present invention. [Figure 9] FIG. 4 is a structural schematic diagram of a solar cell in Example 2 of the present invention. [Figure 10] FIG. 10 is a partial structural schematic diagram of a portion B in FIG. 9. [Figure 11] FIG. 10 is a structural schematic diagram of a solar cell according to Example 3 of the present invention. [Figure 12] FIG. 12 is a partial structural schematic diagram of a portion C in FIG. [Figure 13] FIG. 10 is a structural schematic diagram of a solar cell according to Example 4 of the present invention. [Figure 14] FIG. 14 is a partial structural schematic diagram of a portion D in FIG. [Figure 15] 1 is a schematic diagram of a local structure of a solar cell of the present invention. [Figure 16] FIG. 2 is an SEM image of a pyramidal texture structure according to the present invention. [Figure 17] FIG. 2 is an SEM image of a first region on a backlight surface of a silicon substrate in the present invention. [Figure 18] FIG. 3 is an SEM image of a second region on the backlight surface of the silicon substrate in the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0031] In order to clarify the purpose, technical means and advantages of the present application, the present application will be described in detail below in combination with drawings and specific embodiments, but these embodiments do not limit the present invention, and any structural, method or functional transformations made by those skilled in the art based on these embodiments fall within the protection scope of the present invention.

[0032] Here, it is necessary to explain that, in order to avoid obscuring the present application with unnecessary details, the drawings only show structures and / or process steps closely related to the means of the present application, and omit other details that are not closely related to the present application. The dimensions of some structures or parts in the drawings are exaggerated compared to other structures, and are only used to show the basic structure of the subject matter of the present invention.

[0033] It should also be explained that the technical terms "comprises," "includes," or any other variant thereof, are meant to include a non-exclusive inclusion, such that a process, method, article, or device comprising a set of elements includes other elements not expressly listed, or includes elements inherent in such process, method, article, or device, other than those elements.

[0034] Furthermore, in the present invention, unless otherwise specified or limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in contact via an intermediate medium. Furthermore, a first feature being "above," "above," and "on the upper surface" of a second feature may mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the horizontal height of the first feature is higher than that of the second feature. A first feature being "below," "below," and "on the lower surface" of a second feature may mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the horizontal height of the first feature is lower than that of the second feature.

[0035] According to the inventor's research, the doped polysilicon layer on the backside of TOPCon solar cells cannot be further thinned due to the limited slurry firing window. A thick doped polysilicon layer results in high parasitic absorption of light, which impacts the backside light utilization rate and ultimately cell efficiency. Based on this, the present invention optimizes the passivation contact structure on the backside of TOPCon solar cells to ensure the required thickness in the gate line area and avoid the destruction of the bottom tunnel oxide layer by penetrating the doped polysilicon layer during gate line slurry firing. This ensures the field passivation effect, while also thinning the doped polysilicon layer in non-gate line areas and reducing the parasitic absorption of long-wavelength light on the backside.

[0036] 1 shows a schematic structure of a solar cell 100 of the present invention, which is a TOPCon cell and includes a silicon substrate 10, a passivation contact structure 20 / 30 provided on the back surface of the silicon substrate 10, and electrodes 41 / 42, passivation layers 51 / 52, and anti-reflection layers 61 / 62 provided on the front and back surfaces of the silicon substrate 10, respectively. The solar cell 100 of the present invention achieves field passivation on the back surface by the passivation contact structure 20 / 30, thereby improving the cell efficiency.

[0037] As can be understood, the front surface of the silicon substrate 10 is the light-receiving surface, and the back surface is the backlight surface. The back surface of the silicon substrate 10 includes a metal region and a non-metal region. The metal region may be a gate line region, and the non-metal region may be a non-gate line region. The electrodes include a front electrode 41 provided on the light-receiving surface of the silicon substrate 10 and a back electrode 42 provided in the back gate line region. The passivation layer and anti-reflection layer include a front passivation layer 51, a back passivation layer 52, a front anti-reflection layer 61, and a back anti-reflection layer 62, respectively. The front surface of the silicon substrate 10 may have a structure including a front diffusion layer, a front passivation layer 51, and a front anti-reflection layer 61, which are sequentially provided.

[0038] The present invention optimizes the film layer materials and thicknesses of the backside metal and non-metal areas of the silicon substrate 10, simultaneously improving the backside passivation effect and light utilization rate, by forming a first passivation contact structure 20 on the metal area and a second passivation contact structure 30 on the non-metal area.

[0039] FIG. 2 is a schematic process flow chart for fabricating the passivation contact structure 20 / 30 of the solar cell 100 of the present invention, which includes the steps of: S1: sequentially depositing a tunnel layer 12, a first phosphorus-doped amorphous silicon layer 13, a partition / barrier layer 14, and a second phosphorus-doped amorphous silicon layer 15 on the rear surface of a silicon substrate 10; S2: scanning the gate line region of the second phosphorus-doped amorphous silicon layer 15 and oxidizing it in the gate line region to form an oxide layer mask, preferably by laser processing in a high-oxygen atmosphere; annealing S3 to convert the first phosphorus-doped amorphous silicon layer 13 into a first doped polysilicon layer 131 and the second phosphorus-doped amorphous silicon layer 15 into a second doped polysilicon layer 132; S4 removing the second doped polysilicon layer 132 in the non-gate line areas; S5 removing the oxide layer mask and barrier layer 14 and forming first passivation contact structures 20 in the gate line regions and second passivation contact structures 30 in the non-gate line regions.

[0040] The solar cell and the method for manufacturing the same of the present invention will be described in more detail below in conjunction with specific examples.

[0041] Example 1

[0042] 3 to 8 show the solar cell of Example 1 and the manufacturing method thereof.

[0043] 3 is a structural schematic diagram of a solar cell 100 in Example 1. The solar cell is a TOPCon cell and includes a silicon substrate 10. As shown in FIG. 7a, the silicon substrate 10 includes a first surface S1 and a second surface S2 that are opposed to each other. The second surface S2 includes a first region S21 and a second region S22. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, the second surface S2 is the back surface (i.e., the backlight surface) of the silicon substrate 10, the first region S21 is a back surface metal region, and the second region S22 is a back surface non-metal region. The back surface metal region is a gate line region, and the back surface non-metal region is a non-gate line region.

[0044] The silicon substrate 10 in the first embodiment is an N-type silicon substrate, and has a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0045] Furthermore, a trap structure is formed on the first surface S1 of the silicon substrate 10, and a pyramidal texture structure 70 (shown in FIG. 1) can be formed on the first surface S1 of the silicon substrate 10 by alkali texturing, with the pyramid dimensions being 0.5 μm to 3 μm. The pyramidal texture structure 70 can reduce the front surface reflectance of the solar cell, and in other embodiments, the pyramidal texture structure 70 may adopt a non-pyramid structure.

[0046] In the first embodiment, a front doped layer 11 (i.e., emitter) is formed on the first surface S1 of the silicon substrate 10 by a diffusion process or a PECVD process. Illustratively, the front doped layer 11 is a P-type doped layer (i.e., P+ emitter) formed by a boron doping process, with a doping concentration of 3E+18 cm -3 ~3E+19cm -3 The square resistivity is 40Ω / sq to 300Ω / sq, preferably 150Ω / sq to 250Ω / sq.

[0047] Referring to Figure 3 and combining Figure 4, in Example 1, a first passivation contact structure 20 is formed in a first region S21 on the second surface S2 of a silicon substrate 10. The first passivation contact structure 20 is composed of a tunnel layer 12, a first doped layer 131, a barrier layer / barrier layer 14, and a second doped layer 132, which are sequentially stacked. The tunnel layer 12 is a silicon oxide layer, a silicon oxynitride layer, or a combination of two or more layers, preferably a silicon oxide layer, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2.5 nm. The barrier layer / barrier layer 14 is a silicon oxide layer, a silicon carbide layer, or a combination of two or more layers, with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 2 nm. The materials can be selected based on the needs of the actual application. For example, a silicon carbide layer can be used for the tunnel layer, and a silicon oxynitride layer can be used for the barrier layer / barrier layer, and this will not be described again here. For ease of understanding, the following examples will be described using the barrier layer 14.

[0048] In Example 1, a second passivation contact structure 30 is formed in a second region S22 on the second surface S2 of the silicon substrate 10, and the second passivation contact structure 30 is composed of a tunnel layer 12 and a first doped layer 131 that are sequentially stacked. It can be understood that the tunnel layer 12 and the first doped layer 131 on the second region S22 are completely the same as the tunnel layer 12 and the first doped layer 131 on the first region S21, and will not be described again here.

[0049] In the present invention, the doping type of the first doped layer 131 and the second doped layer 132 is the same as the doping type of the silicon substrate, and the surface doping concentration of the second doped layer 132 can be greater than the surface doping concentration of the first doped layer 131. At the same time, the thickness of the second doped layer 132 can be greater than the thickness of the first doped layer 131. The total thickness of the first doped layer 131 and the second doped layer 132 is 50 nm to 150 nm, preferably 60 nm to 100 nm.

[0050] Illustratively, the first doped layer 131 in Example 1 is a phosphorus-doped polysilicon layer, and the surface doping concentration is 1E+20 cm -3 ~9E+20cm -3 and preferably 3E+20cm -3 ~5E+20cm -3 and the thickness is 1 nm to 100 nm, preferably 1 nm to 50 nm. The second doped layer 132 is a phosphorus-doped polysilicon layer, and the surface doping concentration is 2E+20 cm -3 ~3E+21cm -3 and preferably 5E+20cm -3 ~2E+21cm -3 and the thickness is 1 nm to 100 nm, preferably 1 nm to 50 nm.

[0051] Preferably, a front passivation layer 51 and a front antireflection layer 61 are sequentially stacked on the first surface S1 of the silicon substrate 10 in Example 1, and a back surface passivation layer 52 and a back surface antireflection layer 62 are sequentially stacked on the second surface S2 of the silicon substrate 10, with the back surface passivation layer 52 and the back surface antireflection layer 62 covering the second doped layer 132 and extending into the second region S22. Illustratively, the front surface passivation layer 51 and the back surface passivation layer 52 are both alumina passivation layers with a thickness of 2 nm to 7 nm, preferably 3 nm to 6 nm, and the front surface antireflection layer 61 and the back surface antireflection layer 62 are laminate films made of one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer with a thickness of 60 nm to 130 nm.

[0052] In addition, in Example 1, the front surface electrode 41 is located on the first surface S1 of the silicon substrate 10 and is in contact with the front surface doped layer 11, and the back surface electrode 42 is located on the second surface S2 of the silicon substrate 10, specifically in the first region S21 on the second surface S2, and is in contact with the second doped layer 132.

[0053] 5, the first region S21 in Example 1 includes a plurality of first subregions 101 that are parallel and evenly spaced, and the second region S22 includes a plurality of second subregions 102 that are parallel and evenly spaced, with the first subregions 101 and the second subregions 102 being alternately distributed. The width of the first subregions 101 is smaller than the width of the second subregions 102, and the ratio of the widths may be, for example, 1:(5 to 20). Preferably, the first region S21 occupies about 10% of the entire area of ​​the second surface S2.

[0054] 6, the second electrode 42 is a gate line electrode and includes at least a plurality of thin gate lines 421 distributed in parallel, and the width of the first sub-region 101 is equal to or greater than the width of the thin gate lines 421. Optionally, the second electrode 42 may further include a plurality of main gate lines (not shown) distributed perpendicular to the thin gate lines 421.

[0055] In this embodiment, taking a 210 TOPCon battery as an example, the battery dimensions are 203.396±15 mm, there are 230 thin gate lines 421, the width is 15 μm to 100 μm, and the spacing between adjacent thin gate lines is 0.907±0.015 mm. The spacing between adjacent first sub-regions 101 is equal to the spacing between adjacent thin gate lines, and one thin gate line 421 is distributed in each first sub-region 101. The width of the first sub-region 101 is larger than the width of the thin gate line 421, and the width of the first sub-region is 50 μm to 150 μm. For example, the width of the thin gate line is 40 μm, and the width of the first sub-region is 80 μm.

[0056] When observed from the perspective of an orthographic projection plane along the projection direction facing the second electrode 42, the width dimension of the projection of the metal region on the projection plane is equal to or greater than the width dimension of the projection of the second electrode 42.

[0057] The method for manufacturing a solar cell in this embodiment specifically includes the following steps.

[0058] 1. Double-sided texturing

[0059] As shown in FIG. 7a, a silicon substrate 10 is provided, which includes a first surface S1 and a second surface S2 opposite to each other, the second surface S2 including a first region S21 and a second region S22, the first surface S1 being the front surface (i.e., the light-receiving surface) of the silicon substrate 10, the second surface S2 being the back surface (i.e., the backlight surface) of the silicon substrate 10, the first region S21 being a back gate line region, and the second region S22 being a back non-gate line region.

[0060] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and has a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm.

[0061] As shown in FIG. 7b, in this embodiment, a pyramid texture structure is formed on the first surface S1 and the second surface S2 of the silicon substrate 10 by an alkali texturing process, and the pyramid size is 0.5 μm to 3 μm.

[0062] 2. Boron diffusion As shown in FIG. 7c, a P-type doped front surface doped layer (i.e., P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, the diffusion is performed using a boron source deposition driving method in a high-temperature furnace tube, and the doping concentration of the first doped layer after diffusion is 3E+18 cm -3 ~3E+19cm -3 and the square resistivity is 40Ω / sq to 300Ω / sq, preferably 150Ω / sq to 250Ω / sq. In the boron diffusion process, a BSG (not shown) is formed on the second surface S2 of the silicon substrate.

[0063] 3. Backside polishing As shown in FIG. 7d, the silicon substrate 10 after boron diffusion is passed through a single-sided chain device to remove the backside silicon oxide with a hydrofluoric acid solution, then the backside is alkaline polished to remove edge deposition and backside smearing (BSG), and finally cleaned.

[0064] 4. Fabrication of rear tunnel passivation contact structure As shown in FIG. 7e, a tunnel layer 12, one first doped layer 131, one barrier layer 14, and one second doped layer 132 are sequentially formed on the second surface S2.

[0065] For example, in this embodiment, a silicon oxide tunnel layer having a thickness of 1 nm to 3 nm is first deposited on the back surface by a PECVD process, then a phosphorus-doped amorphous silicon layer is deposited with a thickness of 1 nm to 100 nm, preferably 1 nm to 50 nm, a silicon oxide barrier layer is deposited with a thickness of 1 nm to 3 nm, preferably 1.5 nm to 2 nm, and finally a phosphorus-doped amorphous silicon layer is deposited with a thickness of 1 nm to 50 nm, preferably 50 nm to 100 nm.

[0066] 5. Annealing activation The silicon substrate 10 on which the tunnel layer 12, the first doped layer 131, the barrier layer 14, and the second doped layer 132 are deposited is annealed. Before the annealing, the first doped layer 131 and the second doped layer 132 are both phosphorus-doped amorphous silicon layers, and the annealing is used to convert the phosphorus-doped amorphous silicon layers into doped polysilicon layers.

[0067] For example, in this embodiment, the annealing is performed in a high-temperature annealing furnace, and the annealing temperature is 880°C to 980°C, preferably 900°C to 950°C. After annealing, the doped amorphous silicon is converted into doped polysilicon, the phosphorus is activated, and a tunnel passivation contact structure can be formed on the backside. The surface doping concentration of the first doped layer 131 is 1E+20 cm -3 ~9E+20cm -3 and preferably 3E+20cm -3 ~5E+20cm -3 For example, 4E+20cm -3 and the surface doping concentration of the second doped layer 132 is 2E+20 cm -3 ~3E+21cm -3 and preferably 5E+20cm -3 ~2E+21cm -3 For example, 1E+21cm -3 is.

[0068] 6. Laser oxidation As shown in FIG. 7f, the second doped layer 132 on the first region S21 is treated by a laser process to form an oxide layer 133 on the surface of the second doped layer on the first region S21.

[0069] In the laser oxidation step, a silicon oxide (SiOx) layer is formed on the surface of the phosphorus-doped amorphous silicon layer on the first region S21 by the instantaneous high temperature of the laser, and the silicon oxide layer serves as a mask for subsequent processes.

[0070] Specifically, the laser process is performed in an atmosphere containing oxygen, with the volume concentration of oxygen being 20% ​​to 80%, the laser power being 1 W to 100 W, preferably 30 W to 60 W, the laser frequency being 1 kHz to 1000 kHz, preferably 300 kHz to 600 kHz, the laser scanning speed being 10,000 mm / s to 100,000 mm / s, preferably 30,000 mm / s to 60,000 mm / s, and the number of laser processing times being 1 to 100, preferably 1 to 10. The thickness of the oxide layer 133 formed by the laser process is 1 nm to 50 nm.

[0071] For example, in one specific embodiment, the volume concentration of oxygen in the laser process is 20%, the laser power is 50 W, the laser frequency is 500 kHz, the laser scanning speed is 50,000 mm / s, and the number of laser processing is two.

[0072] 8 shows the laser scanning pattern in the laser process of this embodiment. The black line area corresponds to the laser scanning area, i.e., the first area S21 (i.e., the metal gate line area), and the blank area corresponds to the second area S22 (i.e., the non-gate line area).

[0073] After the laser process, a tunnel layer + phosphorus-doped polysilicon layer + barrier layer + phosphorus-doped polysilicon layer + silicon oxide layer structure is formed in the first region S21, and a tunnel layer + phosphorus-doped polysilicon layer + barrier layer + phosphorus-doped polysilicon layer structure is formed in the second region S22.

[0074] It should be understood that the laser scanning pattern in the present invention can be designed according to different electrode structures, and a patterned silicon oxide mask is formed in the laser scanning area (i.e., the backside metal area), and laser scanning patterns for other electrode structures will not be described here one by one. In addition, the annealing step and the oxidation step can be reversed according to the needs of the actual processing scenario, i.e., the mask can be formed first, and then annealed to convert the phosphorus-doped amorphous silicon layer into a doped polysilicon layer.

[0075] In the prior art, a single layer of mask is typically deposited using a process such as PECVD, and then the mask is patterned. In the present invention, the fabrication of a patterned mask can be achieved through a one-step laser process, greatly simplifying the process flow.

[0076] High temperatures are generated during the laser process, which significantly affects the amount of phosphorus doping. Excess phosphorus easily penetrates and destroys the tunneling layer, resulting in poor surface passivation and a significantly low open-circuit voltage. The barrier layer in the present invention provides a barrier to phosphorus propagation. By controlling the parameters of the laser process, it is possible to accommodate stacked structures with different numbers of barrier layers and doping layers.

[0077] 7. Plating unevenness removal and chemical etching As shown in Figures 7f and 7g, a chemical etching process is used to remove all of the second doped layer 132 on the second region S22 and the oxide layer 133 on the first region S21, leaving only the second doped layer 132 on the first region S21, and then forming a first passivation contact structure 20 in the first region S21 and a second passivation contact structure 30 in the second region S22.

[0078] This step specifically includes: alkaline etching, using the oxide layer 133 as a mask to remove the second doped layer 132 on the second region S22 and simultaneously remove plating irregularities on the front surface and edge using an alkaline solution, the mass part of the alkaline solution is 3% to 5%, and the treatment time is 100 seconds to 500 seconds, preferably 350 seconds; Acid cleaning is performed by using an acid solution to remove the barrier layer 14 on the second region S22 and the oxide layer on the first region S21, while simultaneously removing the PSG on the front surface, the mass part of the acid solution is 5% to 20%, and the treatment time is 100 seconds to 500 seconds, preferably 300 seconds; Finally, RCA cleaning is performed, which is a conventional technique and will not be repeated here.

[0079] Preferably, the acid solution in this embodiment is a mixture of industrial grade hydrofluoric acid solution (parts by mass ~ 40%) and water in a certain ratio, and the alkaline solution is a mixture of industrial grade sodium hydroxide solution (parts by mass ~ 32%) and water in a certain ratio.

[0080] In conventional techniques, a front surface chain process (acid cleaning) is usually required before the alkaline etching step, in which the silicon oxide mask is passed through a hydrofluoric acid bath to remove the surface of the silicon oxide mask that has plating irregularities on the edges. In the present invention, the silicon oxide mask is not manufactured by a PECVD process, so there is no silicon oxide plating irregularities on the edges, and therefore no front surface chain process is required.

[0081] 8. Passivation layer fabrication As shown in FIG. 7h, a front surface passivation layer 51 and a back surface passivation layer 52 are fabricated on the first surface S1 and the second surface S2 of the silicon substrate by the ALD process, respectively. The front surface passivation layer 51 and the back surface passivation layer 52 are both alumina passivation layers, with thicknesses of 2 nm to 7 nm, preferably 3 nm to 6 nm.

[0082] 9. Anti-reflection layer manufacturing As shown in FIG. 7i, a front anti-reflection layer 61 and a back anti-reflection layer 62 are fabricated on the first surface S1 and the second surface S2 of the silicon substrate by a PECVD process, respectively. The front anti-reflection layer 61 and the back anti-reflection layer 62 may be a laminate film made of one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, and have a thickness of 60 nm to 130 nm.

[0083] 10. Printing of metal electrodes As shown in FIG. 7j, a front electrode 41 and a back electrode 42 are printed on the front and back surfaces by a screen printing process, respectively, and then sintered and subjected to optical injection or electrical injection processing to form ohmic contacts.

[0084] The front electrode 41 and the rear electrode 42 are gate line electrodes in the prior art, which usually include a main gate line and a thin gate line. However, since the thin gate line in the rear electrode 42 needs to be printed in the first region, the width of the first sub-region needs to be larger than the width of the thin gate line in the rear electrode 42, so that the alignment of the thin gate line can be achieved.

[0085] TOPCon batteries can be manufactured through the above steps, and finally, the battery sheets are test-selected and stocked.

[0086] Example 2

[0087] 9 and 10, the solar cell 100 in Example 2 is substantially the same as the solar cell structure in Example 1, with the following differences: In Example 2, the second passivation contact structure 30 formed in the second region S22 of the second surface S2 of the silicon substrate 10 is composed of a tunnel layer 12, a first doped layer 131, a barrier layer 14, and a second doped layer 132a, which are stacked in sequence. The tunnel layer 12, the first doped layer 131, and the barrier layer 14 of the second passivation contact structure 30 are completely the same as the tunnel layer 12, the first doped layer 131, and the barrier layer 14 of the first passivation contact structure 20 in the first region S21, with the difference being that the thickness of the second doped layer 132a in the second passivation contact structure 30 is smaller than the thickness of the second doped layer 132 in the first passivation contact structure 20.

[0088] The manufacturing method of the solar cell in this example is almost the same as that of Example 1, except for the seventh step of removing plating irregularities and chemical etching. Example 2 uses a chemical etching process to remove a portion of the second doped layer 132 on the second region S22 and the oxide layer 133 on the first region S21, leaving the second doped layer 132 on the first region S21. Instead of completely removing it, the second doped layer 132 on the second region S22 is thinned to form a second doped layer 132a.

[0089] This step specifically includes the following: Alkaline etching is performed by using an alkaline solution to remove a portion of the second doped layer 132 (finally leaving a portion of the second doped layer 132a) on the second region S22 using the oxide layer 133 as a mask, and simultaneously removing uneven plating on the front surface and the edge, the mass part of the alkaline solution is 3% to 15%, and the processing time is shorter than that in Example 1, for example, 50 seconds; Acid cleaning is performed by using an acid solution to remove the oxide layer 133 on the first region S21 and simultaneously remove the PSG on the front surface, the mass part of the acid solution is 5% to 20%, and the treatment time is 100 seconds to 500 seconds, preferably 300 seconds; Finally, RCA cleaning is performed, which is a conventional technique and will not be described again here.

[0090] In Example 2, the second doped layer 132a was left on a portion of the second region S22, so that when the acid cleaning process was performed, the acid solution would not corrode the barrier layer 14 on the second region S22, and therefore the barrier layer 14 and a portion of the second doped layer 132a were left in the second region.

[0091] Example 3

[0092] Referring to FIG. 11 and combining FIG. 12 , the solar cell 100 in Example 3 is almost the same as the solar cell structure in Example 1, with the difference being that in Example 3, a first doped layer 131 and a barrier layer 14 are provided alternately stacked on the tunnel layer 12 on the second surface S2 of the silicon substrate 10.

[0093] Specifically, in Example 3, a tunnel layer 12, a first doped layer 131, a barrier layer 14, a first doped layer 131, a barrier layer 14, and a second doped layer 132 are sequentially stacked in a first region S21 on the second surface S2 of the silicon substrate 10, and a tunnel layer 12, a first doped layer 131, a barrier layer 14, and a first doped layer 131 are sequentially stacked in a second region S22 on the second surface S2 of the silicon substrate 10. In other words, in Example 3, the first passivation contact structure 20 has six layers, which are sequentially stacked: a tunnel layer 12, a first doped layer 131, a barrier layer 14, a first doped layer 131, a barrier layer 14, and a second doped layer 132. The second passivation contact structure 30 is a four-layer structure consisting of a tunnel layer 12, a first doped layer 131, a barrier layer 14 and a first doped layer 131, which are stacked in sequence.

[0094] The manufacturing method of the solar cell of Example 3 is almost the same as that of Example 1, except for the fourth step of manufacturing the rear surface tunnel passivation structure.

[0095] For example, in Example 3, a 1-3 nm thick silicon oxide tunnel layer is deposited on the back surface by a PECVD process, followed by a phosphorus-doped amorphous silicon layer, a silicon oxide barrier layer, a phosphorus-doped amorphous silicon layer, a silicon oxide barrier layer, and finally a phosphorus-doped amorphous silicon layer, where the total thickness of all the phosphorus-doped amorphous silicon layers is controlled to 50-150 nm, preferably 60-100 nm, and the thickness of the outermost phosphorus-doped amorphous silicon layer is preferably 50-100 nm.

[0096] Correspondingly, in the seventh step of Example 3, the plating irregularity removal and chemical etching step, the second doped layer 132 on the second region S22 was removed by alkaline etching, and the outermost barrier layer 14 on the second region S22 and the oxide layer 133 on the first region S21 were removed by acid solution.

[0097] Example 4

[0098] Referring to Figure 13 and combining Figure 14, the solar cell in Example 4 is almost the same as the solar cell in Example 3, except that in Example 4, the second passivation contact structure 30 on the second region S22 on the second surface S2 of the silicon substrate 10 is composed of a tunnel layer 12, a first doped layer 131, a barrier layer 14, a first doped layer 131, a barrier layer 14, and a second doped layer 132a, which are stacked in sequence. The thickness of the second doped layer 132a is smaller than the thickness of the second doped layer 132 of the first passivation contact structure. In other words, in Example 4, the first passivation contact structure 20 is six layers, and the second passivation contact structure 30 is also six layers.

[0099] The manufacturing method of the solar cell of Example 4 is almost the same as that of Example 3, except for the seventh step of plating irregularity removal and chemical etching. Example 4 uses a chemical etching process to remove a portion of the second doped layer 132 on the second region S22 and the oxide layer 133 on the first region S21, leaving the second doped layer 132 on the first region S21. Instead of completely removing it, the second doped layer 132 on the second region S22 is thinned to form the second doped layer 132a.

[0100] In Example 4, the second doped layer 132a was left on a portion of the second region S22, so that when the acid cleaning process was performed, the acid solution would not corrode the outermost barrier layer 14 on the second region S22, and therefore the outermost barrier layer 14 and a portion of the second doped layer 132a were left in the second region S22.

[0101] Example 5

[0102] The solar cell and manufacturing method in Example 5 are almost the same as those in Example 1, except that the front doped layer 11 in Example 1 can be manufactured by a boron diffusion process, while the front doped layer 11 in Example 5 is manufactured by a PECVD process.

[0103] Specifically, in this embodiment, a boron-doped amorphous silicon layer is first deposited on the first surface S1 by a PECVD process, and then a P-type doped polysilicon layer is formed after high-temperature oxidation annealing.

[0104] It should be understood that in the above Examples 3 and 4, two layers of the second doped layer and two layers of the barrier layer are described as examples, and in other Examples, three or more layers of the second doped layer and the barrier layer may be formed. The technical means of removing all or part of the third doped layer on the second region S22 by alkaline etching are all within the scope of protection of the present invention, and will not be described again here by giving examples.

[0105] In summary, in the solar cell 100 described in Examples 1-5 above, the first passivation contact structure 20 provided in the first region S21 includes a tunnel layer 12, at least one first doped layer 131, at least one barrier layer 14, and a second doped layer 132. The electrode 42 is in contact with the second doped layer 132. The first doped layer 131 and the barrier layer 14 are alternately provided between the tunnel layer 12 and the second doped layer 132 according to the needs of the actual scene. As can be seen, a back surface passivation layer 52 and a back surface anti-reflection layer 62 are further formed on the back surface of the second doped layer 132.

[0106] Similarly, the second passivation contact structure 30 provided in the second region S22 includes a tunnel layer 12 and a first doped layer 131. In some design scenarios, the second passivation contact structure 30 can continue to provide a barrier layer 14 and a first doped layer 131 on the back surface of the first doped layer 131, and in other design scenarios, the second passivation contact structure 30 can continue to provide a barrier layer 14 and a second doped layer 132a on the back surface of the first doped layer 131, and the first doped layer 131 and the barrier layer 14 can be alternately provided between the tunnel layer 12 and the second doped layer 132a. In addition, the second doped layer 132a in the second passivation contact structure 30 and the second doped layer 132 of the first passivation contact structure 20 are the same doped layer, but their thicknesses are different. The back surface passivation layer 52 and the back surface anti-reflection layer 62 are also provided on the back surface of the outermost first doped layer 131 or second doped layer 132 a of the second passivation contact structure 30 .

[0107] 15, in the present invention, a height difference H1 / H2 is formed between both the first passivation contact structure 20 and the second passivation contact structure 30. Symbol H1 indicates the height difference formed between the outside of the back surface antireflection layer 62 in the first region S21 and the outside of the back surface antireflection layer 62 in the second region S22, and symbol H2 indicates the height difference formed along the thickness direction of the silicon substrate 10 between the surface of the outermost layer of the first passivation contact structure 20 and the surface of the outermost layer of the second passivation contact structure 30.

[0108] For the present invention, depending on the number and configuration of layers selected for the first passivation contact structure 20 and the second passivation contact structure 30, the height difference H1 / H2 may be equal to the thickness difference between the second doped layer 132 and the second doped layer 132a, or equal to the sum of the thicknesses of the barrier layer 14 and the second doped layer 132. For example, In Example 1, when the first passivation contact structure 20 is four layers and the second passivation contact structure 30 is two layers, the height difference H1 / H2 of both is equal to the sum of the thicknesses of the barrier layer 14 and the second doped layer 132. In Example 2, when the first passivation contact structure 20 is four layers and the second passivation contact structure 30 is four layers, both of the height differences H1 / H2 are equal to the thickness difference between the second doped layer 132 and the second doped layer 132a. In Example 3, when the first passivation contact structure 20 is six layers and the second passivation contact structure 30 is four layers, the height difference H1 / H2 of both is equal to the sum of the thicknesses of the barrier layer 14 and the second doped layer 132. In Example 4, when the first passivation contact structure 20 is six layers and the second passivation contact structure 30 is six layers, both of the height differences H1 / H2 are equal to the thickness difference between the second doped layer 132 and the second doped layer 132a.

[0109] As can be appreciated, if the thickness of the back surface passivation layer 52 in the first region S21 and the second region S22 is inconsistent and / or the thickness of the back surface anti-reflective layer 62 in the first region S21 and the second region S22 is inconsistent, the height difference H1 / H2 formed between the first and second passivation contact structures 20, 30 will also include the thickness variation difference of the back surface passivation layer / back surface anti-reflective layer 52, 62, which will not be repeated here by way of example.

[0110] In the present invention, the height difference H1 / H2 is preferably 0.01 μm to 8 μm.

[0111] 16 to 18, the dimensions of the pyramid texture structure 70 of the present invention range from 0.5 μm to 3 μm. FIG. 16 is an SEM image of the pyramid texture structure 70 of the present invention. The dimensions of the three pyramids shown are 2.67 μm, 2.60 μm, and 2.75 μm, respectively, with the average dimension of all pyramids being approximately 2.7 μm. The first region S21 and the second region S22 of the second surface S2 are both polished surfaces after polishing the pyramid texture structure. The silicon substrate 10 is recessed in the second region S22, and the dimensions of the pyramid bases in the first region S21 are smaller than those in the second region S22. The pyramid texture structure on the back surface of the silicon substrate is polished during the alkaline polishing process to form pyramid bases, which are the bases remaining after polishing the pyramid-shaped texture. The shape of the pyramid base can be triangular, rectangular, etc., and the pyramid base dimension is defined as the average width of the pyramid base shape. Taking a square pyramid base as an example, the pyramid base dimension is the average length of the square's sides. The pyramid base dimension formed during the alkaline polishing process is larger than the pyramid dimension, and the deeper the etching depth, the larger the pyramid base dimension. In the present invention, the pyramid base dimension on the first region S21 is 3 μm to 20 μm, preferably 8 μm to 15 μm, and the pyramid base dimension on the second region is 3 μm to 50 μm, preferably 15 μm to 30 μm.

[0112] 17 shows an SEM image of the first region S21, where the pyramid base dimensions are 11.37 μm, 11.52 μm, 11.44 μm, 11.53 μm, and 11.13 μm, respectively, with the average pyramid base dimension in the first region S21 being approximately 11.4 μm. FIG. 18 shows an SEM image of the second region S22, where the etching depth in the second region S22 is deep and the pyramid base dimensions formed are large. The pyramid base dimensions are 20.30 μm, 20.23 μm, and 19.29 μm, respectively, with the average pyramid base dimension in the second region S22 being approximately 20 μm.

[0113] The manufacturing process of the SE (Selective Emitter) structure on the back surface of the battery in the present invention is simple, and the oxidation of the first region (metal region) is completed by a laser process, which eliminates the mask manufacturing process in the polysilicon process and the front surface chain process before removing plating irregularities. In addition, the present invention completely or partially removes the second doped layer in the second region (non-metallic region) on the back surface of the battery, leaving the second doped layer in the first region (metallic region) unaffected. This allows for both passivation and reduction of parasitic absorption without changing the slurry, thereby improving the process window and significantly improving the cell efficiency and double-sidedness. By applying a barrier layer to the back surface of the battery, it is possible to effectively improve the doping concentration change of the doped layer during the laser process, avoid the destruction of the tunnel layer, and further enhance the passivation effect. At the same time, the barrier layer has a certain barrier ability against the penetration of the back surface slurry, which helps to reduce the total thickness of the back surface doped layer and increase the open circuit voltage (Voc) of the battery.

[0114] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Therefore, in all respects, the examples are to be considered as illustrative and not limiting, and the scope of the present invention is defined by the appended claims, not the above description. All changes within the meaning and range of equivalency of the claims are intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the scope of the claims.

[0115] It should be understood that although this specification has been described according to the embodiments, each embodiment does not include only one independent technical solution, and the description such as the specification is merely for the purpose of clarification. Those skilled in the art should take the specification as a whole, and may also appropriately combine the technical solutions in each example to form other embodiments that are understandable to those skilled in the art.

[0116] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese patent applications having a filing date of April 19, 2024, application number 202410485399.0, a filing date of May 8, 2024, application number 202410563104.7, a filing date of August 27, 2024, application number 202411184801.8, and a filing date of September 26, 2024, application number 202411352531.7.

Claims

1. a silicon substrate having a front surface and a back surface; a passivation contact structure on the backside of the silicon substrate; a back electrode provided on the passivation contact structure, The passivation contact structure comprises a tunnel layer, a first doped polysilicon layer, a partition layer, and a second doped polysilicon layer, which are sequentially formed on the back surface of the silicon substrate, and wherein the partition layer is discontinuously formed.

2. 2. The solar cell according to claim 1, wherein the partition layer is selected from the group consisting of a silicon oxide layer, a silicon oxynitride layer, and a silicon carbide layer, or a combination of these layers.

3. The solar cell according to claim 1, wherein the thickness of the tunnel layer is 1 nm to 3 nm and / or the thickness of the partition layer is 0.5 nm to 3 nm, and preferably, the thickness of the tunnel layer and the thickness of the partition layer are each 1.5 nm to 2 nm.

4. 2. The solar cell according to claim 1, wherein the thickness of the first doped polysilicon layer is equal to or less than the thickness of the second doped polysilicon layer.

5. The doping type of the first doped polysilicon layer and the second doped polysilicon layer is the same as the doping type of the silicon substrate, and the doping concentration of the second doped polysilicon layer is greater than the doping concentration of the first doped polysilicon layer, or the doping concentration of the first doped polysilicon layer is 1E+20 cm -3 ~9E+20cm -3 and the doping concentration of the second doped polysilicon layer is 2E+20 cm -3 ~3E+21cm -3 2. The solar cell according to claim 1, wherein:

6. The solar cell further includes a back surface passivation layer and a back surface anti-reflection layer sequentially provided on a back surface of the passivation contact structure away from the silicon substrate, the back surface electrode passing through the back surface anti-reflection layer and the back surface passivation layer and contacting the second doped polysilicon layer; and 2. The solar cell of claim 1, further comprising a front diffusion layer, a front passivation layer, a front anti-reflection layer, and a front electrode, which are sequentially provided on the front surface of the silicon substrate, and the front electrode passes through the front anti-reflection layer and the front passivation layer to contact the front diffusion layer.

7. A method for manufacturing a solar cell, comprising: depositing a tunnel layer, a first doped amorphous silicon layer, a partition layer, and a second doped amorphous silicon layer in sequence on a rear surface of a silicon substrate; partially forming a mask on the second doped amorphous silicon layer, preferably the mask layer being formed by laser processing in an oxygen atmosphere; converting the first doped amorphous silicon layer into a first doped polysilicon layer and converting the second doped amorphous silicon layer into a second doped polysilicon layer; removing the second doped polysilicon layer in areas other than the mask; removing the mask and a portion of the partition layer to form a discontinuous partition layer.

8. A method for manufacturing a solar cell, comprising: providing a silicon substrate including first and second opposing surfaces, the second surface including a first region and a second region; sequentially forming a tunnel layer, a first phosphorus-doped amorphous silicon layer, a barrier layer, and a second phosphorus-doped amorphous silicon layer on a second surface of the silicon substrate; converting the first phosphorus-doped amorphous silicon layer into a first doped polysilicon layer and converting the second phosphorus-doped amorphous silicon layer into a second doped polysilicon layer; forming a mask layer on a surface of the second doped polysilicon layer in the first region; removing the second doped polysilicon layer in at least a portion of the second region and the mask layer in the first region, leaving the second doped polysilicon layer in the first region; and forming an electrode in the first region contacting the second doped polysilicon layer.

9. The mask layer is an oxide layer, and the step of removing the second doped polysilicon layer in at least a portion of the second region and the mask layer in the first region and leaving the second doped polysilicon layer in the first region includes: removing all of the second doped polysilicon layer in the second region using an alkaline solution, and removing the outermost partition layer in the second region and the oxide layer in the first region using an acid solution; or 9. The method for manufacturing a solar cell according to claim 8, further comprising the steps of removing a portion of the second doped polysilicon layer in the second region using an alkaline solution and removing the oxide layer in the first region using an acid solution.

10. A solar cell, a silicon substrate including a first surface and a second surface including a first region and a second region, the first surface being provided opposite to each other, wherein a tunnel layer, at least one first doped layer, at least one barrier layer, and a second doped layer are sequentially provided in the first region of the second surface, and the second surface being provided with a tunnel layer and at least one first doped layer in the second region; an electrode located in the first region and in contact with the second doped layer.

11. The first region includes a tunnel layer, a first doped layer, a barrier layer, and a second doped layer, and the second region includes a tunnel layer and a first doped layer, or The first region includes a tunnel layer, a first doped layer, a barrier layer, and a second doped layer, and the second region includes a tunnel layer, a first doped layer, a barrier layer, and a second doped layer, and the thickness of the second doped layer in the second region is smaller than the thickness of the second doped layer in the first region; or The first region is provided with a tunnel layer, at least two alternating first doped layers and at least two alternating barrier layers, and a second doped layer, and the second region is provided with a tunnel layer, at least two alternating first doped layers and at least one alternating barrier layer, or 11. The solar cell of claim 10, wherein the first region includes a tunnel layer, at least two first doped layers and at least two barrier layers alternately stacked, and a second doped layer, and the second region includes a tunnel layer, at least two first doped layers and at least two barrier layers alternately stacked, and a second doped layer, and the thickness of the second doped layer in the second region is smaller than the thickness of the second doped layer in the first region.

12. A solar cell, a silicon substrate including a first surface and a second surface including a metal region and a non-metal region, the first surface and the second surface being disposed opposite each other; a first electrode provided on a first surface of the silicon substrate; a second electrode provided on a second surface of the silicon substrate and located on the metal region; The metal region has a first passivation contact structure, the first passivation contact structure including a tunnel layer, at least one first doped polysilicon layer, at least one partition layer, and a second doped polysilicon layer sequentially disposed on the second surface.

13. 13. The solar cell according to claim 12, wherein a dimension of the orthogonal projection of the metal region on the silicon substrate along the planar direction of the silicon substrate is equal to or greater than a dimension of the orthogonal projection of the second electrode on the silicon substrate along the planar direction of the silicon substrate.

14. the non-metal region has a second passivation contact structure, the second passivation contact structure including a tunnel layer and a first doped polysilicon layer sequentially disposed on the second surface; or the second passivation contact structure includes a tunnel layer, a first doped polysilicon layer, a barrier layer, and a second doped polysilicon layer, sequentially disposed on the second surface; or the second passivation contact structure includes a tunnel layer and a second doped polysilicon layer sequentially disposed on the second surface; or the second passivation contact structure includes a tunnel layer, at least two first doped polysilicon layers, and at least one separator layer disposed sequentially on the second surface; or 14. The solar cell of claim 13, wherein the second passivation contact structure includes a tunnel layer, at least two first doped polysilicon layers, at least two partition layers, and a second doped polysilicon layer, which are sequentially disposed on the second surface.

15. The solar cell according to claim 13 , wherein the first passivation contact structure and the second passivation contact structure have a height difference with respect to the rear surface of the silicon substrate.

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