Multilayer ceramic capacitor and manufacturing method for the same

Abstract

To suppress the occurrence of a structure defect in a multilayer ceramic capacitor.SOLUTION: In a cross section along a stacking direction T and a width direction W at a central part of a multilayer body 110 in a length direction L, each of a plurality of internal electrode layers 150 has an arc part Y that is curved in an arc shape at one of both end parts in the width direction W and the other of both end parts is a bent part Z that is bent so as to have at least one flexion point. The internal electrode layers 150 include an A-shape internal electrode layer 150A in which the arc part Y exists at one end part in the width direction W, and a B-shape internal electrode layer 150B in which the bent part Z exists at the one end part in the width direction W.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2023-35851 (Patent Document 1) is a prior art document that discloses the configuration of a ceramic electronic component. In the manufacturing process of the ceramic electronic component described in Patent Document 1, a reverse pattern paste is printed on a dielectric green sheet in a peripheral area where no electrode pattern is printed, thereby arranging a first pattern and filling in any steps with the electrode pattern. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-35851 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the miniaturization of multilayer ceramic capacitors has progressed, making it difficult to precisely and quickly arrange dielectric patterns around conductive patterns to fill in gaps. As a result, unexpected gaps and overlaps between the dielectric and conductive patterns can occur. If these gaps and overlaps are excessively and continuously stacked, structural defects can occur in the multilayer ceramic capacitor.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a multilayer ceramic capacitor and a manufacturing method thereof that can suppress the occurrence of structural defects. [Means for solving the problem]

[0006] A multilayer ceramic capacitor according to the present invention includes a laminate and external electrodes. The laminate includes a plurality of dielectric layers and a plurality of internal electrode layers stacked along a lamination direction, and includes first and second main surfaces opposing each other in the lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to both the lamination direction and the width direction. External electrodes are provided on each of the first and second end surfaces and connected to the plurality of internal electrode layers. In a cross section of a central portion of the laminate in the length direction, taken along the lamination direction and the width direction, each of the plurality of internal electrode layers has one of its two end portions in the width direction being an arc-shaped portion curved in an arc shape and the other of its two end portions being a bent portion bent so as to have at least one inflection point. The plurality of internal electrode layers include an A-shaped internal electrode layer having an arc-shaped portion located at one end in the width direction, and a B-shaped internal electrode layer having a bent portion located at one end in the width direction. [Effects of the Invention]

[0007] According to the present invention, it is possible to prevent structural defects from occurring in the multilayer ceramic capacitor. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view showing the appearance of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, seen from the direction of the arrows along line II-II. [Figure 3] 3 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1, seen from the direction of the arrows along line III-III. [Figure 4] 4 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 2, seen from the direction of the arrows along line IV-IV. [Figure 5] 3 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 2, seen from the direction of the arrow VV line. [Figure 6]1 is a perspective view showing the appearance of a material sheet in which a conductive pattern is formed on an inner layer ceramic green sheet in a method for manufacturing a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. [Figure 7] 1 is a plan view showing the appearance of a material sheet in which a dielectric pattern is formed on an inner layer ceramic green sheet in a manufacturing method of a multilayer ceramic capacitor according to a first preferred embodiment of the present invention. FIG. [Figure 8] 2 is a diagram showing a state in which outer layer ceramic green sheets and material sheets are laminated in a method for manufacturing the multilayer ceramic capacitor according to the first preferred embodiment of the present invention. FIG. [Figure 9] 5 is a cross-sectional view showing a cross section of a multilayer ceramic capacitor according to a second embodiment of the present invention, taken along the lamination direction and width direction at the center in the length direction. [Figure 10] FIG. 6 is a diagram showing a state in which outer layer ceramic green sheets and material sheets are laminated in a method for manufacturing a multilayer ceramic capacitor according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, multilayer ceramic capacitors according to embodiments of the present invention will be described with reference to the drawings. In the following description of the embodiments, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and description thereof will not be repeated.

[0010] (Embodiment 1) Fig. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, seen from the direction of the arrows along line II-II. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1, seen from the direction of the arrows along line III-III. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 2, seen from the direction of the arrows along line IV-IV. Fig. 5 is a cross-sectional view of the multilayer ceramic capacitor of Fig. 2, seen from the direction of the arrows along line VV. Figs. 1 to 5 show the length direction L of the laminate, the width direction W of the laminate, and the lamination direction T of the laminate, which will be described later.

[0011] 1 to 5, the multilayer ceramic capacitor 100 according to the first embodiment of the present invention includes a laminate 110, a first external electrode 120, and a second external electrode 130. The laminate 110 includes a plurality of dielectric layers 140 and a plurality of internal electrode layers 150 alternately stacked along a stacking direction T.

[0012] The laminate 110 includes a first main surface 111 and a second main surface 112 that face each other in a stacking direction T, a first side surface 113 and a second side surface 114 that face each other in a width direction W that is perpendicular to the stacking direction T, and a first end surface 115 and a second end surface 116 that face each other in a length direction L that is perpendicular to both the stacking direction T and the width direction W. The first external electrode 120 is provided on the first end surface 115. The second external electrode 130 is provided on the second end surface 116.

[0013] The multiple internal electrode layers 150 include multiple first internal electrode layers 151 connected to the first external electrode 120, and multiple second internal electrode layers 152 connected to the second external electrode 130. Although Fig. 2 and Fig. 3 show an example in which five first internal electrode layers 151 and five second internal electrode layers 152 are provided, the number of each of the first internal electrode layers 151 and the second internal electrode layers 152 is not limited to five.

[0014] 4, the first internal electrode layer 151 includes a facing portion 151C facing the second internal electrode layer 152, and a lead portion 151X drawn to the first end surface 115. As shown in Fig. 5, the second internal electrode layer 152 includes a facing portion 152C facing the first internal electrode layer 151, and a lead portion 152X drawn to the second end surface 116.

[0015] As shown in FIGS. 2 to 5, the laminate 110 is divided into an inner layer portion C, a first outer layer portion X1, a second outer layer portion X2, a first side margin portion S1, a second side margin portion S2, a first end margin portion E1, and a second end margin portion E2.

[0016] The inner layer portion C has capacitance due to the opposing portion 151C of the first internal electrode layer 151 and the opposing portion 152C of the second internal electrode layer 152 being stacked in the stacking direction T. The first outer layer portion X1 is located on the first main surface 111 side of the inner layer portion C in the stacking direction T. The second outer layer portion X2 is located on the second main surface 112 side of the inner layer portion C in the stacking direction T.

[0017] The first side margin S1 is located on the first side surface 113 side of the inner layer portion C in the width direction W. The second side margin S2 is located on the second side surface 114 side of the inner layer portion C in the width direction W. The first end margin E1 is located on the first end surface 115 side of the inner layer portion C in the length direction L. The second end margin E2 is located on the second end surface 116 side of the inner layer portion C in the length direction L.

[0018] It is preferable that the corners and ridges of the laminate 110 are rounded. Here, a corner is a portion where three faces of the laminate 110 intersect, and a ridge is a portion where two faces of the laminate 110 intersect.

[0019] The thickness of the dielectric layer 140 located in the inner layer portion C is preferably 0.3 μm or more and 0.8 μm or less. The thickness of the first outer layer portion X1 and the thickness of the second outer layer portion X2 are each preferably 10 μm or more and 30 μm or less. The width of the first side margin portion S1 and the width of the second side margin portion S2 are each preferably 0.1 μm or more and 0.5 μm or less. The length of the first end margin portion E1 and the length of the second end margin portion E2 are each preferably 0.2 mm or more and 1.0 mm or less. The thickness of the dielectric layer 140 located in the inner layer portion C, the thickness of the first outer layer portion X1, the thickness of the second outer layer portion X2, and the length of the first end margin portion E1 and the length of the second end margin portion E2 are each dimensions at the center position in the width direction W of the laminate 110. The width of the first side margin portion S1 and the width of the second side margin portion S2 are each dimensions at the center position in the length direction L of the laminate 110.

[0020] Each of the plurality of dielectric layers 140 contains, as a main component, dielectric particles with a perovskite structure such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Each of the plurality of dielectric layers 140 may contain, in addition to the main component, a minor component in a content less than that of the main component, such as at least one of a Si compound, a Mg compound, a Mn compound, an Fe compound, a Cr compound, a Ni compound, and a Co compound.

[0021] Each of the first internal electrode layer 151 and the second internal electrode layer 152 contains one kind of metal selected from the group consisting of Ni, Cu, Ag, Pd and Au, or an alloy containing the metal. Each of the first internal electrode layer 151 and the second internal electrode layer 152 may further contain dielectric particles having the same composition as the ceramic contained in the dielectric layer 140. Furthermore, Sn may be present at the interface between each of the first internal electrode layer 151 and the second internal electrode layer 152 and the dielectric layer 140.

[0022] The thickness of each of the first internal electrode layer 151 and the second internal electrode layer 152 is preferably 0.3 μm or more and 0.8 μm or less. The number of the internal electrode layers 150 including the first internal electrode layer 151 and the second internal electrode layer 152 is preferably 10 or more and 1000 or less.

[0023] Here, the thickness of each of the dielectric layer 140, the first internal electrode layer 151 and the second internal electrode layer 152 can be measured by the following method.

[0024] First, a surface defined by the stacking direction T and width direction W of the laminate 110, i.e., a surface perpendicular to the length direction L of the laminate 110, is exposed by grinding, and the exposed cross section is observed under a scanning electron microscope. Next, the thickness of the dielectric layer 140 is measured on a center line along the stacking direction T that passes through the center of the exposed cross section, and two lines drawn equally spaced on either side of this center line, for a total of five lines. The average of these five measurements is defined as the thickness of the dielectric layer 140.

[0025] The thickness of each of the first internal electrode layer 151 and the second internal electrode layer 152 can also be measured using a scanning electron microscope on the same cross section as the cross section where the thickness of the dielectric layer 140 was measured, using a method similar to the method for measuring the thickness of the dielectric layer 140.

[0026] The first external electrode 120 is formed over the entire first end face 115 of the laminate 110, and is formed so as to extend from the first end face 115 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114. The first external electrode 120 is electrically connected to the first internal electrode layer 151.

[0027] The second external electrode 130 is formed over the entire second end face 116 of the laminate 110, and is formed so as to extend from the second end face 116 to the first main face 111, the second main face 112, the first side face 113, and the second side face 114. The second external electrode 130 is electrically connected to the second internal electrode layer 152.

[0028] The first external electrode 120 and the second external electrode 130 each include, for example, a base electrode layer and a plating layer disposed on the base electrode layer. The base electrode layer includes at least one layer selected from the group consisting of a baked electrode layer, a resin electrode layer, and a thin-film electrode layer.

[0029] The baked electrode layer is a layer containing glass and metal, and may be a single layer or multiple layers. The baked electrode layer is made of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, such as an alloy of Ag and Pd.

[0030] The baked electrode layer is formed by applying a conductive paste containing glass and metal to the laminate 110 and baking it. Baking may be performed simultaneously with or after baking the laminate 110. The maximum thickness of the baked electrode layer is preferably 20 μm or more and 70 μm or less.

[0031] The resin electrode layer can be formed, for example, as a layer containing conductive particles and a thermosetting resin. When forming the resin electrode layer, it may be formed directly on the laminate without forming a baked electrode layer. The resin electrode layer may be a single layer or multiple layers. The maximum thickness of the resin electrode layer is preferably 20 μm or more and 70 μm or less.

[0032] The thin-film electrode layer is, for example, a layer of 1 μm or less in thickness in which metal particles are deposited, and can be formed by a known thin-film forming method such as sputtering or vapor deposition.

[0033] The plating layer disposed on the base electrode layer is composed of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, and Au, or an alloy containing this metal, such as an alloy of Ag and Pd. The plating layer may be a single layer or multiple layers. However, the plating layer preferably has a two-layer structure in which a Sn plating layer is formed on a Ni plating layer. The Ni plating layer functions to prevent the base electrode layer from being eroded by solder when mounting the multilayer ceramic capacitor 100. The Sn plating layer functions to improve the wettability of the solder when mounting the multilayer ceramic capacitor 100. The thickness of each plating layer is preferably 1 μm or more and 5 μm or less.

[0034] The dimension of the multilayer ceramic capacitor 100 in the length direction L is, for example, 0.1 mm or more and 1.0 mm or less. The dimension of the multilayer ceramic capacitor 100 in the stacking direction T is, for example, 0.05 mm or more and 0.5 mm or less. The dimension of the multilayer ceramic capacitor 100 in the width direction W is, for example, 0.05 mm or more and 0.5 mm or less. The above dimensions include tolerances.

[0035] As shown in Fig. 3, in a cross section along the stacking direction T and the width direction W at the center of the laminate 110 in the length direction L, each of the multiple internal electrode layers 150 has an arc-shaped portion Y at one of its two end portions in the width direction W, which is curved in an arc shape, and a bent portion Z at the other end portion, which is bent so as to have at least one inflection point. Here, the arc-shaped portion refers to a curve that does not have an inflection point. By polishing the laminate 110 up to the center in the length direction L and observing the exposed cross section, the arc-shaped portion Y that is curved in an arc shape can be confirmed.

[0036] The multiple internal electrode layers 150 include an A-shaped internal electrode layer 150A having an arc-shaped portion Y located at one end in the width direction W, and a B-shaped internal electrode layer 150B having a bent portion Z located at the same end in the width direction W.

[0037] In this embodiment, among the plurality of internal electrode layers 150, the A-type internal electrode layers 150A and the B-type internal electrode layers 150B are alternately positioned one layer at a time in the stacking direction T.

[0038] The maximum deviation D1 in the width direction W of the multiple internal electrode layers 150 is 20 μm or less. Specifically, the maximum deviation D1 in the width direction W between the internal electrode layer 150 located closest to the first side face 113 and the internal electrode layer 150 located closest to the second side face 114 of the multiple internal electrode layers 150 is 20 μm or less.

[0039] A method for manufacturing the multilayer ceramic capacitor 100 according to this embodiment will now be described.

[0040] In the manufacturing method of the multilayer ceramic capacitor 100, first, a ceramic slurry containing ceramic powder, a binder, and a solvent is prepared. This ceramic slurry is formed into sheets on a carrier film using a die coater, a gravure coater, a microgravure coater, or the like, to produce ceramic green sheets for inner layers and ceramic green sheets for outer layers, which will be described later.

[0041] The outer layer ceramic green sheets may be formed from the same material as the inner layer ceramic green sheets, or may be formed from a material containing components different from the material of the inner layer ceramic green sheets.

[0042] FIG. 6 is a perspective view showing the appearance of a material sheet in which a conductive pattern is formed on an inner layer ceramic green sheet in the method for manufacturing the multilayer ceramic capacitor according to the first preferred embodiment of the present invention.

[0043] 6, a conductive paste is printed in a strip-like pattern on the inner layer ceramic green sheet 23 by screen printing, inkjet printing, gravure printing, or the like, to form the conductive pattern 24. Specifically, a rectangular conductive pattern 24 having two sides along the width direction W and two sides along the length direction L is printed on one main surface of the inner layer ceramic green sheet 23. The conductive paste contains Ni powder, an organic solvent, a binder, and the like.

[0044] FIG. 7 is a plan view showing the appearance of a material sheet in which a dielectric pattern is formed on an inner layer ceramic green sheet in the method for manufacturing the multilayer ceramic capacitor according to the first preferred embodiment of the present invention.

[0045] 7, a dielectric paste is applied to one main surface of an inner layer ceramic green sheet 23 to form a dielectric pattern 25, so as to surround the conductive pattern 24 and form an overlapping region RS that overlaps with one side N of the two sides of the conductive pattern 24 along the length direction L, and a separation region RC that is separated in the width direction W from the other side M of the two sides of the conductive pattern 24 along the length direction L. The dielectric paste may contain a larger amount of at least one of Mg, Mn, and Si than the material of the inner layer ceramic green sheet.

[0046] The width of each of the overlapping region RS and the separation region RC in the width direction W is 20 μm or more and 30 μm or less. The dielectric pattern 25 may be formed before the conductive pattern 24. In this case, the conductive pattern 24 is superimposed on the dielectric pattern 25 in the overlapping region RS.

[0047] In this way, a material sheet is prepared in which the conductive pattern 24 and the dielectric pattern 25 that will become the internal electrode layer 150 are printed on one main surface of the inner layer ceramic green sheet 23 that will become the dielectric layer 140 located in the inner layer portion C.

[0048] FIG. 8 is a diagram showing a state in which outer layer ceramic green sheets and material sheets are laminated in the method for manufacturing the multilayer ceramic capacitor according to the first preferred embodiment of the present invention.

[0049] As shown in Fig. 8, a plurality of material sheets and outer layer ceramic green sheets 26 are stacked. Specifically, the element sheets shown in Fig. 7 are stacked while being alternately shifted by a predetermined distance in the length direction L. At this time, the plurality of material sheets are stacked so that both ends of the conductive pattern 24 in the width direction W overlap, and the plurality of material sheets are stacked so that material sheets having one side N and another side M overlap each other are included.

[0050] In this embodiment, the plurality of material sheets are stacked one layer at a time so that one side N and the other side M alternately overlap at one end of the conductive pattern 24 in the width direction W. A plurality of outer layer ceramic green sheets 26 are stacked on both sides of the stacked plurality of material sheets in the stacking direction T. That is, the plurality of material sheets are stacked while being alternately rotated 180° in the in-plane direction of one main surface of the inner layer ceramic green sheet 23. As a result, the overlapping region RS and the separation region RC are alternately arranged in the stacking direction T for each material sheet.

[0051] The stacked outer layer ceramic green sheets 26 and the material sheets are thermocompression bonded to produce a mother block. During this process, the conductive pattern 24 located in the overlapping region RS is gently curved in an arc shape toward one side of the stacking direction T. The conductive pattern 24 in contact with the separation region RC is bent so that a portion curved convexly toward one side of the stacking direction T and a portion curved convexly toward the other side of the stacking direction T are continuous in the width direction W, with an inflection point. Because the overlapping region RS and the separation region RC are alternately arranged in the stacking direction T, the arc-shaped portions Y and the bent portions Z are alternately positioned in the stacking direction T, as shown in FIG. 3 . This prevents the arc-shaped portions Y from being stacked excessively continuously in the stacking direction T, and prevents the bent portions Z from being stacked excessively continuously in the stacking direction T, thereby preventing structural defects.

[0052] The mother block is singulated into a plurality of laminate chips using a cutting blade or the like. The laminate chips are heated to sinter the ceramic material, and then barrel polished to form the laminate 110. A conductive paste is applied to each of the first end surface 115 and the second end surface 116 of the laminate 110 to form a metal layer, which is then baked. The baked metal layer is then plated with Ni and then Sn, thereby forming the first external electrode 120 and the second external electrode 130.

[0053] The multilayer ceramic capacitor 100 according to this embodiment can be manufactured through the series of steps described above.

[0054] In the multilayer ceramic capacitor 100 according to this embodiment, in a cross section along the stacking direction T and the width direction W at the center of the laminate 110 in the length direction L, each of the multiple internal electrode layers 150 has an arc-shaped portion Y that is curved in an arc shape at one of its two end portions in the width direction W, and a bent portion Z that is bent so as to have at least one inflection point at the other end portion. The multiple internal electrode layers 150 include an A-shaped internal electrode layer 150A in which the arc-shaped portion Y is located at one end portion in the width direction W, and a B-shaped internal electrode layer 150B in which the bent portion Z is located at the one end portion in the width direction W. This makes it possible to suppress the occurrence of structural defects in the multilayer ceramic capacitor 100.

[0055] In the multilayer ceramic capacitor 100 according to this embodiment, among the plurality of internal electrode layers 150, the A-type internal electrode layers 150A and the B-type internal electrode layers 150B are alternately positioned one layer at a time in the lamination direction T. This makes it possible to effectively suppress the occurrence of structural defects in the multilayer ceramic capacitor 100.

[0056] In the multilayer ceramic capacitor 100 according to this embodiment, the maximum deviation D1 in the width direction W of the multiple internal electrode layers 150 is 20 μm or less. This allows the arc-shaped portions Y and the bent portions Z to be stably overlapped in the stacking direction T, thereby preventing structural defects from occurring.

[0057] (Embodiment 2) Hereinafter, a multilayer ceramic capacitor according to a second embodiment of the present invention will be described with reference to the drawings. The multilayer ceramic capacitor according to the second embodiment of the present invention differs from the multilayer ceramic capacitor 100 according to the first embodiment of the present invention in that multiple layers of A-type internal electrode layers 150A and multiple layers of B-type internal electrode layers 150B are alternately stacked, and therefore, description of the same configuration as that of the multilayer ceramic capacitor 100 according to the first embodiment of the present invention will not be repeated.

[0058] Fig. 9 is a cross-sectional view showing a cross section along the stacking direction and width direction at the center in the length direction of the multilayer ceramic capacitor according to the second embodiment of the present invention. As shown in Fig. 9, in the multilayer ceramic capacitor 200 according to the second embodiment of the present invention, in the plurality of internal electrode layers 150, the A-type internal electrode layers 150A and the B-type internal electrode layers 150B are alternately positioned in groups of multiple layers in the stacking direction T. In the example shown in Fig. 9, the A-type internal electrode layers 150A and the B-type internal electrode layers 150B are alternately positioned in groups of five layers in the stacking direction T. This makes it possible to suppress the occurrence of structural defects in the multilayer ceramic capacitor 200.

[0059] In each of the plurality of layers in the plurality of internal electrode layers 150, the maximum deviation D2 in the width direction W is 10 μm or less. In the example shown in Fig. 9, the maximum deviation D2 in the width direction W in the five A-shaped internal electrode layers 150A is 10 μm or less, and the maximum deviation D2 in the width direction W in the five B-shaped internal electrode layers 150B is 10 μm or less. The maximum deviation in the width direction W in the ten internal electrode layers 150, which is a combination of the five A-shaped internal electrode layers 150A and the five B-shaped internal electrode layers 150B, is 20 μm or less. This allows the arc-shaped portion Y and the bent portion Z to be stably overlapped in the stacking direction T, thereby suppressing the occurrence of structural defects.

[0060] FIG. 10 is a diagram showing a state in which outer layer ceramic green sheets and material sheets are laminated in a method for manufacturing a multilayer ceramic capacitor according to Preferred Embodiment 2 of the present invention.

[0061] As shown in Fig. 10, a plurality of material sheets and outer layer ceramic green sheets 26 are stacked. Specifically, the element sheets shown in Fig. 7 are stacked alternately in the length direction L while being shifted by a predetermined distance. At this time, the plurality of material sheets are stacked in multiple layers so that one side N and another side M alternately overlap at one end position of the conductive pattern 24 in the width direction W. In the example shown in Fig. 10, the conductive pattern 24 is stacked in five layers so that one side N and another side M alternately overlap at one end position of the conductive pattern 24 in the width direction W. As a result, the overlapping region RS and the separation region RC are alternately arranged every five material sheets in the stacking direction T.

[0062] In this embodiment, since it is not necessary to rotate the material sheets 180° each time they are stacked, the time required to stack a plurality of material sheets can be reduced compared to the first embodiment.

[0063] In the above-described embodiments, configurations that can be combined may be combined with each other.

[0064] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0065] 23 inner layer ceramic green sheet, 24 conductive pattern, 25 dielectric pattern, 26 outer layer ceramic green sheet, 100, 200 multilayer ceramic capacitor, 110 laminate, 111 first main surface, 112 second main surface, 113 first side surface, 114 second side surface, 115 first end surface, 116 second end surface, 120 first external electrode, 130 second external electrode, 140 dielectric layer, 150 internal electrode layer, 150A A-type internal electrode layer, 150B B-type internal electrode layer, 151 first internal electrode layer, 151C, 152C opposing portion, 151X, 152X lead-out portion, 152 second internal electrode layer, C internal layer portion, D1, D2 maximum displacement, E1 first end margin portion, E2 second end margin portion, L length direction, M other side, N one side, RC Separation region, RS overlap region, S1 first side margin portion, S2 second side margin portion, T stacking direction, W width direction, X1 first outer layer portion, X2 second outer layer portion, Y arc-shaped portion, Z bent portion.

Claims

1. a laminate including a plurality of dielectric layers and a plurality of internal electrode layers stacked along a stacking direction, the laminate including a first main surface and a second main surface opposing each other in the stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to both the stacking direction and the width direction; an external electrode provided on each of the first end surface and the second end surface and connected to the plurality of internal electrode layers; in a cross section along the stacking direction and the width direction at a central portion of the laminate in the length direction, one of both end portions in the width direction of each of the plurality of internal electrode layers is an arc-shaped portion that is curved in an arc shape, and the other of the both end portions is a bent portion that is bent so as to have at least one inflection point, the plurality of internal electrode layers include an A-type internal electrode layer in which the arc-shaped portion is located at one end in the width direction, and a B-type internal electrode layer in which the bent portion is located at one end in the width direction.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein, in the plurality of internal electrode layers, the A-type internal electrode layers and the B-type internal electrode layers are alternately positioned one layer at a time in the lamination direction.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein, in the plurality of internal electrode layers, the A-type internal electrode layers and the B-type internal electrode layers are alternately positioned in the stacking direction in groups of several layers.

4. 4. The multilayer ceramic capacitor according to claim 1, wherein the maximum amount of misalignment in the width direction of the plurality of internal electrode layers is 20 [mu]m or less.

5. 4. The multilayer ceramic capacitor according to claim 3, wherein the maximum amount of deviation in the width direction in each of the plurality of internal electrode layers is 10 [mu]m or less.

6. providing a plurality of ceramic green sheets; forming a rectangular conductive pattern having two sides along a width direction and two sides along a length direction on one main surface of each of the plurality of ceramic green sheets; forming a dielectric pattern on the one main surface of each of the plurality of ceramic green sheets so as to surround the conductive pattern and to form an overlapping region that overlaps with one of two sides of the conductive pattern along the length direction, and a separation region that is separated in the width direction from the other of the two sides of the conductive pattern along the length direction; and laminating the plurality of ceramic green sheets so that both ends of the conductive pattern in the width direction overlap, while also laminating the plurality of ceramic green sheets so that the one side and the other side overlap each other.

7. 7. The method for manufacturing a multilayer ceramic capacitor according to claim 6, wherein, in stacking the plurality of ceramic green sheets, the plurality of ceramic green sheets are stacked one layer at a time such that the one side and the other side alternately overlap at a position of one end of the conductive pattern in the width direction.

8. 7. The method for manufacturing a multilayer ceramic capacitor according to claim 6, wherein, in stacking the plurality of ceramic green sheets, the plurality of ceramic green sheets are stacked in layers such that the one side and the other side alternately overlap at a position of one end of the conductive pattern in the width direction.

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