Photoelectric conversion device and apparatus

Abstract

To provide a technique by which an image picked up in a temporally preceding frame is hardly affected by picking up an image of a temporally succeeding frame when a moving image is picked up by a global shutter operation.SOLUTION: In a global shutter photoelectric conversion device, in a first pixel, a first charge holding unit is arranged in a first direction with respect to a photoelectric conversion unit, and L1<L2 is satisfied, where L1 is a distance from an optical center of the photoelectric conversion unit to a centroid of the first charge holding unit, and L2 is a distance from the optical center of the photoelectric conversion unit to a centroid of a second charge holding unit. When a distance from the optical center of the photoelectric conversion unit included in a second pixel adjacent to the first pixel in the first direction to the centroid of the first charge holding unit of the first pixel is denoted by L3 and a distance from the optical center of the photoelectric conversion unit included in the second pixel to the centroid of the second charge holding unit of the first pixel is denoted by L4, L3<L4 is satisfied.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] In the field of photoelectric conversion devices such as CMOS image sensors, photoelectric conversion devices with a so-called global shutter function have been proposed. For example, a charge storage unit that temporarily stores signal charge is provided in each pixel, and charge is transferred from the photoelectric conversion unit to the charge storage unit simultaneously in all pixels. By using the global shutter function, the signal accumulation timing in the photoelectric conversion unit can be synchronized for all pixels, thereby suppressing distortion of the subject image even when capturing a fast-moving subject.

[0003] Patent Document 1 proposes a technology for a photoelectric conversion device with a global shutter function that can eliminate periods when signal charge cannot be accumulated between frames, thereby enabling the acquisition of temporally seamless video. In the photoelectric conversion device described in Patent Document 1, two stages of charge storage units are connected to one photoelectric conversion unit. Charges generated in the photoelectric conversion unit during a frame are stored in the charge storage unit at the previous stage during that frame, and at the end of the frame, the signal charges are transferred from the charge storage unit at the previous stage to the charge storage unit at the next stage. The charge storage unit at the next stage is used as a storage unit to hold the transferred signal charges until they are converted into an image signal and output during the next frame. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-172209 Summary of the Invention [Problem to be solved by the invention]

[0005] According to the method described in Patent Document 1, a video can be obtained by capturing consecutive frame images using a so-called global shutter operation. However, when capturing a video of a fast-moving object, for example, a ghost-like image may appear in front of the object's direction of movement. In other words, a type of crosstalk may occur between frames, and capturing an image of a later frame may affect an image of an earlier frame. This is a different phenomenon from the so-called afterimage phenomenon, in which an image of a later frame is affected by an image of a previous frame.

[0006] Therefore, when capturing moving images using the global shutter operation, there is a need for a technology that prevents an image captured in a temporally earlier frame from being affected by capturing an image in a temporally later frame. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided a global shutter type photoelectric conversion device including a plurality of pixels two-dimensionally arranged on a semiconductor substrate, wherein the photoelectric conversion operations of the plurality of pixels are performed in the same period. Each of the plurality of pixels includes a photoelectric conversion unit, a first transfer unit, a first charge holding unit, a second transfer unit, a second charge holding unit, a third transfer unit, and a signal output unit. In each of the plurality of pixels, the charges generated by the photoelectric conversion unit are transferred to the first charge holding unit by the first transfer unit, the charges held in the first charge holding unit are transferred to the second charge holding unit by the second transfer unit, and the charges held in the second charge holding unit are transferred to the signal output unit by the third transfer unit. The plurality of pixels includes a first pixel and a second pixel adjacent to each other in a first direction. In the first pixel, the first charge holding unit is arranged in the first direction with respect to the photoelectric conversion unit. In the first pixel, when the distance from the optical center of the photoelectric conversion unit to the center of gravity of the first charge holding unit is L1 and the distance from the optical center of the photoelectric conversion unit to the center of gravity of the second charge holding unit is L2, the photoelectric conversion unit, the first charge holding unit, and the second charge holding unit are arranged so as to satisfy L1 < L2. When the distance from the optical center of the photoelectric conversion unit of the second pixel to the center of gravity of the first charge holding unit of the first pixel is L3 and the distance from the optical center of the photoelectric conversion unit of the second pixel to the center of gravity of the second charge holding unit of the first pixel is L4, the photoelectric conversion unit of the second pixel, the first charge holding unit of the first pixel, and the second charge holding unit of the first pixel are arranged so as to satisfy L3 < L4. The photoelectric conversion device is characterized by this.

Effects of the Invention

[0008] According to the present invention, it is possible to provide a photoelectric conversion device in which an image captured in a previous frame in time is less likely to be affected by capturing an image in a later frame in time when capturing a moving image in a global shutter operation.

Brief Description of the Drawings

[0009] [Figure 1]FIG. 1 is a block diagram illustrating a schematic configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is an equivalent circuit diagram illustrating the circuit configuration of a pixel included in the photoelectric conversion device according to the first embodiment. [Figure 3] FIG. 4 is a timing chart showing a drive sequence related to the exposure operation of a pixel. [Figure 4] FIG. 4 is a timing chart showing a drive sequence related to a pixel signal readout operation. [Figure 5] FIG. 2 is a plan view illustrating the configuration of a pixel unit formed on a semiconductor substrate of the photoelectric conversion device according to the first embodiment. [Figure 6] FIG. 2 is a plan view illustrating the positional relationship of each element that constitutes a pixel in the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 6 is a cross-sectional view showing a cross section of the pixel portion taken along line AA' in FIG. 5. [Figure 8] FIG. 6 is a cross-sectional view showing a part of a cross section of the pixel portion taken along line BB' in FIG. 5. [Figure 9] 1 is a cross-sectional view showing an embodiment of a back-illuminated image sensor. [Figure 10] FIG. 10 is an equivalent circuit diagram illustrating the circuit configuration of a pixel included in a photoelectric conversion device according to a second embodiment. [Figure 11] FIG. 4 is a timing chart showing a drive sequence related to a pixel signal readout operation. [Figure 12] FIG. 10 is a plan view illustrating the configuration of a pixel unit formed on a semiconductor substrate of a photoelectric conversion device according to a second embodiment. [Figure 13] FIG. 10 is a plan view illustrating the positional relationship of each element that constitutes a pixel in a photoelectric conversion device according to a second embodiment. [Figure 14] 13 is a cross-sectional view showing a cross section of the pixel portion taken along line AA' in FIG. 12. [Figure 15] FIG. 10 is an equivalent circuit diagram illustrating the circuit configuration of a pixel included in a photoelectric conversion device according to a third embodiment. [Figure 16] FIG. 4 is a timing chart showing a drive sequence related to a pixel signal readout operation. [Figure 17]FIG. 10 is a plan view illustrating the configuration of a pixel portion formed on a semiconductor substrate of a photoelectric conversion device according to a third embodiment. [Figure 18] FIG. 10 is a plan view illustrating the positional relationship of each element constituting a pixel in a photoelectric conversion device according to a third embodiment. [Figure 19] FIG. 10 is an equivalent circuit diagram illustrating the circuit configuration of a pixel included in a photoelectric conversion device according to a fourth embodiment. [Figure 20] FIG. 10 is a plan view illustrating the configuration of a pixel portion formed on a semiconductor substrate of a photoelectric conversion device according to a fourth embodiment. [Figure 21] FIG. 10 is a plan view illustrating the positional relationship of each element constituting a pixel in a photoelectric conversion device according to a fourth embodiment. [Figure 22] (a) A schematic diagram for explaining a device according to embodiment 5. (b) A schematic diagram showing an example of a photoelectric conversion system according to embodiment 5. (c) A schematic diagram showing an example of an in-vehicle photoelectric conversion system according to embodiment 5. DETAILED DESCRIPTION OF THE INVENTION

[0010] The inventors have conducted extensive research into the cause of a type of crosstalk occurring between frames in conventional imaging devices, whereby an image of an earlier frame is affected by an image of a later frame being captured, and have come to the following conclusions.

[0011] In conventional imaging devices, two-stage charge storage units are connected in series to the photoelectric conversion unit of each pixel. While the photoelectric conversion unit and the first-stage charge storage unit are used to acquire a photoelectric conversion signal for the current frame, the second-stage charge storage unit stores the signal charge acquired in the previous frame. During the capture of the current frame, a portion of the light incident on the photoelectric conversion unit of the pixel itself or an adjacent pixel may leak from the photoelectric conversion unit due to diffraction, propagate through the semiconductor, and reach the second-stage charge storage unit, where it may generate photocharge. This results in a type of crosstalk between frames, as a portion of the photocharge for the current frame that should not have been added is added to the signal charge acquired in the previous frame. Based on this knowledge, the inventors have created a structure that makes it difficult for light incident on the photoelectric conversion unit of the pixel itself or an adjacent pixel to reach the second-stage charge storage unit.

[0012] A photoelectric conversion device according to an embodiment of the present invention will be described with reference to the drawings. Note that the embodiment shown below is merely an example, and those skilled in the art can appropriately modify and implement the detailed configuration without departing from the spirit and scope of the present invention.

[0013] In the drawings referred to in the following description of the embodiments, elements denoted by the same reference numerals have the same functions unless otherwise specified. When a plurality of identical elements are arranged in a drawing, the reference numerals and their descriptions may be omitted.

[0014] Furthermore, since the drawings may be represented schematically for the convenience of illustration and explanation, the shapes, sizes, arrangements, etc. of elements depicted in the drawings may not strictly correspond to the actual objects. In the following explanation, the photoelectric conversion device viewed from a direction perpendicular to the main surface of the semiconductor layer may be referred to as a planar view.

[0015] [Embodiment 1] A photoelectric conversion device according to embodiment 1 will be described with reference to the drawings. First, the schematic configuration of the photoelectric conversion device, the circuit configuration of the pixel, and the driving method will be described, and then the configuration of the pixel unit formed on the semiconductor substrate will be described.

[0016] (Schematic configuration of photoelectric conversion device) 1 is a block diagram illustrating a schematic configuration of a photoelectric conversion device 1 according to this embodiment. The photoelectric conversion device 1 has a pixel section 10, a vertical scanning circuit 20, a readout circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a control circuit 60. The pixel section 10 is connected to the vertical scanning circuit 20 and the readout circuit 30. The readout circuit 30 is connected to the horizontal scanning circuit 40 and the output circuit 50. The control circuit 60 is connected to the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40.

[0017] The pixel section 10 has a plurality of pixels 12 arranged in a matrix having a plurality of rows and a plurality of columns. Each of the plurality of pixels 12 includes a photoelectric conversion unit formed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel section 10 is not particularly limited. Note that the pixel section 10 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output a signal, and the like, in addition to effective pixels that output pixel signals corresponding to the amount of incident light.

[0018] Each row of the pixel section 10 is provided with a plurality of control lines 14 extending along the row direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to a pixel 12 arranged in the row direction and serves as a control signal line common to these pixels 12. The row direction in which the control lines 14 extend is sometimes referred to as the horizontal direction. Although the control line 14 for each row is shown as a single line in FIG. 1, each row may include multiple control signal lines. The control line 14 is connected to a vertical scanning circuit 20 and transmits control signals output by the vertical scanning circuit 20 to the pixels 12. On a semiconductor substrate, the direction in which the pixels commonly interconnected by the control lines 14 are arranged (row direction, horizontal direction) is sometimes referred to as the first direction DIR1. As indicated by the arrows pointing in both directions in FIG. 1, the "first direction DIR1" may refer to either the leftward or rightward direction.

[0019] Each column of the pixel section 10 is provided with a plurality of vertical output lines 16 extending along a column direction (vertical direction in FIG. 1 ) intersecting the row direction. Each vertical output line 16 is connected to pixels 12 aligned in the column direction and serves as a common signal line for the pixels 12 aligned in the column direction. The column direction in which the vertical output lines 16 extend is sometimes referred to as the vertical direction. The vertical output lines 16 are connected to a readout circuit 30 and transmit pixel signals output by the pixels 12 to the readout circuit 30. On the semiconductor substrate, the direction in which the pixels commonly wired by the vertical output lines 16 are aligned (column direction, vertical direction) is sometimes referred to as a second direction DIR2.

[0020] The vertical scanning circuit 20 is a control circuit that receives control signals from the control circuit 60, generates control signals for driving the pixels 12, and outputs the control signals to the pixels 12 via control lines 14. The vertical scanning circuit 20 may include logic circuits such as a shift register and an address decoder. When reading out signals from the pixel unit 10, the vertical scanning circuit 20 outputs control signals to the control lines 14 for each row, thereby sequentially driving the pixels 12 of the pixel unit 10 row by row. The signals read out from the pixels 12 row by row are input to the readout circuit 30 via vertical output lines 16 arranged in each column of the pixel unit 10.

[0021] The readout circuit 30 has a function of performing predetermined processing, such as amplification and addition, on signals read out from the pixels 12. The readout circuit 30 may include a signal holding unit, a column amplifier, a correlated double sampling (CDS) circuit, an addition circuit, etc. The readout circuit 30 may further include other processing circuits, such as an A / D (analog / digital) conversion circuit, as necessary.

[0022] The horizontal scanning circuit 40 is a control circuit that receives a control signal from the control circuit 60, generates a control signal for transferring the signals processed by the readout circuit 30 to the output circuit 50 sequentially for each column, and outputs the control signal to the readout circuit 30. The horizontal scanning circuit 40 may include logic circuits such as a shift register and an address decoder.

[0023] The output circuit 50 is a circuit section configured with a buffer amplifier, a differential amplifier, etc., and amplifies and outputs the signal output from the readout circuit 30 whose column is selected by the horizontal scanning circuit 40. The output circuit 50 may further include a signal processing section that performs predetermined signal processing on the pixel signal, such as correction processing or HDR synthesis processing.

[0024] The control circuit 60 has a function of supplying control signals for controlling the operations and timings of the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40. Note that at least some of the control signals supplied to the vertical scanning circuit 20, the readout circuit 30, and the horizontal scanning circuit 40 may be supplied from outside the photoelectric conversion device 1.

[0025] (Pixel circuit configuration) 2 is an equivalent circuit diagram illustrating the circuit configuration of a pixel 12 included in the photoelectric conversion device 1 according to this embodiment. Each pixel 12 includes a photoelectric conversion unit PD, a transfer transistor M1 (first transfer unit), a transfer transistor M2 (second transfer unit), a transfer transistor M3 (third transfer unit), a charge holding unit MEM1 (first charge holding unit), and a charge holding unit MEM2 (second charge holding unit). Each pixel 12 also includes an amplification transistor M4, a selection transistor M5, a charge discharging transistor M6, and a reset transistor M7.

[0026] The photoelectric conversion unit PD may be configured with a photoelectric conversion element, such as a photodiode. When electrons are used as signal charges, each transistor may be configured with an N-type MOS transistor. Note that each transistor does not necessarily have to be an N-type MOS transistor, and each transistor may be configured with a P-type MOS transistor and use holes as signal charges.

[0027] The photoelectric conversion unit PD has an anode connected to a ground node and a cathode connected to the sources of the transfer transistor M1 and the charge discharging transistor M6. The drain of the transfer transistor M1 is connected to the source of the transfer transistor M2. The connection node between the drain of the transfer transistor M1 and the source of the transfer transistor M2 includes a capacitance component and functions as a first charge holding unit (charge holding unit MEM1). The drain of the transfer transistor M2 is connected to the source of the transfer transistor M3. The connection node between the drain of the transfer transistor M2 and the source of the transfer transistor M3 includes a capacitance component and functions as a second charge holding unit (charge holding unit MEM2).

[0028] The drain of the transfer transistor M3 is connected to the source of the reset transistor M7 and the gate of the amplification transistor M4. The connection node between the drain of the transfer transistor M3, the source of the reset transistor M7, and the gate of the amplification transistor M4 is a floating diffusion portion FD, which serves as a so-called floating diffusion portion. The floating diffusion portion FD includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion.

[0029] The drain of the reset transistor M7, the drain of the amplifying transistor M4, and the drain of the charge discharging transistor M6 are connected to a power supply voltage line (voltage VDD). Note that any two or three of the voltages supplied to the drain of the reset transistor M7, the voltage supplied to the drain of the amplifying transistor M4, and the voltage supplied to the drain of the charge discharging transistor M6 may be the same, or all of them may be different. The source of the amplifying transistor M4 is connected to the drain of the selection transistor M5. The source of the selection transistor M5 is connected to the vertical output line 16.

[0030] Each of the control lines 14 (FIG. 1) includes six signal lines connected to the gates of the transfer transistor M1, transfer transistor M2, transfer transistor M3, reset transistor M7, selection transistor M5, and charge discharging transistor M6. A control signal GS1 (FIG. 3) is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1. A control signal GS2 (FIG. 3) is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M2. A control signal TX (FIG. 4) is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3. A control signal RES (FIG. 4) is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M7. A control signal SEL (FIG. 4) is output from the vertical scanning circuit 20 to the signal line connected to the gate of the selection transistor M5. A control signal OFG (FIG. 3) is output from the vertical scanning circuit 20 to the signal line connected to the gate of the charge discharging transistor M6.

[0031] When each transistor is an N-type transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical scanning circuit 20, and the corresponding transistor turns off when a low-level control signal is supplied from the vertical scanning circuit 20. However, the conductivity types of the transistors described in the embodiments are merely examples and are not limited to the conductivity types described in the embodiments. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistor can be changed as appropriate in accordance with this change. For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate can be reversed relative to the description in the embodiments in accordance with the change in conductivity type.

[0032] The photoelectric conversion unit PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. The transfer transistor M1 functions as a transfer unit that performs a transfer operation of transferring the electric charge held in the photoelectric conversion unit PD to the charge holding unit MEM1 when turned on. The transfer transistor M2 functions as a transfer unit that performs a transfer operation of transferring the electric charge held in the charge holding unit MEM1 to the charge holding unit MEM2 when turned on. The transfer transistor M3 functions as a transfer unit that performs a transfer operation of transferring the electric charge held in the charge holding unit MEM2 to the floating diffusion unit FD when turned on.

[0033] The amplifier transistor M4 has a drain supplied with a voltage VDD and a source supplied with a bias current from a current source (not shown) via the selection transistor M5, constituting an amplifier unit (source follower circuit) with its gate as an input node. This allows the amplifier transistor M4 to output a signal corresponding to the potential of the floating diffusion region FD to the vertical output line 16 via the selection transistor M5. In this sense, the floating diffusion region FD, the amplifier transistor M4, and the selection transistor M5 can be said to constitute a signal output unit that outputs a signal corresponding to the amount of charge held by the floating diffusion region FD to the vertical output line 16.

[0034] The reset transistor M7 functions as a reset unit that performs a reset operation to reset the floating diffusion unit FD to a voltage corresponding to the voltage VDD when it is turned on. The charge drain transistor M6 functions as an overflow drain unit that drains charges held in the photoelectric conversion unit PD when it is turned on. Alternatively, it can be said that the charge drain transistor M6 functions as a reset unit that performs a reset operation to reset the photoelectric conversion unit PD to a voltage corresponding to the voltage VDD when it is turned on. The selection transistor M5 functions as a selection unit that selects whether or not to output a signal corresponding to the source voltage of the amplification transistor M4 to the vertical output line 16 as a pixel signal.

[0035] (Method of driving a photoelectric conversion device) Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 3 and Fig. 4. Fig. 3 is a timing diagram showing a drive sequence related to the exposure operation of pixels, and Fig. 4 is a timing diagram showing a drive sequence related to the readout operation of pixel signals.

[0036] 3 shows the time variations of a control signal GS1 supplied to the transfer transistor M1, a control signal GS2 supplied to the transfer transistor M2, and a control signal OFG supplied to the charge discharging transistor M6. When each control signal is at a high level, the corresponding transistor is active (on). In this embodiment, since a global shutter driving method is used, the driving timing related to the exposure operation of the pixels 12 is the same for the pixels 12 in all rows. That is, the photoelectric conversion device includes a plurality of pixels arranged two-dimensionally on a semiconductor substrate, performs photoelectric conversion operations for the plurality of pixels in the same period, and sequentially outputs signals for each pixel group (row) arranged along a first direction.

[0037] While Figure 4 shows the readout operation of pixel signals for one frame (the Nth frame), in this embodiment, the same sequence is repeatedly used for each frame to capture a moving image. Note that one frame can be the period required to obtain one image. Furthermore, one frame period, which is the period required to obtain one frame of signals, can be the period from when the signals of a certain pixel row are read out until the signals of that row are read out again. Furthermore, when the vertical scanning circuit is controlled by a vertical synchronization signal, one frame period can also be the period from when the vertical synchronization signal becomes active until it becomes active again.

[0038] In this embodiment, in each frame, the signal charge accumulation operation is executed multiple times (K times) for the accumulation period T. The accumulation period T is a period for accumulating the signal charge in the charge holding unit MEM1. Hereinafter, the i-th accumulation period T i From the Kth accumulation period T KThe operations up to this point will be described with reference to Fig. 3. Here, i is an integer between 1 and K-1. The number of times K can be set to an appropriate number depending on the total accumulation time within one frame period, etc.

[0039] At time t01, the vertical scanning circuit 20 changes the control signal OFG from low to high, which turns on the charge discharging transistor M6 and resets the photoelectric conversion unit PD to a potential corresponding to the voltage VDD.

[0040] At time t02, the vertical scanning circuit 20 changes the control signal OFG from high to low. This turns off the charge discharging transistor M6, and the reset state of the photoelectric conversion unit PD is released. That is, the timing at which the control signal OFG changes from high to low coincides with the accumulation period T i The signal charge generated when a photon is incident on the photoelectric conversion unit PD while the charge discharging transistor M6 is off is accumulated in the photoelectric conversion unit PD.

[0041] During the period from a predetermined timing after time t02 to time t03, the vertical scanning circuit 20 controls the control signal GS1 to a high level. This turns on the transfer transistor M1, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM1. The time t03 at which the transfer transistor M1 turns off is the end of the accumulation period T i That is, the period from time t02 to time t03 is the end time of the signal charge accumulation period T i is.

[0042] Next, the same operation as in the accumulation period from time t01 to time t03 is repeated. For example, as shown in FIG. 3, the accumulation period T i+1 An operation corresponding to the accumulation period T K An operation corresponding to the above is performed.

[0043] In this way, the accumulation period T is executed K times in each frame. As a result, the charge holding unit MEM1 is charged from the accumulation period T1 to the accumulation period T K The signal charge generated in the photoelectric conversion unit PD is held during an accumulation period Ttotal having a length equal to the total length of the K periods up to .

[0044] The signal charges stored in the charge storage unit MEM1 can be transferred to the charge storage unit MEM2 after the readout of the pixel signals based on the signal charges of the (N-1)th frame stored in the charge storage unit MEM2 is completed. Here, it is assumed that the readout of the pixel signals based on the signal charges of the (N-1)th frame stored in the charge storage unit MEM2 is completed by time t10.

[0045] After that, for a predetermined period from time t10, the vertical scanning circuit 20 controls the control signal GS2 to a high level, which turns on the transfer transistor M2 and transfers the signal charge stored in the charge holding unit MEM1 to the charge holding unit MEM2.

[0046] When the charge transfer from the charge storage unit MEM1 to the charge storage unit MEM2 is completed, the charge storage unit MEM1 becomes empty, which makes it possible to store signal charges for the next frame, i.e., the (N+1)th frame, in the charge storage unit MEM1.

[0047] FIG. 4 shows the time variations of the control signal TX supplied to the transfer transistor M3, the control signal SEL supplied to the selection transistor M5, and the control signal RES supplied to the reset transistor M7. When each control signal is at a high level, the corresponding transistor is active (on state). Here, the pixel signal readout operation is performed sequentially for each row. Of the control signals corresponding to each of the multiple rows constituting the pixel unit 10, FIG. 4 shows the control signal supplied to the pixel 12 in the nth row and the control signal supplied to the pixel 12 in the (n+1)th row. The control signal supplied to the pixel 12 in the nth row is marked with (n), and the control signal supplied to the pixel 12 in the (n+1)th row is marked with (n+1).

[0048] In each frame, signals based on the signal charges accumulated in the charge storage units MEM2 of the pixels 12 in each row are read out sequentially for each row. At the start time of the Nth frame, the signal charges accumulated during the accumulation period T of the (N-1)th frame are stored in the charge storage units MEM2 of each pixel 12. Just before time t11, the control signal TX(n) and the control signal SEL(n) are at low level, and the control signal RES(n) is at high level.

[0049] At time t11, the vertical scanning circuit 20 switches the potential of the control signal SEL(n) from low to high. This turns on the selection transistor M5 of the pixel 12 in the nth row, and the amplification transistor M4 of the pixel 12 in each column in the nth row is connected to the vertical output line 16 of the corresponding column via the selection transistor M5. That is, the pixel in the nth row is in a selected state in which signals can be read out. At this time, the reset transistor M7 is on, and the floating diffusion FD is reset to a potential corresponding to the voltage VDD. As a result, a signal corresponding to the reset potential of the floating diffusion FD is output to the vertical output line 16.

[0050] At the next time t12, the vertical scanning circuit 20 switches the potential of the control signal RES(n) from high to low. This turns off the reset transistor M7, and the reset state of the floating diffusion FD is released. The voltage of the vertical output line 16 that stabilizes after the reset transistor M7 is turned off is the reset level voltage VRES of the pixel 12. In this way, the reset level voltage VRES of the pixel 12 is read out to the vertical output line 16.

[0051] During the subsequent period from time t13 to time t14, the vertical scanning circuit 20 switches the potential of the control signal TX(n) from low to high. This turns on the transfer transistor M3 of the pixel 12 in the nth row, and the signal charge held in the charge holding unit MEM2 is transferred to the floating diffusion unit FD. The potential of the floating diffusion unit FD then becomes a potential corresponding to the amount of signal charge transferred from the charge holding unit MEM2, and a voltage corresponding to the potential of the floating diffusion unit FD is output to the vertical output line 16. The voltage of the vertical output line 16 that stabilizes after the transfer transistor M3 is turned off at time t14 is the signal level voltage VSIG of the pixel 12. In this way, the signal level voltage VSIG of the pixel 12, based on the signal charge held in the charge holding unit MEM2, is read out to the vertical output line 16.

[0052] The difference between the reset level voltage VRES and the signal level voltage VSIG obtained in this way, i.e., |VSIG-VRES|, is a physical quantity corresponding to the amount of signal charge held in the charge holding unit MEM2 (correlated double sampling).

[0053] At the next time t15, the vertical scanning circuit 20 switches the potential of the control signal RES(n) from low to high. This turns on the reset transistor M7 of the pixel 12 in the nth row, resetting the floating diffusion FD to a potential corresponding to the voltage VDD. A signal corresponding to the reset potential of the floating diffusion FD is output to the vertical output line 16.

[0054] At subsequent time t16, the vertical scanning circuit 20 switches the potential of the control signal SEL(n) from high to low, thereby turning off the selection transistors M5 of the pixels 12 in the nth row and deselecting the nth row.

[0055] Furthermore, during the period from time t16 to time t17, similar to the period from time t11 to time t16, signals based on the signal charges stored in the charge holding units MEM2 are read out from the pixels 12 in the (n+1)th row. The same is true for the readout operations from the pixels 12 in the other rows.

[0056] In this embodiment, the accumulation operation is performed by dividing the accumulation period Ttotal into K accumulation periods T. Configuring the accumulation periods in this manner prevents the time domain for acquiring signal charges from becoming uneven within a frame and allows the signal charges to be dispersed within the frame. This makes it possible to reduce image jitter and discontinuity between frames during video capture, compared to when the accumulation period Ttotal is performed in a single continuous period. This can achieve a significant improvement in image quality, particularly when capturing an object moving at high speed within the screen or a flashing light source.

[0057] Furthermore, the pixel 12 of the photoelectric conversion device of this embodiment includes a charge storage section that stores signal charge in addition to a charge storage section that stores signal charge from the previous frame. Therefore, signals can be read even during signal charge storage, reducing the time period during each frame during which signal charge cannot be acquired, enabling seamless video capture. Thus, the driving method for the photoelectric conversion device of this embodiment allows high-quality video to be continuously captured.

[0058] (Pixel configuration) FIG. 5 is a plan view illustrating the configuration of a pixel unit formed on a semiconductor substrate in a photoelectric conversion device according to this embodiment. The semiconductor active region, gate electrodes, and connection holes arranged in the active region are illustrated as viewed in a plan view perpendicular to the main surface of the semiconductor substrate. FIG. 5 illustrates a 2-row, 3-column portion of a pixel unit 10 in which a large number of pixels are arranged in a matrix. As illustrated, the pixels are arranged in a two-dimensional array with translational symmetry, and adjacent pixels have the same configuration and function. While FIG. 5 illustrates an example in which a single pixel is arranged translationally symmetrically, a configuration in which multiple pixels are arranged translationally symmetrically as a unit may also be used.

[0059] Fig. 7 is a cross-sectional view showing a cross section of the pixel unit 10 taken along line A-A' in Fig. 5. Each pixel has a microlens 100, a color filter 101, a wiring layer 102, and a semiconductor layer 105. A photoelectric conversion unit PD and a charge holding unit MEM are formed in the semiconductor layer 105.

[0060] The microlens 100 focuses incident light toward the optical center 103 in the photoelectric conversion unit PD, contributing to improved sensitivity. The color filter 101 discriminates light incident on the photoelectric conversion unit PD according to its wavelength, allowing color information to be imparted to the image signal. The wiring layer 102 uses conductors such as aluminum or copper as wiring, and signal wiring such as control lines 14 and vertical output lines 16 is arranged therein. The metal wiring is electrically isolated by an insulating film such as SiO. As shown in FIG. 7 , a waveguide 104 may be provided between the color filter 101 and the photoelectric conversion unit PD. The waveguide 104 is configured to have a refractive index different from that of the adjacent wiring layer 102, preventing light incident through the microlens 100 from leaking into the wiring layer 102 and improving the light-focusing efficiency on the photoelectric conversion unit PD.

[0061] Fig. 8 is a cross-sectional view showing a part of a cross section of the pixel unit 10 taken along line B-B' in Fig. 5. A P-type semiconductor region 201, an N-type semiconductor region 202, an N-type semiconductor region 203, and a P-type semiconductor region 204 are arranged on an N-type semiconductor substrate 200. The photoelectric conversion unit PD includes the P-type semiconductor region 201, the N-type semiconductor region 202, the N-type semiconductor region 203, and the P-type semiconductor region 204, and forms a so-called buried photodiode.

[0062] Electrons photoelectrically converted in the N-type semiconductor region 202 and the N-type semiconductor region 203 are accumulated in the N-type semiconductor region 203. When the transfer transistor M1 is turned on, the accumulated electrons pass through a channel 301 of the transfer transistor M1 and reach the N-type semiconductor region 205 that constitutes the charge storage unit MEM1. The channel 301 is controlled by a gate 302 of the transfer transistor M1 that is arranged above the channel 301 via an insulating film.

[0063] When the transfer transistor M2 is turned on, the electrons held in the N-type semiconductor region 205 constituting the charge holding unit MEM1 move through the channel 303 of the transfer transistor M2 and reach the N-type semiconductor region 206 constituting the charge holding unit MEM2. The channel 303 is controlled by the gate 304 of the transfer transistor M2, which is arranged above the channel 303 via an insulating film.

[0064] When the transfer transistor M3 is turned on, the electrons held in the N-type semiconductor region 206 constituting the charge holding unit MEM2 move through the channel 305 of the transfer transistor M3 and reach the N-type semiconductor region 207 constituting the FD. The channel 305 is controlled by the gate 306 of the transfer transistor M3, which is arranged above the channel 305 via an insulating film.

[0065] The P-type semiconductor region 208 separates the N-type semiconductor region 202 from the N-type semiconductor region 205, the N-type semiconductor region 206, the N-type semiconductor region 207, etc., to prevent charges from mixing with each other.

[0066] 8, the gate 302 of the transfer transistor M1 may be arranged to overlap the N-type semiconductor region 205 that constitutes the charge holding unit MEM1 in plan view. This allows the potential of the charge holding unit MEM1 to be raised when the transfer transistor M1 is turned on, that is, when charges are transferred from the photoelectric conversion unit PD to the charge holding unit MEM1, making it easier to completely transfer the charges to the charge holding unit MEM1.

[0067] 8, the gate 304 of the transfer transistor M2 may be disposed so as to overlap with the N-type semiconductor region 206 that constitutes the charge holding unit MEM2 in plan view. This makes it possible to raise the potential of the charge holding unit MEM2 when the transfer transistor M2 is turned on, that is, when charge is transferred from the charge holding unit MEM1 to the charge holding unit MEM2, making it easier to completely transfer charge to the charge holding unit MEM2.

[0068] FIG. 6 is a diagram for explaining the positional relationship of each element constituting a pixel, and is a plan view in which reference numerals and the like are omitted from FIG. 5 and dimension lines and the like are added. The direction in which pixels commonly wired by control lines 14 in FIG. 1 are arranged (row direction, horizontal direction) is shown as a first direction DIR1 in FIG. 6. As indicated by the arrows pointing in both directions in FIG. 6, the "first direction DIR1" can refer to either the left or right direction. Also, the direction in which pixels commonly wired by vertical output lines 16 in FIG. 1 are arranged (column direction, vertical direction) is shown as a second direction DIR2 in FIG. 6. Unlike the configuration shown in FIG. 6, the direction in which pixels commonly wired by control lines 14 in FIG. 1 are arranged (row direction, horizontal direction) may be the second direction DIR2, and the direction in which pixels commonly wired by vertical output lines 16 in FIG. 1 are arranged (column direction, vertical direction) may be the first direction DIR1. In the following explanation, attention will be focused on pixel PIX1 enclosed by a dotted line, but the same can be said for the other pixels since each pixel is arranged translationally symmetrically.

[0069] The optical center of the photoelectric conversion unit PD of pixel PIX1 is defined as optical center 103, the position of the center of gravity of charge holding unit MEM1 (first charge holding unit) in a planar view is defined as center of gravity position MEM1-G, and the position of the center of gravity of charge holding unit MEM2 (second charge holding unit) in a planar view is defined as center of gravity position MEM2-G. Also, the optical center of the photoelectric conversion unit PD of a pixel (second pixel) adjacent to pixel PIX1 (first pixel) in a first direction DIR1 (left direction in FIG. 6) is defined as optical center 110.

[0070] In pixel PIX1, the charge holding unit MEM1 is arranged in a first direction DIR1 (leftward in FIG. 6) relative to the photoelectric conversion unit PD. Here, "arranged in the first direction DIR1" means that at least a part of the charge holding unit MEM1 and at least a part of the photoelectric conversion unit PD are arranged adjacent to each other in the first direction DIR1. Alternatively, it means that any line parallel to the first direction DIR1 intersects both at least a part of the charge holding unit MEM1 and at least a part of the photoelectric conversion unit PD.

[0071] In the present embodiment, when the distance between the optical center 103 and the center-of-gravity position MEM1-G in a plan view is defined as L1, and the distance between the optical center 103 and the center-of-gravity position MEM2-G is defined as L2, it is configured such that L1 < L2. Further, when the distance between the optical center 110 of adjacent pixels and the center-of-gravity position MEM1-G in a plan view is defined as L3, and the distance between the optical center 110 of adjacent pixels and the center-of-gravity position MEM2-G is defined as L4, it is configured such that L3 < L4.

[0072] As already described, the charge holding unit MEM1 is used to hold the signal charge generated by the photoelectric conversion unit PD during the period of the Nth frame only for the duration of the Nth frame. Further, the charge holding unit MEM2 is used to hold the signal charge of the (N - 1)th frame until the signal charge acquired in the previous frame, i.e., the (N - 1)th frame, is transferred to the floating diffusion section FD and read out through the amplification transistor M4 while the Nth frame is being captured.

[0073] For example, consider the case where strong light is incident on pixel PIX1 during the period of the Nth frame as compared to the (N - 1)th frame. A part of the strong light incident on the photoelectric conversion unit PD of pixel PIX1 may diffract in the semiconductor and leak out as stray light outside the photoelectric conversion unit PD. If such stray light is likely to reach the charge holding unit MEM2, then photocharge due to the stray light is generated in the charge holding unit MEM2 and superimposed on the signal charge of the previous frame that was being held. That is, since a part of the photocharge of the current frame that should not have been added is added to the signal charge acquired in the previous frame held by the charge holding unit MEM2, a kind of crosstalk occurs between frames.

[0074] Alternatively, when strong light is incident on pixels adjacent to pixel PIX1 in the first direction DIR1 during the period of the Nth frame, part of the strong light incident on the photoelectric conversion part PD of the adjacent pixels may diffract in the semiconductor and leak out as stray light outside the photoelectric conversion part PD. If such stray light is likely to reach the charge holding part MEM2 of pixel PIX1, then photocharge due to the stray light is generated in the charge holding part MEM2 and is superimposed on the signal charge of the previous frame that was being held. That is, since a part of the photocharge of the adjacent pixels in the current frame, which should not have been added, is added to the signal charge acquired in the previous frame held by the charge holding part MEM2, a kind of crosstalk occurs between frames.

[0075] Although stray light exponentially decays in the semiconductor according to the distance it travels, according to this embodiment, since it is configured such that L1 < L2, the stray light leaking from the photoelectric conversion part PD of pixel PIX1 is unlikely to reach the charge holding part MEM2. Furthermore, according to this embodiment, since it is configured such that L3 < L4, the stray light leaking from the photoelectric conversion part PD of the pixels adjacent in the first direction DIR1 is unlikely to reach the charge holding part MEM2 of pixel PIX1.

[0076] Therefore, according to the photoelectric conversion device according to this embodiment, when capturing a moving image in global shutter operation, the image of the frame that is temporally previous is less likely to be affected by the image of the frame that is temporally subsequent when capturing the image, and thus a high-quality moving image can be acquired.

[0077] Note that in FIG. 7, an example of a so-called surface incidence type image sensor is shown, but the embodiment is not limited to this. For example, a back-illuminated type image sensor as shown in the cross-section in FIG. 9 may also be used. In the example of FIG. 7, the wiring layer 102 is disposed between the microlens 100 and the photoelectric conversion part PD, but the wiring layer may be disposed on the side opposite to the microlens across the semiconductor layer 105 including the photoelectric conversion part PD as in the example of FIG. 9.

[0078] In the case of the form illustrated in FIG. 7, the waveguide 104 serving as the light incident path is arranged in the region adjacent to the wiring layer 102, which has been a constraint on the space for arranging the wiring layer 102. In the example of FIG. 9, since the wiring layer 102 is arranged on the side opposite to the microlens, the space constraint is eliminated and the degree of freedom in the wiring layout is improved. There is an effect that the functions can be improved by increasing the number of drive lines and signal lines, or the characteristics can be improved by reducing the parasitic capacitance between the wirings.

[0079] A light-shielding portion 106 formed of, for example, metal may be provided in the semiconductor substrate 107. The light-shielding portion 106 is arranged so as to surround at least a part of the periphery of the charge holding portion MEM1 and / or the charge holding portion MEM2, and suppresses the incident light from becoming stray light and entering the charge holding portion.

[0080] Also, as shown in FIG. 9, a stacked sensor in which a first semiconductor substrate 107 including a photoelectric conversion portion PD and a microlens 100 and a second semiconductor substrate 108 are stacked may be used. A circuit is also arranged on the second semiconductor substrate 108, and the circuit density per area can be improved, so that the functions can be improved or the chip area can be reduced. The wiring layer 109 in the second semiconductor substrate 108 is electrically connected to the wiring layer 102 in the first semiconductor substrate and constitutes an electronic circuit.

[0081] Even in such a back-illuminated image sensor, according to the present embodiment, since it is configured such that L1 < L2, the stray light leaking from the photoelectric conversion portion PD of the pixel PIX1 is less likely to reach the charge holding portion MEM2. Further, according to the present embodiment, since it is configured such that L3 < L4, the stray light leaking from the photoelectric conversion portions PD of the adjacent pixels in the first direction DIR1 is less likely to reach the charge holding portion MEM2 of the pixel PIX1. Therefore, when capturing a moving image in the global shutter operation, the image of the previous frame in time is less likely to be affected by the image of the subsequent frame in time, and thus a high-quality moving image can be acquired.

[0082] [Embodiment 2] A photoelectric conversion device according to embodiment 2 will be described with reference to the drawings. Explanations of matters common to embodiment 1 will be simplified or omitted. The schematic configuration of the photoelectric conversion device is the same as embodiment 1 described with reference to FIG. 1. Regarding embodiment 2, the circuit configuration of the pixel and the driving method will be described first, and then the configuration of the pixel unit formed on the semiconductor substrate will be described.

[0083] (Pixel circuit configuration) 10 is an equivalent circuit diagram illustrating the circuit configuration of a pixel 12 included in the photoelectric conversion device according to this embodiment. Each pixel 12 included in the photoelectric conversion device according to this embodiment has two circuit blocks, each of which is composed of one photoelectric conversion unit, three transfer transistors, two charge storage units, and one charge exhaust transistor. Each pixel 12 further has a floating diffusion region FD, a reset transistor M7, an amplifier transistor M4, and a selection transistor M5, which are shared by the two circuit blocks.

[0084] The first circuit block is composed of a photoelectric conversion unit PDA (first photoelectric conversion unit), a transfer transistor M1A (first transfer unit), a transfer transistor M2A (second transfer unit), a transfer transistor M3A (third transfer unit), a charge retention unit MEM1A (first charge retention unit), a charge retention unit MEM2A (second charge retention unit), and a charge discharge transistor M6. The second circuit block is composed of a photoelectric conversion unit PDB (second photoelectric conversion unit), a transfer transistor M1B (fourth transfer unit), a transfer transistor M2B (fifth transfer unit), a transfer transistor M3B (sixth transfer unit), a charge retention unit MEM1B (third charge retention unit), a charge retention unit MEM2B (fourth charge retention unit), and a charge discharge transistor M6.

[0085] The control lines 14 connected from the vertical scanning circuit 20 (FIG. 1) to each pixel include a total of seven signal lines per pixel. A control signal GS1 (FIG. 3) is output from the vertical scanning circuit 20 to the gates of the transfer transistors M1A and M1B, and a control signal GS2 (FIG. 3) is output to the gates of the transfer transistors M2A and M2B. A control signal OFG (FIG. 3) is output to the gates of the two charge discharging transistors M6. A control signal TXA (described later with reference to FIG. 11) is output from the vertical scanning circuit 20 to the gate of the transfer transistor M3A, and a control signal TXB is output from the vertical scanning circuit 20 to the gate of the transfer transistor M3B. When each transistor is an N-type transistor, a high-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor on, and a low-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor off.

[0086] The photoelectric conversion units PDA and PDB convert incident light into charges (photoelectric conversion) in an amount corresponding to the amount of light and store the generated charges. The transfer transistor M1A functions as a transfer unit that performs a transfer operation of transferring charges held by the photoelectric conversion unit PDA to the charge holding unit MEM1A when turned on. The transfer transistor M1B functions as a transfer unit that performs a transfer operation of transferring charges held by the photoelectric conversion unit PDB to the charge holding unit MEM1B when turned on. The transfer transistor M2A functions as a transfer unit that performs a transfer operation of transferring charges held by the charge holding unit MEM1A to the charge holding unit MEM2A when turned on. The transfer transistor M2B functions as a transfer unit that performs a transfer operation of transferring charges held by the charge holding unit MEM1B to the charge holding unit MEM2B when turned on. The transfer transistor M3A functions as a transfer unit that performs a transfer operation of transferring charges held by the charge holding unit MEM2A to the floating diffusion unit FD when turned on. The transfer transistor M3B functions as a transfer unit that, when turned on, transfers the charge held in the charge holding unit MEM2B to the floating diffusion unit FD. The functions and operations of the reset transistor M7, the amplification transistor M4, the selection transistor M5, and the charge discharging transistor M6 are the same as those in the first embodiment.

[0087] (Method of driving a photoelectric conversion device) Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 11. Fig. 11 is a timing chart showing driving related to the signal readout operation of the pixel.

[0088] 11 shows a control signal TXA supplied to the transfer transistor M3A, a control signal TXB supplied to the transfer transistor M3B, a control signal SEL supplied to the selection transistor M5, and a control signal RES supplied to the reset transistor M7. The readout operation of pixel signals from the multiple rows constituting the pixel unit 10 is performed row by row, and FIG. 11 shows control signals supplied to the pixels 12 in the nth row and the (n+1)th row. The control signals supplied to the pixels 12 in the nth row are denoted by (n) and the control signals supplied to the pixels 12 in the (n+1)th row are denoted by (n+1). When each control signal is at a high level, the corresponding transistor is active (on).

[0089] In each frame, signals are read out sequentially row by row to the vertical output lines 16 based on the signal charges accumulated in the charge holding units MEM2A and MEM2B of the pixels 12 in each row. At the start time of the Nth frame, the charge holding units MEM2A and MEM2B of each pixel 12 each hold the signal charges accumulated during the accumulation period T of the (N-1)th frame.

[0090] Immediately before time t21, the control signals TXA(n), TXB(n), and SEL(n) are at low level, and the control signal RES(n) is at high level.

[0091] At time t21, the vertical scanning circuit 20 changes the control signal SEL(n) from low to high. This turns on the selection transistor M5 of the pixel 12 in the nth row, connecting the amplification transistor M4 to the vertical output line 16 of the corresponding column via the selection transistor M5 of the pixel 12 in each column in the nth row, and setting the pixel to a selected state in which pixel signals can be read out. At this time, the reset transistor M7 is on, and the floating diffusion FD is reset to a potential corresponding to the voltage VDD. As a result, a signal corresponding to the reset potential of the floating diffusion FD is output to the vertical output line 16.

[0092] At the next time t22, the vertical scanning circuit 20 changes the control signal RES(n) from high to low. This turns off the reset transistor M7, and the reset state of the floating diffusion FD is released. The voltage of the vertical output line 16 that stabilizes after the reset transistor M7 is turned off is the reset level voltage VRES of the pixel 12. In this way, the reset level voltage VRES of the pixel 12 is read out to the vertical output line 16.

[0093] During the subsequent period from time t23 to time t24, the vertical scanning circuit 20 changes the control signal TXA(n) from low to high. This turns on the transfer transistor M3A of the pixel 12 in the nth row, and the signal charge held in the charge holding unit MEM2A is transferred to the floating diffusion unit FD. The potential of the floating diffusion unit FD then becomes a potential corresponding to the amount of signal charge transferred from the charge holding unit MEM2A, and a voltage corresponding to the potential of the floating diffusion unit FD is output to the vertical output line 16. The voltage of the vertical output line 16 that stabilizes after the transfer transistor M3A is turned off at time t24 is the signal level voltage VSIG1 of the pixel 12. In this way, the signal level voltage VSIG1 of the pixel 12, based on the signal charge held in the charge holding unit MEM2A, is read out to the vertical output line 16.

[0094] During the subsequent period from time t25 to time t26, the vertical scanning circuit 20 changes the control signal TXB(n) from low to high. This turns on the transfer transistor M3B of the pixel 12 in the nth row, and the signal charge stored in the charge storage unit MEM2B is transferred to the floating diffusion unit FD. The potential of the floating diffusion unit FD then becomes a potential corresponding to the amount of signal charge transferred from the charge storage unit MEM2B in addition to the signal charge already transferred from the charge storage unit MEM2A. A voltage corresponding to the potential of the floating diffusion unit FD is output to the vertical output line 16. The voltage of the vertical output line 16 that stabilizes after the transfer transistor M3B is turned off at time t26 is the signal level voltage VSIG2 of the pixel 12. Thus, the signal level voltage VSIG2 of the pixel 12, based on the signal charges stored in the charge storage units MEM2A and MEM2B, is read out to the vertical output line 16.

[0095] The difference between the reset level voltage VRES and the signal level voltage VSIG2 obtained in this way, i.e., |VSIG2-VRES|, is a physical quantity corresponding to the total amount of signal charge held in the charge holding units MEM2A and MEM2B.

[0096] At the next time t27, the vertical scanning circuit 20 changes the control signal RES(n) from low to high. This turns on the reset transistor M7 of the pixel 12 in the nth row, resetting the floating diffusion FD to a potential corresponding to the voltage VDD. A signal corresponding to the reset potential of the floating diffusion FD is output to the vertical output line 16.

[0097] At subsequent time t28, the vertical scanning circuit 20 changes the control signal SEL(n) from high to low, thereby turning off the selection transistors M5 of the pixels 12 in the nth row and deselecting the nth row.

[0098] During the subsequent period up to time t29, signals based on the signal charges accumulated in the charge holding units MEM2A and MEM2B are read from the pixels 12 in the (n+1)th row using the same procedure as the readout of the nth row performed during the period from time t21 to time t28. Signals are also read out from the pixels 12 in the other rows sequentially, row by row, using the same procedure.

[0099] (Pixel configuration) FIG. 12 is a plan view illustrating the configuration of a pixel unit formed on a semiconductor substrate in a photoelectric conversion device according to this embodiment. The semiconductor active region, gate electrodes, and connection holes arranged in the active region are illustrated as viewed in a plan view from a direction perpendicular to the main surface of the semiconductor substrate. FIG. 12 illustrates a 2-row, 3-column portion of a pixel unit 10 in which a large number of pixels are arranged in a matrix. As illustrated, the pixels are arranged in a two-dimensional array with translational symmetry, and adjacent pixels have the same configuration and function. While FIG. 12 illustrates an example in which a single pixel unit is arranged translationally symmetrically, a configuration in which multiple pixel units are arranged translationally symmetrically may also be used.

[0100] The relative positions of the photoelectric conversion unit PDA (first photoelectric conversion unit), transfer transistor M1A (first transfer unit), transfer transistor M2A (second transfer unit), transfer transistor M3A (third transfer unit), charge holding unit MEM1A (first charge holding unit), charge holding unit MEM2A (second charge holding unit), photoelectric conversion unit PDB (second photoelectric conversion unit), transfer transistor M1B (fourth transfer unit), transfer transistor M2B (fifth transfer unit), transfer transistor M3B (sixth transfer unit), charge holding unit MEM1B (third charge holding unit), and charge holding unit MEM2B (fourth charge holding unit) will be described later with reference to Figure 13.

[0101] FIG. 14 is a cross-sectional view showing a cross section of the pixel unit 10 taken along line A-A' in FIG. 12. As shown in FIG. 14, the photoelectric conversion unit PDA and the photoelectric conversion unit PDB constituting one pixel 12 share one microlens 100. In other words, the photoelectric conversion unit PDA and the photoelectric conversion unit PDB are configured to receive light that has passed through different pupil regions of the light that has entered the imaging optical system. That is, the microlens 100 focuses light that has passed through a first pupil region of the exit pupil of the imaging lens on the photoelectric conversion unit PDA, and focuses light that has passed through a second pupil region different from the first pupil region on the photoelectric conversion unit PDB. With this configuration, a signal based on charges generated by the photoelectric conversion unit PDA (image signal A) and a signal based on charges generated by the photoelectric conversion unit PDB (image signal B) can be used as phase difference detection signals for distance measurement. Furthermore, a signal (A image signal+B image signal) based on the total charge generated by the photoelectric conversion units PDA and PDB can be used as a signal for generating an image.

[0102] As described above, according to this embodiment, it is possible to detect a phase difference based on the output signals of the two circuit blocks of each pixel 12, and to obtain information about the distance to the subject and adjust the focus of the lens.

[0103] FIG. 13 is a diagram for explaining the positional relationship of each element constituting a pixel, and is a plan view in which reference numerals and the like are omitted from FIG. 12 and dimension lines and the like are added. The direction in which pixels commonly wired by control lines 14 in FIG. 1 are arranged (row direction, horizontal direction) is shown as a first direction DIR1 in FIG. 13. As indicated by the arrows pointing in both directions in FIG. 13, the "first direction DIR1" can refer to either the left or right direction. Also, the direction in which pixels commonly wired by vertical output lines 16 in FIG. 1 are arranged (column direction, vertical direction) is shown as a second direction DIR2 in FIG. 13. Unlike the configuration shown in FIG. 13, the direction in which pixels commonly wired by control lines 14 in FIG. 1 are arranged (row direction, horizontal direction) may be the second direction DIR2, and the direction in which pixels commonly wired by vertical output lines 16 in FIG. 1 are arranged (column direction, vertical direction) may be the first direction DIR1. In the following explanation, attention will be focused on pixel PIX1 enclosed by a dotted line, but the same can be said for the other pixels since each pixel is arranged translationally symmetrically.

[0104] The optical center of the photoelectric conversion region (photoelectric conversion unit PDA+photoelectric conversion unit PDB) of pixel PIX1 is defined as optical center 103. The position of the center of gravity of charge storage unit MEM1A in a planar view is defined as center of gravity position MEM1A-G, and the position of the center of gravity of charge storage unit MEM2A in a planar view is defined as center of gravity position MEM2A-G. The position of the center of gravity of charge storage unit MEM1B in a planar view is defined as center of gravity position MEM1B-G, and the position of the center of gravity of charge storage unit MEM2B in a planar view is defined as center of gravity position MEM2B-G.

[0105] Furthermore, the optical center of the photoelectric conversion region of the pixel (second pixel) adjacent to pixel PIX1 (first pixel) in the first direction DIR1 (left direction in FIG. 13) is defined as optical center 110. The optical center of the photoelectric conversion region of the pixel (third pixel) adjacent to pixel PIX1 (first pixel) in the first direction DIR1 (right direction in FIG. 13) is defined as optical center 111.

[0106] In pixel PIX1, the charge holding unit MEM1A is arranged in a first direction DIR1 (the left direction in FIG. 13) with respect to the photoelectric conversion unit PDA. Here, being arranged in the first direction DIR1 means that at least a part of the charge holding unit MEM1A and at least a part of the photoelectric conversion unit PDA are arranged so as to be adjacent in the first direction DIR1. Alternatively, it means that any straight line parallel to the first direction DIR1 intersects both at least a part of the charge holding unit MEM1A and at least a part of the photoelectric conversion unit PDA. Also, in pixel PIX1, the charge holding unit MEM1B is arranged in the first direction DIR1 (the right direction in FIG. 13) with respect to the photoelectric conversion unit PDB.

[0107] In the present embodiment, when the distance between the optical center 103 and the centroid position MEM1A-G in a plan view is L1 and the distance between the optical center 103 and the centroid position MEM2A-G is L2, it is configured such that L1 < L2. Also, when the distance between the optical center 103 and the centroid position MEM1B-G in a plan view is L1 and the distance between the optical center 103 and the centroid position MEM2B-G is L2, it is configured such that L1 < L2.

[0108] Also, when the distance between the centroid position MEM1A-G and the optical center 110 of an adjacent pixel in a plan view is L3 and the distance between the centroid position MEM2A-G and the optical center 110 of the adjacent pixel is L4, it is configured such that L3 < L4. Also, when the distance between the centroid position MEM1B-G and the optical center 111 of an adjacent pixel in a plan view is L3 and the distance between the centroid position MEM2B-G and the optical center 111 of the adjacent pixel is L4, it is configured such that L3 < L4.

[0109] As already explained, the charge holding units MEM1A and MEM1B are used to hold the signal charge generated in the photoelectric conversion unit during the period of the Nth frame only for the Nth frame. Furthermore, the charge holding units MEM2A and MEM2B are used to hold the signal charge of the (N-1)th frame while the Nth frame is being captured, until the signal charge acquired in the previous frame, the (N-1)th frame, is transferred to the floating diffusion unit FD and read out through the amplification transistor M4.

[0110] For example, consider a case where, during the Nth frame, stronger light is incident on pixel PIX1 than during the (N-1)th frame. Some of the strong light incident on the photoelectric conversion unit PDA or PDB of pixel PIX1 may diffract within the semiconductor and leak out of the photoelectric conversion unit as stray light. If such stray light is easily able to reach the charge storage unit MEM2A or MEM2B, photocharges due to the stray light are generated in the charge storage unit MEM2A or MEM2B and are superimposed on the signal charge of the previous frame that was held there. In other words, a portion of the photocharge of the current frame that should not have been added is added to the signal charge acquired in the previous frame and held in the charge storage unit MEM2A or MEM2B, resulting in a type of crosstalk between frames.

[0111] Alternatively, during the Nth frame, if strong light is incident on an adjacent pixel adjacent to pixel PIX1 in the first direction DIR1, some of the strong light incident on the photoelectric conversion unit PDA or PDB of the adjacent pixel may diffract in the semiconductor and leak out of the photoelectric conversion unit as stray light. If such stray light is configured to easily reach the charge storage unit MEM2A or MEM2B of pixel PIX1, photocharges due to the stray light may be generated in the charge storage unit MEM2A or MEM2B. In this case, some of the photocharges generated during the current frame are added to the signal charge acquired in the previous frame and held in the charge storage unit MEM2A or MEM2B, resulting in a type of crosstalk between frames.

[0112] Ambient light exponentially decays according to the distance it travels in the semiconductor. However, according to this embodiment, it is configured such that L1 < L2. For this reason, the ambient light leaking from the photoelectric conversion unit of pixel PIX1 is less likely to reach charge holding unit MEM2A and charge holding unit MEM2B. Furthermore, according to this embodiment, since it is configured such that L3 < L4, the ambient light leaking from the photoelectric conversion units of adjacent pixels adjacent in the first direction DIR1 is less likely to reach charge holding unit MEM2A and charge holding unit MEM2B of pixel PIX1.

[0113] Therefore, according to the photoelectric conversion device according to this embodiment, when capturing a moving image in global shutter operation, the image of the frame that is temporally previous is less likely to be affected by the image of the frame that is temporally subsequent when capturing the image, so that a high-quality moving image can be acquired.

[0114] In the example of FIG. 12, charge holding unit MEM1A and charge holding unit MEM1B, and charge holding unit MEM2A and charge holding unit MEM2B are arranged symmetrically with respect to the optical center 103. In other words, with respect to the line passing through the optical center of the photoelectric conversion unit and orthogonal to the first direction, each charge holding unit is arranged to be line-symmetrical. However, the arrangement of each element is not limited to this. As long as the light leaking from the photoelectric conversion unit is arranged at a distance such that it is less likely to reach charge holding unit MEM2A and charge holding unit MEM2B, for example, it may be arranged point-symmetrically with respect to the optical center 103. Thereby, it becomes easy to make the characteristics of the signals output from photoelectric conversion unit PDA and photoelectric conversion unit PDB uniform.

[0115] [Embodiment 3] The photoelectric conversion device according to Embodiment 3 will be described with reference to the drawings. Matters common to Embodiment 1 or Embodiment 2 will be described in a simplified or omitted manner. The schematic configuration of the photoelectric conversion device is the same as that of Embodiment 1 described with reference to FIG. 1. Regarding Embodiment 3, after explaining the circuit configuration and driving method of the pixel, the configuration of the pixel portion formed on the semiconductor substrate will be described.

[0116] (Pixel circuit configuration) 15 is an equivalent circuit diagram illustrating the circuit configuration of a pixel 12 included in the photoelectric conversion device according to this embodiment. Each pixel 12 included in the photoelectric conversion device according to this embodiment has two circuit blocks, each consisting of three transfer transistors and two charge storage units. Furthermore, each pixel 12 has a photoelectric conversion unit PD and a charge discharging transistor M6, which are commonly connected to the input sides of these two circuit blocks. Furthermore, each pixel 12 has a floating diffusion unit FD, a reset transistor M7, an amplification transistor M4, and a selection transistor M5, which are commonly connected to the output sides of these two circuit blocks.

[0117] The first circuit block is composed of a transfer transistor M1L (first transfer unit), a transfer transistor M2L (second transfer unit), a transfer transistor M3L (third transfer unit), a charge holding unit MEM1L (first charge holding unit), and a charge holding unit MEM2L (second charge holding unit). The second circuit block is composed of a transfer transistor M1S (fourth transfer unit), a transfer transistor M2S (fifth transfer unit), a transfer transistor M3S (sixth transfer unit), a charge holding unit MEM1S (third charge holding unit), and a charge holding unit MEM2S (fourth charge holding unit).

[0118] The photoelectric conversion unit PD has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1L, the source of the transfer transistor M1S, and the source of the charge discharging transistor M6. The drain of the transfer transistor M1L is connected to the source of the transfer transistor M2L. A connection node between the drain of the transfer transistor M1L and the source of the transfer transistor M2L includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1L). The drain of the transfer transistor M2L is connected to the source of the transfer transistor M3L. A connection node between the drain of the transfer transistor M2L and the source of the transfer transistor M3L includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2L). The drain of the transfer transistor M1S is connected to the source of the transfer transistor M2S. A connection node between the drain of the transfer transistor M1S and the source of the transfer transistor M2S includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1S). The drain of the transfer transistor M2S is connected to the source of the transfer transistor M3S. The connection node between the drain of the transfer transistor M2S and the source of the transfer transistor M3S includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2S).

[0119] The drains of the transfer transistors M3L and M3S are connected to the source of the reset transistor M7 and the gate of the amplification transistor M4. The connection node between the drain of the transfer transistor M3L, the drain of the transfer transistor M3S, the source of the reset transistor M7, and the gate of the amplification transistor M4 is a so-called floating diffusion portion FD. The floating diffusion portion FD includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion.

[0120] The drains of the reset transistor M7, the amplifier transistor M4, and the charge ejection transistor M6 are connected to the power supply voltage line (voltage VDD). The source of the amplifier transistor M4 is connected to the drain of the selection transistor M5. The source of the selection transistor M5 is connected to the vertical output line 16.

[0121] The control lines 14 connected from the vertical scanning circuit 20 (FIG. 1) to each pixel include a total of nine signal lines per pixel. A control signal GS1L shown in FIG. 16 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1L. A control signal GS2L is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M2L. A control signal TXL is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3L. A control signal GS1S shown in FIG. 16 is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M1S. A control signal GS2S is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M2S. A control signal TXS is output from the vertical scanning circuit 20 to the signal line connected to the gate of the transfer transistor M3S. A control signal RES is output from the vertical scanning circuit 20 to the signal line connected to the gate of the reset transistor M7. A control signal SEL is output from the vertical scanning circuit 20 to the signal line connected to the gate of the selection transistor M5. 16 is output from the vertical scanning circuit 20 to a signal line connected to the gate of the charge discharging transistor M6. When each transistor is an N-type transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned on, and when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned off.

[0122] The photoelectric conversion unit PD converts incident light into an electric charge corresponding to the amount of light (photoelectric conversion) and accumulates the generated electric charge. When turned on, the transfer transistor M1L functions as a transfer unit that transfers the electric charge held in the photoelectric conversion unit PD to the charge holding unit MEM1L. When turned on, the transfer transistor M2L functions as a transfer unit that transfers the electric charge held in the charge holding unit MEM1L to the charge holding unit MEM2L. When turned on, the transfer transistor M3L functions as a transfer unit that transfers the electric charge held in the charge holding unit MEM2L to the floating diffusion unit FD. When turned on, the transfer transistor M1S functions as a transfer unit that transfers the electric charge held in the photoelectric conversion unit PD to the charge holding unit MEM1S. When turned on, the transfer transistor M2S functions as a transfer unit that transfers the electric charge held in the charge holding unit MEM1S to the charge holding unit MEM2S. When the transfer transistor M3S is turned on, it functions as a transfer unit that transfers the charge held in the charge holding unit MEM2S to the floating diffusion unit FD. The functions and operations of the reset transistor M7, the amplification transistor M4, the selection transistor M5, and the charge discharging transistor M6 are the same as those in the first embodiment.

[0123] (Method of driving a photoelectric conversion device) Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 16. Fig. 16 is a timing chart showing driving related to the signal readout operation of the pixel.

[0124] 16 shows a control signal GS1L supplied to the transfer transistor M1L, a control signal GS1S supplied to the transfer transistor M1S, a control signal GS2L supplied to the transfer transistor M2L, a control signal GS2S supplied to the transfer transistor M2S, and a control signal OFG supplied to the charge discharging transistor M6. When each control signal is at a high level, the corresponding transistor is active (on). Note that, since the present embodiment uses a global shutter driving method, driving related to the exposure operation of the pixel unit 10 is performed simultaneously for all rows of pixels 12. Furthermore, the pixel signal readout operation is performed sequentially for each row of pixels.

[0125] In this embodiment, in each frame, a plurality of (Ks) accumulation periods Ts and a plurality of (Kl) accumulation periods Tl are executed. The accumulation periods Ts are periods for accumulating signal charges in the charge holding unit MEM1S, and the accumulation periods Tl are periods for accumulating signal charges in the charge holding unit MEM1L. Hereinafter, the i-th accumulation period Ts among the Ks accumulation periods Ts will be referred to as the i-th accumulation period Ts. i , (i+1)th accumulation period Ts i+1 and the Ks-th accumulation period T sKs and the jth accumulation period Tl among the Kl accumulation periods Tl j and the (j+1)th accumulation period Tl j+1 Here, i is an integer greater than or equal to 1 and less than Ks-2. j is an integer greater than or equal to Kl-1. The numbers Ks and Kl can be set appropriately depending on the total accumulation time within one frame period, and the numbers Ks and Kl may be the same or different. The accumulation period Ts can be set to a time shorter than the accumulation period Tl.

[0126] Just before time t31, the control signal OFG is at a high level. The charge discharging transistor M6 is turned on in response to the high-level control signal OFG, and the photoelectric conversion unit PD is reset to a potential corresponding to the voltage VDD.

[0127] At time t31, the vertical scanning circuit 20 changes the control signal OFG from high to low. This turns off the charge discharging transistor M6, and the reset state of the photoelectric conversion unit PD is released. That is, the timing at which the control signal OFG changes from high to low is the same as the timing at which the accumulation period Ts i The signal charge generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharging transistor M6 is off is accumulated in the photoelectric conversion unit PD.

[0128] During the period from a predetermined timing after time t31 to time t32, the vertical scanning circuit 20 controls the control signal GS1S to a high level. This turns on the transfer transistor M1S, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM1S. The time t32 when the transfer transistor M1S turns off is the end of the accumulation period Ts i That is, the period from time t31 to time t32 is the end time of the signal charge accumulation period Ts i is.

[0129] After time t32, the vertical scanning circuit 20 changes the control signal OFG from low to high, which turns on the charge discharging transistor M6 and resets the photoelectric conversion unit PD to a potential corresponding to the voltage VDD.

[0130] At the next time t33, the vertical scanning circuit 20 changes the control signal OFG from high to low. This turns off the charge discharging transistor M6, and the reset state of the photoelectric conversion unit PD is released. That is, the timing at which the control signal OFG changes from high to low coincides with the accumulation period T1 in the photoelectric conversion unit PD. j The signal charge generated by the incidence of photons on the photoelectric conversion unit PD while the charge discharging transistor M6 is off is accumulated in the photoelectric conversion unit PD.

[0131] During the period from a predetermined timing after time t33 to time t34, the vertical scanning circuit 20 controls the control signal GS1L to a high level. This turns on the transfer transistor M1L, and the signal charge accumulated in the photoelectric conversion unit PD is transferred to the charge holding unit MEM1L. The time t34 when the transfer transistor M1L turns off is the end of the accumulation period T1 in the photoelectric conversion unit PD. j That is, the period from time t33 to time t34 is the end time of the signal charge accumulation period Tl j is.

[0132] Next, the accumulation period Ts and the accumulation period Tl are repeated a predetermined number of times in the same manner as in the period from time t31 to time t34. For example, as shown in FIG. 16, the accumulation period Ts is repeated a predetermined number of times in the period from time t35 to time t36. i+1 During the period from time t37 to time t38, the accumulation period Tl j+1 is performed, and during the period from time t39 to time t40, the accumulation period Ts Ks will be carried out.

[0133] In this way, in each frame, Ks accumulation periods Ts and Kl accumulation periods Tl are executed. Ks The signal charge generated in the photoelectric conversion unit PD is held during an accumulation period Tshort having a length equal to the total length of the Ks periods from the accumulation period Tl1 to the accumulation period Tl Kl The signal charges generated in the photoelectric conversion unit PD are held during an accumulation period Tlong having a length equal to the total length of the Kl periods up to the accumulation period Tlong.

[0134] The signal charge accumulated in the charge holding unit MEM1S can be transferred to the charge holding unit MEM2S after the readout of the pixel signal based on the signal charge of the (N-1)th frame accumulated in the charge holding unit MEM2S is completed. Also, the signal charge accumulated in the charge holding unit MEM1L can be transferred to the charge holding unit MEM2L after the readout of the pixel signal based on the signal charge of the (N-1)th frame accumulated in the charge holding unit MEM2L is completed. Here, it is assumed that the readout of the pixel signal based on the signal charge of the (N-1)th frame accumulated in the charge holding unit MEM2S and the charge holding unit MEM2L is completed by time t40.

[0135] After that, during the period from a predetermined timing after time t40 to time t41, the vertical scanning circuit 20 controls the control signal GS2L to a high level, which turns on the transfer transistor M2L and transfers the signal charge stored in the charge holding unit MEM1L to the charge holding unit MEM2L.

[0136] Furthermore, during the period from a predetermined timing after time t40 to time t42, the vertical scanning circuit 20 controls the control signal GS2S to a high level, which turns on the transfer transistor M2S and transfers the signal charge stored in the charge holding unit MEM1S to the charge holding unit MEM2S.

[0137] Here, the charge transfer from the charge retention unit MEM1L to the charge retention unit MEM2L and the charge transfer from the charge retention unit MEM1S to the charge retention unit MEM2S are performed at different times, but they may also be performed simultaneously. When the charge transfer from the charge retention unit MEM1L and the charge retention unit MEM1S to the charge retention unit MEM2L and the charge retention unit MEM2S is complete, the charge retention units MEM1L and MEM1S become empty. This makes it possible to accumulate signal charge for the next frame (the (N+1)th frame) in the charge retention unit MEM1L and the charge retention unit MEM1S. In this way, this embodiment makes it possible to acquire high-quality moving images with a high dynamic range.

[0138] (Pixel configuration) FIG. 17 is a plan view illustrating the configuration of a pixel unit formed on a semiconductor substrate in a photoelectric conversion device according to this embodiment. The semiconductor active region, gate electrodes, and connection holes arranged in the active region are illustrated as viewed in a plan view perpendicular to the main surface of the semiconductor substrate. FIG. 17 illustrates a 2-row, 3-column portion of a pixel unit 10 in which a large number of pixels are arranged in a matrix. As illustrated, the pixels are arranged in a two-dimensional array with translational symmetry, and adjacent pixels have the same configuration and function. While FIG. 17 illustrates an example in which a single pixel is arranged translationally symmetrically, a configuration in which multiple pixels are arranged translationally symmetrically as a unit may also be used.

[0139] The relative positions of the transfer transistor M1L (first transfer unit), transfer transistor M2L (second transfer unit), transfer transistor M3L (third transfer unit), charge holding unit MEM1L (first charge holding unit), charge holding unit MEM2L (second charge holding unit), transfer transistor M1S (fourth transfer unit), transfer transistor M2S (fifth transfer unit), transfer transistor M3S (sixth transfer unit), charge holding unit MEM1S (third charge holding unit), and charge holding unit MEM2S (fourth charge holding unit) will be described with reference to Figure 18.

[0140] FIG. 18 is a diagram for explaining the positional relationship of each element constituting a pixel, and is a plan view in which reference numerals and the like are omitted from FIG. 17 and dimension lines and the like are added. The direction in which pixels commonly wired by control lines 14 in FIG. 1 are arranged (row direction, horizontal direction) is shown as a first direction DIR1 in FIG. 18. As indicated by the arrows pointing in both directions in FIG. 18, the "first direction DIR1" can refer to either the left or right direction. Furthermore, the direction in which pixels commonly wired by vertical output lines 16 in FIG. 1 are arranged (column direction, vertical direction) is shown as a second direction DIR2 in FIG. 18. In the following explanation, we will focus on pixel PIX1 surrounded by a dotted line, but since each pixel is arranged translationally symmetrically, the same can be said for the other pixels.

[0141] For pixel PIX1, the optical center of the photoelectric conversion unit PD is defined as optical center 103. The position of the center of gravity in the plan view of the charge holding unit MEM1S is defined as the center of gravity position MEM1S-G, and the position of the center of gravity in the plan view of the charge holding unit MEM2S is defined as the center of gravity position MEM2S-G. The position of the center of gravity in the plan view of the charge holding unit MEM1L is defined as the center of gravity position MEM1L-G, and the position of the center of gravity in the plan view of the charge holding unit MEM2L is defined as the center of gravity position MEM2L-G.

[0142] Also, for pixel PIX1 (the first pixel), the optical center of the photoelectric conversion unit of the adjacent pixel (the second pixel) adjacent in the first direction DIR1 (the left direction in FIG. 18) is defined as optical center 110. For pixel PIX1 (the first pixel), the optical center of the photoelectric conversion unit of the adjacent pixel (the third pixel) adjacent in the first direction DIR1 (the right direction in FIG. 18) is defined as optical center 111.

[0143] In pixel PIX1, the charge holding unit MEM1S is arranged in the first direction DIR1 (the left direction in FIG. 18) with respect to the photoelectric conversion unit PD. Here, being arranged in the first direction DIR1 means that at least a part of the charge holding unit MEM1S and at least a part of the photoelectric conversion unit PD are arranged adjacent to each other in the first direction DIR1. Alternatively, it means that any straight line parallel to the first direction DIR1 intersects both at least a part of the charge holding unit MEM1S and at least a part of the photoelectric conversion unit PD. Also, in pixel PIX1, the charge holding unit MEM1L is arranged in the first direction DIR1 (the right direction in FIG. 18) with respect to the photoelectric conversion unit PD.

[0144] In this embodiment, when the distance between the optical center 103 and the center of gravity position MEM1S-G in the plan view is L1, and the distance between the optical center 103 and the center of gravity position MEM2S-G is L2, it is configured such that L1 < L2. Also, when the distance between the optical center 103 and the center of gravity position MEM1L-G in the plan view is L1, and the distance between the optical center 103 and the center of gravity position MEM2L-G is L2, it is configured such that L1 < L2.

[0145] Also, when the distance between the center-of-gravity position MEM1S-G in plan view and the optical center 110 of an adjacent pixel is defined as L3, and the distance between the center-of-gravity position MEM2S-G and the optical center 110 of the adjacent pixel is defined as L4, it is configured such that L3 < L4. Also, when the distance between the center-of-gravity position MEM1L-G in plan view and the optical center 111 of an adjacent pixel is defined as L3, and the distance between the center-of-gravity position MEM2L-G and the optical center 111 of the adjacent pixel is defined as L4, it is configured such that L3 < L4.

[0146] As already explained, the charge holding part MEM1S and the charge holding part MEM1L are used to hold the signal charge generated in the photoelectric conversion part during the period of the Nth frame only for the duration of the Nth frame. Also, the charge holding part MEM2S and the charge holding part MEM2L are used to hold the signal charge of the (N - 1)th frame until the signal charge acquired in the (N - 1)th frame, which is the previous frame, is transferred to the floating diffusion part FD and read out through the amplification transistor M4 during the shooting of the Nth frame.

[0147] For example, consider the case where strong light is incident on pixel PIX1 during the period of the Nth frame as compared to the (N - 1)th frame. A part of the strong light incident on the photoelectric conversion part PD of pixel PIX1 may diffract in the semiconductor and leak out as stray light outside the photoelectric conversion part PD. If such stray light is likely to reach the charge holding part MEM2S or the charge holding part MEM2L, then photocharge due to the stray light is generated in the charge holding part MEM2S or the charge holding part MEM2L and overlaps with the signal charge of the previous frame that was being held. That is, since a part of the photocharge of the current frame that should not originally be added is added to the signal charge acquired in the previous frame held by the charge holding part MEM2S or the charge holding part MEM2L, a kind of cross-talk occurs between frames.

[0148] Alternatively, when strong light is incident on an adjacent pixel adjacent to pixel PIX1 in the first direction DIR1 during the period of the Nth frame, part of the strong light incident on the photoelectric conversion unit PD of the adjacent pixel may diffract in the semiconductor and leak out as stray light outside the photoelectric conversion unit. If such stray light is likely to reach the charge holding unit MEM2S or the charge holding unit MEM2L of pixel PIX1, photocharge due to the stray light may be generated in the charge holding unit MEM2S or the charge holding unit MEM2L. Then, since part of the photocharge generated during the period of the current frame is added to the signal charge acquired in the previous frame held by the charge holding unit MEM2S or the charge holding unit MEM2L, a kind of cross-talk occurs between frames.

[0149] The stray light exponentially decays according to the distance it travels in the semiconductor. According to this embodiment, it is configured such that L1 < L2. For this reason, the stray light leaking from the photoelectric conversion unit PD of pixel PIX1 is unlikely to reach the charge holding unit MEM2S and the charge holding unit MEM2L. Furthermore, according to this embodiment, since it is configured such that L3 < L4, the stray light leaking from the photoelectric conversion unit of the adjacent pixel adjacent in the first direction DIR1 is unlikely to reach the charge holding unit MEM2S and the charge holding unit MEM2L of pixel PIX1.

[0150] Therefore, according to the photoelectric conversion device according to this embodiment, when capturing a moving image in the global shutter operation, the image of the frame temporally preceding is less likely to be affected by the image of the frame temporally following, so a high-quality moving image can be acquired.

[0151] 12, the charge retention units MEM1A and MEM1B, and the charge retention units MEM2A and MEM2B are arranged symmetrically with respect to the optical center 103. In other words, the charge retention units are arranged so as to be line-symmetric with respect to a line that passes through the optical center of the photoelectric conversion unit and is orthogonal to the first direction. However, the arrangement of each element is not limited to this, and they may be arranged, for example, point-symmetrically with respect to the optical center 103, as long as they are arranged at a distance that makes it difficult for light leaking from the photoelectric conversion unit to reach the charge retention unit MEM2. This makes it easy to align the characteristics of the signal during long-second accumulation and the signal during short-second accumulation.

[0152] [Embodiment 4] A photoelectric conversion device according to embodiment 4 will be described with reference to the drawings. Descriptions of matters common to any of the embodiments already described will be simplified or omitted. The schematic configuration of the photoelectric conversion device is the same as that of embodiment 1 described with reference to FIG. 1. Regarding embodiment 4, the circuit configuration of the pixel and the driving method will be described first, and then the configuration of the pixel unit formed on the semiconductor substrate will be described.

[0153] (Pixel circuit configuration) 19 is an equivalent circuit diagram illustrating the circuit configuration of a pixel 12 included in the photoelectric conversion device according to this embodiment. In this embodiment, each pixel 12 has a first circuit block and a second circuit block.

[0154] The first circuit block includes a photoelectric conversion unit PDA (first photoelectric conversion unit), a transfer transistor M1LA (first transfer unit), a transfer transistor M2LA (second transfer unit), a transfer transistor M3LA (third transfer unit), a transfer transistor M1SA (fourth transfer unit), a transfer transistor M2SA (fifth transfer unit), a transfer transistor M3SA (sixth transfer unit), a charge holding unit MEM1LA (first charge holding unit), a charge holding unit MEM2LA (second charge holding unit), a charge holding unit MEM1SA (third charge holding unit), and a charge holding unit MEM2SA (fourth charge holding unit).

[0155] The second circuit block includes a photoelectric conversion unit PDB (second photoelectric conversion unit), a transfer transistor M1LB (seventh transfer unit), a transfer transistor M2LB (eighth transfer unit), a transfer transistor M3LB (ninth transfer unit), a transfer transistor M1SB (tenth transfer unit), a transfer transistor M2SB (eleventh transfer unit), a transfer transistor M3SB (twelfth transfer unit), a charge holding unit MEM1LB (fifth charge holding unit), a charge holding unit MEM2LB (sixth charge holding unit), a charge holding unit MEM1SB (seventh charge holding unit), and a charge holding unit MEM2SB (eighth charge holding unit).

[0156] The photoelectric conversion unit PDA has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1LA, the source of the transfer transistor M1SA, and the source of the charge discharging transistor M6. The drain of the transfer transistor M1LA is connected to the source of the transfer transistor M2LA. The connection node between the drain of the transfer transistor M1LA and the source of the transfer transistor M2LA includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1LA). The drain of the transfer transistor M2LA is connected to the source of the transfer transistor M3LA. The connection node between the drain of the transfer transistor M2LA and the source of the transfer transistor M3LA includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2LA).

[0157] The drain of the transfer transistor M1SA is connected to the source of the transfer transistor M2SA. The connection node between the drain of the transfer transistor M1SA and the source of the transfer transistor M2SA includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1SA). The drain of the transfer transistor M2SA is connected to the source of the transfer transistor M3SA. The connection node between the drain of the transfer transistor M2SA and the source of the transfer transistor M3SA includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2SA).

[0158] The photoelectric conversion unit PDB has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1LB, the source of the transfer transistor M1SB, and the source of the charge discharging transistor M6. The drain of the transfer transistor M1LB is connected to the source of the transfer transistor M2LB. The connection node between the drain of the transfer transistor M1LB and the source of the transfer transistor M2LB includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1LB). The drain of the transfer transistor M2LB is connected to the source of the transfer transistor M3LB. The connection node between the drain of the transfer transistor M2LB and the source of the transfer transistor M3LB includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2LB).

[0159] The drain of the transfer transistor M1SB is connected to the source of the transfer transistor M2SB. The connection node between the drain of the transfer transistor M1SB and the source of the transfer transistor M2SB includes a capacitance component and functions as a charge holding unit (charge holding unit MEM1SB). The drain of the transfer transistor M2SB is connected to the source of the transfer transistor M3SB. The connection node between the drain of the transfer transistor M2SB and the source of the transfer transistor M3SB includes a capacitance component and functions as a charge holding unit (charge holding unit MEM2SB).

[0160] The drains of the transfer transistors M3LA and M3LB are connected to the source of the reset transistor M7 and the gate of the amplifier transistor M4. The connection node between the drains of the transfer transistors M3LA and M3LB, the source of the reset transistor M7, and the gate of the amplifier transistor M4 is a floating diffusion FD1. The drains of the transfer transistors M3SA and M3SB are connected to the source of the reset transistor M7 of the adjacent pixel above in the drawing and the gate of the amplifier transistor M4 of the adjacent pixel above in the drawing. The connection node between the drains of the transfer transistors M3SA and M3SB, the source of the reset transistor M7 of the adjacent pixel below in the drawing, and the gate of the amplifier transistor M4 of the adjacent pixel above in the drawing is a floating diffusion FD2. The floating diffusion FD1 is connected to the floating diffusion FD2 of the adjacent pixel above in the drawing, and the floating diffusion FD2 is connected to the floating diffusion FD1 of the adjacent pixel below in the drawing. The floating diffusion regions FD1 and FD2 include capacitance components (floating diffusion capacitances) and function as charge storage regions.

[0161] The drains of the reset transistor M7, the amplifier transistor M4, and the charge ejection transistor M6 are connected to the power supply voltage line (voltage VDD). The source of the amplifier transistor M4 is connected to the drain of the selection transistor M5. The source of the selection transistor M5 is connected to the vertical output line 16.

[0162] Each of the control lines 14 connected from the vertical scanning circuit 20 (FIG. 1) to each pixel includes a total of 15 signal lines, namely, signal lines connected to the gates of the 12 transfer transistors, reset transistor M7, selection transistor M5, and charge discharging transistor M6 that each pixel has.

[0163] A control signal GS1LA is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1LA. A control signal GS2LA is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M2LA. A control signal TXLA is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3LA. A control signal GS1SA is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1SA. A control signal GS2SA is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M2SA. A control signal TXSA is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3SA.

[0164] A control signal GS1LB is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1LB. A control signal GS2LB is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M2LB. A control signal TXLB is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3LB. A control signal GS1SB is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M1SB. A control signal GS2SB is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M2SB. A control signal TXSB is output from the vertical scanning circuit 20 to a signal line connected to the gate of the transfer transistor M3SB.

[0165] A control signal OFG is output from the vertical scanning circuit 20 to a signal line connected to the gate of the charge discharging transistor M6. A control signal SEL is output from the vertical scanning circuit 20 to a signal line connected to the gate of the selection transistor M5. A control signal RES is output from the vertical scanning circuit 20 to a signal line connected to the gate of the reset transistor M7.

[0166] Note that some of the corresponding transistors in the first circuit block and the second circuit block may be connected to a common signal line. In this case, each of the control lines 14 may be composed of 11 signal lines. That is, the same control signal may be supplied to the gate of the transfer transistor M1LA and the gate of the transfer transistor M1LB via a common signal line. Similarly, the same control signal may be supplied to the gate of the transfer transistor M1SA and the gate of the transfer transistor M1SB via a common signal line. The same control signal may be supplied to the gate of the transfer transistor M2LA and the gate of the transfer transistor M2LB via a common signal line. The same control signal may be supplied to the gate of the transfer transistor M2SA and the gate of the transfer transistor M2SB via a common signal line. This configuration ensures the simultaneity of signals acquired from the two photoelectric conversion units PDA and PDB. Furthermore, when adjacent gates are driven in the same way, the gates may be integrated, and the connection holes connecting the gates to the wiring may be combined.

[0167] The functions and operations of the first and second circuit blocks described above are the same as those of the circuit blocks described in embodiment 2. The functions and operations of the reset transistor M7, the amplification transistor M4, the selection transistor M5, and the charge discharging transistor M6 are the same as those in embodiment 1.

[0168] According to this embodiment, it is possible to acquire high-quality moving images with a high dynamic range. Furthermore, according to this embodiment, it is possible to detect a phase difference based on the output signals of the two circuit blocks of each pixel 12, and it is possible to acquire information about the distance to the subject and perform lens focusing.

[0169] In this embodiment, the charge holding unit MEM2LA is connected to the charge holding unit MEM1LA via the transfer transistor M1LA, and the charge holding unit MEM2SA is connected to the charge holding unit MEM1SA via the transfer transistor M1SA. That is, the pixel 12 has charge holding units MEM2LA and MEM2SA capable of holding charges, separate from the charge holding units MEM1LA and MEM1SA used to store signal charges. Also, the charge holding unit MEM2LB is connected to the charge holding unit MEM1LB via the transfer transistor M1LB, and the charge holding unit MEM2SB is connected to the charge holding unit MEM1SB via the transfer transistor M1SB. That is, the pixel 12 has charge holding units MEM2LB and MEM2SB capable of holding charges, separate from the charge holding unit MEM1LB and MEM1SB used to store signal charges. This allows the pixel 12 to store signal charges for the next frame while retaining the signal charges for the previous frame. This makes it possible to read out signals even during periods when signal charges are being accumulated, reducing the time period during each frame period during which signal charges cannot be acquired, and enabling seamless video to be acquired.

[0170] (Pixel configuration) FIG. 20 is a plan view illustrating the configuration of a pixel unit formed on a semiconductor substrate in a photoelectric conversion device according to this embodiment. The semiconductor active region, gate electrodes, and connection holes arranged in the active region are illustrated as viewed in a plan view perpendicular to the main surface of the semiconductor substrate. FIG. 20 illustrates a one-row, three-column portion of a pixel unit 10 in which a large number of pixels are arranged in a matrix. As illustrated, the pixels are arranged in a two-dimensional array with translational symmetry, and adjacent pixels have the same configuration and function. While FIG. 20 illustrates an example in which a single pixel is arranged translationally symmetrically, a configuration in which multiple pixels are arranged translationally symmetrically as a unit may also be used.

[0171] Photoelectric conversion unit PDA (first photoelectric conversion unit), transfer transistor M1LA (first transfer unit), transfer transistor M2LA (second transfer unit), transfer transistor M3LA (third transfer unit), transfer transistor M1SA (fourth transfer unit), transfer transistor M2SA (fifth transfer unit), transfer transistor M3SA (sixth transfer unit), charge holding unit MEM1LA (first charge holding unit), charge holding unit MEM2LA (second charge holding unit), charge holding unit MEM1SA (third charge holding unit), charge holding unit MEM2SA (fourth charge holding unit), photoelectric conversion unit PDB (second photoelectric The relative positions of the charge holding unit MEM1LB (seventh transfer unit), transfer transistor M2LB (eighth transfer unit), transfer transistor M3LB (ninth transfer unit), transfer transistor M1SB (tenth transfer unit), transfer transistor M2SB (eleventh transfer unit), transfer transistor M3SB (twelfth transfer unit), charge holding unit MEM1LB (fifth charge holding unit), charge holding unit MEM2LB (sixth charge holding unit), charge holding unit MEM1SB (seventh charge holding unit), and charge holding unit MEM2SB (eighth charge holding unit) will be described with reference to Figure 21.

[0172] FIG. 21 is a diagram for explaining the positional relationship of each element constituting a pixel, and is a plan view in which reference numerals and the like are omitted from FIG. 20 and dimension lines and the like are added. The direction in which pixels commonly wired by control lines 14 in FIG. 1 are arranged (row direction, horizontal direction) is shown as a first direction DIR1 in FIG. 21. As indicated by the arrows pointing in both directions in FIG. 21, the "first direction DIR1" can refer to either the leftward or rightward direction. Also, the direction in which pixels commonly wired by vertical output lines 16 in FIG. 1 are arranged (column direction, vertical direction) is shown as a second direction DIR2 in FIG. 21. In the following explanation, attention is focused on the pixel shown in the center of the drawing, but the same can be said for the other pixels because each pixel is arranged translationally symmetrically.

[0173] The optical center of the photoelectric conversion region (photoelectric conversion unit PDA + photoelectric conversion unit PDB) of the pixel located at the center of the figure is defined as optical center 103. The position of the center of gravity of the charge storage unit MEM1LA in a planar view is defined as center of gravity position MEM1LA-G, and the position of the center of gravity of the charge storage unit MEM2LA in a planar view is defined as center of gravity position MEM2LA-G. The position of the center of gravity of the charge storage unit MEM1LB in a planar view is defined as center of gravity position MEM1LB-G, and the position of the center of gravity of the charge storage unit MEM2LB in a planar view is defined as center of gravity position MEM2LB-G. The position of the center of gravity of the charge storage unit MEM1SA in a planar view is defined as center of gravity position MEM1SA-G, and the position of the center of gravity of the charge storage unit MEM2SA in a planar view is defined as center of gravity position MEM2SA-G. The position of the center of gravity of the charge storage unit MEM1SB in a planar view is defined as center of gravity position MEM1SB-G, and the position of the center of gravity of the charge storage unit MEM2SB in a planar view is defined as center of gravity position MEM2SB-G.

[0174] Furthermore, the optical center of the photoelectric conversion region of the adjacent pixel (second pixel) adjacent to the pixel of interest (first pixel) in the first direction DIR1 (left direction in FIG. 21) is defined as optical center 110. The optical center of the photoelectric conversion region of the adjacent pixel (third pixel) adjacent to the pixel of interest (first pixel) in the first direction DIR1 (right direction in FIG. 21) is defined as optical center 111.

[0175] In the pixel of interest, the charge holding units MEM1LA and MEM1SA are arranged in a first direction DIR1 (leftward in FIG. 21) relative to the photoelectric conversion unit PDA. Here, "arranged in the first direction DIR1" means that at least a portion of the charge holding units and at least a portion of the photoelectric conversion unit are arranged adjacent to each other in the first direction DIR1. Alternatively, it means that any line parallel to the first direction DIR1 intersects with both at least a portion of the charge holding units and at least a portion of the photoelectric conversion unit. Furthermore, in pixel PIX1, the charge holding units MEM1LB and MEM1SB are arranged in the first direction DIR1 (rightward in FIG. 21) relative to the photoelectric conversion unit PDB.

[0176] In this embodiment, when the distance between the optical center 103 and the centroid position MEM1LA-G in the plan view of the pixel of interest is L1, and the distance between the optical center 103 and the centroid position MEM2LA-G is L2, it is configured such that L1 < L2. Also, when the distance between the optical center 103 and the centroid position MEM1LB-G in the plan view is L1, and the distance between the optical center 103 and the centroid position MEM2LB-G is L2, it is configured such that L1 < L2. Further, when the distance between the optical center 103 and the centroid position MEM1SA-G in the plan view is L1, and the distance between the optical center 103 and the centroid position MEM2SA-G is L2, it is configured such that L1 < L2. Additionally, when the distance between the optical center 103 and the centroid position MEM1SB-G in the plan view is L1, and the distance between the optical center 103 and the centroid position MEM2SB-G is L2, it is configured such that L1 < L2.

[0177] Also, when the distance between the centroid position MEM1LA-G and the optical center 110 of the adjacent pixel on the left in the plan view is L3, and the distance between the centroid position MEM2LA-G and the optical center 110 of the adjacent pixel on the left is L4, it is configured such that L3 < L4. Further, when the distance between the centroid position MEM1SA-G and the optical center 110 of the adjacent pixel on the left in the plan view is L3, and the distance between the centroid position MEM2SA-G and the optical center 110 of the adjacent pixel on the left is L4, it is configured such that L3 < L4.

[0178] Also, when the distance between the centroid position MEM1LB-G and the optical center 111 of the adjacent pixel on the right in the plan view is L3, and the distance between the centroid position MEM2LB-G and the optical center 111 of the adjacent pixel on the right is L4, it is configured such that L3 < L4. Additionally, when the distance between the centroid position MEM1SB-G and the optical center 111 of the adjacent pixel on the right in the plan view is L3, and the distance between the centroid position MEM2SB-G and the optical center 111 of the adjacent pixel on the right is L4, it is configured such that L3 < L4.

[0179] As already explained, the charge retention units MEM1LA, MEM1LB, MEM1SA, and MEM1SB are used to retain the signal charge generated in the photoelectric conversion unit during the period of the Nth frame only for the Nth frame. Also, the charge retention units MEM2LA, MEM2LB, MEM2SA, and MEM2SB are used to retain the signal charge of the (N-1)th frame while the Nth frame is being captured, until the signal charge acquired in the previous frame, the (N-1)th frame, is transferred to the floating diffusion unit and read out through amplification transistor M4.

[0180] For example, consider a case where, during the Nth frame, pixel PIX1 receives stronger light than during the (N-1)th frame. Some of the strong light incident on the photoelectric conversion unit PDA or PDB of pixel PIX1 may diffract within the semiconductor and leak out of the photoelectric conversion unit as stray light. If the semiconductor configuration allows such stray light to easily reach the charge storage units MEM2LA, MEM2LB, MEM2SA, and MEM2SB, photocharges due to the stray light are generated in these charge storage units and superimposed on the signal charge from the previous frame. In other words, some of the photocharge from the current frame that should not have been added is added to the signal charge acquired in the previous frame and stored in these charge storage units, resulting in a type of crosstalk between frames.

[0181] Alternatively, when strong light is incident on an adjacent pixel adjacent to the pixel of interest in the first direction DIR1 during the period of the Nth frame, a part of the strong light incident on the photoelectric conversion unit PDA or the photoelectric conversion unit PDB of the adjacent pixel may diffract in the semiconductor and leak out as stray light outside the photoelectric conversion unit. Assuming that such stray light is likely to reach the charge holding unit MEM2LA, the charge holding unit MEM2LB, the charge holding unit MEM2SA, and the charge holding unit MEM2SB of the pixel of interest, photoelectrons due to the stray light can be generated in these charge holding units. Then, since a part of the photoelectrons generated during the period of the current frame is added to the signal electrons acquired in the previous frame held by these charge holding units, a kind of cross-talk occurs between frames.

[0182] The stray light exponentially decays according to the distance it travels in the semiconductor. However, according to this embodiment, it is configured such that L1 < L2. For this reason, the stray light leaking from the photoelectric conversion unit of the pixel of interest is unlikely to reach these charge holding units. Furthermore, according to this embodiment, since it is configured such that L3 < L4, the stray light leaking from the photoelectric conversion unit of the adjacent pixel adjacent in the first direction DIR1 is unlikely to reach these charge holding units of the pixel of interest.

[0183] Therefore, according to the photoelectric conversion device according to this embodiment, when capturing a moving image in the global shutter operation, the image of the frame that is temporally previous is less likely to be affected by the image of the frame that is temporally subsequent, so that a high-quality moving image can be acquired.

[0184] 20, the charge retention units MEM1LA and MEM1LB, the charge retention units MEM2LA and MEM2LB, the charge retention units MEM1SA and MEM1SB, and the charge retention units MEM2SA and MEM2SB are each arranged symmetrically with respect to the optical center 103. In other words, the charge retention units are arranged so as to be line-symmetric with respect to a line that passes through the optical center of the photoelectric conversion unit and is perpendicular to the first direction. However, the arrangement of the elements is not limited to this, and they may be arranged, for example, point-symmetric with respect to the optical center 103, as long as they are arranged at a distance that makes it difficult for light leaking from the photoelectric conversion unit to reach the charge retention unit MEM2. This makes it easy to align the signal characteristics during long-second accumulation and short-second accumulation.

[0185] [Embodiment 5] As embodiment 5, a device including a semiconductor device (photoelectric conversion device) according to any of the above-described embodiments will be described. Fig. 22(a) is a schematic diagram for explaining a device 9191 including a semiconductor device 930 (photoelectric conversion device) according to the above-described embodiment. The device 9191 including the semiconductor device 930 will be described in detail.

[0186] The semiconductor device 930 includes a semiconductor device 910 in which a first chip serving as a photoelectric conversion device and a second chip including at least one of a memory circuit and a logic circuit are integrated. The semiconductor device 930 can also include a package 920 that houses the semiconductor device 910, in addition to the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0187] The device 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror provided in correspondence with the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0188] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0189] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0190] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0191] The device 9191 may also be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot. According to the above-described embodiment, heat is efficiently dissipated from the image sensor chip, making it possible to stably acquire images with good characteristics.

[0192] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in transportation equipment, excellent performance can be obtained when photographing the exterior of the transportation equipment or measuring the external environment. Therefore, when manufacturing and selling transportation equipment, deciding to install the semiconductor device according to this embodiment in the transportation equipment is advantageous in improving the performance of the transportation equipment itself. In particular, the semiconductor device 930 is suitable for transportation equipment that performs driving assistance and / or automatic driving using information obtained by the semiconductor device. Note that the application to vehicles, ships, aircraft, etc. is not limited to equipment used for transportation purposes, and can also be suitable for drones and the like that perform aerial photography for various purposes, including inspecting buildings and agricultural facilities and monitoring natural phenomena.

[0193] The photoelectric conversion system and moving object of this embodiment will be described with reference to FIGS. 22(b) and 22(c). FIG. 22(b) illustrates an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device serving as an electronic component described in the above embodiment. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. In other words, the distance information includes information related to the parallax, the amount of defocus, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, or may be realized by a software module. It may also be realized by an FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like.

[0194] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0195] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 22(c) shows a photoelectric conversion system for capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0196] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0197] According to the photoelectric conversion device of the above-described embodiment, when capturing moving images using global shutter operation, the image of a later frame is less likely to be affected by the image of an earlier frame, making it possible to stably obtain images with good characteristics.

[0198] The equipment according to the present embodiment may include at least one of an optical device corresponding to the semiconductor device according to any of the above-described embodiments, a control device for controlling the semiconductor device, and a processing device for processing information obtained from the semiconductor device, or may include at least one of a display device for displaying information obtained from the semiconductor device, a storage device for storing information obtained from the semiconductor device, and a mechanical device that operates based on information obtained from the semiconductor device.

[0199] [Other embodiments] The present invention is not limited to the above-described embodiments, and many modifications are possible within the technical spirit of the present invention. For example, the above-described different embodiments and examples may be combined in whole or in part.

[0200] The photoelectric conversion devices described in the embodiments are not limited to being used exclusively for imaging, but may also be used as distance measuring devices (devices for measuring distance using focus detection or TOF (Time Of Flight)), photometry devices (devices for measuring the amount of incident light, etc.), etc.

[0201] The photoelectric conversion device to which the present invention can be applied is not limited to a specific form, and may be, for example, a front-illuminated sensor or a back-illuminated sensor. It may also be a stacked photoelectric conversion device in which a semiconductor chip having a light receiving unit and a semiconductor chip having an electric circuit such as a logic circuit are stacked.

[0202] The present invention can also be realized by supplying a program that realizes one or more functions of the embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0203] This specification discloses at least the following: [Matter 1] A photoelectric conversion device with a global shutter method that includes a plurality of pixels two-dimensionally arranged on a semiconductor substrate and performs the photoelectric conversion operations of the plurality of pixels in the same period, Each of the plurality of pixels includes a photoelectric conversion unit, a first transfer unit, a first charge holding unit, a second transfer unit, a second charge holding unit, a third transfer unit, and a signal output unit, In each of the plurality of pixels, the charges generated by the photoelectric conversion unit are transferred to the first charge holding unit by the first transfer unit, the charges held in the first charge holding unit are transferred to the second charge holding unit by the second transfer unit, and the charges held in the second charge holding unit are transferred to the signal output unit by the third transfer unit, The plurality of pixels includes a first pixel and a second pixel adjacent in a first direction, In the first pixel, the first charge holding unit is arranged in the first direction with respect to the photoelectric conversion unit, In the first pixel, when the distance from the optical center of the photoelectric conversion unit to the centroid of the first charge holding unit is L1 and the distance from the optical center of the photoelectric conversion unit to the centroid of the second charge holding unit is L, the photoelectric conversion unit, the first charge holding unit, and the second charge holding unit are arranged so as to satisfy L1 < L2, When the distance from the optical center of the photoelectric conversion unit of the second pixel to the centroid of the first charge holding unit of the first pixel is L3 and the distance from the optical center of the photoelectric conversion unit of the second pixel to the centroid of the second charge holding unit of the first pixel is L4, the photoelectric conversion unit of the second pixel, the first charge holding unit of the first pixel, and the second charge holding unit of the first pixel are arranged so as to satisfy L3 < L4. A photoelectric conversion device characterized by this. [Item 2] The photoelectric conversion unit included in each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit arranged along the first direction, Each of the plurality of pixels further includes a fourth transfer unit, a third charge holding unit, a fifth transfer unit, a fourth charge holding unit, and a sixth transfer unit, The plurality of pixels include a third pixel adjacent to the first pixel on the side opposite to the second pixel in the first direction. In each of the plurality of pixels, The charges generated in the first photoelectric conversion unit are transferred to the first charge holding unit by the first transfer unit, the charges held in the first charge holding unit are transferred to the second charge holding unit by the second transfer unit, and the charges held in the second charge holding unit are transferred to the signal output unit by the third transfer unit. The charges generated in the second photoelectric conversion unit are transferred to the third charge holding unit by the fourth transfer unit, the charges held in the third charge holding unit are transferred to the fourth charge holding unit by the fifth transfer unit, and the charges held in the fourth charge holding unit are transferred to the signal output unit by the sixth transfer unit. In the first pixel, the first charge holding unit is arranged in the first direction with respect to the photoelectric conversion unit. When the distance from the first optical center, which is the optical center of the photoelectric conversion unit, to the center of gravity of the first charge holding unit is L1, and the distance from the first optical center to the center of gravity of the second charge holding unit is L2, the photoelectric conversion unit, the first charge holding unit, and the second charge holding unit of the first pixel are arranged so as to satisfy L1 < L2. In the first pixel, the third charge holding unit is arranged in the first direction with respect to the photoelectric conversion unit. When the distance from the first optical center to the center of gravity of the third charge holding unit is L1, and the distance from the first optical center to the center of gravity of the fourth charge holding unit is L2, the photoelectric conversion unit, the third charge holding unit, and the fourth charge holding unit of the first pixel are arranged so as to satisfy L1 < L2. When the distance from the second optical center, which is the optical center of the photoelectric conversion unit of the second pixel, to the center of gravity of the first charge holding unit of the first pixel is L3, and the distance from the second optical center to the center of gravity of the second charge holding unit of the first pixel is L4, the photoelectric conversion unit of the second pixel, the first charge holding unit of the first pixel, and the second charge holding unit of the first pixel are arranged so as to satisfy L3 < L4. When the distance from the third optical center, which is the optical center of the photoelectric conversion unit of the third pixel, to the centroid of the third charge holding unit of the first pixel is L3, and the distance from the third optical center to the centroid of the fourth charge holding unit of the first pixel is L4, the photoelectric conversion unit of the third pixel, the third charge holding unit of the first pixel, and the fourth charge holding unit of the first pixel are arranged so as to satisfy L3 < L4. The photoelectric conversion device according to item 1, characterized by this. [Item 3] In each of the plurality of pixels, The first charge holding unit and the third charge holding unit are arranged symmetrically with respect to a line passing through the optical center of the photoelectric conversion unit and perpendicular to the first direction, or are arranged point-symmetrically with respect to the optical center. The second charge holding unit and the fourth charge holding unit are arranged symmetrically with respect to the line, or are arranged point-symmetrically with respect to the optical center. The photoelectric conversion device according to item 2, characterized by this. [Item 4] Each of the plurality of pixels includes a microlens shared by the first photoelectric conversion unit and the second photoelectric conversion unit. The photoelectric conversion device according to item 2 or 3, characterized by this. [Item 5] Each of the plurality of pixels further includes a fourth transfer unit, a third charge holding unit, a fifth transfer unit, a fourth charge holding unit, and a sixth transfer unit. The plurality of pixels includes a third pixel adjacent to the first pixel on the side opposite to the second pixel in the first direction. In each of the plurality of pixels, the charges generated in the photoelectric conversion unit The charge transferred to the first charge holding part by the first transfer part and held in the first charge holding part is transferred to the second charge holding part by the second transfer part, and the charge held in the second charge holding part is transferred to the signal output part by the third transfer part or transferred to the third charge holding part by the fourth transfer part. The charge held in the third charge holding part is transferred to the fourth charge holding part by the fifth transfer part, and the charge held in the fourth charge holding part is transferred to the signal output part by the sixth transfer part. In the first pixel, the third charge holding part is arranged in the first direction with respect to the photoelectric conversion part. When the distance from the optical center of the photoelectric conversion part to the centroid of the third charge holding part is L1 and the distance from the optical center of the photoelectric conversion part to the centroid of the fourth charge holding part is L2, the photoelectric conversion part, the third charge holding part, and the fourth charge holding part of the first pixel are arranged so as to satisfy L1 < L2. When the distance from the optical center of the photoelectric conversion part of the third pixel to the centroid of the third charge holding part of the first pixel is L3 and the distance from the optical center of the photoelectric conversion part of the third pixel to the centroid of the fourth charge holding part of the first pixel is L4, the photoelectric conversion part of the third pixel, the third charge holding part of the first pixel, and the fourth charge holding part of the first pixel are arranged so as to satisfy L3 < L4. The photoelectric conversion device according to Item 1, characterized in that. [Item 6] In each of the plurality of pixels, The first charge holding part and the third charge holding part are arranged symmetrically with respect to a line passing through the optical center of the photoelectric conversion part and orthogonal to the first direction, or are arranged point-symmetrically with respect to the optical center. The second charge holding part and the fourth charge holding part are arranged symmetrically with respect to the line or are arranged point-symmetrically with respect to the optical center. The photoelectric conversion device according to Item 5, characterized in that. [Item 7] the photoelectric conversion unit included in each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit arranged along the first direction; each of the plurality of pixels further includes a fourth transfer unit, a third charge retention unit, a fifth transfer unit, a fourth charge retention unit, a sixth transfer unit, a second photoelectric conversion unit, a seventh transfer unit, a fifth charge retention unit, an eighth transfer unit, a sixth charge retention unit, a ninth transfer unit, a tenth transfer unit, a seventh charge retention unit, an eleventh transfer unit, an eighth charge retention unit, and a twelfth transfer unit; the plurality of pixels includes a third pixel adjacent to the first pixel on the opposite side to the second pixel in the first direction, In each of the plurality of pixels, the charge generated in the first photoelectric conversion unit is transferred to the first charge holding unit by the first transfer unit, the charge held in the first charge holding unit is transferred to the second charge holding unit by the second transfer unit, and the charge held in the second charge holding unit is transferred to the signal output unit by the third transfer unit, or the charge generated in the first photoelectric conversion unit is transferred to the third charge holding unit by the fourth transfer unit, the charge held in the third charge holding unit is transferred to the fourth charge holding unit by the fifth transfer unit, and the charge held in the fourth charge holding unit is transferred to the signal output unit by the sixth transfer unit; In each of the plurality of pixels, the charge generated in the second photoelectric conversion unit is transferred to the fifth charge holding unit by the seventh transfer unit, the charge held in the fifth charge holding unit is transferred to the sixth charge holding unit by the eighth transfer unit, and the charge held in the sixth charge holding unit is transferred to a second signal output unit different from the signal output unit by the ninth transfer unit, or the charge generated in the second photoelectric conversion unit is transferred to the seventh charge holding unit by the tenth transfer unit, the charge held in the seventh charge holding unit is transferred to the eighth charge holding unit by the eleventh transfer unit, and the charge held in the eighth charge holding unit is transferred to the second signal output unit by the twelfth transfer unit; In the first pixel, the third charge holding part is arranged in the first direction with respect to the photoelectric conversion part. When the distance from the optical center of the photoelectric conversion part to the centroid of the third charge holding part is L1 and the distance from the optical center of the photoelectric conversion part to the centroid of the fourth charge holding part is L2, the photoelectric conversion part, the third charge holding part, and the fourth charge holding part of the first pixel are arranged so as to satisfy L1 < L2. When the distance from the optical center of the photoelectric conversion part of the second pixel to the centroid of the third charge holding part of the first pixel is L3 and the distance from the optical center of the photoelectric conversion part of the second pixel to the centroid of the fourth charge holding part of the first pixel is L4, the photoelectric conversion part of the second pixel, the third charge holding part of the first pixel, and the fourth charge holding part of the first pixel are arranged so as to satisfy L3 < L4. In the first pixel, the fifth charge holding part is arranged in the first direction with respect to the photoelectric conversion part. When the distance from the optical center of the photoelectric conversion part to the centroid of the fifth charge holding part is L1 and the distance from the optical center of the photoelectric conversion part to the centroid of the sixth charge holding part is L2, the photoelectric conversion part, the fifth charge holding part, and the sixth charge holding part of the first pixel are arranged so as to satisfy L1 < L2. When the distance from the optical center of the photoelectric conversion part of the third pixel to the centroid of the fifth charge holding part of the first pixel is L3 and the distance from the optical center of the photoelectric conversion part of the third pixel to the centroid of the sixth charge holding part of the first pixel is L4, the photoelectric conversion part of the third pixel, the fifth charge holding part of the first pixel, and the sixth charge holding part of the first pixel are arranged so as to satisfy L3 < L4. In the first pixel, the seventh charge holding part is arranged in the first direction with respect to the photoelectric conversion part. When the distance from the optical center of the photoelectric conversion part to the centroid of the seventh charge holding part is L1 and the distance from the optical center of the photoelectric conversion part to the centroid of the eighth charge holding part is L2, the photoelectric conversion part, the seventh charge holding part, and the eighth charge holding part of the first pixel are arranged so as to satisfy L1 < L2. When the distance from the optical center of the photoelectric conversion unit included in the third pixel to the centroid of the seventh charge holding unit of the first pixel is L3, and the distance from the optical center of the photoelectric conversion unit included in the third pixel to the centroid of the eighth charge holding unit of the first pixel is L4, the photoelectric conversion unit of the third pixel, the seventh charge holding unit of the first pixel, and the eighth charge holding unit of the first pixel are arranged so as to satisfy L3 < L4. The photoelectric conversion device according to item 1, characterized in that. [Item 8] In each of the plurality of pixels, The first charge holding unit and the fifth charge holding unit are arranged symmetrically with respect to a line passing through the optical center of the photoelectric conversion unit and perpendicular to the first direction, or are arranged point-symmetrically with respect to the optical center. The second charge holding unit and the sixth charge holding unit are arranged symmetrically with respect to the line, or are arranged point-symmetrically with respect to the optical center. The third charge holding unit and the seventh charge holding unit are arranged symmetrically with respect to the line, or are arranged point-symmetrically with respect to the optical center. The fourth charge holding unit and the eighth charge holding unit are arranged symmetrically with respect to the line, or are arranged point-symmetrically with respect to the optical center. The photoelectric conversion device according to item 7, characterized in that. [Item 9] Each of the plurality of pixels includes a microlens shared by the first photoelectric conversion unit and the second photoelectric conversion unit. The photoelectric conversion device according to item 7 or 8, characterized in that. [Item 10] When imaging an image of one frame, The signal charge generated by the photoelectric conversion unit in the current frame is transferred to the first charge holding unit via the first transfer unit, and after the signal charge of the previous frame held in the second charge holding unit is transferred to the signal output unit via the third transfer unit, the signal charge of the current frame held in the first charge holding unit is transferred to the second charge holding unit via the second transfer unit. 2. The photoelectric conversion device according to item 1, [Matter 11] When capturing one frame of image, transferring signal charges generated in the first photoelectric conversion unit in a current frame to the first charge holding unit via the first transfer unit, transferring signal charges of the previous frame held in the second charge holding unit via the third transfer unit to the signal output unit, and then transferring signal charges of the current frame held in the first charge holding unit to the second charge holding unit via the second transfer unit; transferring signal charges generated in the second photoelectric conversion unit in the current frame to the third charge holding unit via the fourth transfer unit, transferring signal charges of the previous frame held in the fourth charge holding unit to the signal output unit via the sixth transfer unit, and then transferring signal charges of the current frame held in the third charge holding unit to the fourth charge holding unit via the fifth transfer unit; 5. The photoelectric conversion device according to any one of items 2 to 4, [Matter 12] When capturing one frame of image, transferring signal charges generated in the photoelectric conversion unit during a first period of a current frame to the first charge holding unit via the first transfer unit, transferring signal charges of the immediately preceding frame held in the second charge holding unit via the third transfer unit to the signal output unit, and then transferring signal charges of the current frame held in the first charge holding unit to the second charge holding unit via the second transfer unit; transferring signal charges generated in the photoelectric conversion unit during a second period of a current frame to the third charge holding unit via the fourth transfer unit, transferring signal charges of the previous frame held in the fourth charge holding unit to the signal output unit via the sixth transfer unit, and then transferring signal charges of the current frame held in the third charge holding unit to the fourth charge holding unit via the fifth transfer unit; 7. The photoelectric conversion device according to item 5 or 6. [Matter 13] The first period and the second period have different lengths. 13. The photoelectric conversion device according to item 12. [Matter 14] a light-shielding portion is provided around at least a portion of the periphery of the first charge retention portion and / or the second charge retention portion; 14. The photoelectric conversion device according to any one of items 1 to 13, [Matter 15] Each of the plurality of pixels includes a microlens and a waveguide disposed between the microlens and the photoelectric conversion unit. 15. The photoelectric conversion device according to any one of items 1 to 14. [Matter 16] Each of the plurality of pixels includes a charge drain transistor that resets the photoelectric conversion unit. 16. The photoelectric conversion device according to any one of items 1 to 15, [Matter 17] A semiconductor chip having an electric circuit is stacked on the semiconductor substrate. 17. The photoelectric conversion device according to any one of items 1 to 16, [Matter 18] each of the plurality of pixels is a back-illuminated sensor including a microlens and a wiring layer disposed on the opposite side of the photoelectric conversion unit from the microlens; 18. The photoelectric conversion device according to any one of items 1 to 17, [Matter 19] The photoelectric conversion device according to any one of items 1 to 18, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes information obtained from the photoelectric conversion device; a display device that displays information obtained from the photoelectric conversion device; a storage device that stores information obtained from the photoelectric conversion device; and a mechanical device that operates based on information obtained from the photoelectric conversion device; and at least one of the six: The device characterized by: [Explanation of symbols]

[0204] 1···Photoelectric conversion device / 10··Pixel unit / 12··Pixel / 14··Control line / 16··Vertical output line / 20··Vertical scanning circuit / 30··Readout circuit / 40··Horizontal scanning circuit / 50··Output circuit / 60··Control circuit / 103··Optical center / 110··Optical center of adjacent pixel / DIR1··First direction / FD··Floating diffusion region / M1, M2, M3··Transfer transistor / M4··Amplification transistor / M5··Selection transistor / M6··Charge discharge transistor / M7··Reset transistor / PD··Photoelectric conversion unit / MEM1··Charge storage unit / MEM2··Charge storage unit / MEM1-G··Center of gravity of charge storage unit MEM1 in plan view / MEM2-G··Center of gravity of charge storage unit MEM2 in plan view / PIX1··Pixel

Claims

1. A global shutter type photoelectric conversion device comprising a plurality of pixels two-dimensionally arranged on a semiconductor substrate, the photoelectric conversion operations of the plurality of pixels being performed in the same period, each of the plurality of pixels includes a photoelectric conversion unit, a first transfer unit, a first charge holding unit, a second transfer unit, a second charge holding unit, a third transfer unit, and a signal output unit; In each of the plurality of pixels, the charge generated in the photoelectric conversion unit is transferred to the first charge holding unit by the first transfer unit, the charge held in the first charge holding unit is transferred to the second charge holding unit by the second transfer unit, and the charge held in the second charge holding unit is transferred to the signal output unit by the third transfer unit, the plurality of pixels include a first pixel and a second pixel adjacent to each other in a first direction, In the first pixel, the first charge holding unit is disposed in the first direction with respect to the photoelectric conversion unit; in the first pixel, when a distance from an optical center of the photoelectric conversion unit to a center of gravity of the first charge retention unit is L1 and a distance from the optical center of the photoelectric conversion unit to a center of gravity of the second charge retention unit is L2, the photoelectric conversion unit, the first charge retention unit, and the second charge retention unit are arranged so as to satisfy L1<L2; where L3 is a distance from the optical center of the photoelectric conversion unit of the second pixel to the center of gravity of the first charge retention unit of the first pixel, and L4 is a distance from the optical center of the photoelectric conversion unit of the second pixel to the center of gravity of the second charge retention unit of the first pixel, the photoelectric conversion unit of the second pixel, the first charge retention unit of the first pixel, and the second charge retention unit of the first pixel are arranged so as to satisfy L3<L4. A photoelectric conversion device characterized by:

2. the photoelectric conversion unit included in each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit arranged along the first direction; each of the plurality of pixels further includes a fourth transfer unit, a third charge holding unit, a fifth transfer unit, a fourth charge holding unit, and a sixth transfer unit; the plurality of pixels includes a third pixel adjacent to the first pixel on the opposite side to the second pixel in the first direction, In each of the plurality of pixels, the charges generated in the first photoelectric conversion unit are transferred to the first charge holding unit by the first transfer unit, the charges held in the first charge holding unit are transferred to the second charge holding unit by the second transfer unit, and the charges held in the second charge holding unit are transferred to the signal output unit by the third transfer unit; the charges generated in the second photoelectric conversion unit are transferred to the third charge holding unit by the fourth transfer unit, the charges held in the third charge holding unit are transferred to the fourth charge holding unit by the fifth transfer unit, and the charges held in the fourth charge holding unit are transferred to the signal output unit by the sixth transfer unit; In the first pixel, the first charge holding portion is disposed in the first direction relative to the photoelectric conversion portion, and when a distance from a first optical center that is an optical center of the photoelectric conversion portion to a center of gravity of the first charge holding portion is L1 and a distance from the first optical center to the center of gravity of the second charge holding portion is L2, the photoelectric conversion portion, the first charge holding portion, and the second charge holding portion of the first pixel are disposed so as to satisfy L1<L2; in the first pixel, the third charge holding portion is disposed in the first direction relative to the photoelectric conversion portion, and when a distance from the first optical center to a center of gravity of the third charge holding portion is L1 and a distance from the first optical center to a center of gravity of the fourth charge holding portion is L2, the photoelectric conversion portion, the third charge holding portion, and the fourth charge holding portion of the first pixel are disposed so as to satisfy L1<L2; when a distance from a second optical center, which is the optical center of the photoelectric conversion unit of the second pixel, to a center of gravity of the first charge retention unit of the first pixel is L3 and a distance from the second optical center to the center of gravity of the second charge retention unit of the first pixel is L4, the photoelectric conversion unit of the second pixel, the first charge retention unit of the first pixel, and the second charge retention unit of the first pixel are arranged so as to satisfy L3<L4, where L3 is a distance from a third optical center, which is the optical center of the photoelectric conversion unit of the third pixel, to a center of gravity of the third charge retention unit of the first pixel, and L4 is a distance from the third optical center to the center of gravity of the fourth charge retention unit of the first pixel, the photoelectric conversion unit of the third pixel, the third charge retention unit of the first pixel, and the fourth charge retention unit of the first pixel are arranged so as to satisfy L3<L4.

2. The photoelectric conversion device according to claim 1.

3. In each of the plurality of pixels, the first charge retention unit and the third charge retention unit are arranged in line symmetry with respect to a line that passes through an optical center of the photoelectric conversion unit and is orthogonal to the first direction, or are arranged in point symmetry with respect to the optical center, the second charge retention portion and the fourth charge retention portion are arranged in line symmetry with respect to the line or in point symmetry with respect to the optical center; 3. The photoelectric conversion device according to claim 2.

4. each of the plurality of pixels includes a microlens shared by the first photoelectric conversion unit and the second photoelectric conversion unit; 3. The photoelectric conversion device according to claim 2.

5. each of the plurality of pixels further includes a fourth transfer unit, a third charge holding unit, a fifth transfer unit, a fourth charge holding unit, and a sixth transfer unit; the plurality of pixels includes a third pixel adjacent to the first pixel on the opposite side to the second pixel in the first direction, In each of the plurality of pixels, the charge generated in the photoelectric conversion unit is the charges are transferred to the first charge holding unit by the first transfer unit, the charges held in the first charge holding unit are transferred to the second charge holding unit by the second transfer unit, the charges held in the second charge holding unit are transferred to the signal output unit by the third transfer unit or are transferred to the third charge holding unit by the fourth transfer unit, the charges held in the third charge holding unit are transferred to the fourth charge holding unit by the fifth transfer unit, and the charges held in the fourth charge holding unit are transferred to the signal output unit by the sixth transfer unit; In the first pixel, the third charge holding portion is disposed in the first direction relative to the photoelectric conversion portion, and when a distance from an optical center of the photoelectric conversion portion to a center of gravity of the third charge holding portion is L1 and a distance from the optical center of the photoelectric conversion portion to a center of gravity of the fourth charge holding portion is L2, the photoelectric conversion portion, the third charge holding portion, and the fourth charge holding portion of the first pixel are disposed so as to satisfy L1<L2; where L3 is a distance from the optical center of the photoelectric conversion unit in the third pixel to the center of gravity of the third charge retention unit in the first pixel, and L4 is a distance from the optical center of the photoelectric conversion unit in the third pixel to the center of gravity of the fourth charge retention unit in the first pixel, the photoelectric conversion unit of the third pixel, the third charge retention unit of the first pixel, and the fourth charge retention unit of the first pixel are arranged so as to satisfy L3<L4.

2. The photoelectric conversion device according to claim 1.

6. In each of the plurality of pixels, the first charge retention unit and the third charge retention unit are arranged in line symmetry with respect to a line that passes through an optical center of the photoelectric conversion unit and is orthogonal to the first direction, or are arranged in point symmetry with respect to the optical center, the second charge retention portion and the fourth charge retention portion are arranged in line symmetry with respect to the line or in point symmetry with respect to the optical center; 6. The photoelectric conversion device according to claim 5.

7. the photoelectric conversion unit included in each of the plurality of pixels includes a first photoelectric conversion unit and a second photoelectric conversion unit arranged along the first direction; each of the plurality of pixels further includes a fourth transfer unit, a third charge retention unit, a fifth transfer unit, a fourth charge retention unit, a sixth transfer unit, a second photoelectric conversion unit, a seventh transfer unit, a fifth charge retention unit, an eighth transfer unit, a sixth charge retention unit, a ninth transfer unit, a tenth transfer unit, a seventh charge retention unit, an eleventh transfer unit, an eighth charge retention unit, and a twelfth transfer unit; the plurality of pixels includes a third pixel adjacent to the first pixel on the opposite side to the second pixel in the first direction, In each of the plurality of pixels, the charge generated in the first photoelectric conversion unit is transferred to the first charge holding unit by the first transfer unit, the charge held in the first charge holding unit is transferred to the second charge holding unit by the second transfer unit, and the charge held in the second charge holding unit is transferred to the signal output unit by the third transfer unit, or the charge generated in the first photoelectric conversion unit is transferred to the third charge holding unit by the fourth transfer unit, the charge held in the third charge holding unit is transferred to the fourth charge holding unit by the fifth transfer unit, and the charge held in the fourth charge holding unit is transferred to the signal output unit by the sixth transfer unit; In each of the plurality of pixels, the charge generated in the second photoelectric conversion unit is transferred to the fifth charge holding unit by the seventh transfer unit, the charge held in the fifth charge holding unit is transferred to the sixth charge holding unit by the eighth transfer unit, and the charge held in the sixth charge holding unit is transferred to a second signal output unit different from the signal output unit by the ninth transfer unit, or the charge generated in the second photoelectric conversion unit is transferred to the seventh charge holding unit by the tenth transfer unit, the charge held in the seventh charge holding unit is transferred to the eighth charge holding unit by the eleventh transfer unit, and the charge held in the eighth charge holding unit is transferred to the second signal output unit by the twelfth transfer unit, In the first pixel, the third charge holding portion is disposed in the first direction relative to the photoelectric conversion portion, and when a distance from an optical center of the photoelectric conversion portion to a center of gravity of the third charge holding portion is L1 and a distance from the optical center of the photoelectric conversion portion to a center of gravity of the fourth charge holding portion is L2, the photoelectric conversion portion, the third charge holding portion, and the fourth charge holding portion of the first pixel are disposed so as to satisfy L1<L2; when a distance from the optical center of the photoelectric conversion unit of the second pixel to a center of gravity of the third charge retention unit of the first pixel is L3 and a distance from the optical center of the photoelectric conversion unit of the second pixel to a center of gravity of the fourth charge retention unit of the first pixel is L4, the photoelectric conversion unit of the second pixel, the third charge retention unit of the first pixel, and the fourth charge retention unit of the first pixel are arranged so as to satisfy L3<L4, in the first pixel, the fifth charge holding portion is disposed in the first direction relative to the photoelectric conversion portion, and when a distance from an optical center of the photoelectric conversion portion to a center of gravity of the fifth charge holding portion is L1 and a distance from the optical center of the photoelectric conversion portion to a center of gravity of the sixth charge holding portion is L2, the photoelectric conversion portion, the fifth charge holding portion, and the sixth charge holding portion of the first pixel are disposed so as to satisfy L1<L2; when a distance from the optical center of the photoelectric conversion unit in the third pixel to a center of gravity of the fifth charge retention unit in the first pixel is defined as L3 and a distance from the optical center of the photoelectric conversion unit in the third pixel to a center of gravity of the sixth charge retention unit in the first pixel is defined as L4, the photoelectric conversion unit of the third pixel, the fifth charge retention unit of the first pixel, and the sixth charge retention unit of the first pixel are arranged so as to satisfy L3<L4, in the first pixel, the seventh charge holding portion is disposed in the first direction relative to the photoelectric conversion portion, and when a distance from an optical center of the photoelectric conversion portion to a center of gravity of the seventh charge holding portion is L1 and a distance from the optical center of the photoelectric conversion portion to the center of gravity of the eighth charge holding portion is L2, the photoelectric conversion portion, the seventh charge holding portion, and the eighth charge holding portion of the first pixel are disposed so as to satisfy L1<L2; where L3 is a distance from the optical center of the photoelectric conversion unit in the third pixel to the center of gravity of the seventh charge retention unit of the first pixel, and L4 is a distance from the optical center of the photoelectric conversion unit in the third pixel to the center of gravity of the eighth charge retention unit of the first pixel, the photoelectric conversion unit of the third pixel, the seventh charge retention unit of the first pixel, and the eighth charge retention unit of the first pixel are arranged so as to satisfy L3<L4.

2. The photoelectric conversion device according to claim 1.

8. In each of the plurality of pixels, the first charge retention unit and the fifth charge retention unit are arranged in line symmetry with respect to a line that passes through an optical center of the photoelectric conversion unit and is orthogonal to the first direction, or are arranged in point symmetry with respect to the optical center, the second charge holding portion and the sixth charge holding portion are arranged in line symmetry with respect to the line or in point symmetry with respect to the optical center, the third charge holding portion and the seventh charge holding portion are arranged in line symmetry with respect to the line or in point symmetry with respect to the optical center, the fourth charge holding portion and the eighth charge holding portion are arranged in line symmetry with respect to the line or in point symmetry with respect to the optical center; 8. The photoelectric conversion device according to claim 7.

9. each of the plurality of pixels includes a microlens shared by the first photoelectric conversion unit and the second photoelectric conversion unit; 8. The photoelectric conversion device according to claim 7.

10. When capturing one frame of image, transferring signal charges generated in the photoelectric conversion unit in the current frame to the first charge holding unit via the first transfer unit, transferring signal charges of the previous frame held in the second charge holding unit via the third transfer unit to the signal output unit, and then transferring signal charges of the current frame held in the first charge holding unit to the second charge holding unit via the second transfer unit; 2. The photoelectric conversion device according to claim 1.

11. When capturing one frame of image, transferring signal charges generated in the first photoelectric conversion unit in a current frame to the first charge holding unit via the first transfer unit, transferring signal charges of the previous frame held in the second charge holding unit via the third transfer unit to the signal output unit, and then transferring signal charges of the current frame held in the first charge holding unit to the second charge holding unit via the second transfer unit; transferring signal charges generated in the second photoelectric conversion unit in the current frame to the third charge holding unit via the fourth transfer unit, transferring signal charges of the previous frame held in the fourth charge holding unit to the signal output unit via the sixth transfer unit, and then transferring signal charges of the current frame held in the third charge holding unit to the fourth charge holding unit via the fifth transfer unit; 3. The photoelectric conversion device according to claim 2.

12. When capturing one frame of image, transferring signal charges generated in the photoelectric conversion unit during a first period of a current frame to the first charge holding unit via the first transfer unit, transferring signal charges of the previous frame held in the second charge holding unit via the third transfer unit to the signal output unit, and then transferring signal charges of the current frame held in the first charge holding unit to the second charge holding unit via the second transfer unit; transferring signal charges generated in the photoelectric conversion unit during a second period of the current frame to the third charge holding unit via the fourth transfer unit, transferring signal charges of the previous frame held in the fourth charge holding unit to the signal output unit via the sixth transfer unit, and then transferring signal charges of the current frame held in the third charge holding unit to the fourth charge holding unit via the fifth transfer unit; 6. The photoelectric conversion device according to claim 5.

13. The first period and the second period have different lengths.

13. The photoelectric conversion device according to claim 12.

14. a light-shielding portion is provided around at least a portion of the periphery of the first charge retention portion and / or the second charge retention portion; 14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

15. Each of the plurality of pixels includes a microlens and a waveguide disposed between the microlens and the photoelectric conversion unit.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

16. Each of the plurality of pixels includes a charge drain transistor that resets the photoelectric conversion unit.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

17. A semiconductor chip having an electric circuit is stacked on the semiconductor substrate.

14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

18. each of the plurality of pixels is a back-illuminated sensor including a microlens and a wiring layer disposed on the opposite side of the photoelectric conversion unit from the microlens; 14. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

19. The photoelectric conversion device according to any one of claims 1 to 13, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes information obtained from the photoelectric conversion device; a display device that displays information obtained from the photoelectric conversion device; a storage device that stores information obtained from the photoelectric conversion device; and a mechanical device that operates based on information obtained from the photoelectric conversion device; and at least one of the following six: The device characterized by:

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