Imaging device

Abstract

To miniaturize an imaging device having an AD conversion part in each column.SOLUTION: An imaging device includes a first photoelectric conversion part; a second photoelectric conversion part arranged adjacent to the first photoelectric conversion part in a first direction; a first signal line having a first part extending in a second direction, to which a first signal based on charge converted by the first photoelectric conversion part is outputted, a second part extending in the first direction, and a third part extending in the second direction; a second signal line having a fourth part extending in the second direction, to which a second signal based on charge converted by the second photoelectric conversion part is outputted, a fifth part extending in the first direction, and a sixth part extending in the second direction; first wiring extending in the second direction, to which a predetermined voltage is supplied, and arranged between the first part and the fourth part; second wiring extending in the second direction, to which the predetermined voltage is supplied, and arranged between the third part and the sixth part; a first processing part for performing signal processing for the first signal; and a second processing part for performing signal processing for the second signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an imaging device. This application claims priority based on Japanese Patent Application No. 2020-173026, filed on October 14, 2020, the contents of which are incorporated herein by reference. [Background technology]

[0002] There is a known image sensor that has an AD conversion unit for each column. There has been a strong demand for miniaturization of image sensors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-197940 Summary of the Invention

[0004] According to a first aspect, an imaging element includes a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and that is disposed adjacent to the first photoelectric conversion unit in a first direction, a signal line that outputs a first signal based on the electric charges converted by the first photoelectric conversion unit, the first signal line having a first portion extending along a second direction intersecting the first direction, a second portion extending in the first direction, and a third portion extending along the second direction, a signal line that outputs a second signal based on the electric charges converted by the second photoelectric conversion unit, the signal line having a fourth portion extending along the second direction, and a fourth portion extending in the first direction. a second signal line having a fifth portion extending in the first direction and a sixth portion extending along the second direction; a first wiring to which a predetermined voltage is supplied, the first wiring being arranged between the first portion and the fourth portion in the first direction and extending in the second direction; a second wiring to which a predetermined voltage is supplied and which is provided separately from the first wiring, the second wiring being arranged between the third portion and the sixth portion in the first direction and extending in the second direction; a first processing unit that performs signal processing on the first signal output to the first signal line; and a second processing unit that performs signal processing on the second signal output to the second signal line. [Brief explanation of the drawings]

[0005] [Figure 1] 1 is a diagram illustrating an example of the configuration of an imaging device according to a first embodiment. [Figure 2] 1 is a block diagram showing an example of the configuration of an imaging element according to a first embodiment. [Figure 3] 1 is a diagram illustrating an example of the configuration of a portion of an imaging element according to a first embodiment. [Figure 4] FIG. 2 is a diagram showing an example of a layout of a part of an imaging element according to the first embodiment. [Figure 5] FIG. 10 is a diagram illustrating an example of the configuration of a portion of an imaging element according to a comparative example. [Figure 6] FIG. 10 is a diagram illustrating an example of the configuration of a portion of an imaging element according to a modified example. [Figure 7] FIG. 10 is a diagram illustrating an example of the configuration of a portion of an imaging element according to a modified example. [Figure 8] FIG. 10 is a diagram illustrating an example of the configuration of a portion of an imaging element according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0006] (First embodiment) 1 is a diagram showing an example of the configuration of a camera 1, which is an example of an imaging device according to a first embodiment. The camera 1 includes a photographing optical system (imaging optical system) 2, an image sensor 3, a control unit 4, a memory 5, a display unit 6, and an operation unit 7. The photographing optical system 2 has multiple lenses, including a focus adjustment lens (focus lens), and an aperture stop, and forms a subject image on the image sensor 3. The photographing optical system 2 may be detachable from the camera 1.

[0007] The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. The imaging element 3 receives a light beam that has passed through the photographing optical system 2 and captures an image of a subject formed by the photographing optical system 2. The imaging element 3 has a plurality of pixels, each having a photoelectric conversion unit, arranged two-dimensionally (in the row and column directions). The photoelectric conversion unit is composed of a photodiode (PD). The imaging element 3 photoelectrically converts the received light to generate a signal and outputs the generated signal to the control unit 4.

[0008] The memory 5 is a recording medium such as a memory card. Image data, control programs, etc. are recorded in the memory 5. Writing data to the memory 5 and reading data from the memory 5 are controlled by the control unit 4. The display unit 6 displays an image based on the image data, information related to shooting such as the shutter speed and aperture value, and a menu screen, etc. The operation unit 7 includes various setting switches such as a release button, a power switch, and switches for switching between various modes, and outputs signals to the control unit 4 based on the respective operations.

[0009] The control unit 4 is configured with a processor such as a CPU, FPGA, or ASIC, and memories such as a ROM or RAM, and controls each unit of the camera 1 based on a control program. The control unit 4 supplies a signal that controls the image sensor 3 to the image sensor 3, thereby controlling the operation of the image sensor 3. When taking a still image, taking a video, or displaying a through image (live view image) of the subject on the display unit 6, the control unit 4 causes the image sensor 3 to capture an image of the subject and output a signal.

[0010] The control unit 4 generates image data by performing various types of image processing on the signal output from the imaging element 3. The control unit 4 also functions as a generation unit 4 that generates image data, and generates still image data and moving image data based on the signal output from the imaging element 3. The image processing includes image processing such as tone conversion processing and color interpolation processing.

[0011] Next, the configuration of an image sensor 3 according to the present embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing an example configuration of an image sensor according to a first embodiment. The image sensor 3 is configured using a substrate (such as a semiconductor substrate) and has multiple layers including a wiring layer. Multiple wires, vias, and the like are formed in the wiring layer. As shown in FIG. 2, the image sensor 3 has a region 100 in which pixels 10 are arranged two-dimensionally, a region 120 in which a processing unit 50 that processes signals output from the pixels 10 is arranged, and a region 110 between the regions 100 and 120. Hereinafter, the region 100 will be referred to as the pixel region 100, the region 110 will be referred to as the intermediate region 110, and the region 120 will be referred to as the circuit region 120. Note that FIG. 2 shows an example of the arrangement of a portion of the image sensor 3, taking as an example a case in which the pixel pitch (the distance between pixels) is larger than the pitch of the processing unit 50.

[0012] In the pixel region 100, a plurality of pixels 10, each including a photoelectric conversion unit 11, are arranged in a horizontal direction (X-axis direction shown in FIG. 2), which is a first direction, and a vertical direction (Y-axis direction shown in FIG. 2), which is a second direction intersecting the first direction. In the pixel region 100, a vertical signal line 20 is provided for each of the plurality of pixels 10 arranged in the horizontal direction (row direction). It can also be said that a vertical signal line 20 is provided for a pixel column, which is a column of a plurality of pixels lined up in the vertical direction (column direction). The vertical signal line 20 is wired in the vertical direction in the pixel region 100. A current source 25 and a processing unit 50 are provided for the vertical signal line 20.

[0013] 3 is a diagram showing an example of the configuration of a portion of the image sensor according to the first embodiment. A pixel 10 has a photoelectric conversion unit 11, a transfer unit 12, a floating diffusion (FD) 13, a reset unit 14, an amplifier unit 15, and a selection unit 16. The photoelectric conversion unit 11 is a photodiode PD, which converts incident light into electric charges and accumulates the photoelectrically converted electric charges.

[0014] The transfer unit 12 is composed of a transistor M1 controlled by a signal TX, and transfers the charges photoelectrically converted by the photoelectric conversion unit 11 to the FD13. The transistor M1 is a transfer transistor. The FD13 accumulates (holds) the charges transferred to the FD13 and converts them into a voltage divided by a capacitance value. The FD13 is an accumulation unit 13, and accumulates the charges generated by the photoelectric conversion unit 11.

[0015] The amplifier unit 15 is composed of a transistor M3 whose gate (terminal) is connected to the FD13, and amplifies and outputs a signal based on the charge accumulated in the FD13. The drain (terminal) and source (terminal) of the transistor M3 are connected to a power supply VDD and a selection unit 16, respectively. The source of the amplifier unit 15 is connected to a vertical signal line 20 via the selection unit 16. The amplifier unit 15 functions as part of a source follower circuit, with a current source 25 as a load current source. The transistor M3 is an amplifying transistor. The amplifier unit 15 and the selection unit 16 constitute an output unit that generates and outputs a signal based on the charge generated by the photoelectric conversion unit 11.

[0016] The reset unit 14 is composed of a transistor M2 controlled by a signal RST, and resets the charge accumulated by the FD13. The reset unit 14 discharges the charge accumulated in the FD13 and resets the voltage of the FD13. The transistor M2 is a reset transistor. The selection unit 16 is composed of a transistor M4 controlled by a signal SEL, and electrically connects or disconnects the amplifier unit 15 and the vertical signal line 20. When the transistor M4 of the selection unit 16 is in an on state, it outputs a signal from the amplifier unit 15 to the vertical signal line 20. The transistor M4 is a selection transistor.

[0017] The current source 25 is connected to each pixel 10 via the vertical signal line 20. The current source 25 generates a current for reading out a signal from the pixel 10, and supplies the generated current to the vertical signal line 20 and each pixel 10. A current source 25 is provided for each vertical signal line 20, and multiple current sources 25 are arranged in the horizontal direction as shown in FIG.

[0018] As described above, the charges photoelectrically converted by the photoelectric conversion unit 11 are transferred to the FD 13 by the transfer unit 12. A signal (pixel signal) corresponding to the charges transferred to the FD 13 is output to the vertical signal line 20. The pixel signal output from the pixel 10 is an analog signal generated based on the charges photoelectrically converted by the photoelectric conversion unit 11.

[0019] In FIG. 2, the readout control unit 80 is provided in common to multiple pixels 10. The readout control unit 80 is composed of multiple circuits including a timing generator. The readout control unit 80 is controlled by the control unit 4 of the camera 1, and supplies signals such as the above-mentioned signal TX, signal RST, and signal SEL to each pixel 10 to control the operation of each pixel 10. The readout control unit 80 supplies signals to the gates of each transistor in the pixels 10 to turn the transistor on (connected state, conductive state, short-circuited state) or off (disconnected state, non-conductive state, open state, blocked state). The pixel signal of the pixel 10 selected by the readout control unit 80 is output to the vertical signal line 20 connected to that pixel 10.

[0020] In the circuit region 120, a plurality of processing units 50, each including an analog-to-digital conversion unit (AD conversion unit) 40, are arranged in the horizontal direction. A buffer 60 is arranged between each of the plurality of processing units 50 arranged in the horizontal direction (every four processing units 50 in FIG. 2). The horizontal sizes (dimensions) of the processing units 50 and the pixels 10 are different. In the example shown in FIG. 2, the width (horizontal width) of the pixel 10 is larger than the width (horizontal width) of the processing unit 50.

[0021] The processing unit 50 receives analog pixel signals from each pixel 10 via the vertical signal lines 20. The processing unit 50 may include an amplifier unit that amplifies the pixel signals received via the vertical signal lines 20 at a predetermined gain (amplification factor). In this case, the pixel signals amplified by the amplifier unit are input to the AD conversion unit 40. The counter 70 shown in FIG. 2 is provided in common to the multiple processing units 50. The counter 70 generates a clock signal indicating a count value and outputs the clock signal to each of the AD conversion units 40 arranged side by side in the horizontal direction.

[0022] The AD conversion unit 40 has a comparison unit 43 and a storage unit 45, and converts pixel signals input via the vertical signal lines 20 into digital signals with a predetermined number of bits. The comparison unit 43 includes a comparator circuit. The comparison unit 43 compares the signals output from the pixels 10 with a reference signal (ramp signal) that changes constantly over time, and outputs an output signal that is the comparison result to the storage unit 45.

[0023] The storage unit 45 is composed of a plurality of latch circuits corresponding to the number of bits of the digital signal to be stored. The storage unit 45 receives an output signal indicating the comparison result from the comparison unit 43 and a clock signal indicating the count value from the counter 70. Based on the output signal from the comparison unit 43 and the clock signal from the counter 70, the storage unit 45 stores, as a digital signal, a count value corresponding to the elapsed time from when the comparison by the comparison unit 43 starts until the comparison result is inverted. In other words, based on the signal output from the comparison unit 43, the storage unit 45 stores, as a digital signal, a count value corresponding to the time until the magnitude relationship between the level of the signal output from the pixel 10 and the level of the reference signal changes (is inverted).

[0024] The buffers 60 are provided between adjacent processing units 50. In the example shown in FIG. 2, a buffer 60 is provided for every four processing units 50, and the four processing units 50 and one buffer 60 are arranged alternately in the horizontal direction. A buffer 60 is provided for every four pixel columns. The buffer 60 buffers (amplifies) the clock signal output from the counter 70 and supplies the clock signal to the storage unit 45 of each AD conversion unit 40. In this way, the clock signal output from the counter 70 is transmitted to each storage unit 45 via the buffer 60, thereby suppressing delays in the clock signal and reductions in the signal level.

[0025] The processing unit 50 outputs the pixel signals converted into digital signals by the AD conversion unit 40 to a signal processing unit (not shown). The signal processing unit performs signal processing such as correlated double sampling and signal amount correction on the input pixel signals, and then outputs the processed pixel signals to the control unit 4.

[0026] 2, the image sensor 3 is provided with the above-mentioned vertical signal line 20, wiring 30 (wiring 30a, wiring 30b), and wiring 35. The vertical signal line 20 and wiring 30 are wired in the same layer among multiple layers of the image sensor 3. The wiring 35 has a width in the vertical direction and is arranged in a layer different from the layer in which the vertical signal line 20 and wiring 30 are wired. The wiring 35 is provided in at least one of a layer below or above the layer in which the vertical signal line 20 and wiring 30 are wired.

[0027] The wirings 30 are arranged to sandwich the vertical signal lines 20, and are supplied with a predetermined voltage (for example, a power supply voltage or a ground voltage). The wirings 30 are arranged between adjacent vertical signal lines 20, and it can also be said that the wirings 30 are arranged on both sides of the vertical signal lines 20. The wirings 30 function as shields by being arranged to sandwich the vertical signal lines 20. By providing the wirings (shield lines) 30, it is possible to prevent noise from being mixed into the pixel signals output to the vertical signal lines 20. Hereinafter, the wirings 30a will be referred to as the shield line 30a, and the wirings 30b will be referred to as the shield line 30b.

[0028] The shield lines 30a and 30b are each arranged in the same layer as the vertical signal lines 20. The shield line 30a extending in the vertical direction is arranged in the pixel region 100 and the intermediate region 110. The shield line 30b extending in the vertical direction is also arranged in the intermediate region 110. In the pixel region 100, the shield line 30a is arranged in the vertical direction and is adjacent to the vertical signal lines 20 in the horizontal direction. In the example shown in FIG. 2, the shield line 30a extends vertically into the intermediate region 110 and is arranged parallel to the vertical signal lines 20.

[0029] The shield line 30b is wired vertically in the intermediate region 110 and is adjacent to the vertical signal line 20 in the horizontal direction. In the example shown in FIG. 2, the shield line 30b is arranged parallel to the vertical signal line 20 and extends to a position near the processing unit 50. Note that the shield lines 30a and 30b do not contact each other in the layer in which the vertical signal line 20 is wired. As will be described later, the shield lines 30a and 30b are electrically connected to each other via wiring 35.

[0030] Wiring 35 extending horizontally is arranged in the intermediate region 110. Wiring 35 is a wiring to which a constant voltage is supplied, such as a power supply line or a ground line. Shielding line 30a is connected to wiring 35 via via 36a, and shielding line 30b is connected to wiring 35 via via 36b. Shielding lines 30a and 30b are electrically connected to each other via vias 36a and 36b, and a voltage (such as a power supply voltage or a ground voltage) is applied via wiring 35. Shielding lines 30a, 30b, and wiring 35 each function as a voltage line to which a predetermined voltage is supplied.

[0031] Each of the multiple vertical signal lines 20 of the image sensor 3 is wired in the vertical direction and in a direction different from the vertical direction (the horizontal direction in FIG. 2) in the intermediate region 110. In the example shown in FIG. 2, the vertical signal lines 20 extend vertically from the pixel region 100 to the intermediate region 110 and are wired horizontally in the intermediate region 110. Furthermore, the vertical signal lines 20 are wired vertically adjacent to the shield line 30b and are connected to the processing unit 50.

[0032] In the intermediate region 110, the vertical signal lines 20 are wired in the horizontal direction and are provided adjacent to other vertical signal lines 20. A portion of each horizontally wired vertical signal line 20 is adjacent to another vertical signal line 20 in at least one of the vertical direction and a direction different from the vertical and horizontal directions (diagonal direction). Portions of the vertical signal lines 20 that are adjacent to each other in the intermediate region 110 do not have a shield line 30 sandwiched between them.

[0033] In the image sensor 3, depending on the horizontal pitch of the pixels 10 and the horizontal pitch of the processing units 50, the vertical signal lines 20 are routed in a direction different from the vertical direction in an intermediate region 110 between the pixels 10 and the processing units 50 and connected to the processing units 50. In the example shown in Fig. 2, the vertical signal lines 20 are routed while being bent in the horizontal direction in order to connect the vertical signal lines 20 to the processing units 50 provided for each pixel 10 connected to the vertical signal lines 20. The vertical signal lines 20 are bent and can also be said to be crank-shaped wiring.

[0034] In this case, if the shield lines 30 that extend vertically adjacent to the vertical signal lines 20 in the pixel region 100 were to be wired horizontally in the intermediate region 110 so as to be adjacent to the vertical signal lines 20 as well, an area would be required in the intermediate region 110 to form the shield lines 30 in the horizontal direction. To place shield lines 30 extending horizontally on both sides of each vertical signal line 20, it would be necessary to ensure the line width of each shield line 30 and the spacing between the shield lines 30 and the vertical signal lines 20, and this would require expanding the intermediate region 110 in the vertical direction. This would increase the area of ​​the image sensor 3 and increase manufacturing costs.

[0035] Therefore, in the image sensor 3 according to this embodiment, in the intermediate region 110, the vertical signal lines 20 are wired so that portions thereof are adjacent to other vertical signal lines 20. No shield lines 30 are arranged between these portions of the adjacent vertical signal lines 20. This makes it possible to narrow the distance between the pixel region 100 and the circuit region 120 compared to a case in which shield lines 30 extending horizontally are provided on both sides of the horizontally wired portions of the vertical signal lines 20 in the intermediate region 110. This shortens the distance between the pixel region 100 and the circuit region 120, allowing the area of ​​the intermediate region 110 to be reduced. This makes it possible to reduce the chip area of ​​the image sensor 3. The configuration of the image sensor 3 according to this embodiment will be further described below with reference to the drawings.

[0036] 4 is a diagram showing an example of a layout of a portion of the image sensor according to the first embodiment. As described above, the vertical signal lines 20 are wired in the vertical direction and in a direction different from the vertical direction in the intermediate region 110. The vertical signal lines 20 have a portion (first portion) 20a wired in the vertical direction, a portion (second portion) 20b wired in a direction different from the vertical direction (the horizontal direction in FIG. 4), and a portion (third portion) 20c wired in the vertical direction.

[0037] Fig. 4 illustrates only some of the vertical signal lines 20 (first portions 20a1-20a4, second portions 20b1-20b4, and third portions 20c1-20c4) and shield lines 30 (shield lines 30a1-30a4 and shield lines 30b1-30b3) among the multiple vertical signal lines 20 and shield lines 30 shown in Fig. 2. Note that Fig. 4 does not illustrate the wiring 35.

[0038] In the image sensor 3, the interval between the vertical signal lines 20 in the horizontal direction differs between the pixel region 100 and the intermediate region 110. In the example shown in Fig. 4, the interval between the vertical signal lines 20 in the intermediate region 110 in the horizontal direction is narrower than the interval between the vertical signal lines 20 in the pixel region 100. The interval between the third portions 20c aligned in the horizontal direction is narrower than the interval between the first portions 20a aligned in the horizontal direction.

[0039] As described above, the second portions 20b of the vertical signal lines 20 wired in the horizontal direction are adjacent to the second portions 20b of other vertical signal lines 20 in at least one of the vertical direction and a direction different from the vertical and horizontal directions (diagonal direction). In the example shown in Fig. 4, the second portions 20b1 and 20b2 are adjacent to each other in the diagonal direction, and the second portions 20b2 and 20b3 are adjacent to each other in the diagonal direction. Furthermore, the second portions 20b3 and 20b4 are adjacent to each other in the vertical direction and the diagonal direction.

[0040] The second portion 20b of the vertical signal line 20 may have a width narrower than at least one of the first portion 20a and the third portion 20c. In the example shown in Fig. 4, the vertical width W2 of the second portion 20b is narrower than the horizontal width W1 of the first portion 20a and the horizontal width W3 of the third portion 20c. The vertical signal line 20 may be formed so that the first portion 20a and the third portion 20c have different widths. By miniaturizing the line width of the vertical signal line 20 in the intermediate region 110, the area of ​​the intermediate region 110 can be reduced.

[0041] The reduction in the area of ​​the intermediate region 110 will be explained below in comparison with a comparative example. FIG. 5 is a diagram showing an example configuration of part of an image sensor according to the comparative example. In the comparative example, shield lines 30 extend horizontally on both sides of the second portions 20b of the vertical signal lines 20, which are wired in the horizontal direction. The second portions 20b of the vertical signal lines 20 are adjacent to the shield lines 30. In the comparative example, multiple shield lines 30 are also wired horizontally in the intermediate region 110, which increases the vertical length of the intermediate region 110. This increases the area of ​​the intermediate region 110, resulting in an increase in the chip area.

[0042] 5, the length of the vertical signal line 20 in the intermediate region 110 accounts for a small proportion of the overall length of the vertical signal line 20. Therefore, even if the portion of the shield line 30 extending in the horizontal direction between adjacent second portions 20b is eliminated, it is thought that the effect on the quality of the pixel signal output to the vertical signal line 20 will be relatively small.

[0043] Therefore, in this embodiment, no shielding line extending horizontally is arranged between adjacent second portions 20b, as shown in Fig. 4. This allows the area of ​​intermediate region 110 to be smaller than when a shielding line is arranged horizontally between adjacent second portions 20b.

[0044] Furthermore, in this embodiment, shield lines 30b are provided on both sides of the third portions 20c of the vertical signal lines 20 that are wired in the vertical direction. This makes it possible to reduce noise contamination of pixel signals output to the vertical signal lines 20 without increasing the chip area of ​​the image sensor 3. As a result, it is possible to prevent degradation in the quality of the pixel signals.

[0045] According to the above-described embodiment, the following effects can be obtained. (1) The image sensor 3 includes a plurality of photoelectric conversion units 11 arranged in a first direction and a second direction different from the first direction, each generating electric charges through photoelectric conversion; signal lines (vertical signal lines 20) arranged in the second direction and outputting signals based on the electric charges generated by the photoelectric conversion units 11; and a processing unit 50 for processing the signals output to the signal lines. The plurality of signal lines are adjacent to each other in at least one of the second direction and a third direction different from the first and second directions in a second region (intermediate region 110) between a first region (pixel region 100) in which the plurality of photoelectric conversion units 11 are arranged in the first and second directions and the plurality of processing units 50. In this embodiment, in the intermediate region 110, the vertical signal lines 20 are arranged so that portions thereof are adjacent to other vertical signal lines 20. This allows the area of ​​the intermediate region 110 to be reduced, thereby preventing an increase in chip area.

[0046] (2) In this embodiment, the shield lines 30 are not arranged between parts of adjacent vertical signal lines 20 in the intermediate region 110. This makes it possible to reduce the area of ​​the intermediate region 110 and prevent an increase in the chip area.

[0047] The following modifications are also within the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiment.

[0048] (Variation 1) In the above-described embodiment, an example has been described in which the image sensor 3 has one vertical signal line 20 per pixel column, but this is not limiting. For example, as shown in FIG. 6, a configuration may be adopted in which two vertical signal lines 20 are provided per pixel column. In the example shown in FIG. 6, two shield lines 30 are provided for each pixel column. For example, of the two vertical signal lines 20 provided for each pixel column, one vertical signal line 20 is connected to each pixel 10 in the odd-numbered rows, and the other vertical signal line 20 is connected to each pixel 10 in the even-numbered rows. This allows signals from pixels in two rows to be read out simultaneously (in parallel).

[0049] 6, in the case of this modification, an increase in chip area can be suppressed by wiring parts of the vertical signal lines 20 adjacent to other vertical signal lines 20 in the intermediate region 110. Note that the image sensor may be configured to have two or more vertical signal lines 20 per pixel column.

[0050] (Variation 2) In the above-described embodiment and modified example, a photodiode is used as the photoelectric conversion unit, but a photoelectric conversion film (organic photoelectric film) may be used as the photoelectric conversion unit.

[0051] (Variation 3) The imaging elements and imaging devices described in the above-mentioned embodiments and variations may be applied to cameras, smartphones, tablets, cameras built into PCs, in-vehicle cameras, cameras mounted on unmanned aerial vehicles (drones, radio-controlled aircraft, etc.), etc.

[0052] (Variation 4) In the above-described embodiment, an example has been described in which the pixel region 100, the intermediate region 110, and the circuit region 120 of the imaging element 3 are arranged on one layer (substrate), but the present invention is not limited to this. 7 and 8 are diagrams showing a fourth modification, and are schematic perspective views based on FIG. 7 and 8, the crank-shaped vertical signal lines 20 are representatively illustrated, but the shield lines 30, pixels 10, AD conversion units 40, etc. are also arranged in the same manner as in FIG. 7 and 8, the pixel region 100, intermediate region 110, and circuit region 120 of the image sensor 3 are arranged on a first substrate and a second substrate stacked on the first substrate in the stacking direction. The stacking direction is the Z axis shown in Figures 7 and 8, and corresponds to a third direction intersecting the first direction (the X-axis direction shown in Figure 2) and the second direction (the Y-axis direction shown in Figure 2).

[0053] As shown in FIG. 7, in the imaging element 3, the pixel region 100 and the intermediate region 110 are arranged on the first substrate 3a, and the circuit region 120 is arranged on the second substrate 3b. In FIG. 7, the vertical signal lines 20 and shield lines 30 of the first substrate 3a penetrate the first substrate 3a in the stacking direction in a region near the periphery of the first substrate 3a and are connected to the vertical signal lines 20 and shield lines 30 arranged in a region near the periphery of the second substrate 3b. In FIG. 7, the circuit region 120 is disposed on all or part of the second substrate 3b.

[0054] As shown in FIG. 8, in the imaging element 3, the pixel region 100 is arranged on the first substrate 3c, and the intermediate region 110 and the circuit region 120 are arranged on the second substrate 3d. In FIG. 8, the vertical signal lines 20 and shield lines 30 of the first substrate 3c penetrate the first substrate 3c in the stacking direction in a region near the periphery of the first substrate 3c and are connected to the vertical signal lines 20 and shield lines 30 arranged in a region near the periphery of the second substrate 3d. In FIG. 8, the circuit region 120 is disposed in all or part of the area other than the intermediate region 110 of the second substrate 3d.

[0055] Although not shown, the imaging element 3 may be configured such that the pixel region 100 is arranged on the first substrate 3a, the circuit region 120 is arranged on the second substrate 3b, and the intermediate region 110 is arranged between the first substrate 3a and the second substrate 3b. Although not shown, the configuration of the first modification (FIG. 6) may also be configured with two substrates, similar to this modification.

[0056] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments that are conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. [Explanation of symbols]

[0057] 1...imaging device, 3...imaging element, 4...control unit, 10...pixel, 11...photoelectric conversion unit, 20...vertical signal line, 25...current source, 30...shield wire, 35...wiring, 40...AD conversion unit, 50...processing unit, 60...buffer, 70...counter, 80...readout control unit, 100...pixel region, 110...intermediate region, 120...circuit region

Claims

[Claim 1] a first photoelectric conversion unit that converts light into electric charges; a second photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the first photoelectric conversion unit in the first direction; a signal line through which a first signal based on the electric charge converted by the first photoelectric conversion unit is output, the first signal line having a first portion extending along a second direction intersecting the first direction, a second portion extending in the first direction, and a third portion extending along the second direction; a signal line through which a second signal based on the charge converted by the second photoelectric conversion unit is output, the second signal line having a fourth portion extending along the second direction, a fifth portion extending in the first direction, and a sixth portion extending along the second direction; a first wiring to which a predetermined voltage is supplied, the first wiring being disposed between the first portion and the fourth portion in the first direction and extending in the second direction; a second wiring that is supplied with a predetermined voltage and is provided separately from the first wiring, that is disposed between the third portion and the sixth portion in the first direction, and that extends in the second direction; a first processing unit that performs signal processing on the first signal output to the first signal line; a second processing unit that performs signal processing on the second signal output to the second signal line; An imaging element comprising:

Images