Semiconductor package

Abstract

To provide a semiconductor package.SOLUTION: A semiconductor package according to an embodiment of the present invention includes a base structure, a first semiconductor chip disposed on an upper surface of the base structure and directly bonded to the base structure, a second semiconductor chip on the first semiconductor chip, a lower encapsulation layer disposed on the upper surface of the base structure and covering a sidewall of the first semiconductor chip, and a molding layer provided on the upper surface of the lower encapsulation layer and covering a sidewall of the second semiconductor chip.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to semiconductor packages, and more particularly to semiconductor packages that include stacked semiconductor chips. [Background technology]

[0002] A semiconductor package is a device that embodies an integrated circuit chip in a form suitable for use in electronic products. Typically, a semiconductor package is formed by mounting a semiconductor chip on a printed circuit board and electrically connecting them using bonding wires or bumps. With the development of the electronics industry, semiconductor packages are required to embody solid-solution characteristics. Furthermore, as electronic products become more compact, there is an increasing demand for miniaturized semiconductor packages. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide a high-spec semiconductor package.

[0004] The problem to be solved by the present invention is to provide a miniaturized semiconductor package. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor package includes a base structure; a first semiconductor chip disposed on an upper surface of the base structure and directly bonded to the base structure; a second semiconductor chip on the first semiconductor chip; a lower encapsulation layer disposed on the upper surface of the base structure and covering a sidewall of the first semiconductor chip; and a molding layer provided on the upper surface of the lower encapsulation layer and covering a sidewall of the second semiconductor chip.

[0006] According to an embodiment of the present invention, a semiconductor package includes a base structure; a first semiconductor chip disposed on an upper surface of the base structure and including a first substrate, a first through via, and a first upper pad; a lower encapsulation layer disposed on the upper surface of the base structure and covering a sidewall of the first semiconductor chip; and an insulating layer disposed on the first substrate and covering a side surface of the first upper pad, the insulating layer extending over the upper surface of the lower encapsulation layer.

[0007] According to an embodiment of the present invention, a semiconductor package includes: a base structure including a base substrate, conductive vias in the base substrate, a base insulating layer on the base substrate, and conductive pads in the base insulating layer; a redistribution layer on a lower surface of the base structure; solder ball terminals provided on the lower surface of the redistribution layer and electrically connected to the conductive vias through the redistribution layer; a first semiconductor chip disposed on an upper surface of the base structure, the first semiconductor chip including a first substrate, a first lower insulating layer on the lower surface of the first substrate, a first lower pad in the first lower insulating layer, a first through via penetrating the first substrate, and a first upper pad electrically connected to the first through via; and a plurality of second semiconductor chips stacked on the first semiconductor chip. two semiconductor chips, each of the second semiconductor chips including a second substrate, a second lower insulating layer, a second lower pad, a second through via, a second upper insulating layer, and a second upper pad; a lower encapsulation layer disposed on the upper surface of the base structure and covering sidewalls of the first semiconductor chip; a molding layer disposed on the lower encapsulation layer and covering sidewalls of the second semiconductor chips; and an insulating layer provided between the lower encapsulation layer and the molding layer and between the first semiconductor chip and a second semiconductor chip that is the lowest of the second semiconductor chips, the insulating layer covering side surfaces of the second upper pads, and the first semiconductor chip being directly bonded to the base structure. [Effects of the Invention]

[0008] According to the present invention, the first semiconductor chip at the chip level that has passed the test can be used in the manufacturing process of the semiconductor package, thereby improving the efficiency of the manufacturing process of the semiconductor package.

[0009] The semiconductor package has high capacity and high performance characteristics. The first semiconductor chip is directly bonded to the base structure, which reduces the size of the semiconductor package. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 is a cross-sectional view showing a semiconductor package according to an embodiment. [Figure 1B] 1B is an enlarged view of region I of the semiconductor package of FIG. 1A. [Figure 1C] 1B is an enlarged view of a region II of the semiconductor package of FIG. 1A. [Figure 1D] 1B is an enlarged view of region III of the semiconductor package of FIG. 1A. [Figure 1E] 1B is an enlarged view of region IV of the semiconductor package of FIG. 1A. [Figure 2] 1 is a cross-sectional view showing a semiconductor package according to an embodiment. [Figure 3] 1 is a cross-sectional view showing a semiconductor package according to an embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor package according to an embodiment. [Figure 5A] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5B] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5C] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5D] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5E] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5F] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5G] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5H] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5I] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5J] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5K] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5L] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5M] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5N] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5O] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 5P] 1 is a diagram illustrating a manufacturing process of a semiconductor package according to an embodiment; [Figure 6] 1 is a diagram illustrating a semiconductor package according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE INVENTION A semiconductor package and a method for manufacturing the same according to an embodiment of the present invention will now be described.

[0012] FIG. 1A is a cross-sectional view showing a semiconductor package according to an embodiment.

[0013] Referring to FIG. 1A, a semiconductor package 10 includes a high bandwidth memory (HBM) The semiconductor package 10 includes a memory package such as a High Bandwidth Memory (HBM) package. The semiconductor package 10 is a chip stack package. The semiconductor package 10 includes a redistribution layer 600, a base structure 500, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, solder ball terminals 700, a lower sealing layer 410, an insulating layer 420, and a molding layer 430.

[0014] The base structure 500 includes a base substrate 510, conductive vias 570, conductive pads 550, and a base insulating layer 520. The base substrate 510 is manufactured using a semiconductor wafer. The base structure 500 may not include integrated circuits or transistors. The first to third semiconductor chips 100, 200, and 300 are electrically connected to the redistribution layer 600 and the solder ball terminals 700 through the base structure 500. "Electrically connected" to the base structure 500 includes "electrically connected" to the conductive vias 570 and the conductive pads 550. "Electrically connected" in this specification includes direct connection and indirect connection through other conductive components. Although not shown, the base structure 500 further includes passive elements therein. Passive elements include capacitors, inductors, or resistors.

[0015] The first direction D1 is parallel to the lower surface of the base substrate 510. The second direction D2 intersects with the lower surface of the base substrate 510. For example, the second direction D2 is perpendicular to the lower surface of the base substrate 510. The second direction D2 is a vertical direction.

[0016] The redistribution layer 600 is disposed on the lower surface of the base substrate 510. The redistribution layer 600 includes an organic insulating layer 610, a redistribution pattern 630, and a redistribution pad 650. Being electrically connected to the redistribution layer 600 includes being electrically connected to the redistribution pattern 630. Each of the redistribution patterns 630 is electrically connected to a corresponding conductive via 570. The redistribution pad 650 is disposed on the lower surface of the redistribution layer 600. The redistribution pad 650 is electrically connected to the redistribution pattern 630. The redistribution pads 650 are laterally spaced apart from each other. Being laterally spaced apart includes being horizontally spaced apart. "Horizontally spaced apart" means being parallel to the lower surface of the base substrate 510.

[0017] The solder ball terminals 700 are disposed on the lower surface of the redistribution layer 600. For example, the solder ball terminals 700 are disposed on the lower surfaces of the redistribution pads 650 and connected to the redistribution pads 650. Each of the solder ball terminals 700 is electrically connected to a corresponding conductive via 570 through the redistribution layer 600. For example, the solder ball terminals 700 are electrically connected to the first to third semiconductor chips 100, 200, and 300 through the redistribution pattern 630 and the base structure 500. The solder ball terminals 700 include a solder material. The solder material may include tin (Sn), silver (Ag), zinc (Zn), and / or an alloy thereof.

[0018] The first semiconductor chip 100 is disposed on the top surface of the base structure 500. The first semiconductor chip 100 is a lower semiconductor chip. The first semiconductor chip 100 is a logic chip. A plurality of second semiconductor chips 200 are provided on the first semiconductor chip 100. The second semiconductor chips 200 are stacked vertically on the top surface of the first semiconductor chip 100. Unless otherwise specified in this specification, "vertically" means aligned in the second direction D2. The second semiconductor chip 200 may be an intermediate semiconductor chip. The third semiconductor chip 300 may be disposed on the topmost one of the second semiconductor chips 200. For example, the second semiconductor chip 200 is interposed between the third semiconductor chip 300 and the first semiconductor chip 100. The third semiconductor chip 300 may be an upper semiconductor chip. Adjacent two chips among the first to third semiconductor chips 100, 200, and 300 are directly bonded to each other.

[0019] The second semiconductor chips 200 may be identical semiconductor chips. Each of the second semiconductor chips 200 is a memory chip such as a DRAM chip. For example, each of the second semiconductor chips 200 is a high bandwidth memory (HRAM) chip. The second semiconductor chips 200 are HBM (High Bandwidth Memory) chips. Each second semiconductor chip 200 has the same storage capacity. The second semiconductor chips 200 have the same size. For example, each second semiconductor chip 200 has substantially the same width and thickness. The width of a given component is measured in a first direction D1. The thickness of a given component is measured in a second direction D2. The equality of the width, thickness, size, level, and width of a given component means that the range of error that may occur during the process is the same. The sidewalls of the second semiconductor chips 200 are aligned vertically to each other.

[0020] The third semiconductor chip 300 is a semiconductor chip of the same type as the second semiconductor chip 200. The third semiconductor chip 300 may be a memory chip such as a DRAM chip. For example, the third semiconductor chip 300 may be a high bandwidth memory (HDRAM). The third semiconductor chip 300 is a High Bandwidth Memory (HBM) chip. The storage capacity of the third semiconductor chip 300 is the same as the storage capacity of each of the second semiconductor chips 200. The width of the third semiconductor chip 300 is substantially equal to the width of each of the second semiconductor chips 200. The sidewalls of the third semiconductor chip 300 are vertically aligned with the sidewalls of the second semiconductor chip 200. However, the thickness of the third semiconductor chip 300 is greater than the thickness of each of the second semiconductor chips 200.

[0021] The first semiconductor chip 100 is a different type of semiconductor chip from the second semiconductor chip 200 and the third semiconductor chip 300. The width of the first semiconductor chip 100 is different from the width of the second semiconductor chip 200 and the width of the third semiconductor chip 300. For example, the width of the first semiconductor chip 100 is greater than the width of the second semiconductor chip 200 and the width of the third semiconductor chip 300. The thickness T of the first semiconductor chip 100 may be 7 μm to 60 μm. This allows the semiconductor package 10 to be miniaturized. The thickness T of the first semiconductor chip 100 corresponds to the distance between the bottom surface of the first semiconductor chip 100 and the first upper pad 160.

[0022] 1A, the number of second semiconductor chips 200 may be varied in various ways. For example, the semiconductor package 10 may include a single second semiconductor chip 200 or four or more second semiconductor chips 200. Alternatively, the semiconductor package 10 may not include a second semiconductor chip 200. In this case, the third semiconductor chip 300 is disposed directly on the first semiconductor chip 100.

[0023] The lower encapsulation layer 410 is disposed on the upper surface of the base structure 500 and covers the sidewalls of the first semiconductor chip 100. The lower encapsulation layer 410 is an insulating layer. For example, the lower encapsulation layer 410 includes a silicon-containing insulating material such as silicon oxide. For another example, the lower encapsulation layer 410 includes an insulating polymer such as benzocyclobutene (BCB) and / or polyimide.

[0024] The molding layer 430 is provided on the lower encapsulation layer 410 to cover the sidewalls of the second semiconductor chip 200 and the sidewalls of the third semiconductor chip 300. The upper surface of the molding layer 430 is coplanar with the upper surface of the third semiconductor chip 300. The molding layer 430 is spaced apart from the lower encapsulation layer 410. For example, the molding layer 430 includes a different insulating material from the lower encapsulation layer 410. For example, the molding layer 430 includes an insulating polymer such as an epoxy molding compound (EMC).

[0025] An insulating layer 420 is provided between the first semiconductor chip 100 and the bottom second semiconductor chip 200 and extends between the lower encapsulation layer 410 and the molding layer 430. The insulating layer 420 includes a silicon-based insulating material. For example, the insulating layer 420 includes silicon oxide, silicon nitride, and / or a combination thereof.

[0026] The outer wall of the molding layer 430 is vertically aligned with the outer wall of the insulating layer 420 , the outer wall of the lower encapsulation layer 410 , the outer wall of the base structure 500 , and the outer wall of the redistribution layer 600 .

[0027] 1B is an enlarged view of region I of the semiconductor package of FIG. 1A. FIG. 1C is an enlarged view of region II of the semiconductor package of FIG. 1A. FIG. 1D is an enlarged view of region III of the semiconductor package of FIG. 1A. FIG. 1E is an enlarged view of region IV of the semiconductor package of FIG. 1A. The redistribution layer 600, the base structure 500, the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the insulating layer 420 will be described in further detail below.

[0028] 1B together with FIG. 1A, a base structure 500 includes a base substrate 510, a conductive via 570, a conductive pad 550, and a base insulating layer 520. The base substrate 510 is a semiconductor substrate. The semiconductor substrate includes a semiconductor material such as silicon, germanium, or silicon-germanium.

[0029] A conductive via 570 is provided in the base substrate 510. For example, the conductive via 570 penetrates the top and bottom surfaces of the base substrate 510. The conductive via 570 includes a metal material such as copper, tungsten, titanium, and / or a combination thereof. A conductive pad 550 is provided on the conductive via 570 and is electrically connected to the conductive via 570. The conductive pad 550 includes a metal such as copper.

[0030] A base insulating layer 520 is provided on the top surface of the base substrate 510 and covers the sides of the conductive pads 550. The base insulating layer 520 may comprise, for example, silicon oxide, silicon nitride carbide, and / or a combination thereof. The top surface of the base structure 500 includes the top surface of the base insulating layer 520 and the top surfaces of the conductive pads 550.

[0031] The redistribution layer 600 includes a plurality of organic insulating layers 610, redistribution patterns 630, and redistribution pads 650. The organic insulating layers 610 are vertically stacked. The number of stacked organic insulating layers 610 may be varied. For example, the organic insulating layers 610 may include the same material. The interface between adjacent organic insulating layers 610 may not be separated. The organic insulating layers 610 may be made of, for example, a photo-imageable insulating material. The top organic insulating layer 610 directly contacts the bottom surface of the base substrate 510. The top organic insulating layer 610 may include an organic material such as a photosensitive polymer (PSPI), a photosensitive polyimide (PSPI), a polybenzoxazole, a phenolic polymer, or a benzocyclobutene-based polymer.

[0032] The rewiring patterns 630 are provided between the organic insulating layers 610 and extend into the organic insulating layers 610. Some of the rewiring patterns 630 are stacked vertically and electrically connected to each other. The rewiring patterns 630 include a metal such as copper and / or a copper alloy.

[0033] Each of the rewiring patterns 630 includes a via portion 630V and a wiring portion 630W. The wiring portion 630W of each of the rewiring patterns 630 is provided between the organic insulating layers 610. The via portion 630V of each of the rewiring patterns 630 is provided in the corresponding organic insulating layer 610. The via portion 630V of each of the rewiring patterns 630 is provided on the lower surface of the wiring portion 630W and is connected to the wiring portion 630W without any boundary surface. The width of the wiring portion 630W of each of the rewiring patterns 630 is greater than the width of the via portion 630V.

[0034] The redistribution layer 600 further includes seed patterns 633. The seed patterns 633 are disposed on the upper surfaces of the redistribution patterns 630. For example, each seed pattern 633 covers the upper surface and sidewall of the via portion 630V and the upper surface of the wiring portion 630W of the corresponding redistribution pattern 630. The top seed pattern 633 is provided between the top redistribution pattern 630 and the conductive via 570. The top seed pattern 633 is in direct contact with the conductive via 570. The seed pattern 633 includes a different material from the redistribution pattern 630. For example, the seed pattern 633 includes a conductive seed material. The conductive seed material includes titanium, copper, and / or an alloy thereof. The seed pattern 633 functions as a barrier layer to prevent diffusion of materials included in the redistribution pattern 630. The redistribution pattern 630 is formed by a plating process using the seed pattern 633 as an electrode.

[0035] The redistribution pads 650 are provided on the lower surface of the lowermost organic insulating layer 610 and extend further into the lowermost organic insulating layer 610. The lower portion of each redistribution pad 650 is disposed on the lower surface of the lowermost organic insulating layer 610. The upper portion of each redistribution pad 650 is disposed within the lowermost organic insulating layer 610. The lower portion of each redistribution pad 650 has a width greater than that of the upper portion and is connected to the lower portion. The redistribution pads 650 are electrically connected to the redistribution pattern 630.

[0036] The redistribution layer 600 further includes a seed pad 653. The seed pad 653 is provided on an upper surface of the redistribution pad 650. The seed pad 653 is provided between the lowermost redistribution pattern 630 and the redistribution pad 650, and extends between the lowermost organic insulating layer 610 and the redistribution pad 650. The seed pad 653 includes a different metal material from that of the redistribution pad 650. The seed pad 653 includes, for example, a conductive seed material.

[0037] The first semiconductor chip 100 is disposed on a base structure 500. The first semiconductor chip 100 includes a first semiconductor substrate 110, a first integrated circuit 115, a first lower insulating layer 121, a first lower pad 150, a first wiring pattern 130, a first through via 170, and a first upper pad 160. The first semiconductor substrate 110 is a first substrate. The first semiconductor substrate 110 includes a semiconductor material such as silicon, germanium, or silicon-germanium.

[0038] 1B, a first integrated circuit 115 is provided on the bottom surface of a first semiconductor substrate 110. The bottom surface of the first semiconductor substrate 110 is referred to as a frontside. The first integrated circuit 115 may be a surface. The first integrated circuit 115 includes, for example, a transistor. The first integrated circuit 115 includes a logic circuit.

[0039] The first lower insulating layer 121 is provided on the lower surface of the first semiconductor substrate 110 and covers the first integrated circuit 115. The first lower insulating layer 121 includes a silicon-based insulating material. The silicon-based insulating material includes, for example, silicon oxide and / or silicon nitride carbide. The first lower insulating layer 121 includes a plurality of stacked layers.

[0040] First wiring patterns 130 are provided in the first lower insulating layer 121. Each of the first wiring patterns 130 is electrically connected to at least one of the first integrated circuits 115 and the first through vias 170. When a component is electrically connected to the semiconductor chip, it means that the component is electrically connected to at least one of the through vias and the integrated circuits of the semiconductor chip.

[0041] The first lower pad 150 is disposed on the lower surface of the first semiconductor chip 100. For example, the first lower pad 150 is disposed on the lower surface of the first semiconductor substrate 110 and in the first lower insulating layer 121. The first lower pad 150 is electrically connected to the first integrated circuit 115 and the first through via 170 via the first wiring pattern 130. The first lower pad 150 includes, for example, copper. The lower surface of the first semiconductor chip 100 includes the lower surface of the first lower pad 150 and the lower surface of the first lower insulating layer 121.

[0042] The following describes bonding between the base structure 500 and the first semiconductor chip 100. For simplicity, a single first lower pad 150 will be described below.

[0043] The first semiconductor chip 100 is directly bonded to the base structure 500. The direct bonding is formed by a hybrid bonding process. For example, the first lower pad 150 is directly disposed on the conductive pad 550 and directly bonded to the conductive pad 550. During the hybrid bonding process, metal atoms in the first lower pad 150 diffuse into the conductive pad 550, and metal atoms in the conductive pad 550 diffuse into the first lower pad 150. This allows the first lower pad 150 to be firmly bonded to the conductive pad 550. If the direct bonding of the first semiconductor chip 100 and the base structure 500 is performed at a temperature above a predetermined temperature, the interface between the first lower pad 150 and the conductive pad 550 may not be distinct. In this case, the interface between the first lower pad 150 and the conductive pad 550 in FIGS. 1A and 1B is a virtual interface. Alternatively, the interface between the first lower pad 150 and the conductive pad 550 may be distinct depending on the bonding process conditions. The first semiconductor chip 100 is directly bonded to the base structure 500, eliminating the need for solder balls between the base structure 500 and the first semiconductor chip 100. This allows the semiconductor package 10 to be made smaller.

[0044] 1B , at least one side of the plurality of first lower pads 150 may not be vertically aligned with a side of the corresponding conductive pad 550. The side of any one of the first lower pads 150 may be offset from the side of the conductive pad 550 in the first direction D1 or in a direction opposite to the first direction D1. Unlike as shown in the figure, the side of the first lower pad 150 may be vertically aligned with the side of the conductive pad 550.

[0045] The first lower insulating layer 121 is in direct contact with the base insulating layer 520 and is directly bonded to the base insulating layer 520. For example, a chemical bond is provided between the first lower insulating layer 121 and the base insulating layer 520. The chemical bond is a covalent bond. This allows the first lower insulating layer 121 to be firmly bonded to the base insulating layer 520. The first lower insulating layer 121 and the base insulating layer 520 may include, but are not limited to, the same material. For example, the interface between the first lower insulating layer 121 and the base insulating layer 520 is not defined. In FIGS. 1A and 1B, the interface between the first lower insulating layer 121 and the base insulating layer 520 is a virtual interface. For another example, the interface between the first lower insulating layer 121 and the base insulating layer 520 is defined.

[0046] The first through vias 170 are provided in the first semiconductor substrate 110 and penetrate the first semiconductor substrate 110. The first through vias 170 further penetrate at least a portion of the first lower insulating layer 121. The first through vias 170 are spaced apart from one another in the laterally spaced apart direction. For example, the first through vias 170 are spaced apart from one another in the first direction D1 or the direction opposite to the first direction D1. The first through vias 170 are electrically connected to the first lower pad 150 and / or the first integrated circuit 115 via the first wiring pattern 130.

[0047] Each of the first through vias 170 includes a first conductive via 175 and a first barrier film 173. The first conductive via 175 includes a metal such as copper or tungsten. The first barrier film 173 is disposed between the first conductive via 175 and the first semiconductor substrate 110. The first barrier film 173 covers a sidewall of the first conductive via 175. The first barrier film 173 includes a metal different from that of the first conductive via 175. The first barrier film 173 prevents the metal included in the first conductive via 175 from diffusing into the first semiconductor substrate 110. The first barrier film 173 includes a barrier metal material. The barrier metal material includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0048] 1C together with FIG. 1A, an insulating layer 400 is disposed on an upper surface 110a of a first semiconductor substrate 110. The upper surface 110a of the first semiconductor substrate 110 faces the lower surface. The upper surface 110a of the first semiconductor substrate 110 faces the backside. The top surface 110a of the first semiconductor substrate 110 may be coplanar with the top surface 410a of the lower encapsulation layer. The insulating layer 400 may include silicon oxide, silicon nitride, and / or a combination thereof.

[0049] The first conductive via 175 is further provided in the insulating layer 400. The first barrier film 173 does not have to extend into the insulating layer 400. For example, the first barrier film 173 is not interposed between the first conductive via 175 and the insulating layer 400. The insulating layer 400 extends onto the top surface of the first barrier film 173 and covers the upper sidewall of the first conductive via 175.

[0050] The first upper pads 160 are disposed on the upper surface 110a of the first semiconductor substrate 110. The first upper pads 160 are provided on the first through vias 170 and are electrically connected to the first through vias 170. For example, each of the first upper pads 160 is provided on a corresponding first conductive via 175 and is electrically connected to the first conductive via 175. For example, each of the first upper pads 160 is spaced apart from a corresponding first barrier film 173. The lower surface of the first upper pad 160 is provided at a level higher than the uppermost surface of the first barrier film 173. In this specification, the level of a component refers to a vertical level.

[0051] The first upper pad 160 is disposed within the insulating layer 400. The lower surface and side surfaces of the first upper pad 160 are covered by the insulating layer 400. The upper surface of the first upper pad 160 is not covered by the insulating layer 400. For example, the upper surface of the first upper pad 160 is disposed at substantially the same level as the insulating layer 400. The upper surface of the first upper pad 160 is coplanar with the insulating layer 400.

[0052] Each of the first upper pads 160 includes a metal pad 165 and a barrier pad 163. The metal pad 165 includes the same metal as the first lower pad 150. For example, the metal pad 165 includes copper. The barrier pad 163 covers the bottom and side surfaces of the metal pad 165. The barrier pad 163 includes a different metal from the metal pad 165. For example, the barrier pad 163 includes a barrier metal material. Hereinafter, a single first upper pad 160 and a single first through via 170 will be described.

[0053] The insulating layer 400 is a multi-layer structure. For example, the insulating layer 400 includes a first layer 421, a second layer 422, and a third layer 423 stacked one on the other. The first layer 421 is provided on the upper surface 110a of the first semiconductor substrate 110 and extends onto the upper sidewall of the first through-via 170. For example, the first layer 421 covers the upper surface of the first barrier film 173 and the upper sidewall of the first conductive via 175. The top surface of the first layer 421 is in physical contact with the lower surface of the first upper pad 160. The first layer 421 extends onto the upper surface 410a of the lower encapsulation layer 410 and covers the upper surface 410a of the lower encapsulation layer 410. The first layer 421 is interposed between the first conductive via 175 and the second layer 422, between the first semiconductor substrate 110 and the second layer 422, and between the lower encapsulation layer 410 and the second layer 422. The second layer 422 is provided on the first layer 421. The second layer 422 is interposed between the first layer 421 and the third layer 423. The third layer 423 is provided on the first layer 421 and covers the side surfaces of the first upper pad 160.

[0054] The second layer 422 includes a different material from the first layer 421 and the third layer 423. For example, the first layer 421 includes silicon oxide, the second layer 422 includes silicon nitride, and the third layer 423 includes silicon oxide. The number and materials of the layers included in the insulating layer 400 can be varied in various ways.

[0055] Unlike the illustration, the top surface 110a of the first semiconductor substrate 110 may be the front surface, or the back surface of the first semiconductor substrate 110 may be the front surface. In this case, the first integrated circuit 115 and the first wiring pattern 130 are disposed on the top surface 110a of the first semiconductor substrate 110.

[0056] Each second semiconductor chip 200 includes a second semiconductor substrate 210, a second integrated circuit 215, a second lower insulating layer 221, a second lower pad 250, a second wiring pattern 230, a second through via 270, a second upper pad 260, and a second upper insulating layer 222. Unless otherwise specified, the materials, arrangements, and electrical connections of the second semiconductor substrate 210, the second integrated circuit 215, the second lower insulating layer 221, the second wiring pattern 230, and the second through via 270 are substantially the same as the materials, arrangements, and electrical connections of the first semiconductor substrate 110, the first integrated circuit 115, the first lower insulating layer 121, the first wiring pattern 130, and the first through via 170, respectively. The second semiconductor substrate 210 is a second substrate.

[0057] A second integrated circuit 215 is provided on the bottom surface of the second semiconductor substrate 210. The second integrated circuit 215 may be a different type of circuit than the first integrated circuit 115. The second integrated circuit 215 is a memory circuit.

[0058] The second semiconductor substrate 210 includes a semiconductor material. A second lower insulating layer 221 is provided on the lower surface of the second semiconductor substrate 210 and covers the second integrated circuit 215. Although not shown, the second lower insulating layer 221 may be multi-layered. A second wiring pattern 230 is provided in the second lower insulating layer 221.

[0059] The second lower insulating layer 221 and the second lower pad 250 are provided on the lower surface of the second semiconductor chip 200. For example, the second lower insulating layer 221 and the second lower pad 250 are disposed on the lower surface of the second semiconductor substrate 210. The second lower pad 250 is disposed within the second lower insulating layer 221. The upper and side surfaces of the second lower pad 250 are covered by the second lower insulating layer 221. The lower surface of the second lower pad 250 is coplanar with the lower surface of the second lower insulating layer 221 and is disposed at substantially the same level as the lower surface of the second lower insulating layer 221. The lower surface of the second semiconductor chip 200 includes the lower surface of the second lower pad 250 and the lower surface of the second lower insulating layer 221. The second lower pad 250 is electrically connected to the second integrated circuit 215 and / or the second through via 270 via the second wiring pattern 230. The second lower pad 250 includes the same metal as the metal pad 165. The second lower pad 250 includes, for example, copper. For simplicity, a single second lower pad 250 and a single first upper pad 160 will be described below.

[0060] The bottom second semiconductor chip 200 is directly bonded to the first semiconductor chip 100. The direct bonding of two chips is formed by a hybrid bonding process. Direct bonding of two chips includes direct bonding of conductive components at opposing positions of the two chips and direct bonding of insulating components at opposing positions of the two chips. Direct bonding of insulating components includes forming a chemical bond between the insulating components. For example, the second lower pad 250 is provided directly on the first upper pad 160 and directly bonded to the first upper pad 160. During the hybrid bonding process, metal atoms in the second lower pad 250 diffuse into the first upper pad 160, and metal atoms in the first upper pad 160 diffuse into the second lower pad 250. This allows the second lower pad 250 to be firmly bonded to the first upper pad 160. For example, the interface between the first upper pad 160 and the second lower pad 250 is not distinct. 1A and 1C, the interface between the first upper pad 160 and the second lower pad 250 is a virtual interface. As another example, the interface between the first upper pad 160 and the second lower pad 250 is divided. As shown in FIG. 1C, at least one side of the second lower pads 250 may not be aligned perpendicularly to the side of the corresponding first upper pad 160. The side of any one of the second lower pads 250 is offset from the side of the first upper pad 160 in the first direction D1 or in the direction opposite to the first direction D1. Unlike the illustrations, the side of the second lower pad 250 may be aligned perpendicularly to the side of the first upper pad 160.

[0061] The second lower insulating layer 221 of the bottom second semiconductor chip 200 is in direct contact with the insulating layer 400 and is connected to it by direct bonding. For example, the second lower insulating layer 221 of the bottom second semiconductor chip 200 includes the same insulating material as the insulating layer 400. A chemical bond is formed between the second lower insulating layer 221 of the bottom second semiconductor chip 200 and the third layer 423 of the insulating layer 400. The chemical bond is a covalent bond. This allows the bottom second semiconductor chip 200 to be firmly bonded to the first semiconductor chip 100. For example, the interface between the second lower insulating layer 221 and the third layer 423 of the bottom second semiconductor chip 200 may not be distinct. In this case, the interface between the third layer 423 and the second lower insulating layer 221 of the bottom second semiconductor chip 200 in FIG. 1C is a virtual interface. As another example, the interface between the third layer 423 and the second lower insulating layer 221 of the bottom second semiconductor chip 200 is partitioned.

[0062] The second through vias 270 are provided in the second semiconductor substrate 210 and penetrate the second semiconductor substrate 210. The second through vias 270 further penetrate at least a portion of the second lower insulating layer 221 to be electrically connected to the second wiring pattern 230. Although not shown, each of the second through vias 270 includes a second conductive via and a second barrier film. The second barrier film is disposed between the second conductive via and the second semiconductor substrate 210. The second barrier film includes a different metal from that of the second conductive via.

[0063] 1A, a second upper insulating layer 222 is disposed on the upper surface of the second semiconductor substrate 210. The upper surface of the second semiconductor substrate 210 is the backside surface. The second upper insulating layer 222 includes a silicon-based insulating material and is a multi-layer structure. For example, the second upper insulating layer 222 may include silicon oxide, silicon carbide nitride, and / or a combination thereof.

[0064] The second through via 270 protrudes above the top surface of the second semiconductor substrate 210. The second through via 270 extends further into the second upper insulating layer 222.

[0065] The second upper pad 260 is provided on the second through via 270 and is electrically connected to the second through via 270. The second upper pad 260 is disposed in the second upper insulating layer 222. For example, the lower surface and side surfaces of the second upper pad 260 are covered by the second upper insulating layer 222. The upper surface of the second upper pad 260 is not covered by the second upper insulating layer 222. For example, the upper surface of the second upper pad 260 is disposed at substantially the same level as the second upper insulating layer 222 and is coplanar with the second upper insulating layer 222. The second upper pad 260 includes the same metal as the second lower pad 250. The second upper pad 260 includes, for example, copper.

[0066] The following describes bonding between the second semiconductor chips 200. For simplicity, a single second upper pad 260 and a single second lower pad 250 will be described.

[0067] The second semiconductor chips 200 are directly bonded to each other. For example, adjacent second semiconductor chips 200 include a second lower semiconductor chip 201 and a second upper semiconductor chip 202 as shown in FIG. 1D . The second upper semiconductor chip 202 is disposed directly on the second lower semiconductor chip 201 and directly bonded to the second lower semiconductor chip 201. For example, the second upper pads 260 of the second lower semiconductor chip 201 and the second lower pads 250 of the second upper semiconductor chip 202 are in direct contact with each other and are directly bonded to each other. The interface between the second upper pads 260 of the second lower semiconductor chip 201 and the second lower pads 250 of the second upper semiconductor chip 202 is not defined. The interface between the second upper pads 260 of the second lower semiconductor chip 201 and the second lower pads 250 of the second upper semiconductor chip 202 is a virtual interface. As another example, the interface between the second upper pads 260 of the second lower semiconductor chip 201 and the second lower pads 250 of the second upper semiconductor chip 202 is partitioned.

[0068] At least one side of the plurality of second upper pads 260 may not be aligned vertically with a side of the corresponding second lower pad 250. The side of any one of the second upper pads 260 may be offset from the side of the second lower pad 250 in the first direction D1 or in a direction opposite to the first direction D1. Unlike as illustrated, the side of the second upper pad 260 may be aligned vertically with the side of the second lower pad 250.

[0069] The second lower insulating layer 221 of the second upper semiconductor chip 202 is in direct contact with the second upper insulating layer 222 of the second lower semiconductor chip 201 and is directly bonded to the second upper insulating layer 222. For example, the second lower insulating layer 221 of the second upper semiconductor chip 202 includes the same insulating material as the second upper insulating layer 222 of the second lower semiconductor chip 201. A chemical bond is formed between the second lower insulating layer 221 of the second upper semiconductor chip 202 and the second upper insulating layer 222 of the second lower semiconductor chip 201. The chemical bond is a covalent bond. For example, the interface between the second lower insulating layer 221 of the second upper semiconductor chip 202 and the second upper insulating layer 222 of the second lower semiconductor chip 201 is not defined. The interface between the second upper insulating layer 222 and the second lower insulating layer 221, which are in contact with each other, is a virtual interface. Alternatively, the interface between the second upper insulating layer 222 and the second lower insulating layer 221 that contact each other is divided.

[0070] 1A, a third semiconductor chip 300 includes a third semiconductor substrate 310, a third integrated circuit 315, a third lower insulating layer 321, a third lower pad 350, and a third wiring pattern 330. The materials, arrangements, and electrical connections of the third semiconductor substrate 310, the third integrated circuit 315, the third lower insulating layer 321, the third lower pad 350, and the third wiring pattern 330 are substantially the same as the materials, arrangements, and electrical connections of the second semiconductor substrate 210, the second integrated circuit 215, the second lower insulating layer 221, and the second wiring pattern 230, respectively.

[0071] A third integrated circuit 315 is provided on the bottom surface of the third semiconductor substrate 310. The third integrated circuit 315 includes, for example, a transistor. The third integrated circuit 315 is a memory circuit and is the same type of circuit as the second integrated circuit (215 in FIG. 1C).

[0072] A third lower insulating layer 321 is provided on the lower surface of the third semiconductor substrate 310. The third lower insulating layer 321 includes silicon oxide, silicon nitride carbide, and / or a combination thereof. Although not shown, the third lower insulating layer 321 may be multi-layered. A third wiring pattern 330 is provided in the third lower insulating layer 321 and electrically connected to the third integrated circuit 315.

[0073] The third lower pad 350 is provided on the lower surface of the third semiconductor chip 300. For example, the third lower pad 350 is disposed on the lower surface of the third semiconductor substrate 310 and within the third lower insulating layer 321. The upper and side surfaces of the third lower pad 350 are covered by the third lower insulating layer 321. The lower surface of the third lower pad 350 is coplanar with the lower surface of the third lower insulating layer 321. The third lower pad 350 is electrically connected to the third integrated circuit 315 via the third wiring pattern 330. However, the third lower pad 350 includes the same metal as the second upper pad 260. The third lower pad 350 includes, for example, copper. The lower surface of the third semiconductor chip 300 includes the lower surface of the third lower pad 350 and the lower surface of the third lower insulating layer 321.

[0074] The following describes bonding between the uppermost second semiconductor chip 200 among the second semiconductor chips 200 and the third semiconductor chip 300. For simplicity, the following description will be made in terms of a single second upper pad 260 and a single third lower pad 350.

[0075] The third semiconductor chip 300 is directly bonded to the uppermost second semiconductor chip 200. For example, the third lower pad 350 of the third semiconductor chip 300 and the second upper pad 260 of the uppermost second semiconductor chip 200 are in direct contact with and directly bonded to each other. As an example, the interface between the second upper pad 260 and the third lower pad 350 is not defined. In this case, the interface between the second upper pad 260 and the third lower pad 350 that contact each other in FIGS. 1A and 1E is a virtual interface. As another example, the interface between the second upper pad 260 and the third lower pad 350 is defined. As shown in FIG. 1C, at least one side of the plurality of third lower pads 350 may not be vertically aligned with the side of the corresponding second upper pad 260. The side of the at least one third lower pad 350 is offset from the side of the second upper pad 260 in a first direction D1 or in a direction opposite to the first direction D1. Contrary to what is shown, the side of the third lower pad 350 may be aligned vertically with the side of the second upper pad 260 .

[0076] The third lower insulating layer 321 is in direct contact with the second upper insulating layer 222 of the uppermost second semiconductor chip 200 and is connected to the second upper insulating layer 222 by direct bonding. For example, the third lower insulating layer 321 includes the same insulating material as the second upper insulating layer 222 of the uppermost second lower semiconductor chip 200. A chemical bond is provided between the second upper insulating layer 222 and the third lower insulating layer 321 of the uppermost second semiconductor chip 200. The chemical bond is a covalent bond. The interface between the second upper insulating layer 222 and the third lower insulating layer 321 is not defined. In this case, the interface between the second upper insulating layer 222 and the third lower insulating layer 321 of the uppermost second semiconductor chip 200 in FIGS. 1A and 1E is a virtual interface. As another example, the interface between the second upper insulating layer 222 and the third lower insulating layer 321 is defined.

[0077] 2 is a cross-sectional view showing a semiconductor package according to an embodiment. Hereinafter, explanations that overlap with those described above will be omitted.

[0078] 2, the semiconductor package 10A is a memory package such as a high-bandwidth memory package. The semiconductor package 10A is a chip stack package. The semiconductor package 10A includes a redistribution layer 600, a base structure 500, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, solder ball terminals 700, a lower encapsulation layer 410, an insulating layer 420, and a molding layer 430, as well as first solder bumps 710 and second solder bumps 720.

[0079] The first solder bumps 710 are provided between the second semiconductor chips 200 and are electrically connected to the second semiconductor chips 200. The bottom second semiconductor chip 200 is not directly bonded to the first semiconductor chip 100. For example, the first solder bumps 710 are interposed between the opposing second upper pads 260 and second lower pads 250 and are electrically connected to the opposing second upper pads 260 and second lower pads 250. The first solder bumps 710 include a solder material.

[0080] The semiconductor package 10A further includes a first insulating film 441. Each of the first insulating films 441 is provided between adjacent second semiconductor chips 200 and covers the sidewalls of the first solder bumps 710. The first insulating film 441 is a non-conductive film. The first insulating film 441 includes an insulating polymer.

[0081] The second solder bumps 720 are provided between the uppermost second semiconductor chip 200 and the third semiconductor chip 300 and are electrically connected to the uppermost second semiconductor chip 200 and the third semiconductor chip 300. The third semiconductor chip 300 is not directly bonded to the uppermost second semiconductor chip 200. For example, the second solder bumps 720 are interposed between the opposing second upper pads 260 and the third lower pads 350. The second solder bumps 720 are electrically connected to the opposing second upper pads 260 and the third lower pads 350. The second solder bumps 720 include a solder material.

[0082] The semiconductor package 10A further includes a second insulating film 442. The second insulating film 442 is provided between the uppermost second semiconductor chip 200 and the third semiconductor chip 300 and covers the sidewalls of the second solder bumps 720. For example, the second insulating film 442 includes a non-conductive film.

[0083] FIG. 3 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0084] Referring to FIG. 3, the semiconductor package 10B is a memory package such as a high-bandwidth memory package. The semiconductor package 10B is a chip stack package. The semiconductor package 10B includes a redistribution layer 600, a base structure 500, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, solder ball terminals 700, a lower encapsulation layer 410, an insulating layer 420, and a molding layer 430, as well as first solder bumps 710 and second solder bumps 720. The first solder bumps 710 and second solder bumps 720 are substantially the same as those described in the example of FIG. 2. The semiconductor package 10B may not include the first insulating film 441 and the second insulating film 442 of FIG. 2.

[0085] The molding layer 430 is provided on the top surface of the insulating layer 420 to cover the sidewalls of the second and third semiconductor chips 200 and 300. The molding layer 430 may be a molded underfill. For example, molding layer 430 extends between second semiconductor chip 200 to seal first solder bumps 710. Molding layer 430 further extends between third semiconductor chip 300 and the top second semiconductor chip 200 to seal second solder bumps 720.

[0086] FIG. 4 is a cross-sectional view showing a semiconductor package according to an embodiment.

[0087] 4, the semiconductor package 10C includes a redistribution layer 600, a base structure 500, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, solder ball terminals 700, a lower encapsulation layer 410, an insulating layer 420, and a molding layer 430. The semiconductor package 10C includes 11 second semiconductor chips 200. The number of stacked second semiconductor chips 200 can be varied in various ways. For example, the semiconductor package 10C may include 19 or more second semiconductor chips 200.

[0088] At least two of the embodiments of the present invention may be combined with each other. For example, the semiconductor package 10C of Fig. 4 further includes the first solder bump 710 and the second solder bump 720, just like the semiconductor package 10A of Fig. 2. However, the embodiments of the present invention are not limited thereto and may be combined in various ways.

[0089] 5A to 5P are views illustrating a manufacturing process of a semiconductor package according to an embodiment. Hereinafter, descriptions that overlap with those described above will be omitted. In the following description of FIGS. 5A to 5P, for consistency, the terms upper surface, lower surface, top, and bottom will be used with reference to FIGS. 5A and 5P.

[0090] 5A, a base structure 500 is prepared. The base structure 500 is the same or similar in the examples of FIGS. 1A and 1B. However, the base structure 500 therein is prepared at the wafer level. For example, the base structure 500 includes a plurality of base units. Each of the plurality of base units includes a base substrate 510, a conductive via 570, a conductive pad 550, and a base insulating layer 520. The conductive via 570 penetrates the upper surface of the base substrate 510 but is spaced apart from the lower surface of the base substrate 510. For example, the lower surface of the conductive via 570 is provided within the base substrate 510.

[0091] A test process is performed on the base structure 500. The base structure 500 that has passed the test process can be used in the manufacture of a semiconductor package.

[0092] 5B, a plurality of first semiconductor chips 100 are prepared. Each of the plurality of first semiconductor chips 100 includes a first semiconductor substrate 110, a first integrated circuit (115 in FIG. 1B), a first lower insulating layer 121, a first lower pad 150, a first wiring pattern 130, and a first through via 170. The first through via 170 may penetrate the lower surface of the first semiconductor substrate 110 but not the upper surface of the first semiconductor substrate 110. The upper surface of the first through via 170 is provided within the first semiconductor substrate 110. For example, the upper surface of the first through via 170 may be provided at a lower level than the upper surface of the first semiconductor substrate 110. Each of the first semiconductor chips 100 may not include the first upper pad 160 described in the examples of FIGS. 1A and 1B.

[0093] The plurality of first semiconductor chips 100 are provided on the upper surface of the base substrate 510. For example, the plurality of first semiconductor chips 100 are directly disposed on the upper surface of the base substrate 510. The plurality of first semiconductor chips 100 are disposed laterally spaced apart from one another. At this time, the lower surface of the first lower pad 150 is in direct contact with the upper surfaces of the plurality of conductive pads 550, and the lower surface of the first lower insulating layer 121 is in direct contact with the upper surface of the base insulating layer 520.

[0094] Through the hybrid bonding process, the first semiconductor chip 100 is directly bonded to the base substrate 510. Performing the hybrid bonding process includes performing a heat treatment process on the base substrate 510 and the plurality of first semiconductor chips 100. Performing the hybrid bonding process may further include, but is not limited to, performing a plasma treatment process on the upper surface of the base substrate 510 and the lower surface of the first semiconductor chip 100 prior to the heat treatment process. During the heat treatment process, pressure may be further applied to the base substrate 510 and the plurality of first semiconductor chips 100, but is not limited to this.

[0095] When the first semiconductor chips 100 are bonded at the wafer level, it is difficult to selectively remove defective (faulty) first semiconductor chips 100 in the semiconductor package manufacturing process. According to the embodiment, the first semiconductor chips 100 are provided at the chip level. For example, the first semiconductor chips 100 are provided on the base structure 500 while separated from each other. A test process for the first semiconductor chips 100 is performed before the bonding process for the first semiconductor chips 100. According to the embodiment, each of the first semiconductor chips 100 is a semiconductor chip that has passed the test. As a result, the defective (faulty) first semiconductor chips 100 are not used in the manufacturing of the semiconductor package. A good first semiconductor chip 100 is used in the manufacturing of the semiconductor package. Similarly, a good base structure 500 is used in the bonding process. This improves the efficiency of the semiconductor package manufacturing process. The yield of the semiconductor package manufacturing process is improved.

[0096] 5C, a thinning process is performed on the plurality of first semiconductor chips 100 to reduce the thickness of the first semiconductor chips 100. The thinning process is called "post-bonding grinding." After the thinning process, the top surface of the first through via 170 is provided in the first semiconductor substrate 110. The thinning process reduces the distance between the top surface of the first through via 170 and the top surface of the first semiconductor substrate 110.

[0097] 5D, a lower encapsulation layer 410 is formed on a base substrate 510 to cover a plurality of first semiconductor chips 100. The lower encapsulation layer 410 covers the upper surface of the base insulating layer 520, the sidewalls of the first semiconductor chips 100, and the upper surfaces of the first semiconductor chips 100. The lower encapsulation layer 410 fills gaps between the first semiconductor chips 100. The upper surface of the lower encapsulation layer 410 is provided at a higher level than the upper surfaces of the first semiconductor chips 100. When the lower encapsulation layer 410 includes a silicon-containing insulating material, the lower encapsulation layer 410 is formed by a deposition process such as chemical vapor deposition. When the lower encapsulation layer 410 includes an insulating polymer, the lower encapsulation layer 410 is formed by coating fixation.

[0098] 5E and 5F, a grinding process is performed on the lower encapsulation layer 410 to expose an end of the first through via 170. The grinding process includes a chemical mechanical polishing (CMP) process. The grinding process removes an upper portion of the lower encapsulation layer 410 to expose an upper surface of the first semiconductor substrate 110. The exposed upper surface of the first semiconductor substrate 110 is ground to remove the upper portion of the first semiconductor substrate 110. The grinding process is performed until an end of the first through via 170 is exposed. For example, the grinding process exposes a portion of the first barrier film 173. The exposed portion of the first barrier film 173 is further removed to expose an end 175E of the first conductive via 175. The end 175E of the first conductive via 175 protrudes from the upper surface 110a of the first semiconductor substrate 110. The top surface of the remaining first barrier film 173 is provided at the same or similar level as the upper surface 110a of the first semiconductor substrate 110. The upper surface 110a of the first semiconductor substrate 110 is provided at substantially the same level as the upper surface 410a of the lower encapsulation layer 410.

[0099] 5G and 5H, an insulating layer 420 is formed on the upper surface 110a of the first semiconductor substrate 110 and the upper surface 410a of the lower encapsulation layer 410. The insulating layer 420 is formed at wafer level. The insulating layer 420 includes a first layer 421, a second layer 422, and a third layer 423. The first layer 421, the second layer 422, and the third layer 423 are each formed by a deposition process. The first layer 421 is formed to conformally cover the upper surface 410a of the lower encapsulation layer 410, the upper surface 110a of the first semiconductor substrate 110, the upper surface of the first barrier film 173, and the exposed end 175E of the first conductive via 175. The second layer 422 conformally covers the first layer 421 over the upper surface 410a of the lower encapsulation layer 410, the upper surface 110a of the first semiconductor substrate 110, and the exposed end 175E of the first conductive via 175. Then, a portion of the second layer 422 and a portion of the first layer 421 are removed to expose the end 175E of the first conductive via 175. A third layer 423 is formed on the second layer 422. A first upper pad 160 is formed in the third layer 423 and on the upper surface of the first conductive via 175 to connect with the first conductive via 175. Forming the first upper pad 160 includes forming a barrier pad 163 and a metal pad 165. The first upper pad 160 does not have to extend above the upper surface of the insulating layer 420. The upper surface of the first upper pad 160 may be provided at the same or similar level as the upper surface of the insulating layer 420, but is not limited to this. After the first upper pads 160 are formed, the thickness T of the first semiconductor chip 100 is 7 μm to 60 μm.

[0100] 5I, a plurality of second semiconductor chips 200 are prepared. The second semiconductor chips 200 are disposed on the plurality of first semiconductor chips 100, respectively. The second semiconductor chips 200 are directly bonded to the corresponding first semiconductor chips 100 using a hybrid bonding process. For example, directly bonding the second semiconductor chips 200 to the first semiconductor chips 100 includes applying heat to the first semiconductor chips 100 and the second semiconductor chips 200.

[0101] The placement of the second semiconductor chips 200 is repeated to form a plurality of stacked second semiconductor chips 200. A hybrid bonding process may be performed to directly bond the second semiconductor chips 200 that are vertically adjacent to each other.

[0102] A third semiconductor chip 300 is prepared. The third semiconductor chip 300 includes a third semiconductor substrate 310, a third integrated circuit 315, a third lower insulating layer 321, a third lower pad 350, and a third wiring pattern 330 as described in the examples of Figures 1A and 1E, but may not include a third through via, a third upper pad, and a third upper insulating layer.

[0103] The third semiconductor chip 300 is disposed on the uppermost second semiconductor chip 200, and the third semiconductor chip 300 is directly bonded to the uppermost second semiconductor chip 200. The direct bonding between the uppermost second semiconductor chip 200 and the third semiconductor chip 300 is performed by a hybrid bonding process. The third semiconductor chip 300 is one of the plurality of third semiconductor chips 300. The plurality of third semiconductor chips 300 are disposed spaced apart from each other in the horizontal direction.

[0104] 5J, a molding layer 430 is formed on the upper surface of the base structure 500 to cover the sidewalls of the plurality of first semiconductor chips 100, the sidewalls of the plurality of second semiconductor chips 200, and the sidewalls of the plurality of third semiconductor chips 300. The molding layer 430 also covers the upper surfaces 300a of the third semiconductor chips 300. Each of the upper surfaces 300a of the third semiconductor chips 300 corresponds to the upper surface of the corresponding third semiconductor substrate 310. The molding layer 430 is formed at the wafer level. Then, a grinding process is performed on the upper surface of the molding layer 430 to expose the upper surface 300a of the third semiconductor chip 300. After the grinding process, the upper surface 300a of the third semiconductor chip 300 is positioned at substantially the same level as the upper surface 430a of the molding layer 430. The grinding process includes a chemical mechanical polishing (CMP) process.

[0105] 5K, a carrier substrate 990 is provided on the upper surface 300a of the third semiconductor chip 300 and the upper surface 430a of the molding layer 430. A carrier adhesive layer 980 is formed between the carrier substrate 990 and the third semiconductor chip 300 and between the carrier substrate 990 and the molding layer 430. The carrier substrate 990 is attached to the third semiconductor chip 300 and the molding layer 430 by the carrier adhesive layer 980. The carrier substrate 990 is a temporary substrate or a support substrate. The carrier substrate 990 supports a wafer package. The wafer package includes a base structure 500, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, a lower encapsulation layer 410, an insulating layer 420, and a molding layer 430.

[0106] Referring to FIG. 5L, the wafer package and carrier substrate 990 are flipped over so that the base structure 500 faces upward.

[0107] 5M, a grinding process is performed on the base structure 500 to thin the base substrate 510. The grinding process exposes the lower surfaces of the conductive vias 570. The lower surfaces of the conductive vias 570 are coplanar with the lower surface of the base substrate 510. The conductive via 570 is one of the plurality of conductive vias 570. The grinding process includes a chemical mechanical polishing (CMP) process. The lower surface of the base structure 500 includes the lower surfaces of the plurality of conductive vias 570 and the lower surface of the base substrate 510.

[0108] 5N, a redistribution layer 600 is formed on the lower surface of the base structure 500. Forming the redistribution layer 600 includes forming an organic insulating layer 610 through a coating process, forming a redistribution pattern 630 through a first plating process, and forming a redistribution pad 650 through a second plating process. The redistribution layer 600 is formed in a chip first process. The solder ball terminals 700 are formed on the lower surface of the redistribution layer 600 and are electrically connected to the redistribution pads 650.

[0109] Referring to FIG. 5O, the wafer package and carrier substrate 990 are turned over so that the solder ball terminals 700 face downwards.

[0110] Referring to FIG. 5P, the carrier substrate 990 and the carrier adhesive layer 980 may be removed to expose the top surface of the third semiconductor chip 300 and the top surface of the molding layer 430 .

[0111] A sawing process is performed on the molding layer 430, the insulating layer 420, the lower encapsulation layer 410, the base structure 500, and the redistribution layer 600 to cut the molding layer 430, the insulating layer 420, the lower encapsulation layer 410, the base structure 500, and the redistribution layer 600 as indicated by the dashed-dotted lines. This completes the manufacturing of the semiconductor packages 10. The semiconductor packages 10 are separated from one another by the sawing process. Each of the semiconductor packages 10 is identical to the semiconductor package 10 described in the example of FIG. 1A . For example, each of the semiconductor packages 10 includes a redistribution layer 600, a base structure 500, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, solder ball terminals 700, the lower encapsulation layer 410, the insulating layer 420, and the molding layer 430.

[0112] FIG. 6 is a diagram illustrating a semiconductor package according to an embodiment.

[0113] Referring to FIG. 6, the semiconductor package 1 includes solder balls 825, a package substrate 820, interposer solder balls 815, an interposer substrate 810, a semiconductor device 20, and a chip stack package 10'.

[0114] The package substrate 820 includes substrate wiring 823. For example, a printed circuit board is used as the package substrate 820. The substrate wiring 823 is provided within the package substrate 820. Being electrically connected to the package substrate 820 means being electrically connected to at least one of the substrate wiring 823. The substrate wiring 823 includes a metal such as copper, aluminum, tungsten, and / or titanium.

[0115] Solder balls 825 are provided on the bottom surface of the package substrate 820 and are electrically connected to the substrate traces 823. An external electrical signal is transmitted to the solder balls 825. The solder balls 825 include a solder material.

[0116] An interposer substrate 810 is provided on a package substrate 820. The interposer substrate 810 includes upper interposer pads 811 and interposer wiring 813. The upper interposer pads 811 are disposed on the upper surface of the interposer substrate 810. The upper interposer pads 811 include a metal. The interposer wiring 813 is provided within the interposer substrate 810 and is electrically connected to the upper interposer pads 811. Being electrically connected to the interposer substrate 810 means being electrically connected to at least one of the interposer wiring 813. The interposer wiring 813 includes a metal such as copper, aluminum, tungsten, and / or titanium.

[0117] The interposer solder balls 815 are disposed between the package substrate 820 and the interposer substrate 810 and are electrically connected to the package substrate 820 and the interposer substrate 810. The pitch of the interposer solder balls 815 is smaller than the pitch of the solder balls 825. The interposer solder balls 815 include a solder material.

[0118] The chip stack package 10′ is disposed on the upper surface of the interposer substrate 810. The semiconductor package 10 described in the example of FIG. 1A is used as the chip stack package 10′. For example, the chip stack package 10′ includes a redistribution layer 600, a base structure 500, a first semiconductor chip 100, a second semiconductor chip 200, a third semiconductor chip 300, solder ball terminals 700, a lower encapsulation layer 410, an insulating layer 420, and a molding layer 430. Alternatively, the semiconductor package 10A of FIG. 2, the semiconductor package 10B of FIG. 3, or the semiconductor package 10C of FIG. 4 may be used as the chip stack package 10′.

[0119] The solder ball terminals 700 are disposed on the upper interposer pads 811 and are electrically connected to the upper interposer pads 811. For example, the solder ball terminals 700 are bonded to the upper surfaces of the corresponding upper interposer pads 811. The pitch of the solder ball terminals 700 is smaller than the pitch of the interposer solder balls 815.

[0120] The semiconductor device 20 is provided on the interposer substrate 810 and is laterally spaced apart from the chip stack package 10'. The semiconductor device 20 is a graphics processing unit (GPS). It includes a Graphics Processing Unit (GPU) or Central Processing Unit (CPU).

[0121] The semiconductor device 20 includes an integrated circuit and chip pads. The integrated circuit is provided within the semiconductor device 20. The chip pads are provided on the bottom surface of the semiconductor device 20 and are electrically connected to the integrated circuit of the semiconductor device 20.

[0122] The lower bumps 770 are interposed between the interposer substrate 810 and the semiconductor device 20. For example, the lower bumps 770 connect to the chip pads of the semiconductor device 20 and the corresponding upper interposer pads 811. The lower bumps 770 include a solder material. The pitch of the lower bumps 770 is smaller than the pitch of the interposer solder balls 815. The semiconductor device 20 is electrically connected to the chip stack package 10′ or the solder balls 825 via the interposer substrate 810.

[0123] A molding pattern 480 is disposed on the upper surface of the interposer substrate 810 to cover the sidewalls of the chip stack package 10′ and the sidewalls of the semiconductor device 20. The molding pattern 480 includes a polymer such as an epoxy molding material. The molding pattern 480 has insulating properties.

[0124] Unlike the illustrated example, the semiconductor package 1 includes two or more chip stack packages 10', in which case the semiconductor device 20 is disposed between the chip stack packages 10'.

[0125] According to the present invention, the first semiconductor chip at the chip level that has passed the test can be used in the manufacturing process of the semiconductor package, thereby improving the efficiency of the manufacturing process of the semiconductor package.

[0126] The semiconductor package has high capacity and high performance characteristics. The first semiconductor chip is directly bonded to the base structure, which reduces the size of the semiconductor package.

[0127] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments, and various other combinations, modifications, and environments can be used within the scope of the gist of the invention.

Claims

1. a base structure; a first semiconductor chip disposed on an upper surface of the base structure and directly bonded to the base structure; a second semiconductor chip on the first semiconductor chip; a lower encapsulation layer disposed on the upper surface of the base structure and covering a sidewall of the first semiconductor chip; a molding layer provided on an upper surface of the lower encapsulation layer and covering a sidewall of the second semiconductor chip;

2. The semiconductor package of claim 1 , further comprising an insulating layer disposed between the first semiconductor chip and the second semiconductor chip and extending between the lower encapsulation layer and the molding layer.

3. The first semiconductor chip a first semiconductor substrate; a first through via in the first semiconductor substrate; a first upper pad on the top surface of the first through via; the first through via extends further into the insulating layer; The semiconductor package according to claim 2 , wherein the insulating layer covers a side surface of the first upper pad.

4. The semiconductor package of claim 3 , wherein an upper surface of the lower encapsulation layer is coplanar with an upper surface of the first semiconductor substrate.

5. The semiconductor package of claim 3 , wherein the insulating layer further covers an upper sidewall of the first through via.

6. The semiconductor package of claim 2 , wherein an outer wall of the molding layer is vertically aligned with an outer wall of the insulating layer and an outer wall of the lower encapsulation layer.

7. the second semiconductor chip further includes a second lower insulating layer on its lower surface; The semiconductor package of claim 2 , wherein the insulating layer is directly bonded to an upper surface of the second lower insulating layer.

8. The base structure includes: a conductive via in the base substrate; an insulating base layer on the base substrate; a conductive pad on the conductive via and in the base insulative layer; the first semiconductor chip includes first lower pads on a lower surface thereof; The semiconductor package of claim 1 , wherein the conductive pad is directly bonded to the first lower pad.

9. a base structure; a first semiconductor chip disposed on the upper surface of the base structure, the first semiconductor chip including a first substrate, a first through via, and a first upper pad; a lower encapsulation layer disposed on the upper surface of the base structure and covering a sidewall of the first semiconductor chip; an insulating layer disposed on the first substrate and covering a side surface of the first upper pad; The insulating layer extends over an upper surface of the lower encapsulation layer.

10. a base structure including a base substrate, conductive vias in the base substrate, a base insulating layer on the base substrate, and conductive pads in the base insulating layer; a redistribution layer on a lower surface of the base structure; a solder ball terminal provided on the lower surface of the redistribution layer and electrically connected to the conductive via through the redistribution layer; a first semiconductor chip disposed on the upper surface of the base structure, the first semiconductor chip including a first substrate, a first lower insulating layer on the lower surface of the first substrate, a first lower pad in the first lower insulating layer, a first through via penetrating the first substrate, and a first upper pad electrically connected to the first through via; a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the second semiconductor chips including a second substrate, a second lower insulating layer, a second lower pad, a second through via, a second upper insulating layer, and a second upper pad; a lower encapsulation layer disposed on the upper surface of the base structure and covering a sidewall of the first semiconductor chip; a molding layer disposed on the lower encapsulation layer and covering sidewalls of the plurality of second semiconductor chips; an insulating layer provided between the lower encapsulation layer and the molding layer and between the first semiconductor chip and a second semiconductor chip that is the bottommost of the second semiconductor chips, the insulating layer covers a side surface of the second upper pad; The first semiconductor chip is directly bonded to the base structure.

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