Driving circuit, display device, and electrophoretic display device

Abstract

To provide a driving circuit, a display device, and an electrophoretic display device capable of reducing the speed of transistor deterioration even if the level of a driving signal is increased.SOLUTION: A unit circuit 1a of a gate driving circuit includes a transistor T1 to which a clock signal CKA is applied, a transistor T2 in which a set signal is input to a gate electrode, a VDD signal is applied to a source electrode, and a drain electrode is connected to a node N1, and a transistor T3 in which a reset signal is input to a gate electrode, a VSS signal is applied to a source electrode, and a drain electrode is connected to the node N1. The difference between a voltage value (VGH2) of the VDD signal and a voltage value (VGL) of the VSS signal is smaller than an amplitude A1 of the clock signal CKA.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a drive circuit, a display device, and an electrophoretic display device. [Background technology]

[0002] The shift register circuit described in Patent Document 1 constitutes a gate line driving circuit. The shift register circuit includes multiple unit shift register circuits. Each unit shift register circuit includes a first transistor to which a clock signal is input, a second transistor to whose gate a set signal is input, and a third transistor to which a reset signal is input. A high-level DC voltage is applied to the drain of the second transistor. A low-level DC voltage is applied to the third transistor. When a set signal is input to the second transistor and a clock signal is input to the first transistor, the unit shift register circuit outputs an output signal of the same level as the clock signal. The difference between the high-level DC voltage and the low-level DC voltage is equal to the amplitude of the clock signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-135910 Summary of the Invention [Problem to be solved by the invention]

[0004] Here, the higher the voltage applied to a transistor, the faster it deteriorates. In the shift register circuit described in Patent Document 1, if an attempt is made to increase the level of the output signal (the drive signal to be output), the transistor deteriorates more quickly.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a drive circuit, a display device, and an electrophoretic display device that can reduce the rate at which transistors deteriorate even when the level of the drive signal is increased. [Means for solving the problem]

[0006] To solve the above problems, a first aspect of the present invention provides a drive circuit that includes multiple stages and supplies drive signals to a group of scanning signal lines in response to input of multiple clock signals. The drive circuit includes a unit circuit that constitutes one of the multiple stages and outputs the drive signal to any one of the scanning signal lines of the group of scanning signal lines. The unit circuit includes a first node, a first transistor that outputs the drive signal to the scanning signal line, the first transistor having a gate electrode connected to the first node and a source electrode to which a first clock signal having a first voltage is applied, a second transistor that receives a set signal for the unit circuit, the second transistor having a gate electrode to which the set signal is input, a source electrode to which a second DC voltage is applied, and a drain electrode to which the second transistor is connected to the first node, and a third transistor that receives a reset signal for the unit circuit, the third transistor having a gate electrode to which the reset signal is input, a source electrode to which a third DC voltage is applied, and a drain electrode to which the third transistor is connected to the first node. A difference between the second voltage and the third voltage is smaller than the amplitude of the first voltage.

[0007] A display device according to a second aspect includes the drive circuit according to the first aspect and a display on which the group of scanning signal lines is arranged.

[0008] An electrophoretic display device according to a third aspect comprises a driving circuit according to the first aspect, a pixel transistor connected to one of the scanning signal lines, a pixel electrode connected to the pixel transistor, a counter electrode arranged opposite the pixel electrode, and charged particles arranged between the pixel electrode and the counter electrode. [Effects of the Invention]

[0009] According to the above configuration, even when the level of the drive signal is increased, the rate at which the transistor deteriorates can be reduced. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing the internal configuration of the display panel 10. As shown in FIG. [Figure 3] FIG. 3 is a circuit diagram showing the configuration of the pixel 21. [Figure 4] FIG. 4 is a cross-sectional view showing the configuration of the display unit 2. As shown in FIG. [Figure 5] FIG. 5 is a diagram showing the configuration of the gate drive circuit 1. As shown in FIG. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of the unit circuit 1a. [Figure 7] FIG. 7 is a timing chart for explaining the operation of the gate drive circuit 1 (unit circuit 1a). [Figure 8] FIG. 8 is a circuit diagram showing the configuration of a unit circuit according to a comparative example. [Figure 9] FIG. 9 is a circuit diagram showing the configuration of a gate drive circuit 201 according to the second embodiment. [Figure 10] FIG. 10 is a timing chart for explaining the operation of the unit circuit 1a according to the second embodiment. [Figure 11] FIG. 11 is a block diagram showing the configuration of a display device 300 according to the third embodiment. [Figure 12]FIG. 12 is a diagram showing the configuration of a gate drive circuit 301 according to the third embodiment. [Figure 13] FIG. 13 is a block diagram showing the configuration of a unit circuit 301a according to the third embodiment. [Figure 14] FIG. 14 is a timing chart for explaining the operation (forward scan) of the unit circuit 301a according to the third embodiment. [Figure 15] FIG. 15 is a timing chart for explaining the operation (reverse scanning) of the unit circuit 301a according to the third embodiment. [Figure 16] FIG. 16 is a circuit diagram showing the configuration of a gate drive circuit 401 according to the fourth embodiment. [Figure 17] FIG. 17 is a circuit diagram showing the configuration of a gate drive circuit 501 according to the fifth embodiment. [Figure 18] FIG. 18 is a circuit diagram showing the configuration of a gate drive circuit 601 according to the sixth embodiment. [Figure 19] FIG. 19 is a circuit diagram showing the configuration of a gate drive circuit 701 according to the seventh embodiment. [Figure 20] FIG. 20 is a circuit diagram showing the configuration of a gate drive circuit 801 according to the eighth embodiment. [Figure 21] FIG. 21 is a block diagram showing the configuration of a display device 900 according to the ninth embodiment. [Figure 22] FIG. 22 is a diagram showing the configuration of a gate drive circuit 901 according to the ninth embodiment. [Figure 23] FIG. 23 is a circuit diagram showing the configuration of a unit circuit 901a according to the ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications can be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in common between different drawings for identical parts or parts having similar functions, and repeated description thereof will be omitted. The configurations described in the embodiments and modifications may be combined or modified as appropriate within the scope of the gist of the present disclosure. To facilitate understanding of the description, the drawings referred to below show simplified or schematic configurations, and some components may be omitted.

[0012] [First embodiment] (Overall configuration of the display device) Fig. 1 is a block diagram showing the configuration of a display device 100 in a first embodiment. Fig. 2 is a block diagram showing the internal configuration of a display panel 10. Fig. 3 is a circuit diagram showing the configuration of a pixel 21. Fig. 4 is a cross-sectional view showing the configuration of a display unit 2.

[0013] The display device 100 according to the first embodiment is configured as an electrophoretic display and a non-emissive display. The display device 100 is also an electronic paper display. As shown in FIG. 1, the display device 100 includes a display panel 10, a control board 20, and a flexible printed circuit board 30. The display panel 10 includes two gate drive circuits 1, a display section 2 that is an area where an image is displayed, and a source drive circuit 3. The control board 20 is provided with a timing controller 4, a power supply circuit 5, and a level shifter circuit 6. The flexible printed circuit board 30 connects the display panel 10 and the control board 20.

[0014] 1, the timing controller 4 receives timing signals (horizontal synchronization signal, vertical synchronization signal, data enable signal, etc.) and video signals, and generates a digital video signal DV, a source start pulse signal SSP, a source clock signal SCK, a gate start pulse signal GSPa, and a gate clock signal GCKa based on the received signals. The timing controller 4 transmits the digital video signal DV, the source start pulse signal SSP, and the source clock signal SCK to each source driver circuit 3 via a flexible printed circuit board 30. The timing controller 4 also transmits the gate start pulse signal GSPa and the gate clock signal GCKa to a level shifter circuit 6.

[0015] The power supply circuit 5 generates a first gate-on voltage VGH1, a second gate-on voltage VGH2, and a gate-off voltage VGL based on power input from an external power supply or a battery (not shown). The first gate-on voltage VGH1, the second gate-on voltage VGH2, and the gate-off voltage VGL are DC voltages having constant levels (voltage values). In the first embodiment, the voltage values ​​have the relationship VGH1>VGH2>VGL. The power supply circuit 5 inputs the generated first gate-on voltage VGH1, the second gate-on voltage VGH2, and the gate-off voltage VGL to the level shifter circuit 6.

[0016] The level shifter circuit 6 generates clock signals CKA and CKB having a voltage value equal to the difference between the first gate-on voltage VGH1 and the gate-off voltage VGL, a VDD signal having a second gate-on voltage VGH2, and a VSS signal having the gate-off voltage VGL. The level shifter circuit 6 inputs the generated signals to the two gate drive circuits 1 via the flexible printed circuit board 30. The clock signal CKB is a signal whose phase is shifted by 180 degrees from the clock signal CKA.

[0017] 2, the two gate drive circuits 1 include a gate drive circuit 1 arranged on one side relative to the display unit 2 and a gate drive circuit 1 arranged on the other side relative to the display unit 2. The gate drive circuit 1 arranged on one side relative to the display unit 2 and the gate drive circuit 1 arranged on the other side relative to the display unit 2 have the same configuration. The two gate drive circuits 1 are gate drivers on arrays (GOA: Gate on Array) formed on an array substrate 41 (see FIG. 4) of the display panel 10.

[0018] The display panel 10 is provided with a plurality of (e.g., n) gate lines 11 constituting a group of scanning signal lines connected to a gate drive circuit 1, and a plurality of (e.g., m) source lines 12 constituting a group of source signal lines connected to a source drive circuit 3. n and m are both natural numbers. The gate lines 11 and the source lines 12 are arranged to intersect with each other, and pixels 21 are arranged in each region defined by the gate lines 11 and the source lines 12. The pixels 21 are arranged in a matrix on the display panel 10. The display panel 10 also is provided with a common voltage line 13 that supplies a common voltage Vcom to counter electrodes 24 (see FIG. 3) of the pixels 21.

[0019] 3, a pixel 21 is provided with a pixel transistor 22 and a pixel electrode 23. A gate electrode of the pixel transistor 22 is connected to a gate line 11. A source electrode of the pixel transistor 22 is connected to a source line 12. A drain electrode of the pixel transistor 22 is connected to the pixel electrode 23. A capacitance is formed between the pixel electrode 23 and a counter electrode 24 disposed opposite the pixel electrode 23.

[0020] As shown in FIG. 4, the display unit 2 includes an array substrate 41, a protective sheet 42, and an ink imaging film 43. The ink imaging film 43 is a front panel laminate (FPL) that uses electrophoretic ink technology, also known as electronic ink. The ink imaging film 43 includes a plurality of microcapsules 51, a plurality of charged particles 52a and 52b, a dispersion medium 53, and an insulating layer 54. The microcapsules 51 are disposed within the insulating layer 54. The plurality of charged particles 52a and 52b and the dispersion medium 53 are encapsulated within the microcapsules 51. The plurality of charged particles 52a and 52b include white charged particles 52a and black charged particles 52b. The white charged particles 52a are, for example, positively charged, and the black charged particles 52b are, for example, negatively charged. The dispersion medium 53 is an insulating liquid, such as an organic solvent. The insulating layer 54 fills the ink imaging film 43. The insulating layer 54 is made of, for example, a polymer resin material.

[0021] When the pixel transistor 22 is turned on by a drive signal (gate signal) supplied via the gate line 11, the source signal supplied via the source line 12 is written to (charged into) the pixel electrode 23. As a result, an electric field is generated between the pixel electrode 23 and the counter electrode 24. When the pixel electrode 23 is positive and the counter electrode 24 is negative, the black charged particles 52b are attracted to the pixel electrode 23, and the white charged particles 52a are attracted to the counter electrode 24. In this case, the display device 100 displays white to a user observing from the counter electrode 24 side. The counter electrode 24 is made of an electrode (indium tin oxide (ITO))) that transmits visible light.

[0022] (Configuration of gate drive circuit 1) Fig. 5 is a diagram showing the configuration of the gate drive circuit 1. Fig. 6 is a circuit diagram showing the configuration of a unit circuit 1a.

[0023] As shown in Fig. 5, the gate drive circuit 1 is made up of multiple (n) stages and includes a shift register circuit that sequentially supplies drive signals to gate lines 11 in response to input of clock signals CKA and CKB. The gate drive circuit 1 comprises multiple unit circuits 1a that constitute one of the multiple stages and output drive signals to the connected gate lines 11. The number of unit circuits 1a is the same as the number of gate lines 11. Fig. 5 shows unit circuits 1a from the k-th (natural number) stage to the k+2th stage.

[0024] The unit circuit 1a according to the first embodiment receives clock signals CKA and CKB, a VDD signal, and a VSS signal from the level shifter circuit 6. The k-th unit circuit 1a receives a drive signal output from the terminal OUT of the (k-1)th unit circuit 1a as a set signal at its terminal S. The k-th unit circuit 1a receives a drive signal output from the terminal OUT of the (k+1)th unit circuit 1a as a reset signal at its terminal R. As a result, when a gate start pulse signal is input as a set signal to the first-stage unit circuit 1a, drive signals are output to the gate lines 11 in sequence up to the n-th stage unit circuit 1a.

[0025] As shown in FIG. 6, the unit circuit 1a includes an output circuit 61, drive control circuits 62 to 64, and a node N1. The node N1 connects the output circuit 61 to the drive control circuits 62 to 64. The output circuit 61 is a circuit that outputs a drive signal to the gate line 11 connected to the unit circuit 1a. The drive control circuit 62 is a circuit that increases (charges) the potential of the node N1 in response to an input of a set signal. The drive control circuit 63 is a circuit that decreases (discharges) the potential of the node N1 in response to an input of a reset signal. The drive control circuit 64 is a circuit that separates the node N1 into a first portion N1a and a second portion N1b.

[0026] The output circuit 61 includes a transistor T1, a transistor T5, and a bootstrap capacitor Cbst. The transistor T1 is a transistor that outputs a drive signal to the gate line 11 in response to a clock signal CKA. The transistor T5 is a transistor that lowers (pulls down) the potential of the gate line 11 to the level of the VSS signal in response to the clock signal CKB. The bootstrap capacitor Cbst is a capacitor that turns on the transistor T1 with an increased potential due to charging.

[0027] The gate electrode of the transistor T1 is connected to the first portion N1a of the node N1. The source electrode of the transistor T1 is connected to a terminal to which a clock signal CKA is input. The drain electrode of the transistor T1 is connected to a terminal OUT to which a drive signal is output. One end of a bootstrap capacitor Cbst is connected to the gate electrode of the transistor T1, and the other end of the bootstrap capacitor Cbst is connected to the drain electrode of the transistor T1. The gate electrode of the transistor T5 is connected to a terminal to which a clock signal CKB is input. The source electrode of the transistor T5 is connected to a terminal to which a VSS signal is input. The drain electrode of the transistor T5 is connected to the terminal OUT to which a drive signal is output.

[0028] The drive control circuit 62 includes a transistor T2. The gate electrode of the transistor T2 is connected to a terminal S to which a set signal is input. The source electrode of the transistor T2 is connected to a terminal to which a VDD signal is input. The drain electrode of the transistor T2 is connected to the second portion N1b of the node N1.

[0029] The drive control circuit 63 includes a transistor T3. The gate electrode of the transistor T3 is connected to a terminal R to which a reset signal is input. The source electrode of the transistor T3 is connected to a terminal to which a VSS signal is input. The drain electrode of the transistor T3 is connected to the second portion N1b of the node N1.

[0030] The drive control circuit 64 includes a transistor T4. The gate electrode of the transistor T4 is connected to a terminal to which a VDD signal is input. The source electrode of the transistor T4 is connected to the second portion N1b. The drain electrode of the transistor T4 is connected to the first portion N1a.

[0031] The semiconductor layers of the transistors T1 to T5 contain an oxide semiconductor. The oxide semiconductor can be an In-Ga-Zn-O-based oxide semiconductor that is crystalline. This makes it possible to reduce power consumption, increase driving speed, and achieve higher resolution compared to when each transistor is made of amorphous silicon.

[0032] (Operation of unit circuit 1a) FIG. 7 is a timing diagram illustrating the operation of the gate drive circuit 1 (unit circuit 1a). As shown in FIG. 7, during a period before time t1, the potentials of the first portion N1a, the second portion N1b, and the terminal OUT are maintained at a low level (the potential of the gate-off voltage VGL). The clock signals CKA and CKB alternately go to a high level (the potential of the first gate-on voltage VGH1) each time a horizontal synchronization signal (1H) is input. The clock signal CKA is 180 degrees out of phase with the clock signal CKB. The amplitude A1 between the high and low levels of the clock signals CKA and CKB is equal to the difference between the first gate-on voltage VGH1 and the gate-off voltage VGL. The high level refers to a state in which the voltage is either the first gate-on voltage VGH1 or the second gate-on voltage VGH2, and the low level refers to a state in which the voltage is the gate-off voltage VGL.

[0033] In the first embodiment, the voltage value of the VDD signal is equal to the voltage value of the second gate-on voltage VGH2. The voltage value of the VSS signal is equal to the voltage value of the gate-off voltage VGL. As described above, there is a voltage relationship of VGH1>VGH2>VGL. Therefore, the difference Vd1 between the second gate-on voltage VGH2 and the gate-off voltage VGL is smaller than the amplitude A1.

[0034] At time t1, a set signal is input, and the potential of the terminal S changes from low to high. This turns on the transistor T2 (see FIG. 6), and the second portion N1b is charged to the second gate-on voltage VGH2. At this time t1, the transistor T4 also turns on. As a result, the first portion N1a is charged from low to the second gate-on voltage VGH2 minus the threshold voltage of the transistor T4 (VGH2-Vth4), where Vth4 is the threshold voltage of the transistor T4. Furthermore, the first portion N1a is in a floating state. Furthermore, as the potential of the first portion N1a rises, the transistor T1 is turned on. However, because the clock signal CKA is low, the potential of the terminal OUT is maintained at low.

[0035] At time t2, the clock signal CKA changes from low to high. This causes the transistor T1 to turn on, and the potential of the terminal OUT rises from low to high. At this time, the first portion N1a is floating. Due to the coupling between the capacitance of the bootstrap capacitor Cbst and the on-capacitance of the transistor T1, the potential of the first portion N1a increases by α × (VGH1 − VGL) from the potential (VGH2 − Vth4) (bootstrap operation). That is, the potential of the first portion N1a becomes (VGH2 − Vth4) + α × (VGH1 − VGL). Here, “α” is the coupling ratio of the first portion N1a, and α = (capacitance of the bootstrap capacitor Cbst + on-capacitance of the transistor T1) ÷ (total capacitance of the first portion N1a). This keeps the transistor T1 on, and the change in the clock signal CKA is directly output as a drive signal from the terminal OUT.

[0036] At time t3, when the clock signal CKA changes from high to low, the potential at the terminal OUT drops from high to low, causing the voltage of the first portion N1a, which had increased due to the bootstrap operation, to drop to the potential (VGH2-Vth4) before the increase.

[0037] At time t4, when the reset signal changes from low to high, the transistor T3 turns on, the second portion N1b is discharged from the second gate-on voltage VGH2 to low, and the first portion N1a is discharged from the potential of (VGH2-Vth4) to low.

[0038] (Comparison results between examples of the first embodiment and comparative examples) Next, a comparison result between the unit circuit 1a according to the example of the first embodiment and a unit circuit according to a comparative example will be described. Fig. 8 is a circuit diagram showing the configuration of the unit circuit according to the comparative example. The unit circuit according to the comparative example is configured to explain the effects of the example, and is not intended to explain the prior art.

[0039] 8, the unit circuit according to the comparative example includes transistors T1c, T2c, T3c, and T5c, a node N1c, and a bootstrap capacitor Cbstc. In the comparative example, a set signal is input to the gate electrode and source electrode of transistor T2c. The materials and characteristics of transistors T1c, T2c, T3c, and T5c are the same as those of transistors T1, T2, T3, and T5, respectively.

[0040] Here, if the threshold voltage of transistor T2c is Vth2, the voltage applied between the source electrode and drain electrode of transistor T2c (referred to as "stress voltage Vds") and the stress voltage Vds applied to transistor T3c are expressed by the following equation (1). Note that Vdc is the difference between the voltage value applied to the source electrode of transistor T2c and the potential of the VSS signal, α is the coupling ratio, and A1 is the amplitude of clock signal CKA. Furthermore, Vth2 is a value smaller than Vdc and A1. Vds = Vdc-Vth2+α×A1 (1) Furthermore, the voltage applied between the gate electrode and source electrode of the transistor T1c (referred to as "stress voltage Vgs") is given by the following equation (2). Vgs = Vdc-Vth2+(α-1)×A1 (2)

[0041] In the comparative example, the high level of the set signal is the same as the level of the drive signal in the previous stage (first gate-on voltage VGH1). Therefore, Vdc is equal to the difference between the first gate-on voltage VGH1 and the gate-off voltage VGL. As a result, A1 is equal to Vdc, and the stress voltage Vds is (1 + α)A1 - Vth2. Furthermore, the voltage Vgs is α × Vdc - Vth2. In the unit circuit of the comparative example, if VGH1 = 40V, VGL = -40V, A1 = 80V, α = 0.9, and Vth2 = 2V, Vds is 150V. Furthermore, Vgs is 70V.

[0042] Therefore, in the unit circuit of the comparative example, if such a high stress voltage is applied to the transistor, there is a high possibility that degradation will be accelerated.

[0043] In the unit circuit 1a according to the example of the first embodiment, a transistor T4 (see FIG. 6) is provided to isolate the node N1, and therefore the stress voltage Vds applied to the transistor T2 and the stress voltage Vds applied to the transistor T3 are expressed by the following formula (3). If the threshold voltage of the transistor T4 is Vth4, the stress voltage Vgs applied to the transistor T1 is expressed by the following formula (4). Note that Vth4 is a value smaller than Vd1 and A1. Furthermore, Vd1 is the difference between the voltage value applied to the source electrode of the transistor T2 and the potential of the VSS signal, α is the coupling ratio, and A1 is the amplitude of the clock signal CKA. Vds = Vd1 (3) Vgs = Vd1-Vth4+(α-1)×A1 (4)

[0044] Here, Vd1 is equal to the difference between the second gate-on voltage VGH2 and the gate-off voltage VGL. In the unit circuit 1a according to the embodiment, if VGH1=40 V, VGH2=0 V, VGL=-40 V, A1=80 V, α=0.9, and Vth4=2 V, Vds is 40 V. Also, Vgs is 30 V.

[0045] The Vds of the comparative example is 150 V, while the Vds of the example is 40 V. Furthermore, the Vgs of the comparative example is 70 V, while the Vgs of the example is 30 V. In this way, the voltage applied to the transistors T1 to T3 can be reduced, and therefore the rate at which the transistors T1 to T3 deteriorate can be reduced.

[0046] [Second embodiment] Next, the configuration of a gate drive circuit 201 according to the second embodiment will be described with reference to Figures 9 and 10. In a unit circuit 201a of the second embodiment, a drive control circuit 265 (stabilization circuit) is further provided in addition to the unit circuit 1a of the first embodiment. Note that the same components as in the first embodiment are denoted by the same reference numerals as in the first embodiment, and description thereof will be omitted.

[0047] 9 is a circuit diagram showing the configuration of a gate drive circuit 201 according to the second embodiment. As shown in FIG. 9, the gate drive circuit 201 according to the second embodiment includes a unit circuit 201a. The unit circuit 201a includes a node N2, an output circuit 261, and a drive control circuit 265. The output circuit 261 includes a transistor T15. Unlike the transistor T5 according to the first embodiment, the transistor T15 has a gate electrode connected to the node N2.

[0048] The drive control circuit 265 includes transistors T6 to T8. The source electrode and gate electrode of the transistor T6 are connected to a terminal to which a VDD signal is input. The drain electrode of the transistor T6 is connected to a node N2. The gate electrode of the transistor T7 is connected to the second portion N1b of the node N1. The source electrode of the transistor T7 is connected to a terminal to which a VSS signal is supplied. The drain electrode of the transistor T7 is connected to the node N2. The gate electrode of the transistor T8 is connected to the node N2. The source electrode of the transistor T8 is connected to a terminal to which a VSS signal is supplied. The drain electrode of the transistor T8 is connected to the second portion N1b of the node N1.

[0049] FIG. 10 is a timing diagram illustrating the operation of the unit circuit 1a according to the second embodiment. As shown in FIG. 10, the operation of the unit circuit 201a from time t1 to time t4 is the same as the operation from time t1 to time t4 shown in FIG. 7. Before time t1 and after time t4, the first portion N1a and the second portion N1b of the node N1 are constantly pulled down by the transistor T8 (they are not floating, but are maintained in the VGL state). Also, before time t1 and after time t4, the potential of the terminal OUT is constantly pulled down by the transistor T5 (they are not floating, but are maintained in the VGL state). Note that in the first embodiment, before time t1 and after time t4, the node N1 is in a floating state, and the terminal OUT is pulled down (with a 50% duty) only for 50% of the period during which the clock signal CKB is input.

[0050] Here, when node N1 is in a floating state, the potential of node N1 may fluctuate due to noise in the clock signal or other signals, which may cause noise to appear in the drive signal output from the gate drive circuit. In contrast, according to the second embodiment, node N1 can be prevented from entering a floating state, thereby preventing the potential of node N1 from fluctuating due to noise in the clock signal CKA or other signals. As a result, noise can be prevented from appearing in the drive signal output from gate drive circuit 201. Note that other configurations and effects of the second embodiment are similar to those of the first embodiment.

[0051] [Third embodiment] Next, the configuration of a display device 300 according to a third embodiment will be described with reference to Figures 11 to 15. A gate drive circuit 301 according to the third embodiment is configured to not only be capable of sequentially transmitting drive signals to the first to nth (final) gate lines 11 (called "forward scan"), but also be capable of sequentially transmitting drive signals to the nth to first gate lines 11 (called "reverse scan"). Note that the same components as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0052] Fig. 11 is a block diagram showing the configuration of a display device 300 according to the third embodiment. Fig. 12 is a diagram showing the configuration of a gate drive circuit 301 according to the third embodiment. Fig. 13 is a block diagram showing the configuration of a unit circuit 301a according to the third embodiment.

[0053] As shown in FIG. 11, the display device 300 includes a gate drive circuit 301 and a level shifter circuit 306 provided on a control board 320. The level shifter circuit 306 outputs a VFWD signal and a VBWD signal in addition to the signals output from the level shifter circuit 6 according to the first embodiment. When performing forward scanning, the level shifter circuit 306 sets the level of the VFWD signal to the second gate-on voltage VGH2 and the level of the VBWD signal to the gate-off voltage VGL. When performing reverse scanning, the level shifter circuit 306 sets the level of the VFWD signal to the gate-off voltage VGL and the level of the VBWD signal to the second gate-on voltage VGH2.

[0054] As shown in Fig. 12, a VFWD signal and a VBWD signal are input to each unit circuit 301a in the gate drive circuit 301. As shown in Fig. 13, the unit circuit 301a includes a drive control circuit 362 including a transistor T32 and a drive control circuit 363 including a transistor T33. Unlike the transistor T2 according to the first embodiment, the transistor T32 receives a VFWD signal at its source electrode. Unlike the transistor T3 according to the first embodiment, the transistor T33 receives a VBWD signal at its source electrode.

[0055] FIG. 14 is a timing diagram illustrating the operation (forward scan) of the unit circuit 301a according to the third embodiment. FIG. 15 is a timing diagram illustrating the operation (reverse scan) of the unit circuit 301a according to the third embodiment. As shown in FIG. 14, when forward scan is performed, the level of the VFWD signal becomes the second gate-on voltage VGH2 and the level of the VBWD signal becomes the gate-off voltage VGL, so that the unit circuit 301a operates in the same manner as the unit circuit 1a according to the first embodiment (see FIG. 7). Also, as shown in FIG. 15, when reverse scan is performed, the level of the VFWD signal becomes the gate-off voltage VGL and the level of the VBWD signal becomes the second gate-on voltage VGH2. Therefore, the signal input to the terminal R functions as a set signal, and the signal input to the terminal S functions as a reset signal. As a result, the unit circuits 301a operate sequentially from the final stage (nth stage) to the first stage. That is, at time t1a, the level of the terminal R becomes High. The potentials at time points t2a and t3a are the same as the potentials at time points t2 and t3 in Fig. 7. At time point t4a, the potential of terminal S changes from low level to high level. At time point t5a, the potential of terminal S changes from high level to low level.

[0056] The difference between the level of the VFWD signal and the level of the VBWD signal is VGH2-VGL, which is smaller than A1. As a result, even in the bidirectional scanning configuration of the third embodiment, the rate at which the transistors T1, T32, and T33 deteriorate can be reduced. Note that the same components as in the first embodiment are designated by the same reference numerals as in the first embodiment, and their description will be omitted.

[0057] [Fourth embodiment] Next, the configuration of a gate drive circuit 401 according to a fourth embodiment will be described with reference to Fig. 16. The fourth embodiment has a configuration that combines the drive control circuit 265 (stabilization circuit) of the second embodiment with the configuration capable of bidirectional scanning of the third embodiment. Note that the same components as those of any of the first to third embodiments are denoted by the same reference numerals as those of the first to third embodiments, and their description will be omitted.

[0058] Fig. 16 is a circuit diagram showing the configuration of a gate drive circuit 401 according to the fourth embodiment. As shown in Fig. 16, a unit circuit 401a of the gate drive circuit 401 includes an output circuit 261 and drive control circuits 265, 362, and 363. As a result, according to the fourth embodiment, it is possible to achieve both the effects of the second embodiment and the effects of the third embodiment.

[0059] [Fifth embodiment] Next, the configuration of a gate drive circuit 501 according to the fifth embodiment will be described with reference to Fig. 17. Unlike the first embodiment, the fifth embodiment does not include a drive control circuit 64. This allows the number of elements to be reduced compared to the gate drive circuit 1 of the first embodiment. Note that the same components as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and their description will be omitted.

[0060] FIG. 17 is a circuit diagram showing the configuration of a gate drive circuit 501 according to the fifth embodiment. A unit circuit 501a of the gate drive circuit 501 includes a node N51. In the fifth embodiment, since the transistor T4 is not provided, the node N51 is formed by directly connecting the first portion N1a and the second portion N1b according to the first embodiment. The stress voltage Vds applied to the transistor T2 and the stress voltage Vds applied to the transistor T3 are given by the following equation (5). Here, it is assumed that VGH > VGH2 and that the voltage difference is sufficiently larger than the threshold voltage Vth2 of T2. The voltage Vgs applied to the gate electrode of the transistor T1 is given by the following equation (6). Here, using the same values ​​as in the example and comparative example described above, Vds is 112V and Vgs is 32V. That is, while the Vds in the comparative example is 150V and the Vgs in the comparative example is 70V, in the fifth embodiment, the voltages applied to the transistors T1 to T3 can be reduced. Vds = (VGH2+α×A1)-(VGL) = Vd1+α×A1 (5) Vgs = (VGH2+α×A1)-(VGH) = Vd1+(α-1)×A1 (6)

[0061] [Sixth embodiment] Next, the configuration of a gate drive circuit 601 according to a sixth embodiment will be described with reference to Fig. 18. In the sixth embodiment, each of the transistors T62 to T64 includes two thin film transistors connected in series. Note that the same components as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and their description will be omitted.

[0062] Fig. 18 is a circuit diagram showing the configuration of a gate drive circuit 601 according to the sixth embodiment. As shown in Fig. 18, a unit circuit 601a of the gate drive circuit 601 includes drive control circuits 662 to 664. The drive control circuit 662 includes a transistor T62. The drive control circuit 663 includes a transistor T63. The drive control circuit 664 includes a transistor T64. The transistor T62 includes thin-film transistors T62a and T62b. The transistor T63 includes thin-film transistors T63a and T63b. The transistor T64 includes thin-film transistors T64a and T64b.

[0063] The gate electrode of the thin-film transistor T62a is connected to the gate electrode of the thin-film transistor T62b. The thin-film transistors T62a and T62b are connected in series, and the drain electrode of the thin-film transistor T62a is connected to the source electrode of the thin-film transistor T62b. This allows the source electrode of the thin-film transistor T62a to function as the source electrode of the transistor T62, and the drain electrode of the thin-film transistor T62b to function as the drain electrode of the transistor T62. The function of the transistor T62 is similar to that of the transistor T2 according to the first embodiment.

[0064] The gate electrode of the thin-film transistor T63a is connected to the gate electrode of the thin-film transistor T63b. The thin-film transistors T63a and T63b are connected in series, and the source electrode of the thin-film transistor T63a is connected to the drain electrode of the thin-film transistor T63b. As a result, the drain electrode of the thin-film transistor T63a functions as the drain electrode of the transistor T62, and the source electrode of the thin-film transistor T63b functions as the source electrode of the transistor T63. The function of the transistor T63 is similar to that of the transistor T3 according to the first embodiment.

[0065] The gate electrode of the thin-film transistor T64a is connected to the gate electrode of the thin-film transistor T64b. The thin-film transistors T64a and T64b are connected in series, and the drain electrode of the thin-film transistor T64a is connected to the source electrode of the thin-film transistor T63b. As a result, the source electrode of the thin-film transistor T64a functions as the source electrode of the transistor T64, and the drain electrode of the thin-film transistor T64b functions as the drain electrode of the transistor T64. The function of the transistor T64 is similar to that of the transistor T4 according to the first embodiment.

[0066] According to the sixth embodiment, it is possible to reduce the stress voltage applied to each of the thin film transistors constituting the transistors T62 to T64. Other configurations and effects of the sixth embodiment are similar to those of the first embodiment.

[0067] [Seventh embodiment] Next, the configuration of a gate drive circuit 701 according to the seventh embodiment will be described with reference to Fig. 19. The seventh embodiment is a combination of the configuration of the second embodiment (stabilization circuit) and the configuration of the sixth embodiment. Fig. 19 is a circuit diagram showing the configuration of the gate drive circuit 701 according to the seventh embodiment. Note that the same components as those in any of the first to sixth embodiments are denoted by the same reference numerals as those in any of the first to sixth embodiments, and their description will be omitted.

[0068] As shown in FIG. 19, the gate drive circuit 701 includes an output circuit 261, drive control circuits 662 to 664, and a drive control circuit 765. The drive control circuit 765 includes a transistor T78. The transistor T78 includes thin-film transistors T78a and T78b connected in series. The gate electrode of the thin-film transistor T78a is connected to the gate electrode of the thin-film transistor T78b. The thin-film transistors T78a and T78b are also connected in series, and the source electrode of the thin-film transistor T78a is connected to the drain electrode of the thin-film transistor T78b. As a result, the drain electrode of the thin-film transistor T78a functions as the drain electrode of the transistor T78, and the source electrode of the thin-film transistor T78b functions as the source electrode of the transistor T78. The function of the transistor T78 is similar to that of the transistor T8 according to the second embodiment.

[0069] According to the seventh embodiment, it is possible to reduce the stress voltage applied to each thin film transistor constituting the transistor T78. The other configurations and effects of the seventh embodiment are similar to those of the second or sixth embodiment.

[0070] [Eighth embodiment] Next, the configuration of a gate drive circuit 801 according to an eighth embodiment will be described with reference to Fig. 20. The eighth embodiment is a combination of the configuration of the seventh embodiment and the configuration of the third embodiment (bidirectional scanning). Fig. 20 is a circuit diagram showing the configuration of a gate drive circuit 801 according to the eighth embodiment. Note that the same components as those in any of the first to seventh embodiments are denoted by the same reference numerals as those in any of the first to seventh embodiments, and description thereof will be omitted.

[0071] 20, the gate drive circuit 801 includes drive control circuits 862 and 863. The drive control circuit 862 includes a transistor T62. The drive control circuit 863 includes a transistor T63. A VFWD signal is input to the drive control circuit 862. A VBWD signal is input to the drive control circuit 863. As a result, according to the eighth embodiment, bidirectional scanning is possible, while achieving the same effects as those of the seventh embodiment.

[0072] [Ninth embodiment] Next, the configuration of a display device 900 according to a ninth embodiment will be described with reference to Figures 21 to 23. In the ninth embodiment, a clear signal is supplied to a unit circuit 901a at least immediately after the power is turned on or immediately before the power is turned off. Note that the same components as those in any of the first to eighth embodiments are denoted by the same reference numerals as those in any of the first to eighth embodiments, and description thereof will be omitted.

[0073] FIG. 21 is a block diagram showing the configuration of a display device 900 according to the ninth embodiment. FIG. 22 is a diagram showing the configuration of a gate drive circuit 901 according to the ninth embodiment. FIG. 23 is a circuit diagram showing the configuration of a unit circuit 901a according to the ninth embodiment. As shown in FIG. 21, the display device 900 includes a gate drive circuit 901 and a control substrate 920. The control substrate 920 is provided with a level shifter circuit 906. The level shifter circuit 906 transmits a CLR signal to the gate drive circuit 901 when the display device 900 is powered on and before driving (scanning) of the gate drive circuit 901 starts. Furthermore, when the display device 900 is powered off, the level shifter circuit 906 transmits a CLR signal to the gate drive circuit 901 after driving (scanning) of the gate drive circuit 901 has finished and before the power is turned off.

[0074] 22, the gate drive circuit 901 includes a plurality of unit circuits 901a. A CLR signal is input to each of the plurality of unit circuits 901a.

[0075] As shown in FIG. 23, the unit circuit 901a includes initialization control circuits 909 to 911 in addition to the configuration of the unit circuit 801a according to the eighth embodiment.

[0076] The initialization control circuit 909 includes a transistor T9. The transistor T9 includes two thin film transistors connected in series, and a CLR signal is input to the gate electrode of the transistor T9. The source electrode of the transistor T9 is connected to a terminal to which a VSS signal is supplied. The drain electrode of the transistor T9 is connected to the second portion N1b of the node N1.

[0077] The initialization control circuit 910 includes a transistor T10. A CLR signal is input to the gate electrode of the transistor T10. A source electrode of the transistor T10 is connected to a terminal to which a VSS signal is supplied. A drain electrode of the transistor T10 is connected to the terminal OUT.

[0078] The initialization control circuit 911 includes a transistor T11. A CLR signal is input to the gate electrode of the transistor T11. A source electrode of the transistor T11 is connected to a terminal to which a VSS signal is supplied. A drain electrode of the transistor T11 is connected to a node N2.

[0079] According to the ninth embodiment, charges can be removed from the node N1, the node N2, and the terminal OUT at least one of immediately after the power is turned on and immediately before the power is turned off. It is possible to prevent unexpected operation caused by charges present at the node N1, the node N2, and the terminal OUT immediately after the power is turned on. Furthermore, when the display device 900 is configured as an electronic paper display, control is executed in the following order: rewriting of a page (image), power off, power on, and page rewriting. Therefore, according to the ninth embodiment, it is possible to prevent a voltage caused by charges from being applied to each transistor in the unit circuit 901a after the power is turned off.

[0080] [Variations] Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the invention. Therefore, the present invention is not limited to the above-described embodiments, and can be modified as appropriate within the scope of the spirit of the invention. Modifications of the above-described embodiments will be described below.

[0081] (1) In the first to ninth embodiments, the display device is configured as an electrophoretic display device, but the present disclosure is not limited to this. For example, the display device may be configured as a liquid crystal display device, an organic EL display device, a micro LED display device, or the like.

[0082] (2) In the first to ninth embodiments, examples have been shown in which the display device is provided with two gate drive circuits, but the present disclosure is not limited to this. For example, the display device may be provided with only one gate drive circuit, or may be provided with three or more gate drive circuits.

[0083] (3) In the first to ninth embodiments, an example was shown in which the clock signal has two phases, CKA and CKB, but the present disclosure is not limited to this. The clock signal may have two phases (single phase or three or more phases).

[0084] (4) In the first to ninth embodiments, examples of values ​​for the voltage and coupling ratio are shown, but the present disclosure is not limited to the above-mentioned examples.

[0085] (5) In the first to ninth embodiments, the transistor includes a crystalline In-Ga-Zn-O oxide semiconductor, but the present disclosure is not limited to this. The transistor may include an amorphous In-Ga-Zn-O oxide semiconductor, an oxide semiconductor other than In-Ga-Zn-O, or silicon.

[0086] (6) In the first to ninth embodiments, examples have been shown in which the bootstrap capacitor Cbst is provided in the unit circuit, but the present disclosure is not limited to this. If the bootstrap operation can be performed by the capacitance of the transistor T1, the bootstrap capacitor does not need to be provided in the unit circuit.

[0087] The above-described configuration can also be explained as follows.

[0088] A drive circuit according to a first configuration includes a plurality of stages and supplies a drive signal to a group of scanning signal lines in response to input of a plurality of clock signals. The drive circuit includes a unit circuit constituting one of the stages and outputting the drive signal to one of the scanning signal lines. The unit circuit includes a first node, a first transistor that outputs the drive signal to the scanning signal line, the first node being connected to a gate electrode of the first transistor and receiving a first clock signal having a first voltage at a source electrode of the first transistor, a second transistor that receives a set signal for the unit circuit, the second transistor receiving the set signal at a gate electrode of the second transistor, a second DC voltage being applied to a source electrode of the second transistor, and a drain electrode of the second transistor connected to the first node, and a third transistor that receives a reset signal for the unit circuit, the third transistor receiving the reset signal at a gate electrode of the third transistor, a third DC voltage being applied to a source electrode of the third transistor, and a drain electrode of the third transistor connected to the first node. The difference between the second voltage and the third voltage is smaller than the amplitude of the first voltage (first configuration).

[0089] Here, the amplitude of the first voltage is A1, the difference between the second and third voltages is Vd1, the threshold voltage of the second transistor is Vth2, and a multiplier α is based on the capacitance between the first node and the drain electrode of the first transistor. During the period when the drive circuit is operating, the voltage applied between the source and drain electrodes of the second transistor (referred to as "stress voltage Vds") and the stress voltage Vds applied to the third transistor are expressed by the following equation (1a). Note that Vth2 is a smaller value than Vd1 and A1. Vds = Vd1-Vth2+α×A1 (1a) Moreover, the voltage Vgs applied to the gate electrode of the first transistor is given by the following equation (2a). Vgs = Vd1-Vth2+(α-1)×A1 (2a)

[0090] Typically, A1 is equal to Vd1, so in this case, the stress voltage Vds is (1 + α)A1 - Vth2. The voltage Vgs is α × Vd1 - Vth2. For example, if A1 = 80 V, α = 0.9, and Vth2 = 2 V, Vds is 150 V. Vgs is 70 V. Increasing the level of the drive signal output from the drive circuit in this manner can result in a high stress voltage being applied to the transistors, accelerating their degradation. In contrast, with the first configuration, the difference (Vd1) between the second and third voltages is smaller than the amplitude (A1) of the first voltage, so the stress voltages applied to the second and third transistors can be reduced. Furthermore, the voltage applied to the gate electrode of the first transistor can be reduced. As a result, even when the level of the drive signal output from the drive circuit is increased in this manner, the rate of degradation of the first, second, and third transistors can be reduced.

[0091] In the first configuration, the first node may include a first portion connected to the first transistor and a second portion connected to the second transistor and the third transistor. The unit circuit may further include a fourth transistor connected between the first portion and the second portion, a gate electrode of the fourth transistor to which a DC fourth voltage is applied, a source electrode of the fourth transistor to which the second portion is connected, and a drain electrode of the fourth transistor to which the first portion is connected. A difference between the fourth voltage and the third voltage may be configured to be smaller than the amplitude of the first voltage (second configuration).

[0092] According to the second configuration, the fourth transistor can separate the first node into a first portion and a second portion. As a result, the stress voltage Vds applied to the second transistor and the stress voltage Vds applied to the third transistor are expressed by the following equation (3a): Vds = Vd1 (3a) As a result, the stress voltage Vds applied to the second transistor and the stress voltage Vds applied to the third transistor can be further reduced.

[0093] In the first or second configuration, the second transistor may be configured such that the second voltage is applied to a source electrode of the second transistor when the drive circuit scans from a first stage to a last stage of the plurality of stages in sequence, and the third voltage is applied to a source electrode of the second transistor when the drive circuit scans from the last stage to the first stage in reverse. The third transistor may be configured such that the third voltage is applied to a source electrode of the third transistor when the drive circuit scans from the first stage to the last stage in sequence, and the second voltage is applied to a source electrode of the third transistor when the drive circuit scans from the last stage to the first stage in reverse (third configuration).

[0094] According to the third configuration, even when the drive circuit is configured to be drivable so as to perform bidirectional scanning, the rate at which the first transistor, the second transistor, and the third transistor deteriorate can be reduced.

[0095] In any one of the first to third configurations, the drive circuit may further include a fifth transistor connected to a drain electrode of the first transistor, a gate electrode of the fifth transistor receiving a second clock signal having a phase different from that of the first clock signal, and a source electrode of the fifth transistor receiving a fifth DC voltage. A difference between the second voltage and the fifth voltage may be smaller than the amplitude of the first voltage (fourth configuration).

[0096] According to the fourth configuration, even when the fifth transistor for pull-down is provided in the drive circuit, the rate at which the fifth transistor deteriorates can be reduced.

[0097] In any one of the first to third configurations, the drive circuit may include a second node, a fifth transistor connected to a drain electrode of the first transistor, the fifth transistor having a gate electrode connected to the second node and a source electrode to which a DC fifth voltage is applied, a sixth transistor having a source electrode to which a DC sixth voltage is applied and a gate electrode to which a DC sixth voltage is applied and a drain electrode to which the sixth transistor is connected, a seventh transistor having a gate electrode to which the first node is connected, a source electrode to which the second node is connected, and a drain electrode to which a seventh voltage lower than the sixth voltage is applied, and an eighth transistor having a gate electrode to which the second node is connected, a source electrode to which the first node is connected, and a drain electrode to which the seventh voltage is applied. The gate electrode of the fifth transistor may be connected to the second node. A difference value between the second voltage and the fifth voltage may be smaller than the amplitude of the first voltage, and a difference value between the sixth voltage and the seventh voltage may be smaller than the amplitude of the first voltage (fifth configuration).

[0098] Here, when the first-node is in a floating state, the potential of the first-node may fluctuate due to noise in the first clock signal or other signals, causing noise to appear in the drive signal output from the drive circuit. In contrast, the fifth configuration described above can prevent the first-node from entering a floating state, thereby preventing the potential of the first-node from fluctuating due to noise in the first clock signal or other signals. As a result, it is possible to prevent noise from appearing in the drive signal output from the drive circuit.

[0099] In any one of the first to fifth configurations, at least one of the second transistor and the third transistor may include two thin film transistors connected in series (sixth configuration).

[0100] According to the sixth configuration, at least one of the second transistor and the third transistor includes two thin film transistors, so that the stress voltage applied to each thin film transistor can be reduced.

[0101] In any one of the second, third, and sixth configurations, the fourth transistor may include two thin film transistors connected in series (seventh configuration).

[0102] According to the seventh configuration, the fourth transistor includes two thin film transistors, so that the stress voltage applied to each thin film transistor can be reduced.

[0103] In any one of the fifth to seventh configurations, the eighth transistor may include two thin film transistors connected in series (eighth configuration).

[0104] According to the eighth configuration, the eighth transistor includes two thin film transistors, so that the stress voltage applied to each thin film transistor can be reduced.

[0105] In any one of the first to eighth configurations, the drive circuit may further include a ninth transistor connected to the first node, the ninth transistor receiving a clear signal at a gate electrode thereof, the clear signal being supplied at least one time point immediately after power is turned on or immediately before power is turned off, the first node being connected to a drain electrode of the ninth transistor, and a DC eighth voltage being applied to a source electrode of the ninth transistor. A difference between the second voltage and the eighth voltage may be configured to be smaller than an amplitude of the first voltage (ninth configuration).

[0106] According to the ninth configuration, charge can be removed from the first node at least one of immediately after power is turned on and immediately before power is turned off. When charge is removed from the first node immediately after power is turned on, it is possible to prevent unexpected operation caused by the charge. Furthermore, when charge is removed from the first node immediately before power is turned off, it is possible to prevent voltage caused by the charge from being applied to the first transistor, the second transistor, and the third transistor after power is turned off.

[0107] In any one of the fourth to ninth configurations, the drive circuit may further include a tenth transistor connected to the fifth transistor, wherein a clear signal supplied at least immediately after the power is turned on or immediately before the power is turned off is input to the gate electrode of the tenth transistor, the drain electrode of the fifth transistor is connected to the drain electrode of the tenth transistor, and the fifth voltage is applied to the source electrode of the tenth transistor (tenth configuration).

[0108] According to the tenth configuration, when the charge is removed from the drain electrode of the fifth transistor immediately after the power is turned on, it is possible to prevent unexpected operation caused by the charge. Also, when the charge is removed from the drain electrode of the fifth transistor immediately before the power is turned off, it is possible to prevent a voltage caused by the charge from being applied to the fifth transistor and the first transistor connected to the fifth transistor after the power is turned off.

[0109] In any one of the fifth to tenth configurations, the drive circuit may further include an eleventh transistor connected to the second node, wherein a clear signal supplied at least immediately after the power is turned on or immediately before the power is turned off is input to a gate electrode of the eleventh transistor, the second node is connected to a drain electrode of the eleventh transistor, and the seventh voltage is applied to a source electrode of the eleventh transistor (eleventh configuration).

[0110] According to the eleventh configuration, charge can be removed from the second-node at least one of immediately after power is turned on and immediately before power is turned off. When charge is removed from the second-node immediately after power is turned on, it is possible to prevent unexpected operation caused by the charge. Furthermore, when charge is removed from the second-node immediately before power is turned off, it is possible to prevent voltage caused by the charge from being applied to the sixth transistor, the seventh transistor, and the eighth transistor after power is turned off.

[0111] In any one of the first to eleventh configurations, at least one of the second transistor and the third transistor may include an oxide semiconductor (twelfth configuration). In the twelfth configuration, the oxide semiconductor may include an In-Ga-Zn-O-based oxide semiconductor (thirteenth configuration). In the thirteenth configuration, the In-Ga-Zn-O-based oxide semiconductor may include a crystalline In-Ga-Zn-O-based oxide semiconductor (fourteenth configuration).

[0112] According to any one of the twelfth to fourteenth configurations, it is possible to reduce power consumption, increase driving speed, and achieve higher definition, compared to when the transistors are made of amorphous silicon.

[0113] A display device according to a fifteenth configuration includes the drive circuit of any one of the first to fourteenth configurations and a display on which the group of scanning signal lines is arranged (fifteenth configuration).

[0114] According to the above-mentioned 15th configuration, it is possible to provide a display device that can reduce the rate at which the first transistor, the second transistor, and the third transistor deteriorate, even when the level of the drive signal output from the drive circuit is increased in this manner.

[0115] An electrophoretic display device according to a sixteenth configuration comprises a driving circuit according to any one of the first to fourteenth configurations, a pixel transistor connected to one of the scanning signal line groups, a pixel electrode connected to the pixel transistor, a counter electrode arranged opposite the pixel electrode, and charged particles arranged between the pixel electrode and the counter electrode (sixteenth configuration).

[0116] Here, a higher voltage is applied to the transistors in the electrophoretic display device than to a liquid crystal display. According to the sixteenth configuration, the voltage applied to the first transistor, the second transistor, and the third transistor can be reduced, thereby slowing down the rate at which the transistors in the electrophoretic display device, which are relatively susceptible to deterioration, deteriorate. [Explanation of symbols]

[0117] 1: gate drive circuit, 1a: unit circuit, 2: display unit, 3: source drive circuit, 4: timing controller, 5: power supply circuit, 6: level shifter circuit, 10: display panel, 11: gate line, 12: source line, 13: common voltage line, 20: control board, 21: pixel, 22: pixel transistor, 23: pixel electrode, 24: counter electrode, 30: flexible printed circuit board, 34: insulating layer, 41: array board, 42: protective sheet, 43: ink imaging film, 51: microcapsules, 52a: charged particles, 52b: charged particles, 53: dispersion medium, 54: insulating layer, 61: output output circuit, 62: drive control circuit, 63: drive control circuit, 64: drive control circuit, 100: display device, 201: gate drive circuit, 201a: unit circuit, 261: output circuit, 265: drive control circuit, 300: display device, 301: gate drive circuit, 301a: unit circuit, 306: level shifter circuit, 320: control board, 362: drive control circuit, 363: drive control circuit, 401: gate drive circuit, 401a: unit circuit, 501: gate drive circuit, 501a: unit circuit, 601: gate drive circuit, 601a: unit circuit, 662: drive control circuit, 663: drive control circuit, 6 64: drive control circuit, 701: gate drive circuit, 765: drive control circuit, 801: gate drive circuit, 801a: unit circuit, 862: drive control circuit, 863: drive control circuit, 900: display device, 901: gate drive circuit, 901a: unit circuit, 906: level shifter circuit, 909: initialization control circuit, 910: initialization control circuit, 911: initialization control circuit, 920: control board, A1: amplitude, CKA: clock signal, CKB: clock signal, Cbst: bootstrap capacitor, Cbstc: bootstrap capacitor, DV: digital video signal, GCKa : Gate clock signal, GSP: Gate start pulse signal, GSPa: Gate start pulse signal, N1: Node, N1a: First part, N1b: Second part, N1c: Node, N2: Node, N51: Node, OUT: Terminal, R: Terminal, S: Terminal, SCK: Source clock signal, SSP: Source start pulse signal, T1: Transistor, T10: Transistor, T11: Transistor, T15: Transistor, T1c: Transistor, T2: Transistor, T2c: Transistor, T3: Transistor, T32: Transistor, T33: Transistor,T3c: transistor, T4: transistor, T5: transistor, T6: transistor, T62: transistor, T62a: thin film transistor, T62b: thin film transistor, T63: transistor, T63a: thin film transistor, T63b: thin film transistor, T64: transistor, T64a: thin film transistor, T64b: thin film transistor, T7: transistor, T78: transistor, T78a: thin film transistor, T78b: thin film transistor, T8: transistor, T9: transistor, Vgs: voltage, VGH1: first gate on voltage, VGH2: second gate on voltage, VGL: gate off voltage, Vcom: common voltage, Vd1: difference value, Vds: stress voltage,

Claims

1. A driving circuit that is made up of a plurality of stages and supplies driving signals to a group of scanning signal lines in response to input of a plurality of clock signals, a unit circuit that configures one of the plurality of stages and outputs the drive signal to any one of the scanning signal lines of the scanning signal line group; The unit circuit comprises: a first node; and a first transistor that outputs the drive signal to the scanning signal line, the first node being connected to a gate electrode of the first transistor, and a first clock signal having a first voltage being applied to a source electrode of the first transistor; a second transistor to which a set signal for the unit circuit is input, the set signal being input to a gate electrode of the second transistor, a second DC voltage being applied to a source electrode of the second transistor, and a drain electrode of the second transistor being connected to the first node; a third transistor to which a reset signal for the unit circuit is input, the reset signal being input to a gate electrode of the third transistor, a third DC voltage being applied to a source electrode of the third transistor, and a drain electrode of the third transistor being connected to the first node; A drive circuit, wherein a difference value between the second voltage and the third voltage is smaller than an amplitude of the first voltage.

2. the first node includes a first portion connected to the first transistor and a second portion connected to the second transistor and the third transistor; the unit circuit further includes a fourth transistor connected between the first portion and the second portion, a gate electrode of the fourth transistor to which a DC fourth voltage is applied, a source electrode of the fourth transistor to which the second portion is connected, and a drain electrode of the fourth transistor to which the first portion is connected; The drive circuit according to claim 1 , wherein a difference between the fourth voltage and the third voltage is smaller than an amplitude of the first voltage.

3. The second transistor is when the drive circuit scans the plurality of stages in order from the first stage to the last stage, the second voltage is applied to the source electrode of the second transistor; the third voltage is applied to a source electrode of the second transistor when the drive circuit scans from the last stage to the first stage in reverse order; The third transistor is When the drive circuit scans from the first stage to the last stage in order, the third voltage is applied to a source electrode of the third transistor; 2. The drive circuit according to claim 1, wherein the second voltage is applied to the source electrode of the third transistor when the drive circuit scans from the last stage to the first stage in reverse order.

4. the drive circuit further includes a fifth transistor connected to a drain electrode of the first transistor, a gate electrode of the fifth transistor receiving a second clock signal having a phase different from that of the first clock signal, and a source electrode of the fifth transistor receiving a DC fifth voltage; The drive circuit according to claim 1 , wherein a difference between the second voltage and the fifth voltage is smaller than an amplitude of the first voltage.

5. The drive circuit a second node; and a fifth transistor connected to a drain electrode of the first transistor, the fifth transistor having a gate electrode connected to the second node and a source electrode to which a DC fifth voltage is applied; a sixth transistor, a source electrode of the sixth transistor and a gate electrode of the sixth transistor to which a DC sixth voltage is applied, and a drain electrode of the sixth transistor is connected to the second node; a seventh transistor, the first node being connected to a gate electrode of the seventh transistor, the second node being connected to a source electrode of the seventh transistor, and a seventh voltage lower than the sixth voltage being applied to a drain electrode of the seventh transistor; an eighth transistor, the second node being connected to a gate electrode of the eighth transistor, the first node being connected to a source electrode of the eighth transistor, and the seventh voltage being applied to a drain electrode of the eighth transistor; a difference between the second voltage and the fifth voltage is smaller than the amplitude of the first voltage; The drive circuit according to claim 1 , wherein a difference between the sixth voltage and the seventh voltage is smaller than an amplitude of the first voltage.

6. The drive circuit of claim 1 , wherein at least one of the second transistor and the third transistor includes two thin film transistors connected in series.

7. The drive circuit of claim 2 , wherein the fourth transistor comprises two thin film transistors connected in series.

8. The drive circuit of claim 5 , wherein the eighth transistor comprises two thin film transistors connected in series.

9. the drive circuit further includes a ninth transistor connected to the first node, the ninth transistor receiving a clear signal at a gate electrode thereof, the clear signal being supplied at least one time point immediately after power is turned on or immediately before power is turned off, the first node being connected to a drain electrode of the ninth transistor, and a DC eighth voltage being applied to a source electrode of the ninth transistor; The drive circuit according to claim 1 , wherein a difference between the second voltage and the eighth voltage is smaller than an amplitude of the first voltage.

10. 5. The drive circuit according to claim 4, further comprising: a tenth transistor connected to the fifth transistor, a gate electrode of which receives a clear signal supplied at least immediately after power is turned on or immediately before power is turned off, a drain electrode of which is connected to the drain electrode of the fifth transistor, and a source electrode of which receives the fifth voltage.

11. 6. The drive circuit according to claim 5, further comprising an eleventh transistor connected to the second node, wherein a clear signal supplied at least immediately after power is turned on or immediately before power is turned off is input to a gate electrode of the eleventh transistor, the second node is connected to a drain electrode of the eleventh transistor, and the seventh voltage is applied to a source electrode of the eleventh transistor.

12. The drive circuit according to claim 1 , wherein at least one of the second transistor and the third transistor includes an oxide semiconductor.

13. 13. The drive circuit according to claim 12, wherein the oxide semiconductor includes an In--Ga--Zn--O based oxide semiconductor.

14. 14. The drive circuit according to claim 13, wherein the In--Ga--Zn--O-based oxide semiconductor includes an In--Ga--Zn--O-based oxide semiconductor having crystallinity.

15. A drive circuit according to claim 1; a display on which the group of scanning signal lines is arranged.

16. A drive circuit according to claim 1; a pixel transistor connected to one of the scanning signal lines; a pixel electrode connected to the pixel transistor; a counter electrode disposed opposite the pixel electrode; and charged particles disposed between the pixel electrodes and the counter electrode.

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