Semiconductor device

Abstract

To provide a semiconductor device that can suppress an adverse effect by a leak current at a high temperature.SOLUTION: A semiconductor device 200 includes: a switch circuit 3 that includes at least one switch 3A which is connected across both terminals of a predetermined element 2A, and which is configured as a MOSFET; and a leak cancelling circuit 5 which includes at least one MOS transistor 5A that is configured as a MOSFET, is connected to the switch circuit through a predetermined node Nd, and is configured to inject or draw a leak current with respect to the predetermined node.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, as one type of constant voltage generating circuit, an ED type constant voltage source that combines a depletion type N-channel MOSFET (metal oxide semiconductor field effect transistor) and an enhancement type N-channel MOSFET is widely known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 172001

[0004] [overview] However, there is room for improvement in the temperature characteristics of the output voltage of the constant voltage generating circuit. Furthermore, when attempting to improve this, it is necessary to take into account the effects of leakage current at high temperatures.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress the influence of leakage current at high temperatures.

[0006] A semiconductor device according to one embodiment of the present disclosure includes: a switch circuit having at least one switch configured as a MOSFET connected between both ends of a predetermined element; The circuit is configured to include a leakage cancellation circuit having at least one MOS transistor configured as a MOSFET, connected to the switch circuit at a predetermined node, and configured to inject or extract leakage current into or from the predetermined node. [Brief explanation of the drawings]

[0007] [Figure 1]FIG. 1 is a diagram showing a configuration of a constant voltage generating circuit according to a comparative example. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a constant voltage generating circuit according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing a first specific configuration example of the constant voltage generating circuit. [Figure 4] FIG. 4 is a diagram illustrating an example of a table map. [Figure 5] FIG. 5 is a diagram schematically showing temperature characteristics. [Figure 6] FIG. 6 is a diagram illustrating an example of the temperature characteristic of the output voltage. [Figure 7] FIG. 7 is a diagram showing a second specific configuration example of the constant voltage generating circuit. [Figure 8] FIG. 8 is a diagram showing another example of the table map. [Figure 9] FIG. 9 is a diagram showing the configuration of the first embodiment in which a leak current countermeasure is implemented. [Figure 10] FIG. 10 is a diagram showing an example of the vertical structure of an NMOS transistor. [Figure 11] FIG. 11 is a diagram showing the configuration of a second embodiment in which a countermeasure against leakage current is implemented. [Figure 12] FIG. 12 is a diagram showing the configuration of a third embodiment in which a leak current countermeasure is implemented. [Figure 13] FIG. 13 is a diagram showing the configuration of a fourth embodiment in which measures against leakage current are taken. [Figure 14] FIG. 14 is an external perspective view showing an example of a semiconductor device.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. A constant voltage generation circuit according to this embodiment is provided in a semiconductor device. FIG. 14 is an external perspective view showing an example of a semiconductor device. The semiconductor device 200 shown in FIG. 14 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the semiconductor device 200. The semiconductor device 200 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. The number of external terminals of the semiconductor device 200 and the type of housing for the semiconductor device 200 shown in FIG. 14 are merely examples and can be designed as desired. The constant voltage generation circuit according to this embodiment is included in a semiconductor integrated circuit.

[0009] <Comparative Example> FIG. 1 is a diagram showing a comparative example of a constant voltage generating circuit (basic configuration to be compared with the embodiments described later). The constant voltage generating circuit 1 of this comparative example is a so-called ED type reference voltage source. Referring to this diagram, the constant voltage generating circuit 1 includes a transistor M1 and a transistor M2. The transistor M1 is configured as a depletion type N-channel MOSFET. The transistor M2 is configured as an enhancement type N-channel MOSFET.

[0010] The depletion type is a type in which a drain current flows even when the gate-source voltage is 0V, while the enhancement type is a type in which no drain current flows when the gate-source voltage is 0V.

[0011] The drain of the transistor M1 is connected to a terminal to which the input voltage Vin is applied. The source and back gate of the transistor M2 are connected to a ground terminal (a terminal to which the ground potential is applied). The gate, source, and back gate of the transistor M1 and the gate and drain of the transistor M2 are all connected to an output terminal Tout, which is a terminal to which the output voltage Vout is applied.

[0012] In the constant voltage generating circuit 1 of this comparative example, the gate and source of transistor M1 are short-circuited. Therefore, the gate-source voltage Vgs1 of transistor M1 is 0 V. Therefore, transistor M1 functions as a constant current source that generates a constant drain current Idd1. In other words, a constant bias current (= drain current Idd1) flows through transistor M2. As a result, a constant output voltage Vout corresponding to the gate-source voltage Vgs2 of transistor M2 is generated.

[0013] Here, if the currents flowing through the transistors M1 and M2 operating in the saturation region are I1 and I2, respectively, the currents I1 and I2 are expressed by the following equations (1a) and (1b).

[0014]

number

[0015] In the above equations (1a) and (1b), μ1 and μ2 are the carrier mobilities of transistors M1 and M2, respectively. Cox is the oxide capacitance of transistors M1 and M2, respectively. W1 and W2 are the gate widths of transistors M1 and M2, respectively. L1 and L2 are the gate lengths of transistors M1 and M2, respectively. Vth1 and Vth2 are the threshold voltages of transistors M1 and M2, respectively.

[0016] In the constant voltage generating circuit 1, I1=I2 holds. Therefore, the output voltage Vout is expressed by the following equation (2).

[0017]

number

[0018] The threshold voltage Vth1 of the depletion-type transistor M1 is a negative value. Therefore, the above-mentioned formula (2) can be expressed as the following formula (3).

[0019]

number

[0020] Therefore, by appropriately designing the W / L of each of the transistors M1 and M2, the temperature characteristics of the threshold voltages Vth1 and Vth2 can be offset.

[0021] However, the constant voltage generating circuit 1 of this comparative example does not have a current capacity, and when a load (not shown) connected to the output terminal Tout requires a current capacity, there is a problem that the output voltage Vout drops. An example of a load requiring a current capacity is a resistive voltage divider circuit.

[0022] <Constant voltage generating circuit according to the present disclosure> 2 is a diagram showing the configuration of a constant voltage generating circuit 11 according to an exemplary embodiment of the present disclosure. The constant voltage generating circuit 11 includes transistors M1 and M2, as in the comparative example, and also includes transistors M3 and M4. Here, differences in the configuration from the comparative example will be mainly described.

[0023] The transistor M3 is configured by a depletion-type N-channel MOSFET. The drain of the transistor M3 is connected to the drain of the transistor M1. The gate of the transistor M3 is connected to the source of the transistor M1. The source of the transistor M3 is connected to the gate of the transistor M2. The gate of the transistor M2 is connected to the output terminal Tout. The output voltage Vout is output from the output terminal Tout.

[0024] By providing such a transistor M3, a source follower is configured. A current can be supplied from the output terminal Tout to the load LD via the transistor M3, and the constant voltage generating circuit 11 can have a current capability without affecting the output voltage Vout.

[0025] Furthermore, transistor M4 is configured as a depletion-type N-channel MOSFET. The drain of transistor M4 is connected to the source of transistor M3. The gate and source of transistor M4 are shorted. The source of transistor M4 is connected to the ground terminal. This transistor M4 configures a constant current source CI. The constant current source CI can also be considered an active load formed by an active element (transistor M4). When load LD is not connected, the constant current source CI absorbs the leakage current that flows through transistor M3 at high temperatures, thereby preventing the output voltage Vout from increasing.

[0026] Furthermore, the constant voltage generating circuit 11 according to this embodiment can be configured with depression-type transistors M1, M3, and M4 and an enhancement-type transistor M2. In other words, it can be configured with two types of elements. This has the advantage of suppressing the effects of element variations and simplifying the element layout.

[0027] The transistor M2 may be a depletion type transistor with p-type impurities implanted into the gate. In this case, the transistors M1, M3, and M4 are depletion type transistors with n-type impurities implanted into the gate. The transistor M2 configured in this way can have a positive threshold voltage, making it possible to use it instead of an enhancement type transistor. Furthermore, the transistors M1 to M4 share the same device structure (particularly the portions below the gate). This makes it possible to further reduce the effects of element variations. The element layout can also be simplified.

[0028] <Specific first configuration example> 3 is a diagram showing a first specific configuration example of the constant voltage generating circuit 11 described above. The constant voltage generating circuit 11 shown in FIG. 3 includes a first transistor stage 1, a second transistor stage 2, a switch circuit 3, and a selection signal generating unit 4. The constant voltage generating circuit 11 also includes a third transistor unit 1B on the high-potential side of the first transistor stage 1. Note that FIG. 3 also shows the transistors M3 and M4 described above.

[0029] The first transistor stage 1 has first transistor sections 1A connected in series. The first transistor section 1A and the third transistor section 1B are each composed of a depletion-type N-channel MOSFET. Each first transistor section 1A consists of a single transistor, and in the example of Figure 3, five first transistor sections 1A are connected in series. The source and drain of adjacent first transistor sections 1A are connected. The third transistor section 1B is connected between the application terminal of the input voltage Vin and the drain of the first transistor section 1A on the highest potential side (upper side). The third transistor section 1B is composed of, for example, multiple transistors connected in parallel. The drain of the third transistor section 1B is connected to the application terminal of the input voltage Vin, and the source of the third transistor section 1B is connected to the drain of the first transistor section 1A on the highest potential side. The gates of the first transistor section 1A and the third transistor section 1B are commonly connected to the source of the first transistor section 1A on the lowest potential side (lower side). The back gates of the first transistor sections 1A are commonly connected to the source of the first transistor section 1A on the lowest potential side, and the back gate of the first transistor section 1B is connected to the source of the first transistor section 1B.

[0030] Such a first transistor stage 1 corresponds to transistor M1 (FIG. 2). For example, if the gate length of each first transistor section 1A is 10 μm, then the first transistor stage 1 corresponds to transistor M1 with a gate length L1 = 10 × 5 μm. The third transistor section 1B generates a voltage that is higher than voltage Vdep, which is the source voltage of the first transistor section 1A on the lowest potential side, by a voltage equivalent to the threshold voltage (negative value) of the third transistor section 1B, and is used to suppress the effects of fluctuations in input voltage Vin.

[0031] The configuration of the first transistor stage 1 shown in FIG. 3 is merely an example, and the first transistor stage 1 may be configured by, for example, one first transistor portion 1A.

[0032] The second transistor stage 2 has second transistor sections 2A connected in series. Each second transistor section 2A is composed of one transistor and is an enhancement-type N-channel MOSFET. The drain of the second transistor section 2A on the highest potential side is connected to the source of the first transistor section 1A on the lowest potential side. The sources and drains of adjacent second transistor sections 2A are connected. The source of the second transistor section 2A on the lowest potential side is connected to the ground terminal. The gates of the second transistor sections 2A are commonly connected to the output terminal Tout. The back gates of the second transistor sections 2A are commonly connected to the ground terminal. Note that any second transistor section 2A may be configured with multiple transistors connected in parallel. Furthermore, although the number of second transistor sections 2A in the second transistor stage 2 is six in the example of FIG. 3, it may be any number.

[0033] The switch circuit 3 has a plurality of switches 3A. Each switch 3A is provided corresponding to a corresponding second transistor section 2A. The switches 3A are configured by N-channel MOSFETs. The drains of the switches 3A are connected to the drains of the corresponding second transistor sections 2A, and the sources of the switches 3A are connected to the sources of the corresponding second transistor sections 2A. When a switch 3A is turned on, the corresponding second transistor section 2A is bypassed and disabled. When a switch 3A is turned off, the corresponding second transistor section 2A is enabled. The back gates of the switches 3A are commonly connected to the ground terminal.

[0034] The second transistor stage 2 functions as a transistor M2 (FIG. 2) having the sum of the gate lengths of the second transistor sections 2A enabled by the switch circuit 3. In the example of FIG. 3, the gate lengths of the six second transistor sections 2A are set to 1 μm, 2 μm, 4 μm, 8 μm, 16 μm, and 32 μm, respectively. n (n is an integer between 0 and m) The gate length is set to 2 μm (here m=5). 0 μm~2 0 +···+2 m The gate length can be selected from a range of 1 μm to 63 μm by the switch circuit 3 (in the above example, 1 μm to 63 μm).

[0035] The selection signal generator 4 generates a selection signal S1 for controlling the on / off state of each switch 3A in the switch circuit 3. The selection signal generator 4 includes an OR circuit 4A, an inverter 4B, and a fuse 4C and resistor 4D connected in series between the input voltage Vin application terminal and the ground terminal. The number of such components (six in this example) corresponds to the number of switches 3A. A selection signal S2 output from a node connecting the fuse 4C and resistor 4D is input to a first input terminal of the OR circuit 4A via the inverter 4B. A selection signal S3 is input to a second input terminal of the OR circuit 4A. The selection signal S3 is input from an electrode pad or logic unit (not shown). The selection signal S1 output from the OR circuit 4A is input to the gate of the corresponding switch 3A. When the fuse 4C is not blown, the selection signal S2 is high, and the output of the inverter 4B is low. Therefore, when the fuse 4C is not blown, the level of the selection signal S1 output from the OR circuit 4 can be selected by the selection signal S3. On the other hand, if the selection signal S3 is fixed at a low level, the level of the selection signal S1 can be selected depending on whether or not the fuse 4C is blown. Specifically, if the fuse 4C is not blown, the selection signal S1 is at a low level, and if the fuse 4C is blown, the selection signal S1 is at a high level. When the selection signal S1 is at a high level, the switch 3A is turned on, and when the selection signal S1 is at a low level, the switch 3A is turned off.

[0036] Next, a description will be given of a method for selecting the second transistor section 2A in the second transistor stage 2 in the constant voltage generating circuit 11 configured as shown in Fig. 3. The selection method is performed by an operator in the following steps.

[0037] First, in the first step, the second transistor section 2A to be enabled is selected by the switch 3A so that the gate length of the second transistor stage 2 is a predetermined reference value (e.g., 36 μm). At this time, the fuse 4C is not cut, and the switch 3A is turned on or off by the selection signal S3. In this selected state, the output voltage Vout is measured when the temperature is a predetermined temperature T0 (e.g., room temperature).

[0038] In the second step, the drain current Idd1 flowing through the first transistor stage 1, i.e., transistor M1 (Figure 2), is measured under the above-mentioned selected state and temperature conditions. The drain current Idd1 is measured by, for example, applying a voltage higher than the output voltage Vout to the output terminal Tout from the outside, turning off transistor M3, and measuring the drain current flowing through transistor M4. Because transistor M4 and the transistors in the first transistor stage 1 are both depletion-mode N-channel MOSFETs with their gates and sources shorted, they are subject to the same tendency for manufacturing variations to affect them. Therefore, the drain current Idd1 flowing through transistor M1 can be estimated based on the measured drain current. For example, the drain current Idd1 can be estimated from the ratio of the on-resistances of transistors M1 and M4.

[0039] In the third step, the gate length L2 of the second transistor stage 2 is determined based on the output voltage Vout measured in step S1, the drain current Idd1 measured in step S2, and the table map.

[0040] Fig. 4 is a diagram showing an example of the table map. As shown in Fig. 4, in the table map, the vertical axis represents the output voltage Vout and the horizontal axis represents the drain current Idd1, and characteristic lines (straight lines) are defined for each gate length. In the table map, the gate length of the characteristic line that intersects with point P specified by the measured drain current Idd1 and the measured output voltage Vout is determined as the selected gate length.

[0041] In the example table map of FIG. 4, point P, which is specified by 150 nA, which is the reference value of the drain current Idd1, and 900 mV, which is the reference value of the output voltage Vout, intersects with the characteristic line of the gate length=38 μm, which is the reference value.

[0042] Here, as shown in FIG. 5, in the above formula (2),

number

[0043] Here, the current capabilities of the depletion-mode transistor M1 and the enhancement-mode transistor M2 each vary due to manufacturing variations. Hereinafter, the typical current capability is represented as T (Typ), a higher current capability as F (Fast), and a lower current capability as S (Slow), and the combination of the current capabilities of transistors M1 and M2 due to variations is represented as ENH / DEP. For example, if both transistors M1 and M2 are typical values, ENH / DEP is represented as T / T.

[0044] When ENH / DEP=T / T, the parameters in (A) above (mobility, gate width, gate length) become values ​​corresponding to the typical current capability, and point P, which represents the combination of Idd1 and Vout, is located on the characteristic line for L2=36 μm, which is the reference value, as shown in Figure 4. In other words, with L2=36 μm, the temperature characteristic of Vout becomes almost flat, as shown in Figure 5.

[0045] Here, if the current capabilities of transistors M1 and M2 vary in the same direction, such as ENH / DEP=S / S ​​or T / T, the parameters in (A) above will also vary in the same direction. As a result, as shown in Figure 4, point P will be located at, for example, L2=37 μm or 35 μm, and the temperature characteristics will be close to flat even if L2 remains at the reference value (36 μm).

[0046] Furthermore, when ENH / DEP=S / T or F / T, the Vout value at point P will be higher or lower than when ENH / DEP=T / T, as shown in Figure 4. When ENH / DEP=S / T, the temperature characteristic of Vout will be positive, and when ENH / DEP=F / T, the temperature characteristic of Vout will be negative, resulting in non-flat characteristics. Therefore, as shown in Figure 4, by adjusting L2, for example, to L2=30 μm when ENH / DEP=S / T, or to L2=44 μm when ENH / DEP=F / T, the temperature characteristic can be made closer to flat.

[0047] Furthermore, when ENH / DEP=T / F, the Idd1 value and Vout value at point P are higher than when ENH / DEP=T / T, as shown in Figure 4. In this case, the temperature characteristic of Vout becomes positive, and as shown in Figure 4, by adjusting L2 to, for example, 30 μm, the temperature characteristic can be made closer to flat. Similarly, when ENH / DEP=T / S, as shown in Figure 4, the Idd1 value and Vout value at point P are lower than when ENH / DEP=T / T. In this case, the temperature characteristic of Vout becomes negative, and as shown in Figure 4, by adjusting L2 to, for example, 46 μm, the temperature characteristic can be made closer to flat.

[0048] In this way, for example, by adjusting L2 to the value of L2 on the characteristic line where point P representing the combination of Idd1 and Vout intersects in the table map shown in FIG. 4, the temperature characteristic of Vout can be made closer to flat.

[0049] Then, in step 4, the selection signal generation unit 4 determines whether to cut or not cut each fuse 4C in order to select the second transistor section 2A to be enabled so that the gate length L2 in the second transistor stage 2 becomes the gate length determined above. When used as a product, the selection signal S3 is fixed to a low level.

[0050] FIG. 6 is a diagram showing an example of the temperature characteristic of the output voltage Vout. In FIG. 6, the output voltage Vout is shown with a value that is 1.0% of the value of the output voltage Vout at a predetermined room temperature Tx. By adjusting the gate length L2 of the second transistor stage 2 as described above, for example, the positive temperature characteristic before correction (solid line) can be corrected as shown by the arrow, and the negative temperature characteristic before correction (dashed line) can be corrected as shown by the arrow. As a result, the output voltage Vout can be kept within ±α% in the temperature range WT shown by the dashed line frame in FIG. 6.

[0051] <Specific second configuration example> 7 is a diagram showing a specific second configuration example of the above-mentioned constant voltage generating circuit 11. Here, differences in the configuration from the first configuration example (FIG. 3) will be mainly described.

[0052] In the configuration shown in FIG. 7, a switch 3A in the switch circuit 3 is provided corresponding to each first transistor unit 1A in the first transistor stage 1. That is, the switch 3A switches the corresponding first transistor unit 1A between enabled and disabled. A selection signal S1 generated by a selection signal generation unit 4 is input to the gate of the switch 3A. The gate lengths of the first transistor units 1A are set to respective values. Some of the first transistor units 1A may be composed of multiple transistors connected in parallel. For example, if some of the first transistor units 1A are configured with one transistor with a gate length of 50 μm, one transistor with a gate length of 5 μm, and two transistors with a gate length of 5 μm connected in parallel, enabling these first transistor units 1A allows the setting of L1 = 50 + 5 + 5 / 2 = 47.5 μm. As mentioned above, the third transistor unit 1B is used to suppress the effects of fluctuations in the input voltage Vin.

[0053] In addition, in the configuration of FIG. 7, a circuit for selecting the second transistor section 2A in the second transistor stage 2 is not provided, and the gate length L2 in the second transistor stage 2 is fixed.

[0054] 7, the first transistor portion 1A in the first transistor stage 1 is selected using, for example, a table map such as that shown in Fig. 8, as in the previously described embodiment. In the table map, a characteristic line of the gate length L1 is defined.

[0055] That is, when the gate length L1 in the first transistor section 1A is set to a reference value and the temperature is set to a predetermined value, the drain current Idd1 and output voltage Vout are measured, and the gate length L1 is determined based on the measurement results and the table map. In the example of FIG. 8, the reference value of the gate length L1 is set to 47.5 μm. Note that, as shown in FIG. 8, the lower the output voltage Vout in the table map, the shorter the gate length L1 characteristic line becomes, which is the opposite relationship to the gate length L2 characteristic line shown in the table map of FIG. 4 described above.

[0056] In the configuration shown in Figure 3 or Figure 7, the on-resistance of switch 3A needs to be lower than the on-resistance of the transistor section to be selected. However, by providing switch 3A for the first transistor stage 1 as in the configuration shown in Figure 7, the on-resistance of switch 3A can be made relatively high because the on-resistance of the first transistor section 1A is relatively high, and the circuit area due to switch 3A can be reduced.

[0057] On the other hand, in the configuration shown in FIG. 3, the switch circuit 3 is provided on the low potential side, so that the operating voltage at the input voltage Vin can be lowered.

[0058] <Leak current countermeasures> <<First Embodiment>> Here, a description will be given of measures to prevent leakage current in the constant voltage generating circuit as described above. Fig. 9 shows a first embodiment in which measures to prevent leakage current are taken in the constant voltage generating circuit 11 (Fig. 3) according to the first configuration example described above.

[0059] In Figure 9, switch 3A, which constitutes switch circuit 3, generates leakage currents at high temperatures. Leakage currents occur between the drain and source, between the drain and backgate, and between the source and backgate. These leakage currents are drawn from node Nd (the node to which the drain of switch 3A, the highest potential side, is connected) where voltage Vdep is generated, so there is a risk that voltage Vdep will drop at high temperatures. Switch 3A in particular must have a low on-resistance, and because it is large in size, the impact of leakage current is significant.

[0060] 9, a leakage cancellation circuit 5 is provided in the constant voltage generation circuit 11. In this disclosure, "cancellation" includes not only complete cancellation of the leakage current, but also partial cancellation of the leakage current.

[0061] The leakage cancellation circuit 5 has multiple MOS transistors 5A and one MOS transistor 5B. Each of the multiple MOS transistors 5A has the same configuration as each of the switches 3A. That is, each of the multiple MOS transistors 5A is configured as an enhancement-type N-channel MOSFET. Here, "same configuration" refers to transistors having the same polarity (N-type or P-type), size, etc., but even if they are identical in design, actual errors may occur. Note that "same size" refers to transistor main electrodes (drain, source, gate, etc.) and the sizes of each layer that makes up the transistor being identical.

[0062] The multiple MOS transistors 5A are connected in series. That is, the source and drain of adjacent MOS transistors 5A are connected. The drain of the MOS transistor 5A on the highest potential side is connected to the source of the third transistor section 1B. The MOS transistor 5B is composed of an enhancement-type N-channel MOSFET. The drain of the MOS transistor 5B is connected to the source of the MOS transistor 5A on the lowest potential side. The source of the MOS transistor 5B is connected to the Vdep application terminal (i.e., node Nd). The back gates of the multiple transistors 4A are commonly connected to the back gate of the MOS transistor 5B. The back gate and source of the MOS transistor 5B are short-circuited.

[0063] The gate of each of the multiple transistors 4A is connected to the gate of the switch 3A corresponding to the transistor 4A. That is, the selection signal S1 is input in common to the gates of the corresponding switch 3A and transistor 4A. For example, the selection signal S1 input to the gate of the switch 3A on the highest potential side is also input to the gate of the transistor 4A on the highest potential side. As a result, the corresponding switch 3A and transistor 4A are turned on or off in synchronization with the selection signal S1.

[0064] The gate and source of MOS transistor 5B are short-circuited. Therefore, MOS transistor 5B is in the off state. This suppresses the influence of transistor 4A on voltage Vdep at normal temperatures (when not high temperatures). Note that MOS transistor 5B is not essential. Also, if there is no switch 3A corresponding to some of the second transistor sections 2A in the second transistor stage 2 (for example, the second transistor section 2A on the highest potential side), all of the switches 3A may be in the on state, so it is important to keep MOS transistor 5B in the off state.

[0065] By providing such a leakage cancellation circuit 5, leakage currents occurring between the drain and source, between the drain and backgate, and between the source and backgate of transistor 4A can be injected into node Nd, thereby canceling the leakage current occurring in switch circuit 3 and suppressing a drop in voltage Vdep.

[0066] As shown in Fig. 9, the wiring 30 connected to each of the multiple switches 3A is commonly connected to an application terminal of the input voltage Vin. Fig. 10 shows an example of the vertical structure of an N-channel MOSFET. That is, the structure shown in Fig. 10 applies to both the switch 3A and the MOS transistor 5A.

[0067] An N-channel MOSFET 10 shown in FIG. 10 has the following structure. A base substrate 101 is a P-type semiconductor substrate. An N-type buried layer (B / L) 102 is formed above the base substrate 101. A P-type well layer (HVPW) 103 is formed above the buried layer 102. A P-type well layer (PW) 104 is formed above the P-type well layer 103.

[0068] A pair of N-type LDD layers (MVNLDD) 105 are formed at an interval on the surface of the P-type well layer 104. Each of the pair of N-type LDD layers 105 includes n + type source layer 106 and n + An n-type drain layer 107 is formed on the pair of N-type LDD layers 105. The region between the pair of N-type LDD layers 105 is a channel region 108. A gate electrode 109 is formed above the channel region 108. + The source layer 106 is connected to a source (S) wiring. + A drain (D) wiring is connected to the type drain layer 107.

[0069] The surface layer of the P-type well layer 104 is + type source layer 106 and n + On the outer periphery of the drain layer 107, + A mold layer 110 is formed. +The mold layer 110 is connected to a back gate (BG) wiring.

[0070] Above the buried layer 102, an intermediate layer 113 is formed on the outer periphery of the P-type well layers 103 and 104. The intermediate layer 113 has an N-type well layer 111 below it and an N-type well layer 112 above it. + A mold layer 114 is formed. + The wiring WR is formed on the mold layer 114 .

[0071] The wiring WR corresponds to the wiring 30 connected to the switch 3A. A leakage current flowing from the application terminal of the input voltage Vin through the wiring 30 and the buried layer 102 of the switch 3A to the back gate does not affect the voltage Vdep. However, the wiring WR corresponds to the wiring 50 connected to the MOS transistor 5A, and the wiring 50 of each of the multiple transistors 4A is connected to the source of the third transistor portion 1B. Therefore, the leakage current flowing through the back gate through the wiring 50 and the buried layer 102 of the MOS transistor 5A is injected into the node Nd, and therefore affects the voltage Vdp. However, because this leakage current is small, its effect on the voltage Vdp is minimal.

[0072] 9, the total number of MOS transistors 5A and 5B is seven, and the total number of switches 3B and MOS transistors Tr is also seven, the same number, but the MOS transistors Tr are dummy. Specifically, the back gate, drain, and source of the MOS transistor Tr are short-circuited, and the back gate is connected to the ground terminal. The gate of the MOS transistor Tr is also connected to the ground terminal. The wiring corresponding to the wiring WR connected to the MOS transistor Tr is also connected to the terminal to which the input voltage Vin is applied.

[0073] <<Second embodiment>> FIG. 11 shows a second embodiment in which a leak current countermeasure is implemented in the constant voltage generating circuit 11 (FIG. 3) according to the first configuration example described above.

[0074] This embodiment differs from the first embodiment (FIG. 9) in that the back gates of the multiple MOS transistors 5A in the leakage cancellation circuit 5 are connected to the ground terminal. This causes the leakage current flowing through the back gate via the wiring 50 and the buried layer 102 in the MOS transistor 5A to flow to the ground terminal, thereby suppressing the effect on the voltage Vdep. However, the leakage current flowing between the drain and back gate and between the source and back gate of the switch 3A is not canceled in this embodiment, and in this respect the first embodiment is advantageous.

[0075] 11, the gate and source of the MOS transistor 5A on the lowest potential side in the leakage cancellation circuit 5 are short-circuited, thereby turning off the MOS transistor 4 and suppressing the effect on the voltage Vdep at normal temperatures.

[0076] <<Third Embodiment>> FIG. 12 shows a third embodiment in which a leak current countermeasure is implemented in the constant voltage generating circuit 11 (FIG. 3) according to the first configuration example described above.

[0077] 12, in this embodiment, the leakage cancellation circuit 5 has a current mirror 5C in addition to a MOS transistor 5A. The back gates of the multiple MOS transistors 5A are commonly connected to the ground terminal. The gate and source of the MOS transistor 5A on the lowest potential side are shorted, and the source is connected to the ground terminal.

[0078] The current mirror 5C has PMOS transistors PM1 and PM2. The PMOS transistors PM1 and PM2 are configured by P-channel MOSFETs. The drain of the PMOS transistor PM1 is connected to the drain of the MOS transistor 5A on the highest potential side. The gate and drain of the PMOS transistor PM1 are shorted. The sources of the PMOS transistors PM1 and PM2 are connected to the application terminal of the input voltage Vin. The gates of the PMOS transistors PM1 and PM2 are connected to each other. The drain of the PMOS transistor PM2 is connected to the node Nd.

[0079] With this configuration, leakage currents flowing between the drain and source, between the drain and backgate, and between the source and backgate of the MOS transistor 5A are mirrored by the current mirror 5C and injected into the node Nd. This cancels the leakage current flowing through the switch circuit 3, thereby suppressing fluctuations in the voltage Vdep. Furthermore, in this embodiment, the wiring 50 connected to the MOS transistor 5A is connected to the terminal to which the input voltage Vin is applied. Therefore, the leakage current flowing from the terminal to which the input voltage Vin is applied, via the wiring 50 and the buried layer 102 in the MOS transistor 5A and through the backgate, flows to the ground terminal, thereby suppressing the effect on the voltage Vdep.

[0080] <<Fourth Embodiment>> FIG. 13 shows a fourth embodiment in which a leak current countermeasure is implemented in the constant voltage generating circuit 11 (FIG. 7) according to the second configuration example described above.

[0081] In this embodiment, a leakage cancellation circuit 6 is provided. The leakage cancellation circuit 6 has a plurality of MOS transistors 6A and a current mirror 6B. The MOS transistors 6A are configured by P-channel MOS transistors. The plurality of MOS transistors 6A are connected in series. The drains and sources of adjacent MOS transistors 6A are connected. The source of the MOS transistor 6A on the highest potential side is connected to the source of the third transistor section 1B. The back gates of the plurality of MOS transistors 6A are commonly connected to the source of the third transistor section 1B. The buried layer of the MOS transistor 6A is connected to the back gate.

[0082] The current mirror 6B has NMOS transistors NM1 and NM2. The NMOS transistors NM1 and NM2 are configured by N-channel MOSFETs. The drain of the NMOS transistor NM1 is connected to the drain of the MOS transistor 6A on the lowest potential side. The gate and drain of the NMOS transistor NM1 are shorted. The sources of the NMOS transistors NM1 and NM2 are connected to the ground terminal. The gates of the NMOS transistors NM1 and NM2 are connected to each other. The drain of the NMOS transistor NM2 is connected to the node Nd. The gate and source of the MOS transistor 6A on the lowest potential side are shorted.

[0083] With this configuration, the leakage current flowing through the MOS transistor 6A is mirrored by the current mirror 6B and extracted from the node Nd, thereby canceling the leakage current flowing through the switch circuit 3 and suppressing fluctuations in the voltage Vdep.

[0084] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0085] For example, the above-described countermeasures against leakage current are applicable not only to constant voltage generating circuits but also to other circuits. The element that is switched between enabled and disabled by switch 3A in switch circuit 3 is not limited to a MOSFET as in the above-described embodiment, but may also be, for example, a resistor element.

[0086] <Additional Notes> As described above, the semiconductor device (200) according to one embodiment of the present disclosure includes: a switch circuit (3) having at least one switch (3A) configured as a MOSFET connected across a predetermined element (2A); The configuration includes a leakage cancellation circuit (5) having at least one MOS transistor (5A) configured as a MOSFET, connected to the switch circuit at a predetermined node (Nd), and configured to inject or extract leakage current into or from the predetermined node (first configuration, FIG. 9).

[0087] According to this configuration, the leakage current generated in the switch circuit at high temperatures can be canceled by the leakage cancel circuit, so that the influence of the leakage current can be suppressed.

[0088] In the first configuration, the MOS transistor (5A) may be configured as a MOSFET (for example, N-channel type) of the same polarity as the switch (3A) (second configuration, FIG. 9).

[0089] In the second configuration, the switch circuit includes a plurality of switches (3A) connected in series, In the leakage cancel circuit, the MOS transistors (5A) are connected in series, Each of the plurality of MOS transistors may have the same configuration as each of the plurality of switches (third configuration, FIG. 9).

[0090] In the third configuration, the gates of the plurality of MOS transistors (5A) may be connected to the gates of the plurality of switches (3A) (fourth configuration, FIG. 9).

[0091] In any one of the first to fourth configurations, in the leakage cancel circuit, the plurality of MOS transistors (5A) are connected in series, The back gates of the plurality of MOS transistors are connected to the predetermined node (Nd), The source of the MOS transistor on the lowest potential side among the plurality of MOS transistors may be directly or indirectly connected to the predetermined node (fifth configuration, FIG. 9).

[0092] In any one of the first to fourth configurations, in the leakage cancel circuit, the plurality of MOS transistors (5A) are connected in series, a back gate of each of the plurality of MOS transistors is connected to an application terminal of a ground potential; The source of the MOS transistor on the lowest potential side among the plurality of MOS transistors may be directly or indirectly connected to the predetermined node (Nd) (sixth configuration, FIG. 11).

[0093] In any one of the first to fourth configurations, in the leakage cancel circuit, the plurality of MOS transistors (5A) configured as N-channel MOSFETs are connected in series, a back gate of each of the plurality of MOS transistors is connected to an application terminal of a ground potential; a source of the MOS transistor on the lowest potential side among the plurality of MOS transistors is directly or indirectly connected to the application terminal of the ground potential; the leakage cancellation circuit further includes a first current mirror (5C); The first current mirror includes a first PMOS transistor (PM1) having a drain connected to the drain of the MOS transistor on the highest potential side among the plurality of MOS transistors; and a second PMOS transistor (PM2) including a drain connected to the predetermined node (Nd) (seventh configuration, FIG. 12).

[0094] In any one of the first to fourth configurations, in the leakage cancel circuit (6), the plurality of MOS transistors (6A) configured as P-channel MOSFETs are connected in series, a back gate of each of the plurality of MOS transistors is connected to an application terminal of a predetermined voltage; a source of the MOS transistor on the highest potential side among the plurality of MOS transistors is connected to an application terminal of the predetermined voltage; the leakage cancellation circuit further includes a second current mirror (6B); The second current mirror includes a first NMOS transistor (NM1) having a drain connected to the drain of the MOS transistor on the lowest potential side among the plurality of MOS transistors; and a second NMOS transistor (NM2) including a drain connected to the predetermined node (Nd) (eighth configuration, FIG. 13).

[0095] In any one of the first to eighth configurations, in the leakage cancel circuit (5), the plurality of MOS transistors (5A) are connected in series, The leakage cancel circuit may further include a transistor (5B) connected to the MOS transistor with the lowest potential among the plurality of MOS transistors and having its gate and source short-circuited (ninth configuration, FIG. 9).

[0096] In any one of the first to eighth configurations, in the leakage cancel circuit (5), the plurality of MOS transistors (5A) are connected in series, The gate and source of the MOS transistor on the lowest potential side among the plurality of MOS transistors may be short-circuited (tenth configuration, FIG. 11).

[0097] In any one of the first to tenth configurations, a first transistor stage (1) configured by connecting a plurality of first transistor sections (1A) as depletion-type N-channel MOSFETs in series; a second transistor stage (2) connected to the first transistor stage at the predetermined node (Nd) and configured by connecting in series a plurality of second transistor sections (2A) as enhancement-type N-channel MOSFETs; the switch circuit (3) including a plurality of the switches (3A); a constant voltage generating circuit (11) having the leak cancel circuit (5), Each of the plurality of switches may be configured to be connected between both ends of the plurality of first transistor units as the specified element, or between both ends of the plurality of second transistor units as the specified element (eleventh configuration, Figure 9). [Industrial Applicability]

[0098] The present disclosure can be used in various circuits, such as a constant voltage generating circuit. [Explanation of symbols]

[0099] 1 First transistor stage 1A 1st transistor section 1B Third transistor section 2 second transistor stage 2A Second transistor section 3 Switch Circuit 3A switch 31 Unit Circuit 31A fuse 31B Switch 4. Selection signal generator 4A OR circuit 4B inverter 4C fuse 4D resistance 5. Leak cancellation circuit 5A MOS transistor 5B MOS transistor 5C current mirror 6. Leak cancellation circuit 6A MOS transistor 6B Current mirror 50 Wiring 6. Leak cancellation circuit 6A MOS transistor 6B Current mirror 10 NMOS transistor 101 Base board 102 Embedding Layer 103 P-type well layer 104 P-type well layer 105 N-type LDD layer 106n + Type Source Layer 107n + Type drain layer 108 channel region 109 Gate electrode 110 P + mold layer 111 N-type well layer 112 N-type well layer 113 Middle Class 114 P + mold layer 11,100 Constant voltage generation circuit 200 Semiconductor device CI constant current source LD load NM1, NM2 NMOS transistors M1~M4 transistors PM1, PM2 PMOS transistors Tout output end Tr MOS transistor WR wiring

Claims

1. a switch circuit having at least one switch configured as a MOSFET connected across a predetermined element; a leakage cancellation circuit having at least one MOS transistor configured as a MOSFET, connected to the switch circuit at a predetermined node, and configured to inject or extract a leakage current into or from the predetermined node; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein said MOS transistor is configured as a MOSFET having the same polarity as said switch.

3. In the switch circuit, the switches are connected in series, In the leakage cancel circuit, the MOS transistors are connected in series, 3. The semiconductor device according to claim 2, wherein each of said plurality of MOS transistors has the same configuration as each of said plurality of switches.

4. 4. The semiconductor device according to claim 3, wherein the gates of the plurality of MOS transistors are connected to the gates of the plurality of switches, respectively.

5. In the leakage cancel circuit, the MOS transistors are connected in series, the back gates of the plurality of MOS transistors are connected to the predetermined node; 2. The semiconductor device according to claim 1, wherein a source of said MOS transistor on the lowest potential side among said plurality of MOS transistors is connected directly or indirectly to said predetermined node.

6. In the leakage cancel circuit, the MOS transistors are connected in series, a back gate of each of the plurality of MOS transistors is connected to an application terminal of a ground potential; 2. The semiconductor device according to claim 1, wherein a source of said MOS transistor on the lowest potential side among said plurality of MOS transistors is connected directly or indirectly to said predetermined node.

7. In the leakage cancel circuit, the MOS transistors configured as N-channel MOSFETs are connected in series, a back gate of each of the plurality of MOS transistors is connected to an application terminal of a ground potential; a source of the MOS transistor on the lowest potential side among the plurality of MOS transistors is directly or indirectly connected to an application terminal of the ground potential; the leakage cancellation circuit further includes a first current mirror; The first current mirror comprises: a first PMOS transistor having a drain connected to the drain of the MOS transistor on the highest potential side among the plurality of MOS transistors; a second PMOS transistor having a drain connected to the predetermined node; The semiconductor device according to claim 1 , comprising:

8. In the leakage cancel circuit, the MOS transistors configured as P-channel MOSFETs are connected in series, a back gate of each of the plurality of MOS transistors is connected to an application terminal of a predetermined voltage; a source of the MOS transistor on the highest potential side among the plurality of MOS transistors is connected to an application terminal of the predetermined voltage; the leakage cancellation circuit further includes a second current mirror; The second current mirror comprises: a first NMOS transistor having a drain connected to the drain of the MOS transistor on the lowest potential side among the plurality of MOS transistors; a second NMOS transistor having a drain connected to the predetermined node; The semiconductor device according to claim 1 , comprising:

9. In the leakage cancel circuit, the MOS transistors are connected in series, 2. The semiconductor device according to claim 1, wherein said leakage cancel circuit further comprises a transistor connected to said MOS transistor on the lowest potential side among said plurality of MOS transistors, and having its gate and source short-circuited.

10. In the leakage cancel circuit, the MOS transistors are connected in series, 2. The semiconductor device according to claim 1, wherein the gate and source of said MOS transistor on the lowest potential side among said plurality of MOS transistors are short-circuited.

11. a first transistor stage configured by connecting a plurality of first transistor units in series as depletion-type N-channel MOSFETs; a second transistor stage connected to the first transistor stage at the predetermined node and configured by connecting a plurality of second transistor units as enhancement type N-channel MOSFETs in series; the switch circuit including a plurality of the switches; a constant voltage generating circuit having the leakage cancel circuit, 11. The semiconductor device according to claim 1, wherein each of the plurality of switches is connected between both ends of the plurality of first transistor units as the predetermined element or between both ends of the plurality of second transistor units as the predetermined element.

Images