Semiconductor package
The semiconductor package design addresses heat dissipation challenges by using an insulating layer, through vias, a wiring structure, a molding layer, and conductive posts to enhance heat dissipation, improving reliability and performance.
Patent Information
- Application Number
- JP2025003813
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-04-26
- Filing Date
- 2025-01-10
- Publication Date
- 2025-11-07
AI Technical Summary
The challenge of heat dissipation in semiconductor packages containing multiple chips, which generates significant heat, affects the reliability and performance of electronic components.
A semiconductor package design incorporating an insulating layer, through vias, a wiring structure, a chip stack, a molding layer, and conductive posts to enhance heat dissipation by dispersing heat generated from semiconductor chips vertically and horizontally.
Improves heat dissipation characteristics, enhancing the reliability and performance of semiconductor packages by effectively dissipating heat generated from multiple chips.
Smart Images
Figure 2025168218000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to semiconductor packages. [Background technology]
[0002] With the development of the electronics industry and user demands, there is a demand for smaller and lighter electronic components mounted in electronic products. To meet these demands, semiconductor packages mounted on electronic components are required to be small in volume and capable of processing large amounts of data. To this end, semiconductor packages containing multiple chips that perform various functions have been proposed.
[0003] To solve the problem of heat generated by the operation of the multiple chips, research is being conducted to improve the heat dissipation performance of semiconductor packages. Summary of the Invention [Problem to be solved by the invention]
[0004] SUMMARY OF THE INVENTION The present invention provides a semiconductor package that dissipates heat generated from a semiconductor chip, thereby improving product reliability.
[0005] The technical problems of the present invention are not limited to those described above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]
[0006] In order to achieve the above technical objective, a semiconductor package according to some embodiments of the present invention includes a first semiconductor chip, an insulating layer surrounding side surfaces of the first semiconductor chip, a through via penetrating the insulating layer, a wiring structure on the first semiconductor chip and the insulating layer and electrically connected to the first semiconductor chip and the through via, a chip stack on the wiring structure, a molding layer on the wiring structure surrounding at least a portion of the chip stack, and conductive posts that penetrate the molding layer and are electrically connected to the wiring structure.
[0007] To achieve the above technical objective, a semiconductor package according to some embodiments of the present invention includes an insulating layer, a first logic semiconductor chip within the insulating layer, a through via within the insulating layer and spaced apart from the first logic semiconductor chip, a wiring structure on the insulating layer and electrically connected to the first logic semiconductor chip and the through via, and a first chip stack including a first memory semiconductor chip stacked on the wiring structure, but not including a buffer chip.
[0008] In order to achieve the above technical objectives, a semiconductor package according to some embodiments of the present invention includes a package substrate, a first semiconductor chip on the package substrate, an insulating layer surrounding side surfaces of the first semiconductor chip, a through via penetrating the insulating layer, a wiring structure on the first semiconductor chip and the insulating layer and electrically connected to the first semiconductor chip and the through via, a chip stack on the wiring structure and electrically connected to the wiring structure, a molding layer on the wiring structure and surrounding at least a portion of the chip stack, conductive posts penetrating the molding layer and electrically connected to the wiring structure, a heat transfer material layer on the molding layer, and a heat dissipation member on the heat transfer material layer.
[0009] Specific details of other embodiments are included in the detailed description and drawings. [Brief explanation of the drawings]
[0010] [Figure 1] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 2] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 3] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 4] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 5] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 6] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 7] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 8] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 9] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 10] 1A and 1B are diagrams illustrating semiconductor packages according to some embodiments. [Figure 11] 1A-1D are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor package according to some embodiments. [Figure 12] 1A-1D are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor package according to some embodiments. [Figure 13] 1A-1D are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor package according to some embodiments. [Figure 14] 1A-1D are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor package according to some embodiments. [Figure 15] 1A-1D are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor package according to some embodiments. [Figure 16] 1A-1D are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor package according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION
[0011] Embodiments of the present invention will now be described with reference to the accompanying drawings, which illustrate embodiments of the inventive concept. In the drawings, like elements will be designated by like reference numerals, and redundant description will be omitted. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. When an element is referred to as "on," "attached to," "connected to," "coupled to," "contacting," or the like, it can be understood that it is directly on, attached to, connected to, coupled to, or in contact with the other element, or that intervening elements may be present. On the other hand, when an element is referred to as "directly on," "directly attached to," "directly connected to," "directly coupled to," or "directly in contact with" another element, no intervening elements are present. Aspects described in connection with one embodiment may be integrated with other embodiments, even if not specifically described. That is, all embodiments and / or features of all embodiments may be combined in any manner and / or combination.
[0012] FIG. 1 is a diagram illustrating a semiconductor package according to some embodiments.
[0013] Referring to FIG. 1, the package may include a package substrate 10, external terminals 14, first connection terminals 44, second connection terminals 64, a first semiconductor chip 100, an insulating layer 160, a through via 165, a wiring structure 170, a chip stack 200, a molding layer 260, conductive posts 265, a heat transfer material layer 310, and a heat dissipation member 320.
[0014] The package substrate 10 may be a substrate for a semiconductor package. For example, the package substrate 10 may be a printed circuit board (PCB). External terminals 14 are arranged on the bottom surface of the package substrate 10. The package substrate 10 is mounted on a main board of an electronic device or the like via the external terminals 14.
[0015] The external terminals 14 may include at least one of a conductive material, such as solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). The external terminals 14 may have various shapes, such as lands, balls, pins, and pillars. The number, spacing, and arrangement of the external terminals 14 are not limited to those shown in the drawings and may vary depending on the design.
[0016] The first semiconductor chip 100 is disposed on the upper surface of the package substrate 10. The first semiconductor chip 100 may include a first semiconductor substrate 110, first through-electrodes 115, a first semiconductor element layer 120, a chip insulating layer 130, and chip pads 132.
[0017] Hereinafter, the terms upper surface, lower surface, top, and bottom are defined based on the direction from the package substrate 10 toward the first semiconductor chip 100. That is, the upper surface of the package substrate 10, which is opposite to the bottom surface of the package substrate 10 on which the external terminals 14 are arranged, can function as a reference plane. Therefore, the vertical direction is the direction perpendicular to the top surface of the package substrate 10, and the horizontal direction is the direction parallel to the top surface of the package substrate 10.
[0018] The first semiconductor substrate 110 may include a first front surface 110a and a first rear surface 110b, which are opposite to each other. The first front surface 110a may be an active surface on which semiconductor devices are formed. For example, the first front surface 110a may include a conductive region, such as a well doped with impurities. The first front surface 110a may also include various isolation structures, such as insulating regions, such as shallow trench isolation (STI).
[0019] The first semiconductor device layer 120 is disposed on the first front surface 110a of the first semiconductor substrate 110. The chip insulating layer 130 is disposed on the first semiconductor device layer 120. The first semiconductor device layer 120 is disposed between the chip insulating layer 130 and the first semiconductor substrate 110. The chip pads 132 are disposed in the chip insulating layer 130. The chip pads 132 may be electrically connected to the first semiconductor device layer 120. The first through-electrodes 115 may penetrate the first semiconductor substrate 110. The first through-electrodes 115 may be electrically connected to the first semiconductor device layer 120.
[0020] The insulating layer 160 may surround at least a portion of the first semiconductor chip 100 or may be located on at least a portion of the first semiconductor chip 100. The insulating layer 160 may surround a side surface of the first semiconductor chip 100 or may be located on a side surface of the first semiconductor chip 100. The first semiconductor chip 100 is disposed within the insulating layer 160. For example, the top surface of the insulating layer 160 may be flush with the top surface of the first semiconductor chip 100, and the bottom surface of the insulating layer 160 may be flush with the bottom surface of the first semiconductor chip 100. The insulating layer 160 may include, for example, an oxide.
[0021] The through vias 165 penetrate the insulating layer 160. The through vias 165 are disposed in the insulating layer 160. The through vias 165 are spaced apart from the first semiconductor chip 100. For example, the through vias 165 may be arranged to surround at least a portion of the first semiconductor chip 100 in a plan view parallel to the top surface of the package substrate 10. The through vias 165 may include a metal.
[0022] The first semiconductor chip 100 and the through vias 165 are mounted on the package substrate 10. The first semiconductor chip 100 and the through vias 165 may be electrically connected to the package substrate 10.
[0023] For example, a first pad 142 and a second pad 162 are arranged on the lower surface of the insulating layer 160. The first pad 142 is arranged on the lower surface of the first semiconductor chip 100 and may be electrically connected to the first semiconductor chip 100. The second pad 162 is arranged on the lower surface of the through via 165 and may be electrically connected to the through via 165. First and second substrate pads 42 and 62 are arranged on the upper surface of the package substrate 10. The first and second substrate pads 42 and 62 may be electrically connected to the package substrate 10. A first connection terminal 44 is arranged between the first pad 142 and the first substrate pad 42. A second connection terminal 64 is arranged between the second pad 162 and the second substrate pad 62.
[0024] The sizes and arrangements of the first pads 142 and the second pads 162, the first connection terminals 44 and the second connection terminals 64, and the first substrate pads 42 and the second substrate pads 62 are not limited to those shown in the drawings, and may vary depending on the design.
[0025] The first connection terminal 44 and the second connection terminal 64 may each include a conductive material such as solder, tin (Sn), silver (Ag), copper (Cu), and / or aluminum (Al). The first connection terminal 44 and the second connection terminal 64 may each have various shapes such as a land, a ball, a pin, or a pillar.
[0026] The wiring structure 170 is disposed on the insulating layer 160 and the first semiconductor chip 100. The wiring structure 170 is electrically connected to the first semiconductor chip 100 and the through via 165. The wiring structure 170 may include a wiring insulating layer 172, wiring vias 174V1, 174V2, 174V3, a wiring pad 176, and a thermal pad 178. The wiring vias 174V1, 174V2, 174V3, the wiring pad 176, and the thermal pad 178 are disposed in the wiring insulating layer 172.
[0027] The first and second wiring vias 174V1, 174V2 are arranged on the first semiconductor chip 100. The first and second wiring vias 174V1, 174V2 can be electrically connected to the first semiconductor chip 100. For example, the first and second wiring vias 174V1, 174V2 can be electrically connected to the chip pads 132 of the first semiconductor chip 100. The third wiring via 174V3 is arranged on the through via 165. The third wiring via 174V3 can be electrically connected to the through via 165. For example, the third wiring via 174V3 can be electrically connected to the through via 165.
[0028] The wiring pad 176 may be electrically connected to the first wiring via 174V1. The wiring pad 176 may be electrically connected to the first semiconductor chip 100. For example, the wiring pad 176 may be connected to the first wiring via 174V1.
[0029] The thermal pad 178 may be electrically connected to the second and third wiring vias 174V2 and 174V3. For example, the thermal pad 178 may be electrically connected to the second and third wiring vias 174V2 and 174V3. The thermal pad 178 may be electrically connected to the first semiconductor chip 100 and the through via 165.
[0030] For example, the wiring structure 170 may include a multi-layer wiring pattern and a via pattern electrically connecting the wiring patterns. The wiring pad 176 may be a wiring pattern disposed at the top of the wiring pattern and electrically connected to the chip stack 200, and the thermal pad 178 may be a wiring pattern disposed at the top of the wiring pattern and electrically connected to the conductive post 265. The first and second wiring vias 174V1 and 174V2 may be via patterns disposed at the bottom of the via patterns and electrically connected to the first semiconductor chip 100, and the third wiring via 174V3 may be a via pattern disposed at the bottom of the via patterns and electrically connected to the through via 165.
[0031] The wiring insulating layer 172 includes an oxide (eg, silicon oxide). The wiring vias 174V1, 174V2, and 174V3, the wiring pad 176, and the thermal pad 178 may each include a metal.
[0032] The chip stack 200 is disposed on the first semiconductor chip 100. The chip stack 200 may be electrically connected to the first semiconductor chip 100. The chip stack 200 may include stacked second semiconductor chips 201-208. The number of second semiconductor chips 201-208 included in the chip stack 200 may vary.
[0033] Each of the second semiconductor chips 201 to 207 may include a second semiconductor substrate 210, a second through electrode 215, a second semiconductor element layer 220, a first bonding insulating layer 230, a first bonding pad 232, a second bonding insulating layer 240, and a second bonding pad 242. The second semiconductor chip 208 may include a second semiconductor substrate 210, a second semiconductor element layer 220, a first bonding insulating layer 230, and a first bonding pad 232.
[0034] The second semiconductor substrate 210 may include a second front surface 210a and a second rear surface 210b, which are opposite to each other. The second front surface 210a may be an active surface on which semiconductor devices are formed. For example, the second front surface 210a may include a conductive region, such as a well doped with impurities. The second front surface 210a may also include various isolation structures, such as an insulating region, e.g., shallow trench isolation (STI).
[0035] The first semiconductor substrate 110 and the second semiconductor substrate 210 may each be, for example, bulk silicon or silicon-on-insulator (SOI). The first semiconductor substrate 110 and the second semiconductor substrate 210 may each be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first semiconductor substrate 110 and the second semiconductor substrate 210 may each be an epitaxial layer formed on a base substrate.
[0036] The second semiconductor device layer 220 is formed on the second front surface 210a of the second semiconductor substrate 210. The first semiconductor device layer 120 and the second semiconductor device layer 220 may each include various types of individual devices and / or interlayer insulating films.
[0037] The discrete elements may include various microelectronic devices, for example, metal-oxide-semiconductor field effect transistors (MOSFETs) such as complementary metal-insulator-semiconductor transistors (CMOS transistors), system large scale integration (LSIs), flash memories, image sensors such as DRAMs, SRAMs, EEPROMs, PRAMs, MRAMs, RRAMs, CISs (CMOS imaging sensors), micro-electro-mechanical systems (MEMS), active elements, passive elements, etc. The first semiconductor element layer 120 and the second semiconductor element layer 220 may each include wiring connected to the discrete elements.
[0038] The first bonding insulating layer 230 is disposed on the second semiconductor device layer 220. The second semiconductor device layer 220 is disposed between the second semiconductor substrate 210 and the first bonding insulating layer 230. The first bonding pad 232 is disposed in the first bonding insulating layer 230. The first bonding pad 232 may be electrically connected to the second semiconductor device layer 220.
[0039] A second bonding insulating layer 240 is disposed on the second surface 210b of the second semiconductor substrate 210. A second bonding pad 242 is disposed in the second bonding insulating layer 240.
[0040] The second through-electrode 215 penetrates the second semiconductor substrate 210. The second through-electrode 215 may be electrically connected to the second bonding pad 242. The second through-electrode 215 may be electrically connected to the second semiconductor element layer 220. The second through-electrode 215 may be electrically connected to the first bonding pad 232 via the second semiconductor element layer 220.
[0041] Adjacent second semiconductor chips 201-208 are bonded together. In some embodiments, second semiconductor chips 201-208 may be bonded together using a hybrid bonding method. Adjacent first bonding insulating layers 230 and second bonding insulating layers 240 and adjacent first bonding pads 232 and second bonding pads 242 may be bonded together in contact with each other.
[0042] For example, the second bonding insulating layer 240 and the second bonding pad 242 of the second semiconductor chip 201 may be bonded to and in contact with the first bonding insulating layer 230 and the first bonding pad 232 of the second semiconductor chip 202, respectively. The second semiconductor chips 201 to 208 may be electrically connected to each other through the first bonding pad 232 and the second bonding pad 242. The interface between the first bonding insulating layer 230 and the second bonding insulating layer 240 that contact each other is not defined.
[0043] The first bonding insulating layer 230 and the second bonding insulating layer 240 may each include an insulating material such as SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN. The first bonding pad 232 and the second bonding pad 242 may each include a metal such as copper (Cu), tungsten (W), aluminum (Al), tungsten nitride (WN), tantalum nitride (TaN), and / or titanium nitride (TiN). When the first bonding insulating layer 230 and the second bonding insulating layer 240 are each formed of oxide (e.g., silicon oxide) and the first bonding pad 232 and the second bonding pad 242 are each formed of copper (Cu), the hybrid bonding method may be copper-oxide hybrid bonding.
[0044] The chip stack 200 is mounted on the wiring structure 170. The chip stack 200 is electrically connected to the wiring structure 170. In some embodiments, the chip stack 200 may be bonded to the wiring insulating layer 172 and the wiring pad 176. The chip stack 200 may be bonded to the wiring insulating layer 172 and the wiring pad 176 by a hybrid bonding method. The adjacent wiring insulating layer 172 and the first bonding insulating layer 230 of the second semiconductor chip 201, and the adjacent wiring pad 176 and the first bonding pad 232, may be bonded in contact with each other.
[0045] The chip stack 200 may be a high bandwidth memory (HBM) chip that does not include a buffer chip, and each of the second semiconductor chips 201-208 may be a memory semiconductor chip. The first semiconductor chip 100 may be a logic semiconductor chip and may also serve as a buffer chip for the chip stack 200. The first semiconductor chip 100 may transmit signals and / or power from an external or external source to the chip stack 200, or may transmit signals from the chip stack 200 to an external or external source.
[0046] The logic semiconductor chip may be, for example, an application processor (AP) such as a central processing unit (CPU), a graphic processing unit (GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an application-specific integrated circuit (ASIC). The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). As another example, the memory semiconductor chip may be a non-volatile memory semiconductor chip such as a phase-change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (RRAM).
[0047] The molding layer 260 is disposed on the wiring structure 170. The molding layer 260 may surround at least a portion of the wiring structure 170 on the wiring structure 170. The molding layer 260 may surround at least a portion of the chip stack 200 on the chip stack 200. The molding layer 260 may cover the side surfaces of the chip stack 200 on the side surfaces of the chip stack 200. For example, the molding layer 260 may expose at least a portion of the top surface of the chip stack 200. As another example, the molding layer 260 may not cover the top surface of the chip stack 200 or may cover at least a portion of the top surface of the chip stack 200. The molding layer 260 may include an insulating material, for example, an insulating polymer material such as EMC.
[0048] The conductive posts 265 are disposed on the wiring structure 170. The conductive posts 265 penetrate the molding layer 260. The conductive posts 265 are spaced apart from the chip stack 200. The conductive posts 265 are electrically connected to the thermal pads 178. In some embodiments, the conductive posts 265 can be in contact with the thermal pads 178.
[0049] The conductive posts 265 may be pillar structures having a predetermined height. The conductive posts 265 may include a metal such as copper (Cu). In some embodiments, the conductive posts 265 may be formed by forming a seed layer and performing an electroplating process using the seed layer. The seed layer may include various metals such as copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), and / or tantalum nitride (TaN).
[0050] The number, spacing, and arrangement of the through vias 165, second pads 162, wiring vias 174V1, 174V2, 174V3, wiring pads 176, thermal pads 178, and conductive posts 265 are not limited to those shown in the figure, and may vary depending on the design.
[0051] The thermal transfer material layer 310 is disposed on the molding layer 260. The thermal transfer material layer 310 may be disposed on the conductive posts 265, covering at least a portion of the conductive posts 265. The thermal transfer material layer 310 may be in contact with the conductive posts 265. The thermal transfer material layer 310 may be disposed on, for example, the top surface of the chip stack 200 and the top surface of the molding layer 260.
[0052] The thermal transfer material layer 310 may include, for example, a thermal interface material (TIM). The thermal transfer material layer 310 may include a thermally conductive adhesive tape, a thermally conductive grease, a thermally conductive adhesive, etc. The thermal transfer material layer 310 may include, for example, at least one metal material selected from silver (Ag), aluminum (Al), copper (Cu), gold (Au), zinc (Zn), nickel (Ni), and / or iron (Fe), or an alloy of the metal material.
[0053] The heat dissipation member 320 is disposed on the heat transfer material layer 310. The heat dissipation member 320 may be adhered onto the molding layer 260 and the conductive posts 265 by the heat transfer material layer 310.
[0054] The heat dissipation member 320 may be, for example, a heat sink, a heat spreader, a heat pipe, etc. The heat dissipation member 320 may include, for example, silver (Ag), copper (Cu), nickel (Ni), gold (Au), or a combination thereof.
[0055] In some embodiments, the heat transfer material layer 310 and the heat dissipation member 320 may be omitted.
[0056] In semiconductor packages according to some embodiments, the first semiconductor chip 100, which generates a relatively large amount of heat, may be thermally connected to the thermal pad 178, the through vias 165, and the conductive posts 265. Therefore, heat generated from the first semiconductor chip 100 can be dispersed in various directions. For example, heat generated from the first semiconductor chip 100 can be dissipated to the thermal pad 178 via the wiring structure 170, and then dissipated to the through vias 165 and / or the conductive posts 265 via the wiring structure 170. That is, heat generated from the first semiconductor chip 100 can be dissipated vertically and / or horizontally. Therefore, the heat dissipation characteristics of the semiconductor package can be improved and / or enhanced.
[0057] 2 to 10 are diagrams illustrating semiconductor packages according to some embodiments. For convenience of explanation, parts that overlap with those described above with reference to FIG. 1 will be briefly described or omitted.
[0058] 2 and 3, a semiconductor package according to some embodiments may further include a metal foil layer 250. The metal foil layer 250 may be a copper foil (Cu foil).
[0059] 2 , in a semiconductor package according to some embodiments, a metal foil layer 250 is disposed on a chip stack 200. The metal foil layer 250 is disposed on the top surface of the chip stack 200. The metal foil layer 250 extends along the top surface of the chip stack 200. A molding layer 260 can expose at least a portion of the top surface of the metal foil layer 250.
[0060] 3 , in a semiconductor package according to some embodiments, a metal foil layer 250 is disposed on the chip stack 200 and the molding layer 260. The metal foil layer 250 may extend along the top surface of the chip stack 200 and the top surface of the molding layer 260. The metal foil layer 250 is disposed on the conductive posts 265.
[0061] Referring to FIG. 4, in a semiconductor package according to some embodiments, a first conductive pad 262 and a solder ball 264 are disposed between a conductive post 265 and a thermal pad 178 .
[0062] The first conductive pad 262 is disposed on the thermal pad 178. The first conductive pad 262 may be connected to the thermal pad 178. The first conductive pad 262 and the thermal pad 178 may include, for example, copper (Cu).
[0063] The solder ball 264 is disposed between the first conductive pad 262 and the conductive post 265. The solder ball 264 can electrically connect the first conductive pad 262 and the conductive post 265.
[0064] Referring to FIG. 5, in a semiconductor package according to some embodiments, a first conductive pad 262 and a second conductive pad 266 are disposed between a conductive post 265 and a thermal pad 178 .
[0065] The first conductive pad 262 is disposed on the thermal pad 178. The first conductive pad 262 may be connected to the thermal pad 178. The first conductive pad 262 and the thermal pad 178 may include, for example, copper (Cu).
[0066] The second conductive pad 266 is disposed between the first conductive pad 262 and the conductive post 265. The second conductive pad 266 may electrically connect the first conductive pad 262 and the conductive post 265. The second conductive pad 266 is disposed on the lower surface of the first conductive pad 262. The second conductive pad 266 may include, for example, tin (Sn).
[0067] 6, in a semiconductor package according to some embodiments, a first conductive pad 262 is disposed between a conductive post 265 and a thermal pad 178. The first conductive pad 262 may be connected to the thermal pad 178. The conductive post 265 may include a first conductive film 265a and a second conductive film 265b.
[0068] The first conductive film 265a may be a pillar structure having a predetermined height. The second conductive film 265b may extend along the side and bottom surfaces of the first conductive film 265a. The second conductive film 265b may expose at least a portion of the top surface of the first conductive film 265a.
[0069] For example, the first conductive pad 262 and the first conductive film 265a may include copper (Cu), and the second conductive film 265b may include tin (Sn).
[0070] Referring to FIG. 7, a semiconductor package according to some embodiments may include a first logic semiconductor chip 100a, a second logic semiconductor chip 100b, and a chip stack 200.
[0071] The first logic semiconductor chip 100a and the second logic semiconductor chip 100b are disposed on the upper surface of the package substrate 10. The first logic semiconductor chip 100a and the second logic semiconductor chip 100b are mounted on the package substrate 10. The first logic semiconductor chip 100a and the second logic semiconductor chip 100b are disposed spaced apart on the package substrate 10. The first logic semiconductor chip 100a and the second logic semiconductor chip 100b are the same as or similar to the first semiconductor chip 100 of FIG. 1, and therefore detailed description thereof will be omitted.
[0072] The wiring structure 170 may be electrically connected to the first logic semiconductor chip 100a and the second logic semiconductor chip 100b. The conductive posts 265 may be electrically connected to the first logic semiconductor chip 100a and the second logic semiconductor chip 100b.
[0073] The chip stack 200 is disposed on the first logic semiconductor chip 100a and the second logic semiconductor chip 100b. The chip stack 200 can be electrically connected to the first logic semiconductor chip 100a and the second logic semiconductor chip 100b. That is, the chip stack 200 can be electrically connected to a plurality of first semiconductor chips 100.
[0074] Referring to FIG. 8, a semiconductor package according to some embodiments may include a first semiconductor chip 100, a first chip stack 200a, and a second chip stack 200b.
[0075] The first chip stack 200a and the second chip stack 200b are disposed on the wiring structure 170. The first chip stack 200a and the second chip stack 200b are disposed spaced apart on the wiring structure 170. The first chip stack 200a and the second chip stack 200b are each the same as or similar to the chip stack 200 of FIG. 1, and therefore a detailed description thereof will be omitted.
[0076] The first chip stack 200a and the second chip stack 200b can be electrically connected to the wiring structure 170. The first chip stack 200a and the second chip stack 200b can be electrically connected to the first semiconductor chip 100. That is, the multiple chip stacks 200 can be electrically connected to the first semiconductor chip 100.
[0077] 9, in a semiconductor package according to some embodiments, adjacent second semiconductor chips 201-208 may be electrically connected by third connection terminals 254. The third connection terminals 254 are disposed between the adjacent second semiconductor chips 201-208. The chip stack 200 may be electrically connected to the wiring structure 170 by the third connection terminals 254.
[0078] Each of the second semiconductor chips 201 to 207 may include a second semiconductor substrate 210, a second through-electrode 215, a second semiconductor element layer 220, a lower pad 251, and an upper pad 252. The lower pad 251 is disposed on the second semiconductor element layer 220. The second semiconductor chip 208 may include the second semiconductor substrate 210, the second semiconductor element layer 220, the lower pad 251, and an upper pad 252. The lower pad 251 may be electrically connected to the second semiconductor element layer 220. The upper pad 252 is disposed on a second surface 210b of the second semiconductor substrate 210. The upper pad 252 may be electrically connected to the second through-electrode 215.
[0079] The third connection terminal 254 is disposed between the adjacent lower pad 251 and upper pad 252. The third connection terminal 254 can connect the adjacent lower pad 251 and upper pad 252. For example, the third connection terminal 254 is disposed between the upper pad 252 of the second semiconductor chip 201 and the lower pad 251 of the second semiconductor chip 202.
[0080] The third connection terminal 254 is disposed between the chip stack 200 and the wiring structure 170. The third connection terminal 254 is disposed between the lower pad 251 of the second semiconductor chip 201 and the wiring pad 176 of the wiring structure 170. The third connection terminal 254 can connect the lower pad 251 of the second semiconductor chip 201 and the wiring pad 176 of the wiring structure 170.
[0081] The third connection terminals 254 may include a conductive material such as solder, tin (Sn), silver (Ag), copper (Cu), and / or aluminum (Al). The third connection terminals 254 may have various shapes such as lands, balls, pins, pillars, etc. The number, spacing, and arrangement of the third connection terminals 254 are not limited to those shown in the drawings and may vary depending on the design.
[0082] The underfill material layer 258 may surround the third connection terminals 254 between the adjacent second semiconductor chips 201 to 208. The underfill material layer 258 may fill at least a portion of the space between the adjacent second semiconductor chips 201 to 208. The underfill material layer 258 may surround the third connection terminals 254 between the second semiconductor chip 201 and the wiring structure 170. The underfill material layer 258 may fill at least a portion of the space between the chip stack 200 and the wiring structure 170. The underfill material layer 258 may include, for example, an epoxy resin.
[0083] 10 , a semiconductor package according to some embodiments may include a connecting substrate 400. The connecting substrate 400 is disposed on the wiring structure 170. The bottom surface of the connecting substrate 400 may be in contact with the wiring structure 170.
[0084] The connection substrate 400 may include a plurality of insulating patterns 410 and a plurality of conductive patterns 420. The plurality of insulating patterns 410 are stacked vertically. Each conductive pattern 420 is disposed within each insulating pattern 410. The conductive patterns 420 may penetrate the insulating patterns 410. The conductive patterns 420 may penetrate the insulating patterns 410 to be electrically connected to the wiring structure 170. The conductive patterns 420 may be connected to the thermal pads 178 of the wiring structure 170. The conductive patterns 420 may penetrate the edge patterns 410 to contact the thermal transfer material layer 310.
[0085] The connection substrate 400 may include a through-hole 400H that penetrates the interior of the connection substrate 400. The through-hole 400H can expose at least a portion of the top surface of the wiring structure 170. The chip stack 200 is disposed in the through-hole 400H. The chip stack 200 is spaced apart from the connection substrate 400.
[0086] The molding layer 260 may be on the connecting substrate 400 and cover at least a portion of the connecting substrate 400. The molding layer 260 may fill at least a portion of the space between the connecting substrate 400 and the chip stack 200. The molding layer 260 may fill at least a portion of the space between the connecting substrate 400 and the thermal transfer material layer 310. The molding layer 260 may expose at least a portion of the top surface of the conductive pattern 420.
[0087] The first semiconductor chip 100 may be thermally connected to the thermal pad 178, the through vias 165, and the conductive pattern 420. Heat generated from the first semiconductor chip 100 may be dispersed in various directions. The heat generated from the first semiconductor chip 100 may be released to the thermal pad 178 via the wiring structure 170, and then released to the through vias 165 and / or the conductive pattern 420 via the wiring structure 170.
[0088] 11 to 16 are views illustrating intermediate stages of a method for manufacturing a semiconductor package according to some embodiments. For convenience of explanation, portions that overlap with those described above with reference to FIGS. 1 to 10 will be briefly described or omitted.
[0089] 11, a first semiconductor chip 100 is formed on a carrier substrate 20. The carrier substrate 20 may be, for example, a semiconductor substrate, a glass substrate, a ceramic substrate, or a plastic substrate.
[0090] The first semiconductor chip 100 may include a first semiconductor substrate 110, a first through-electrode 115, a first semiconductor element layer 120, a chip insulating layer 130, and a chip pad 132. The first semiconductor chip 100 may be formed on the carrier substrate 20 such that the second surface 110b of the first semiconductor substrate 110 faces the carrier substrate 20.
[0091] 12 , a pre-insulating film 160p is formed on the carrier substrate 20. The pre-insulating film 160p may cover at least a portion of the carrier substrate 20 and the first semiconductor chip 100. The pre-insulating film 160p may cover the top surface of the carrier substrate 20 and the top surface and side surfaces of the first semiconductor chip 100.
[0092] Referring to FIG. 13, an insulating layer 160 and a through via 165 are formed.
[0093] A planarization process is performed on the top surface of the pre-insulating film 160p to form the insulating layer 160. The insulating layer 160 may expose at least a portion of the top surface of the first semiconductor chip 100. At least a portion of the chip insulating layer 130 and the chip pads 132 of the first semiconductor chip 100 may be exposed.
[0094] A through via 165 is formed in the insulating layer 160. The through via 165 may extend through the insulating layer 160.
[0095] Referring to FIG. 14, a wiring structure 170 is formed on the first semiconductor chip 100 and the insulating layer 160 .
[0096] The wiring structure 170 may include a wiring insulating layer 172, wiring vias 174V1, 174V2, and 174V3, a wiring pad 176, and a thermal pad 178. The wiring insulating layer 172 may cover at least a portion of the first semiconductor chip 100 and the insulating layer 160. The wiring vias 174V1, 174V2, and 174V3, the wiring pad 176, and the thermal pad 178 are formed in the wiring insulating layer 172. The first and second wiring vias 174V1 and 174V2 are formed on the first semiconductor chip 100. The third wiring via 174V3 is formed on the through via 165. The wiring pad 176 is formed on the first wiring via 174V1. The thermal pad 178 is formed on the second and third wiring vias 174V2 and 174V3. The wiring insulating layer 172 can expose the top surfaces of the thermal pads 178 and at least a portion of the top surfaces of the wiring pads 176 .
[0097] 15, a chip stack 200 is formed on the wiring structure 170. The chip stack 200 may be electrically connected to the wiring structure 170. A second bonding insulating layer 240 and a second bonding pad 242 of a second semiconductor chip 201 may be bonded to a wiring insulating layer 172 and a first bonding pad 232 of the wiring structure 170, respectively.
[0098] 16 , a molding layer 260 and conductive posts 265 are formed on the wiring structure 170. The molding layer 260 may cover at least a portion of the wiring structure 170 and the chip stack 200. The molding layer 260 may surround the chip stack 200 on the chip stack 200. The conductive posts 265 may penetrate the molding layer 260 and be connected to the thermal pads 178.
[0099] For example, the conductive posts 265 may be formed on the thermal pads 178 of the wiring structure 170. The conductive posts 265 may be formed, for example, by forming a seed layer and performing an electroplating process using the seed layer. Next, a molding layer 260 is formed to cover the conductive posts 265 and at least a portion of the chip stack 200. A planarization process may be performed on the upper surface of the molding layer 260 to expose the upper surfaces of the conductive posts 265 and / or at least a portion of the upper surface of the chip stack 200. In some embodiments, the planarization process may also remove a portion of the upper portion of the conductive posts 265.
[0100] For example, after forming a molding layer 260 that covers at least a portion of the wiring structure 170 and the chip stack 200, holes are formed through the molding layer 260 to expose at least a portion of the top surface of the thermal pad 178. The conductive posts 265 may be formed by performing a plating process on the holes. For example, the conductive posts 265 may be formed by a plating process, an electroless plating process, a vapor deposition process, or the like. A planarization process may be performed on the top surface of the molding layer 260 to expose the top surfaces of the conductive posts 265 and / or at least a portion of the top surface of the chip stack 200. In some embodiments, the planarization process may also remove the top portions of the conductive posts 265.
[0101] Next, referring to FIG. 1, a heat transfer material layer 310 and a heat dissipation member 320 are formed on the molding layer 260 .
[0102] The carrier substrate 20 is removed to expose the through vias 165 and at least a portion of the first semiconductor chip 100. For example, the carrier substrate 20 may be removed after attaching the carrier substrate to the heat dissipation member 320. First pads 142 may be formed on the exposed first semiconductor chip 100, and second pads 162 may be formed on the through vias 165, at least a portion of which is exposed. First connection terminals 44 may be formed on the first pads 142, and second connection terminals 64 may be formed on the second pads 162.
[0103] Next, a package including the first semiconductor chip 100, the insulating layer 160, the through vias 165, the wiring structure 170, the chip stack 200, the molding layer 260, the conductive posts 265, the heat transfer material layer 310, and the heat dissipation member 320 is formed on the package substrate 10. The first connection terminal 44 may be connected to the first substrate pad 42, and the second connection terminal 64 may be connected to the second substrate pad 62.
[0104] Although the present invention has been described above with reference to the accompanying drawings, it should be understood that the present invention is not limited to the above-described embodiments and can be manufactured in various different forms, and that those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting.
Claims
1. a first semiconductor chip; an insulating layer on the first semiconductor chip; a through via that penetrates the insulating layer; a wiring structure on the first semiconductor chip and the insulating layer, the wiring structure being electrically connected to the first semiconductor chip and the through via; a chip stack on the wiring structure; a molding layer on the wiring structure and on at least a portion of the chip stack; a semiconductor package including conductive posts that pass through the molding layer and are electrically connected to the wiring structure;
2. The semiconductor package of claim 1 , further comprising a connection terminal between the wiring structure and the conductive post.
3. The semiconductor package of claim 1 , wherein the wiring structure and the conductive post are in direct contact with each other.
4. The semiconductor package of claim 1 , wherein the conductive post includes a first metal film and a second metal film on the first metal film, the second metal film including a different material from the first metal film.
5. The semiconductor package according to claim 1 , wherein the chip stack includes stacked second semiconductor chips, and bonding insulating layers and bonding pads between adjacent second semiconductor chips.
6. an insulating layer; a first logic semiconductor chip within the insulating layer; a through via in the insulating layer, the through via being spaced apart from the first logic semiconductor chip; a wiring structure electrically connected to the first logic semiconductor chip and the through via on the insulating layer; a first chip stack including a first memory semiconductor chip stacked on the wiring structure and not including a buffer chip;
7. The semiconductor package of claim 6 , further comprising a second chip stack including a second memory semiconductor chip stacked on the wiring structure and not including a buffer chip.
8. The semiconductor package according to claim 6 , further comprising a second logic semiconductor chip disposed within the insulating layer, the second logic semiconductor chip being spaced apart from the first logic semiconductor chip and electrically connected to the wiring structure.
9. the wiring structure includes a wiring insulating layer and a wiring pad in the wiring insulating layer; the first chip stack includes a bonding insulating layer and a bonding pad; the wiring insulating layer is in contact with the bonding insulating layer; The semiconductor package of claim 6 , wherein the wiring pads contact the bonding pads.
10. A package substrate; a first semiconductor chip on the package substrate; an insulating layer on the first semiconductor chip; a through via that penetrates the insulating layer; a wiring structure on the first semiconductor chip and the insulating layer, the wiring structure being electrically connected to the first semiconductor chip and the through via; a chip stack on the wiring structure and electrically connected to the wiring structure; a molding layer on the wiring structure and on at least a portion of the chip stack; a conductive post that penetrates the molding layer and is electrically connected to the wiring structure; a heat transfer material layer on the molding layer; The semiconductor package further comprises a heat dissipation member on the heat transfer material layer.