Signal transfer circuit and manufacturing method for signal transfer circuit

Abstract

To provide a clock transfer circuit capable of forming a clock tree traversing a plurality of circuit regions having the identical circuit pattern.SOLUTION: A clock transfer circuit 80 includes a plurality of circuit regions 81 having a mutually common circuit pattern, arranged along a direction D1. The circuit pattern of each of the plurality of circuit regions 81 has: circuit elements E0 to E6 capable of switching between a high-impedance state and a passage state; and wiring connected to a circuit pattern of an adjacent circuit region 81. A clock tree traversing the plurality of circuit regions 81 is configured by controlling a state of the circuit elements E0 to E6 of the plurality of circuit regions 81 to a predetermined state defined for each circuit region 81.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a clock transmission circuit, an imaging device, and a method for manufacturing a clock transmission circuit. [Background technology]

[0002] Patent Document 1 discloses a buffering technology using structured delay skew. Patent Document 1 also describes a tree structure routing method. Patent Document 2 discloses a technology related to an exposure apparatus that forms a desired pattern on a substrate by overlapping and exposing parts of a projected image of a pattern formed on a reticle. Patent Document 3 describes performing overlapping exposure when manufacturing display devices for large display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-060036 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-110708 [Patent Document 3] Japanese Patent Application Laid-Open No. 2001-154371 Summary of the Invention [Problem to be solved by the invention]

[0004] When a clock signal propagates within a semiconductor device, delays occur in the clock signal depending on the length and load of the clock wiring. Therefore, when a clock signal needs to be input to multiple circuits at the same time, a clock tree is used. In a clock tree, it is desirable for the clock signal to branch symmetrically with respect to the center position of the circuit group to which the clock is supplied.

[0005] On the other hand, in the photolithography process for manufacturing large-area semiconductor devices, multiple shots with a common exposure pattern are sometimes joined together to form a single device. This technique is called splice exposure. When manufacturing semiconductor devices using splice exposure, multiple circuit regions with the same circuit pattern are lined up, so while it is easy to form a clock tree within each circuit region, it is difficult to form a clock tree that crosses multiple circuit regions. This creates the problem of clock signal delays between multiple circuit regions.

[0006] The present disclosure aims to provide a clock distribution circuit that enables the formation of a clock tree that crosses multiple circuit regions having the same circuit pattern, and a method for manufacturing the clock distribution circuit, and also aims to provide an image sensor that has little clock signal delay. [Means for solving the problem]

[0007] The clock transmission circuit according to the present disclosure is a clock transmission circuit including a clock tree provided on a single substrate. This clock transmission circuit includes multiple circuit areas that share a common circuit pattern and are aligned in one direction. The circuit pattern of each of the multiple circuit areas includes at least two circuit elements that can be switched between a high-impedance state and a pass-through state, and wiring that is connected to the circuit pattern of an adjacent circuit area. At least a portion of a clock tree that traverses the multiple circuit areas is configured by controlling the states of the at least two circuit elements in the multiple circuit areas to a predetermined state that is determined for each circuit area.

[0008] A manufacturing method for a clock distribution circuit according to the present disclosure is a method for manufacturing a clock distribution circuit including a clock tree provided on a single substrate. The manufacturing method includes a step of forming multiple circuit regions that share a common circuit pattern and are aligned in one direction by performing splice exposure using a common exposure pattern. The circuit pattern of each of the multiple circuit regions includes at least two circuit elements that can be switched between a high-impedance state and a pass-through state, and wiring that is connected to the circuit pattern of an adjacent circuit region. At least a portion of a clock tree that traverses the multiple circuit regions is configured by controlling the states of the at least two circuit elements in the multiple circuit regions to a predetermined state determined for each circuit region.

[0009] These clock transmission circuits and methods for manufacturing clock transmission circuits enable the formation of a clock tree that crosses multiple circuit areas having the same circuit pattern, thereby reducing the delay of the clock signal between the multiple circuit areas.

[0010] In the clock transmission circuit, the circuit pattern may include multiple circuit sections configured to respectively handle multiple branching stages of the clock tree, in which case the branching stages of the clock tree can be suitably realized by the circuit sections of each stage.

[0011] In the clock transmission circuit, one of the multiple-stage circuit portions may include first and second circuit elements included in the at least two circuit elements, with output terminals connected to each other. The wiring may include a first wiring portion for connecting the input terminal of the first circuit element to the input terminal of a second circuit element in an adjacent circuit area on one side, and a second wiring portion for connecting the input terminal of the second circuit element to the input terminal of the first circuit element in an adjacent circuit area on the other side. When a clock signal propagates through the circuit portion, the circuit portion can input the clock signal from the first wiring portion or the second wiring portion and output the clock signal from a first node between the output terminal of the first circuit element and the output terminal of the second circuit element. This allows the circuit portion to be easily implemented.

[0012] In the clock transmission circuit, at least one of the multiple-stage circuit portions may include third, fourth, and fifth circuit elements included in the at least two circuit elements. The output terminal of the third circuit element, the input terminal of the fourth circuit element, and the input terminal of the fifth circuit element may be connected to the second node, and the input terminal of the third circuit element and the output terminal of the fourth circuit element may be connected to the third node. The wiring may include a third wiring portion for connecting the second node to the third node of an adjacent circuit area on one side, and a fourth wiring portion for connecting the third node to the second node of an adjacent circuit area on the other side. When a clock signal propagates through the circuit portion, the circuit portion can receive the clock signal at the third node and output the clock signal from the output terminal of the fifth circuit element as needed. Furthermore, the propagation direction of the clock signal can be controlled by controlling the states of the third and fourth circuit elements. This allows for easy implementation of circuit portions, particularly in the first or middle stages.

[0013] In the clock transmission circuit, the at least two circuit elements may be tristate (registered trademark) type. In this case, each of the at least two circuit elements can be simply configured with a single functional part. Furthermore, since the output resistance of the circuit elements in the pass-through state can be kept low, the delay of the clock signal caused by the resistance of the circuit elements can be reduced.

[0014] In the above clock transmission circuit, of the at least two circuit elements, at least the circuit element constituting the circuit portion in the final stage may be of a tri-state type, and the output terminal of the circuit element may be connected to a pull-up resistor or a pull-down resistor. Alternatively, in the above clock transmission circuit, of the at least two circuit elements, at least the circuit element constituting the circuit portion in the final stage may be configured to include a logic circuit. With any of these configurations, it is possible to prevent the signal level to the clock supply destination from becoming unstable, thereby preventing malfunction of the clock supply destination.

[0015] The imaging element according to the present disclosure includes a pixel array including a plurality of pixels arranged one-dimensionally or two-dimensionally; an analog / digital converter array including a plurality of analog / digital converters that convert a plurality of analog signals output from each of the plurality of pixels into a digital signal; a memory array having a plurality of storage areas for storing the plurality of digital signals output from the analog / digital converter array; and a horizontal scanning circuit that sequentially outputs the plurality of digital signals stored in the memory array as a serial signal. At least one of the analog / digital converter array and the horizontal scanning circuit receives a clock signal via any one of the clock transmission circuits described above. This imaging element can reduce the delay in the clock signal between the plurality of digital signals, thereby reducing the frequency of errors when reading out the serial signal. [Effects of the Invention]

[0016] According to the present disclosure, it is possible to provide a clock distribution circuit and a method for manufacturing the clock distribution circuit that enable the formation of a clock tree that crosses multiple circuit areas having the same circuit pattern, and also to provide an image sensor with little delay in the clock signal. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a side view schematically illustrating a configuration of an exposure apparatus used to manufacture an imaging element according to an embodiment. [Figure 2] FIG. 2 is a plan view schematically showing a reticle pattern of a photomask. [Figure 3] 1A is a plan view showing the circuit-forming surface of the wafer after exposure and development, FIG. 1B is an enlarged view of a portion of FIG. 1A, and FIG. 1C is a cross-sectional view taken along line IIIc-IIIc in FIG. 1B. [Figure 4] FIG. 2 is a diagram illustrating a specific example of the configuration of each of a plurality of image pickup elements. [Figure 5] FIG. 2 is a diagram schematically illustrating a configuration of a clock tree. [Figure 6] FIG. 2 is a circuit diagram showing a configuration of a clock transmission circuit. [Figure 7] FIG. 2 is a circuit diagram showing the circuit patterns of each circuit area. [Figure 8] 10A and 10B are circuit diagrams showing other examples of circuit patterns in each circuit region. [Figure 9] FIG. 2 is a circuit diagram showing an example of a circuit that controls circuit elements in each circuit area. [Figure 10] FIG. 10 is a diagram illustrating another example of control of the clock transmission circuit. [Figure 11] 1 is a flowchart illustrating a method for manufacturing a clock distribution circuit according to an embodiment. [Figure 12] FIG. 1 is a diagram schematically illustrating a clock transmission circuit as a reference example. [Figure 13] 1A and 1B are diagrams illustrating the influence of clock signal delay. (a) shows a clock signal input to one end of a series circuit. (b) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit area close to one end of the series circuit. (c) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit area far from one end of the series circuit. [Figure 14] 1A to 1C are circuit diagrams showing configuration examples of circuit elements. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of a clock transfer circuit, an image sensor, and a method for manufacturing a clock transfer circuit according to the present disclosure will be described in detail with reference to the accompanying drawings. Note that in the description of the drawings, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0019] FIG. 1 is a side view schematically illustrating the configuration of an exposure apparatus 1 used to manufacture an imaging element according to an embodiment of the present disclosure. As shown in FIG. 1, the exposure apparatus 1 is an apparatus that exposes a resist R coated on a wafer W and includes a light source 10, a photomask 20, and a lens 30. The light source 10 outputs light L having a wavelength to which the resist R is sensitive. The photomask 20 has a reticle pattern (exposure pattern) for forming an imaging element 40 (see FIG. 3), which will be described later. The photomask 20 is disposed opposite the light source 10. The lens 30 is disposed between the photomask 20 and the wafer W. The light L output from the light source 10 passes through the photomask 20, is collected by the lens 30, and reaches the resist R on the wafer W. The resist R may be either positive or negative.

[0020] FIG. 2 is a plan view schematically illustrating a reticle pattern 21 of the photomask 20. The reticle pattern 21 includes at least a first portion 211, a second portion 212, and a third portion 213. The first portion 211 is a portion for forming the light-receiving portion of the image sensor 40 and includes an exposure pattern corresponding to a circuit pattern common to each of a plurality of circuit regions when the light-receiving portion of the image sensor 40 is divided into the plurality of circuit regions. The second portion 212 is a portion for forming a circuit region 42 (see FIG. 3) arranged on one side of the light-receiving portion of the image sensor 40. The third portion 213 is a portion for forming a circuit region 43 (see FIG. 3) arranged on the other side of the light-receiving portion of the image sensor 40. The second portion 212 and the third portion 213 include exposure patterns corresponding to a circuit for supplying bias power to the light-receiving portion, etc.

[0021] FIG. 3(a) is a plan view showing the circuit formation surface of the wafer W after exposure and development. FIG. 3(b) is an enlarged view of a portion of FIG. 3(a). As shown in FIG. 3(a), multiple image pickup elements 40 are formed on the wafer W by exposure using the exposure apparatus 1 and subsequent development. The multiple image pickup elements 40 are arranged along a direction D2 intersecting the direction D1, with the direction D1 being the longitudinal direction. As shown in FIG. 3(b), each of the multiple image pickup elements 40 has a circuit area group 44 consisting of multiple circuit areas 41 arranged along the direction D1, a circuit area 42 arranged on one end side of the circuit area group 44 in the direction D1, and a circuit area 43 arranged on the other end side of the circuit area group 44 in the direction D1. The circuit area group 44 includes a light receiving portion.

[0022] Each of the multiple circuit regions 41 is a region formed by splicing exposure using the first portion 211 shown in FIG. 2. That is, the multiple circuit regions 41 are regions formed by exposing the resist R while moving the first portion 211 along direction D1. At this time, adjacent regions exposed by the first portion 211 may partially overlap each other. The multiple circuit regions 41 have the same circuit pattern. Circuit region 42 is a region formed by exposure using the second portion 212 shown in FIG. 2. Circuit region 43 is a region formed by exposure using the third portion 213 shown in FIG. 2. Circuit region 42 has a circuit pattern different from that of circuit region 41. Circuit region 43 has a circuit pattern different from that of circuit regions 41 and 42.

[0023] Fig. 3(c) is a diagram showing a cross section taken along line IIIc-IIIc in Fig. 3(b). As shown in Fig. 3(c), the circuit region group 44, the circuit region 42, and the circuit region 43 are provided on a single substrate 62 cut out from the wafer W. The length of the substrate 62 in the direction D1 is, for example, not less than 20 mm and not more than 300 mm.

[0024] FIG. 4 is a diagram showing a specific configuration example of each of the multiple image sensors 40. As shown in FIG. 4, the circuit area group 44 includes a pixel array 45, an amplifier array 46, an analog-to-digital (A / D) converter array 47, a memory array 48, a horizontal scanning circuit group 49, an output circuit group 50, a clock transmission circuit 80A for the A / D converter, and a clock transmission circuit 80B for the horizontal scanning circuit and the output circuit. The pixel array 45 is formed by arranging multiple regions 451, each included in multiple circuit areas 41, side by side along the direction D1. The amplifier array 46 is formed by arranging multiple regions 461, each included in multiple circuit areas 41, side by side along the direction D1. The A / D converter array 47 is formed by arranging multiple regions 471, each included in multiple circuit areas 41, side by side along the direction D1. The memory array 48 is formed by arranging multiple regions 481, each included in multiple circuit areas 41, side by side along the direction D1. The horizontal scanning circuit group 49 is formed by arranging a plurality of regions 491, each included in a plurality of circuit regions 41, side by side along the direction D1. The output circuit group 50 is formed by arranging a plurality of regions 501, each included in a plurality of circuit regions 41, side by side along the direction D1. Note that in Fig. 4, only some of the plurality of circuit regions 41 located near both ends of the circuit region group 44 in the direction D1 are shown, and the other circuit regions 41 are not shown.

[0025] The pixel array 45 includes multiple pixels arranged one-dimensionally or two-dimensionally. The multiple pixels are aligned at least along the direction D1. Each of the multiple regions 451 includes two or more pixels. Therefore, for example, if each of P regions 451 includes Q pixels, the total number of pixels in the pixel array 45 is (P × Q) (P and Q are integers greater than or equal to 2). The Q pixels are arranged in n columns and m rows (n × m = Q, where n and m are natural numbers). Each pixel generates an amount of charge corresponding to the intensity of light incident on that pixel. Each pixel may include an in-pixel amplifier and perform current-to-voltage conversion within the pixel. Each pixel may be formed, for example, by ion implantation on the surface of the wafer W. Wiring connected to each pixel may be formed, for example, by etching on the surface of the wafer W. The multiple regions 451 have the same circuit pattern, and the exposure pattern used during ion implantation and etching is common to all of the multiple regions 451.

[0026] The amplifier array 46 may include multiple amplifiers that perform current-to-voltage conversion on each of the multiple analog signals output from each of the multiple pixels in the pixel array 45. Alternatively, if current-to-voltage conversion is performed within each pixel, the amplifier array 46 may include multiple amplifiers that amplify each of the multiple analog signals. The multiple amplifiers correspond to the multiple pixel columns in the pixel array 45. Each of the multiple regions 461 includes two or more amplifiers. For example, if each of the P regions 451 includes n pixel columns, each of the P regions 461 includes n amplifiers. Therefore, the total number of amplifiers in the amplifier array 46 is at least (P × n). Each of the multiple amplifiers may be configured, for example, by an amplifier circuit including a transistor. The drain and source regions of the transistor may be formed, for example, by ion implantation into the surface of the wafer W. The gates of the transistors and wiring connected to the drain and source regions may be formed on the surface of the wafer W, for example, by a lift-off method or the like. The multiple regions 461 have the same circuit pattern, and the exposure patterns used during ion implantation and lift-off are common to the multiple regions 461.

[0027] The A / D converter array 47 includes a plurality of A / D converters that convert a plurality of analog signals output from a plurality of pixels in the pixel array 45 into digital signals. The plurality of A / D converters correspond to a plurality of amplifiers in the amplifier array 46. Each of the plurality of regions 471 includes two or more A / D converters. For example, if each of the P regions 461 includes n amplifiers, each of the P regions 471 includes n A / D converters. Therefore, the total number of A / D converters in the A / D converter array 47 is at least (P×n). The plurality of regions 471 have the same circuit pattern, and the exposure pattern used to form the A / D converters is common to the plurality of regions 471.

[0028] The memory array 48 has a plurality of memory cells (storage areas) that store the plurality of digital signals output from the A / D converter array 47. The plurality of memory cells correspond to the plurality of A / D converters, respectively. Each of the plurality of areas 481 includes two or more memory cells. For example, if each of the P areas 471 includes n A / D converters, each of the P areas 481 includes n memory cells. Therefore, the total number of memory cells in the memory array 48 is (P×n). The plurality of areas 481 have the same circuit pattern, and the exposure pattern used to form the memory cells is common to the plurality of areas 481.

[0029] The horizontal scanning circuit group 49 sequentially outputs the multiple digital signals stored in the memory array 48 as serial signals. The horizontal scanning circuit group 49 has multiple regions 491. Each of the multiple regions 491 includes two or more horizontal scanning circuits. In one example, the number of horizontal scanning circuits included in each of the multiple regions 491 is two. In that case, if each of the P regions 481 includes n memory cells, then (n / 2) memory cells correspond to one horizontal scanning circuit. Each horizontal scanning circuit sequentially outputs the digital signals from these (n / 2) memory cells as serial signals to the corresponding region 501 of the output circuit group 50. The multiple regions 491 have the same circuit pattern, and the exposure pattern used to form the horizontal scanning circuits is common to the multiple regions 491.

[0030] The output circuit group 50 has a plurality of regions 501. Each of the plurality of regions 501 is connected to a respective one of the plurality of regions 491 of the horizontal scanning circuit group 49. Each region 501 includes an output circuit corresponding to the horizontal scanning circuit included in each region 491 of the horizontal scanning circuit group 49, and each output circuit receives digital signals sequentially output as serial signals from the corresponding horizontal scanning circuit. The output circuit of each region 501 generates output data Dout from these digital signals and outputs the output data Dout to outside the image sensor 40.

[0031] The circuit area 42 includes, for example, a timing control circuit 421. The timing control circuit 421 transmits a common clock signal to the pixel array 45, the amplifier array 46, a clock transfer circuit 80A for the A / D converter, and a clock transfer circuit 80B for the horizontal scanning circuit.

[0032] The circuit area 43 includes, for example, a bias voltage generation circuit 431. The bias voltage generation circuit 431 is connected to each of the multiple pixels in the pixel array 45, each of the multiple amplifiers in the amplifier array 46, and each of the multiple A / D converters in the A / D converter array 47 via wiring (not shown), and supplies bias voltages to the multiple pixels in the pixel array 45, the multiple amplifiers in the amplifier array 46, and the multiple A / D converters in the A / D converter array 47.

[0033] Next, the configuration of the clock transmission circuits 80A, 80B will be described in detail. The clock transmission circuits 80A, 80B include a clock tree provided on a single substrate 62 (see FIG. 3(c)). FIG. 5 is a diagram schematically illustrating the configuration of a clock tree 70 as an example. The clock tree 70 has multiple branches between a wiring 76 that inputs a clock signal and a circuit 77 that uses the clock signal. Each branch branches a single clock wiring into at least two. FIG. 5 illustrates, as an example, a total of three branches: a first stage C1, a second stage C2, and a third (final) stage C3. Repeater buffers 78 are provided in the wiring between the first stage C1 and the second stage C2, the wiring between the second stage C2 and the third stage C3, and the wiring between the third stage C3 and the circuit 77.

[0034] Fig. 6 is a circuit diagram showing the configuration of clock transmission circuit 80. Clock transmission circuits 80A and 80B shown in Fig. 4 have a configuration similar to that of clock transmission circuit 80. Circuit 77 in Fig. 6 includes all the A / D converters included in the multiple regions 471 in A / D converter array 47, all the horizontal scanning circuits included in the multiple regions 491 in horizontal scanning circuit group 49, and all the output circuits included in the multiple regions 501 in output circuit group 50.

[0035] The clock transmission circuit 80 includes a plurality of circuit areas 81. Each of the plurality of circuit areas 81 is included in a respective one of the plurality of circuit areas 41 (see FIGS. 3 and 4). The plurality of circuit areas 81 have a common circuit pattern and are arranged side by side along direction D1. Each circuit area 81 is in contact with and continuous with the adjacent circuit area 81.

[0036] FIG. 7 is a circuit diagram showing the circuit pattern of each circuit region 81. As shown in FIG. 7, the circuit pattern of each circuit region 81 has at least two (nine in this embodiment) circuit elements E0 to E8 and wirings W1 to W6. At least the circuit elements E0 to E6 (circuit elements E0 to E8 in this embodiment) are circuit elements that can switch between a high-impedance state and a pass-through state, and are, for example, tristate (registered trademark) type circuit elements. The tristate type is also called a three-state type. The high-impedance state refers to a state having a resistance value that is an insulating state or close to the insulating state. The pass-through state refers to a state in which a signal that follows the logic of an input signal is output. In one example, the circuit elements E0 to E8 are tristate buffers or tristate inverters. The circuit elements E0 to E8 function as repeater buffers in the clock tree. The wirings W1 to W6 are wirings that are connected to the circuit patterns of adjacent circuit regions 81. The circuit pattern of each circuit area 81 includes a clock supply portion 82, a first-stage (initial stage) circuit portion 83, a second-stage circuit portion 84, and a third-stage (final stage) circuit portion 85.

[0037] The clock supply section 82 is a section for supplying a clock signal input from outside the clock transmission circuit 80 to the clock tree. The clock supply section 82 includes circuit elements E0 and E1 and wiring W5 and W6. One end of wiring W5 is connected to wiring W6 of an adjacent circuit region 81 on one side (the left side of the figure). The other end of wiring W5 is connected to the input terminal of circuit element E0. Circuit element E0 receives at its input terminal a clock signal input from outside the clock transmission circuit 80 via the adjacent circuit region 81. One end of wiring W6 is connected to the output terminal of circuit element E0. The other end of wiring W6 is connected to wiring W5 of an adjacent circuit region 81 on the other side (the right side of the figure). In addition, the input terminal of circuit element E1 is connected to wiring W6.

[0038] When circuit element E0 is in a pass-through state, the clock signal propagates from wire W5 to wire W6. When circuit element E0 is in a high-impedance state, the clock signal does not propagate from wire W5 to wire W6. When circuit elements E0 and E1 are both in a pass-through state, the clock signal propagates from wire W5 to the first-stage circuit portion 83. When circuit element E0 is in a pass-through state and circuit element E1 is in a high-impedance state, the clock signal propagates through wires W5 and W6 but does not propagate to the first-stage circuit portion 83.

[0039] The first-stage circuit portion 83 is a portion for branching the clock signal supplied from the clock supply portion 82. The circuit portion 83 includes a circuit element E2 (third circuit element), a circuit element E3 (fourth circuit element), and a circuit element E4 (fifth circuit element). In addition, the circuit portion 83 includes a wiring W3 (third wiring portion) and a wiring W4 (fourth wiring portion).

[0040] The output terminal of circuit element E2, the input terminal of circuit element E3, and the input terminal of circuit element E4 are connected to node N2 (second node). The input terminal of circuit element E2 and the output terminal of circuit element E3 are connected to node N3 (third node). In other words, circuit elements E2 and E3 are connected in parallel between nodes N2 and N3, facing in opposite directions. The input terminal of circuit element E4 is connected to one end of this parallel circuit. Wiring W3 is a wiring portion for connecting node N2 to node N3 of an adjacent circuit region 81 on one side (left side of the figure). Wiring W4 is a wiring portion for connecting node N3 to node N2 of an adjacent circuit region 81 on the other side (right side of the figure). Node N3 is connected to a clock supply wiring from outside the clock transmission circuit 80, i.e., the output terminal of circuit element E1 of the clock supply section 82.

[0041] When circuit element E2 is in a pass state and circuit element E3 is in a high impedance state, the clock signal propagates from node N3 to node N2. Conversely, when circuit element E2 is in a high impedance state and circuit element E3 is in a pass state, the clock signal propagates from node N2 to node N3. Circuit elements E2 and E3 are never in a pass state at the same time. When both circuit elements E2 and E3 are in a high impedance state, the clock signal does not propagate between node N2 and node N3. When circuit element E4 is in a pass state, the clock signal propagates from node N2 to second-stage circuit portion 84. When circuit element E4 is in a high impedance state, the clock signal does not propagate from node N2 to second-stage circuit portion 84.

[0042] When a clock signal propagates through circuit portion 83, circuit portion 83 receives the clock signal at node N3 and can output the clock signal from the output terminal of circuit element E4 as needed. Furthermore, the propagation direction of the clock signal can be controlled by controlling the states of circuit elements E2 and E3. Note that the clock tree includes branches that cross multiple circuit areas 81 and branches that occur within each circuit area 81, and circuit portion 83 is responsible for the initial and middle branches of the branches that cross multiple circuit areas 81.

[0043] The second-stage circuit portion 84 is a portion for further branching the clock signal supplied from the first-stage circuit portion 83. The circuit portion 84 includes a circuit element E5 (first circuit element) and a circuit element E6 (second circuit element). In addition, the circuit portion 84 includes a wiring W1 (first wiring portion) and a wiring W2 (second wiring portion).

[0044] The output terminals of the circuit elements E5 and E6 are connected to each other. In other words, the output terminals of the circuit elements E5 and E6 are connected to the node N1. The wiring W1 is a wiring portion for connecting the input terminal of the circuit element E5 to the input terminal of the circuit element E6 in the adjacent circuit area 81 on one side (the left side of the figure). The wiring W1 is connected to the wiring W2 in the adjacent circuit area 81 on one side. Furthermore, the wiring W1 is connected to the output terminal of the circuit element E4. The wiring W2 is a wiring portion for connecting the input terminal of the circuit element E6 to the input terminal of the circuit element E5 in the adjacent circuit area 81 on the other side (the right side of the figure). The wiring W2 is connected to the wiring W1 in the adjacent circuit area 81 on the other side.

[0045] When circuit element E5 is in a pass state and circuit element E6 is in a high impedance state, the clock signal propagates from wire W1 to node N1. When circuit element E5 is in a high impedance state and circuit element E6 is in a pass state, the clock signal propagates from wire W2 to node N1. Circuit elements E5 and E6 are never in a pass state at the same time. When both circuit elements E5 and E6 are in a high impedance state, the clock signal does not propagate to node N1.

[0046] When a clock signal propagates through circuit portion 84, circuit portion 84 receives the clock signal via wire W1 or wire W2 and can output the clock signal from node N1. As described above, the clock tree has branches that span multiple circuit areas 81 and branches that occur within each circuit area 81, and this circuit portion 84 is responsible for the final branch of the branches that span multiple circuit areas 81.

[0047] The third-stage circuit portion 85 is a portion responsible for branching within each circuit area 81. The circuit portion 85 includes a circuit element E7 and a circuit element E8. The input terminals of the circuit elements E7 and E8 are connected to the node N1 and to each other. As shown in FIG. 6 , the output terminals of the circuit elements E7 and E8 are branched into a plurality of wirings 87, which are then connected to a plurality of clock supply targets included in the circuit 77 that uses the clock (for example, a plurality of A / D converters in the A / D converter array 47, a plurality of horizontal scanning circuits in the horizontal scanning circuit group 49, or a plurality of output circuits in the output circuit group 50). The output terminals of the circuit elements E7 and E8 may be connected to a wiring that is commonly provided across the plurality of circuit areas 81 and connected to a plurality of clock supply targets of the circuit 77 via the wiring.

[0048] In other words, in the clock supply section 82, as shown in FIG. 6, the circuit elements E0 of the multiple circuit areas 81 are connected in series with the same orientation. The input terminal of the circuit element E1 of each circuit area 81 is connected to a node between adjacent circuit elements E0. In the first-stage circuit section 83, the circuit elements E2 of the multiple circuit areas 81 are connected in series with the same orientation, and the circuit elements E3 of the multiple circuit areas 81 are connected in series with the same orientation but in the opposite direction to the circuit element E2. The node between adjacent circuit elements E2 is common to the node between adjacent circuit elements E3. The node between the circuit elements E2 is alternately connected to the output terminal of circuit element E1 and the input terminal of circuit element E4. In the second-stage circuit section 84, the circuit elements E5 and E6 are alternately connected in series, with the circuit element E6 oriented in the opposite direction to the circuit element E5. The output terminal of the circuit element E4 is connected to the node between the input terminal of the circuit element E5 and the input terminal of the circuit element E6.

[0049] 6 shows an example of a clock tree that can be realized by a plurality of circuit regions 81 having the above-described configuration. Circuit elements present on the clock propagation path F1 are in a passing state (shown in white in the figure), and circuit elements present outside the clock propagation path F1 are in a high-impedance state (shown in half-tone in the figure). A specific description will be given below.

[0050] 6, circuit elements E0 in two circuit areas 81A and 81B on one side are set to a passing state, and circuit elements E0 in two circuit areas 81C and 81D on the other side are set to a high-impedance state. Furthermore, circuit element E1 in circuit area 81B is set to a passing state, and circuit elements E1 in the other circuit areas 81A, 81C, and 81D are set to a high-impedance state. Thus, a clock signal supplied from outside the clock transmission circuit 80 passes through circuit elements E0 in circuit areas 81A and 81B and circuit element E1 in circuit area 81B, and reaches the apex (clock input terminal) of the clock tree located in circuit area 81B.

[0051] Next, in the first-stage circuit portion 83, circuit element E2 in circuit area 81B is set to a passing state, and circuit elements E2 in the other circuit areas 81A, 81C, and 81D are set to a high-impedance state. Circuit element E3 in circuit area 81C is set to a passing state, and circuit elements E3 in the other circuit areas 81A, 81B, and 81D are set to a high-impedance state. Furthermore, circuit elements E4 in circuit areas 81B and 81D are set to a passing state, and circuit element E4 in the other circuit areas 81A and 81C is set to a high-impedance state. As a result, the clock signal is branched into a clock signal that passes through circuit elements E2 and E4 in circuit area 81B, and a clock signal that passes through circuit element E3 in circuit area 81C and circuit element E4 in circuit area 81D.

[0052] Next, in the second-stage circuit portion 84, circuit element E5 in circuit areas 81B and 81D is set to a passing state, and circuit element E5 in the other circuit areas 81A and 81C is set to a high-impedance state. Furthermore, circuit element E6 in circuit areas 81A and 81C is set to a conducting state, and circuit element E6 in the other circuit areas 81B and 81D is set to a high-impedance state. The clock signal that passed through circuit element E4 in circuit area 81B is thereby branched into a clock signal that passes through circuit element E6 in circuit area 81A and a clock signal that passes through circuit element E5 in circuit area 81B. The clock signal that passed through circuit element E4 in circuit area 81D is thereby branched into a clock signal that passes through circuit element E6 in circuit area 81C and a clock signal that passes through circuit element E5 in circuit area 81D.

[0053] Next, in the third-stage circuit portion 85 of each of the circuit areas 81A to 81D, the clock signal that has passed through circuit element E5 or E6 is branched into a clock signal that passes through circuit element E7 and a clock signal that passes through circuit element E8. The clock signals thus branched into eight are supplied to the circuit 77 that uses the clock via branch wiring 87.

[0054] Although the present embodiment describes a case where the circuit portion 83 is provided in only one stage, the circuit portion 83 may be provided in multiple stages as shown in Fig. 8. In this case, the node N3 of the circuit portion 83 provided in the stage following the circuit portion 83 is connected to the output end of the circuit element E4 of the circuit portion 83 in the stage preceding it. This makes it possible to increase the number of branches in the middle stages among the branches spanning multiple circuit areas 81 of the clock tree to any number.

[0055] Furthermore, in the above example, the A / D converter array 47, the horizontal scanning circuit group 49, and the output circuit group 50 all receive the clock signal via the clock transmission circuit 80, but only one or two of the A / D converter array 47, the horizontal scanning circuit group 49, and the output circuit group 50 may receive the clock signal via the clock transmission circuit 80.

[0056] Here, we will explain the circuits that control the circuit elements E0 to E8 in each circuit area 81. Fig. 9 is a circuit diagram showing an example of a circuit that controls the circuit elements E0, E1 in each circuit area 81. Note that the control circuits for the other circuit elements E2 to E8 have a similar configuration, so they are not shown in the figures.

[0057] Each circuit area 81 further includes a plurality of flip-flops 88 corresponding to the circuit elements E0 to E8, respectively. The flip-flop 88 corresponding to the circuit element E0 is cascade-connected across the plurality of circuit areas 81. The flip-flop 88 corresponding to the circuit element E1 is also cascade-connected across the plurality of circuit areas 81. The flip-flops 88 corresponding to the circuit elements E2 to E8 are also cascade-connected across the plurality of circuit areas 81.

[0058] One end of the cascade circuit corresponding to the circuit element E0 is connected to a binary signal S E0 is input. The binary signal S E0 is a signal that takes on an on / off value in synchronization with the clock CLK supplied to the cascade connection circuit. In the example shown in the figure, four cycles of the clock CLK are shown. The binary signal S in the first cycle E0 The output value of the flip-flop 88 in the circuit area 81D located at the innermost position of the cascade-connected circuit is controlled in accordance with the value of the binary signal S in the second period, thereby controlling the circuit element E0 in the circuit area 81D. E0 The output value of the flip-flop 88 in the circuit area 81C is controlled in accordance with the value of the binary signal S in the third period, and the circuit element E0 in the circuit area 81C is controlled accordingly. E0 The output value of the flip-flop 88 in the circuit area 81B is controlled in accordance with the value of the binary signal S E0 In accordance with the value of the binary signal S, the output value of the flip-flop 88 in the circuit area 81A is controlled, and the circuit element E0 in the circuit area 81A is controlled. E0By setting the value of the binary signal S to an arbitrary value for each cycle of the clock CLK, it is possible to individually control the circuit elements E0 of the multiple circuit areas 81. The circuit elements E1 of the multiple circuit areas 81 also control the binary signal S E1 The value of each of the circuit elements E2 to E8 can be individually controlled by setting it to an arbitrary value for each cycle of the clock CLK.

[0059] FIG. 10 illustrates another control example of the clock transmission circuit 80. In this example, the control state of the circuit elements E0 and E1 in the clock supplying section 82 (see FIG. 7) is the same as in the example illustrated in FIG. 6, but in circuit areas 81A, 81C, and 81D, all of the circuit elements E2 to E8 included in the first-stage circuit section 83, the second-stage circuit section 84, and the third-stage circuit section 85 are set to a high-impedance state. Only in circuit area 81B are the circuit elements E2 to E8 controlled in the same manner as in FIG. 6. In this manner, a clock tree may be configured using only some of the multiple circuit areas 81. When some of the multiple clock supply targets included in the clock-using circuit 77 are not used, power consumption can be reduced by configuring the clock tree using only some of the circuit areas 81.

[0060] FIG. 11 is a flowchart showing a method for manufacturing a clock transmission circuit 80 according to this embodiment. When manufacturing the clock transmission circuit 80, a common exposure pattern for the circuit regions 81 is first formed in the first portion 211 of the reticle pattern 21 shown in FIG. 2, for example, and this exposure pattern is used to perform continuous exposure on the resist R (see FIG. 1) (step S1). Next, the resist R is developed and hardened to form a mask (step S2). Then, ion implantation, semiconductor etching, or metal lift-off is performed through the mask to produce the circuit elements E0-E8 or wiring W1-W6 components (step S3). The above steps S1-S3 are repeated the number of times required to manufacture the clock transmission circuit 80 (step S4). The wafer is then cut into individual pieces (step S5). Through these steps, a clock transmission circuit 80 having multiple circuit regions 81 aligned along direction D1 and sharing a common circuit pattern can be manufactured on a single substrate.

[0061] The effects obtained by the clock transfer circuit 80, the image sensor 40, and the manufacturing method for the clock transfer circuit 80 according to the present embodiment described above will now be described. FIG. 12 is a diagram schematically illustrating a clock transfer circuit 100 as a reference example. In this clock transfer circuit 100, multiple circuit areas 110 arranged along direction D1 each include repeater buffers 101 to 104. The repeater buffers 101 and 102 are alternately connected in series across the multiple circuit areas 110. The input terminals of the repeater buffers 103 and 104 are connected to a node between the repeater buffer 101 and the repeater buffer 102. A clock signal is input to one end of a series circuit made up of the repeater buffers 101 and 102, and while propagating through this series circuit, it is branched to the repeater buffers 103 and 104 in each circuit area 110.

[0062] In this clock transmission circuit 100, the longer the distance the clock signal propagates in the series circuit consisting of repeater buffers 101 and 102, the greater the delay in the clock signal. Therefore, the farther the circuit area 110 is from the end of the series circuit where the clock signal is input, the greater the delay in the clock signal. Figure 13 illustrates the effect of clock signal delay. Figure 13(a) shows a clock signal input to one end of the series circuit. Figure 13(b) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit area 110 closer to the end of the series circuit. Figure 13(c) shows an example of a serial signal output from a circuit driven by a clock signal output from a circuit area 110 farther from the end of the series circuit. If a delay occurs in some circuit areas 110, a delay T occurs between the serial signals. This may reduce the accuracy of signal recognition in the circuit that reads the serial signal.

[0063] Therefore, clock trees are used to input clock signals to multiple circuits at the same time. However, when performing splice exposure during the photolithography process for manufacturing large-area semiconductor devices, multiple circuit regions with the same circuit pattern are lined up. While it is easy to form a clock tree within each circuit region, it is difficult to form a clock tree that crosses multiple circuit regions. While it is possible to form a clock tree by using different circuit patterns for each circuit region, this requires preparing multiple types of exposure patterns, which increases manufacturing costs and complicates the manufacturing process.

[0064] In this embodiment, the circuit pattern of each of the multiple circuit areas 81 includes circuit elements E0-E6 that can switch between a high-impedance state and a pass-through state, and wiring W1-W6 that is connected to the circuit pattern of an adjacent circuit area 81. The states of the circuit elements E0-E6 of the multiple circuit areas 81 are controlled to a predetermined state determined for each circuit area 81, as shown in FIG. 6, for example, to form a clock tree that traverses the multiple circuit areas 81. This allows for the formation of a clock tree that traverses the multiple circuit areas 81 having the same circuit pattern. Therefore, clock signal delays between the multiple circuit areas 81 can be reduced. Furthermore, because it is not necessary to have different circuit patterns for each circuit area, it is not necessary to prepare multiple types of exposure patterns, reducing manufacturing costs and simplifying the manufacturing process.

[0065] As in this embodiment, the circuit pattern of each circuit area 81 may include multi-stage circuit portions 83, 84 configured to respectively handle the branching of the clock tree at multiple stages. In this case, the branching of the clock tree at each stage can be suitably realized by the circuit portions 83, 84 at each stage.

[0066] As in this embodiment, the circuit portion 84 may include circuit elements E5 and E6 whose output terminals are connected to each other. The wirings W1 to W6 may include a wiring W1 for connecting the input terminal of the circuit element E5 to the input terminal of the circuit element E6 in the adjacent circuit region 81 on one side, and a wiring W2 for connecting the input terminal of the circuit element E6 to the input terminal of the circuit element E5 in the adjacent circuit region 81 on the other side. The circuit portion 84 through which the clock signal propagates can receive the clock signal from the wiring W1 (or alternatively, the wiring W2) and output the clock signal from a node N1 between the output terminal of the circuit element E5 and the output terminal of the circuit element E6. This allows for a simple implementation of the circuit portion 84 responsible for one stage of branching.

[0067] As in this embodiment, the circuit portion 83 may include circuit elements E2, E3, and E4. The output terminal of circuit element E2, the input terminal of circuit element E3, and the input terminal of circuit element E4 may be connected to node N2, and the input terminal of circuit element E2 and the output terminal of circuit element E3 may be connected to node N3. The wirings W1 to W6 may include wiring W3 for connecting node N2 to node N3 in an adjacent circuit region 81 on one side, and wiring W4 for connecting node N3 to node N2 in an adjacent circuit region 81 on the other side. The circuit portion 83 through which the clock signal propagates can receive the clock signal at node N3 and output the clock signal from the output terminal of circuit element E4 as needed. The propagation direction of the clock signal can be controlled by controlling the states of circuit elements E2 and E3. This allows for easy implementation of the circuit portion 83, particularly for branching in the initial or middle stages.

[0068] As in this embodiment, the circuit elements E0 to E6 may be tristate. In this case, each of the circuit elements E0 to E6 can be simply configured with a single functional part. Furthermore, since the output resistance of the circuit elements E0 to E6 in the pass-through state can be kept low, the delay of the clock signal caused by the resistance of the circuit elements E0 to E6 can be reduced.

[0069] In the image sensor 40 of this embodiment, at least one of the A / D converter array 47, the horizontal scanning circuit group 49, and the output circuit group 50 receives a clock signal via a clock transmission circuit having a configuration similar to that of the clock transmission circuit 80. This image sensor 40 can reduce the delay in the clock signal between multiple digital signals, thereby reducing the frequency of errors when reading out a serial signal.

[0070] The clock transfer circuit, image sensor, and method of manufacturing a clock transfer circuit according to the present disclosure are not limited to the above-described embodiments, and various other modifications are possible. For example, in the above-described embodiments, an example was described in which each circuit area 81 has nine circuit elements E0 to E8, but as long as each circuit area 81 has at least a circuit portion 84, a clock tree spanning two circuit areas 81 can be realized. In other words, each circuit area 81 only needs to have at least two circuit elements E5 and E6.

[0071] In addition, although the above embodiment illustrates the case where the circuit elements E0 to E6 are tri-state, the circuit elements E0 to E6 are not limited to this as long as they can be switched between a high-impedance state and a passing state. For example, the circuit elements E0 to E6 may be configured to include a repeater buffer and a switch connected in series. Even in this case, the high-impedance state and the passing state can be switched by controlling the switch.

[0072] Furthermore, it is desirable that the circuit elements E7 and E8 constituting the final-stage circuit portion 85 have a configuration for preventing the potential of the clock signal supplied to the circuit 77 from becoming unstable. Figures 14(a) to 14(c) are circuit diagrams showing configuration examples of such circuit elements.

[0073] The circuit elements shown in FIGS. 14(a) and 14(b) include logic circuits. Specifically, the circuit element shown in FIG. 14(a) includes a logical product (AND) element 91. In one example, the circuit element consists solely of the AND element 91. The clock CLK from the preceding circuit portion 84 is input to one of the two input terminals of the AND element 91, and the control signal Sctrl from the cascade-connected flip-flop 88 (see FIG. 9) is input to the other input terminal. The AND element 91 outputs the logical product of the clock signal Sclk and the control signal Sctrl to the circuit 77. In addition, the circuit element shown in FIG. 14(b) includes a logical sum (OR) element 92 and a not (NOT) element 93. In one example, the circuit element consists solely of the OR element 92 and the NOT element 93. The clock signal Sclk from the preceding circuit portion 84 is input to one of the two input terminals of the OR element 92. The other of the two input terminals of the OR element 92 is connected to the output terminal of a NOT element 93. A control signal Sctrl from the cascade-connected flip-flop 88 (see FIG. 9) is input to this other input terminal via the NOT element 93. The OR element 92 outputs to the circuit 77 the logical sum of the clock signal Sclk and a signal obtained by inverting the logic of the control signal Sctrl.

[0074] The circuit element shown in FIG. 14(c) includes a tri-state circuit element 94 and a pull-up resistor 95. In one example, the circuit element consists only of the tri-state circuit element 94 and the pull-up resistor 95. The pull-up resistor 95 is connected between the output terminal of the circuit element 94 and the power supply voltage Vdd. Note that this circuit element may have a pull-down resistor connected between the output terminal of the circuit element 94 and a reference potential (ground potential) instead of or in addition to the pull-up resistor 95. With any of the configurations shown in FIGS. 14(a) to 14(c), it is possible to prevent the level of the clock signal to the circuit 77 from becoming unstable, thereby preventing malfunction of the circuit 77.

[0075] Furthermore, in the above embodiment, an example is shown in which the clock transfer circuit 80 is applied to an image sensor, but the clock transfer circuit 80 is not limited to an image sensor and can be applied to various semiconductor devices.

[0076] Furthermore, in the above embodiment, the clock tree is completed by a plurality of circuit areas 81 having a common circuit pattern, but the clock tree does not necessarily have to be completed only by a plurality of circuit areas 81 having a common circuit pattern. For example, another circuit area that is aligned with the plurality of circuit areas 81 and has a circuit pattern different from that of the plurality of circuit areas 81 may form part of the clock tree. [Explanation of symbols]

[0077] 1... exposure device, 10... light source, 20... photomask, 21... reticle pattern, 30... lens, 40... imaging element, 41 to 43... circuit area, 44... group of circuit areas, 45... pixel array, 46... amplifier array, 47... A / D converter array, 48... memory array, 49... horizontal scanning circuit group, 50... output circuit group, 62... substrate, 70... clock tree, 76... wiring, 77... circuit using clock signal, 78... repeater buffer, 80, 80A, 80B... clock transmission circuit, 81, 81A to 81D... circuit area, 82... clock supply part, 83 to 85... circuit part, 86... wiring, 87... branch wiring, 88... flip-flop, 91...AND element, 92...OR element, 93...NOT element, 94...circuit element, 95...pull-up resistor, 100...clock transmission circuit, 101-104...repeater buffer, 110...circuit area, 211...first part, 212...second part, 213...third part, 421...timing control circuit, 431...bias voltage generation circuit, 451, 461, 471, 481, 491, 501...area, C1...first stage, C2...second stage, C3...third stage (final stage), CLK...clock, D1, D2...direction, Dout...output data, E0-E8...circuit element, F1...clock propagation path, L...light, N1-N3...node, R...resistor, S E0 ,S E1 ...binary signal, Sclk...clock signal, Sctrl...control signal, W...wafer, W1 to W6...wiring.

Claims

1. A signal transmission circuit provided on a single substrate, a plurality of circuit regions each having a common circuit pattern and arranged in one direction; The circuit pattern in each of the plurality of circuit regions is a first circuit element, a second circuit element, and a third circuit element that are switchable between a high impedance state and a passing state; a first wiring portion connecting an output terminal of the first circuit element to an input terminal of the second circuit element and an input terminal of the third circuit element; a second wiring portion for connecting an input terminal of the first circuit element to an output terminal of the second circuit element and to the first wiring portion of the circuit region adjacent to one side; A signal transmission circuit comprising:

2. The circuit pattern in each of the plurality of circuit regions is a fourth circuit element and a fifth circuit element that are switchable between a high impedance state and a passing state; a third wiring portion connecting an input terminal of the fourth circuit element to an output terminal of the third circuit element; a fourth wiring portion connecting an output terminal of the fourth circuit element to an output terminal of the fifth circuit element; a fifth wiring portion for connecting an input end of the fifth circuit element to the third wiring portion of the circuit region adjacent to the one side; The signal transmission circuit according to claim 1 , further comprising:

3. The circuit pattern in each of the plurality of circuit regions is further including a sixth circuit element and a seventh circuit element switchable between a high impedance state and a pass state; 3. The signal transmission circuit according to claim 2, wherein the input terminals of the sixth circuit element and the seventh circuit element are connected to the fourth wiring portion.

4. The circuit pattern in each of the plurality of circuit regions is an eighth circuit element and a ninth circuit element that are switchable between a high impedance state and a passing state; a seventh wiring portion connected to the input terminal of the eighth circuit element; an eighth wiring portion for connecting an output terminal of the eighth circuit element to an input terminal of the ninth circuit element and to the seventh wiring portion of the circuit region adjacent to the one side; Further comprising:

4. The signal transmission circuit according to claim 1, wherein an output terminal of the ninth circuit element is connected to the second wiring portion.

5. A method for manufacturing the signal transmission circuit according to any one of claims 1 to 4, comprising the steps of: A method for manufacturing a signal transmission circuit, comprising the step of forming the plurality of circuit regions by performing splice exposure using a common exposure pattern.

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