Insulative gate bipolar transistor

Abstract

To provide an IGBT (Insulative Gate Bipolar Transistor) which can reduce turn-on power loss and perform screening of a gate insulator.SOLUTION: An insulative gate bipolar transistor comprises: a gate trench 7a which extends in a specified extension direction set in advance in a plane view; a first insulator film 8a which is arranged at a bottom face of the gate trench 7a and at least a part of lateral face; a bottom gate conductive component 9a which is embedded in the gate trench 7a through the first insulator film 8a; a first split insulator film 10a which is arranged on the bottom gate conductive component 9a; an upper gate conductive component 11a which is embedded in the gate trench 7a through the first split insulator film 10a; a gate surface electrode 16 which is overlapped with one end of the gate trench 7a in the extension direction; a first contact hole 13c which electrically connects the gate surface electrode 16 with the bottom gate conductive component 9a; and a second contact hole 13a which electrically connects the gate surface electrode 16 with the upper gate conductive component 11a.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a trench-gate insulated gate bipolar transistor (IGBT). [Background technology]

[0002] Conventionally, trench gate IGBTs can maintain breakdown voltage even when a high-concentration carrier accumulation layer is provided by narrowly arranging the gate trenches. In this case, the density of the gate trenches increases, resulting in an increase in gate charge capacitance Qg. Therefore, by making part of the gate trench a dummy trench connected to the emitter potential, the increase in gate charge capacitance Qg is eliminated. However, by providing a dummy trench, the potential around the gate trench is lowered, and the gate-collector capacitance C GC increases, causing a collector voltage tail, which increases turn-on losses.

[0003] Non-Patent Document 1 proposes a split gate structure in which the electrode in the gate trench is divided into two parts, upper and lower, and the upper electrode is connected to the gate potential and the lower electrode is connected to the emitter potential. GC In addition, in Patent Document 1, the electrode of the dummy trench is divided into two parts, and the upper conductive member is connected to the emitter potential and the lower conductive member is connected to the gate potential, thereby reducing the gate-collector capacitance C GC and the collector-emitter capacitance C CE It is described that the following can be adjusted.

[0004] The lower electrode of the gate trench in Non-Patent Document 1 and the lower conductive portion in Patent Document 1 are connected to the emitter potential, making it difficult to apply a voltage to screen the dielectric strength of the insulating film in the gate trench or dummy trench. Screening during the manufacturing process is possible, but this increases manufacturing costs. In Patent Document 1, the gate electrodes are adjacent to each other, so holes accumulated on the upper surface at turn-on raise the potential, causing a displacement current to flow through the gate electrode. This increases the rate of change of the transient current, di / dt, and increases noise. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2018 / 074427 [Non-patent literature]

[0006] [Non-Patent Document 1] K. Nishi et al., "CSTBT™ based split-gate RC-IGBT with low loss and EMI noise," Proceedings of the 32nd International Symposium on Power Semiconductor Devices & ICs (ISPSD), September 2020, pp. 138-141. Summary of the Invention [Problem to be solved by the invention]

[0007] In view of the above problems, an object of the present invention is to provide an insulated gate bipolar transistor that can reduce turn-on loss and allows screening of the gate insulating film. [Means for solving the problem]

[0008] One aspect of the present invention is an insulated gate bipolar transistor comprising: a gate trench extending in a predetermined extension direction in a planar view; a first insulating film provided on a bottom surface and at least a portion of a side surface of the gate trench; a bottom gate conductive member embedded in the gate trench with the first insulating film interposed therebetween; a first divided insulating film provided on the bottom gate conductive member; an upper gate conductive member embedded in the gate trench with the first divided insulating film interposed therebetween; a gate surface electrode overlapping one end of the gate trench in the extension direction; a first contact hole electrically connecting the gate surface electrode and the bottom gate conductive member; and a second contact hole electrically connecting the gate surface electrode and the upper gate conductive member. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an insulated gate bipolar transistor that can reduce turn-on loss and enable screening of the gate insulating film. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic plan view showing an example of an IGBT according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a perspective schematic view including a cross section seen from the direction of line AA in FIG. [Figure 3] FIG. 2 is a schematic cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 3 is a schematic cross-sectional view taken along line CC in FIG. 2. [Figure 5] FIG. 3 is a diagram showing an example of a turn-on waveform of the IGBT according to the first embodiment. [Figure 6] 4 is a diagram showing an example of a potential distribution around the gate trench during turn-on of the IGBT according to the first embodiment. FIG. [Figure 7] FIG. 1 is a schematic cross-sectional view showing an example of an IGBT of a comparative example. [Figure 8] FIG. 10 is a diagram showing an example of a turn-on waveform of an IGBT of a comparative example. [Figure 9]FIG. 10 is a diagram showing an example of a potential distribution around a gate trench during turn-on of an IGBT of a comparative example. [Figure 10] FIG. 2 is a schematic plan view showing an example of an IGBT according to a first modified example of the first embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view taken along line DD in FIG. [Figure 12] 11 is a schematic cross-sectional view taken along the line EE in FIG. 10. [Figure 13] FIG. 10 is a schematic plan view showing an example of an IGBT according to a second modified example of the first embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view taken along the line FF in FIG. [Figure 15] FIG. 14 is a schematic cross-sectional view taken along line GG in FIG. [Figure 16] FIG. 10 is a schematic cross-sectional view showing an example of an IGBT according to a second embodiment. [Figure 17] FIG. 10 is a schematic plan view illustrating an example of an IGBT according to a third embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view taken along line HH in FIG. 17. [Figure 19] FIG. 18 is a schematic cross-sectional view taken along line II in FIG. 17. [Figure 20] 18 is a schematic cross-sectional view taken along line JJ in FIG. 17. [Figure 21] FIG. 11 is a schematic cross-sectional view showing an example of a connection between a trench and a diode of an IGBT according to a third embodiment. [Figure 22] FIG. 10 is a diagram showing an example of a turn-on waveform of the IGBT according to the third embodiment. [Figure 23] FIG. 10 is a diagram showing an example of a turn-off waveform of the IGBT according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0012] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical concept of the present invention. For example, if an object is rotated 90 degrees and observed, up and down are read as left and right, and if it is rotated 180 degrees and observed, up and down are read as reversed. The following description will exemplify a case in which the first conductivity type is n-type and the opposite second conductivity type is p-type. However, the conductivity types may be reversed, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, + or - appended to n or p indicates a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without a + or - appended. However, semiconductor regions with the same n and n appended do not necessarily have the exact same impurity concentration.

[0013] (First embodiment) FIG. 1 is a plan view schematically illustrating trenches (7a, 7b) disposed in an active region of an IGBT according to a first embodiment of the present invention. As shown in FIG. 1, the trenches (7a, 7b) are composed of striped gate trenches 7a and striped dummy trenches 7b arranged side by side on both sides of the gate trenches 7a in a plan view. While the gate trenches 7a and dummy trenches 7b are alternately arranged in FIG. 1, this arrangement is not limiting. For example, one or more dummy trenches 7b may be arranged side by side between adjacent gate trenches 7a. Each gate trench 7a has an upper gate conductive member 11a connected to a gate surface electrode 16 via a wiring layer 12a and a contact hole 13a. A bottom gate conductive member 9a separated from the upper gate conductive member 11a by a dividing insulating film 10a is exposed at the tip of each gate trench 7a in the depth direction. Each dummy trench 7b has an upper dummy conductive member 11b connected to an emitter surface electrode 15 via a wiring layer 12b and a contact hole 13b. At the tip of the dummy trench 7b in the depth direction, a bottom dummy conductive member 9b separated from the upper dummy conductive member 11b by a dividing insulating film 10b is exposed. The bottom gate conductive member 9a and the bottom dummy conductive member 9b are connected to the gate surface electrode 16 via a wiring layer 12c and a contact hole 13c. Although not shown, a gate pad electrically connected to an external gate drive circuit or the like may be disposed at the end of the active portion. Also, a peripheral portion having a voltage-resistant structure may be provided around the active portion.

[0014] FIG. 2 is a cross-sectional view taken in a direction perpendicular to the direction in which the trenches (7a, 7b) extend in parallel, as viewed from an oblique direction. As shown in FIG. 2, - A base region 5 of the second conductivity type (p type) is disposed on the drift layer 3 of the second conductivity type (p type). +An n-type emitter region 6 is provided. An n-type accumulation layer 4 having a higher impurity concentration than the drift layer 3 is provided below the base region 5. Trenches (7a, 7b) are provided from the upper surface of the emitter region 6 through the base region 5 and the accumulation layer 4. The emitter region 6, the base region 5, and the accumulation layer 4 contact the respective side surfaces of the trenches (7a, 7b), and are also in contact with a part of the drift layer 3. The trenches (7a, 7b) extend from the emitter region 6 through the base region 5 and the accumulation layer 4 to reach the drift layer 3. Dummy trenches 7b are provided on both sides of the gate trench 7a so as to face each other with the emitter region 6, the base region 5, and the accumulation layer 4 sandwiched therebetween. An n-type accumulation layer 4 having a higher impurity concentration than the base region 5 is provided above the base region 5. + Mold contact regions 25 are also provided. The contact regions 25 are provided alternately with the emitter regions 6 in the direction in which the trenches (7a, 7b) extend in parallel.

[0015] 2, a gate insulating film 8a is provided on the bottom and side surfaces of the gate trench 7a. Split gate electrodes (9a, 11a) are buried inside the gate trench 7a with the gate insulating film 8a interposed therebetween. The gate electrodes (9a, 11a) are formed by a bottom gate conductive member 9a provided at the bottom of the gate trench 7a and a split insulating film on the bottom gate conductive member 9a. The dummy trench 7b is composed of an upper gate conductive member 11a provided with a split insulating film 10a interposed therebetween. A dummy insulating film 8b is provided on the bottom and side surfaces of the dummy trench 7b. Split dummy electrodes (9b, 11b) are embedded inside the dummy trench 7b with the dummy insulating film 8b interposed therebetween. The dummy electrodes (9b, 11b) are composed of a bottom dummy conductive member 9b provided at the bottom of the dummy trench 7b and an upper dummy conductive member 11b provided on the bottom dummy conductive member 9b with the split insulating film 10b interposed therebetween. The lower surfaces of the upper gate conductive member 11a and the upper dummy conductive member 11b are located below the level of the lower surface of the base region 5. The upper surfaces of the bottom gate conductive member 9a and the bottom dummy conductive member 9b are located below the level of the upper surface of the drift layer 3.

[0016] The gate insulating film 8a may be a silicon dioxide (SiO2) film, or a single layer of any one of silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, and bismuth oxide (Bi2O3) film, or a composite film formed by stacking two or more of these films. The division insulating films 10a and 10b may be tetraethoxysilane (TEOS) oxide film or a high-resistance polysilicon film. The gate electrodes (9a, 11a) and dummy electrodes (9b, 11b) may be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of impurities such as phosphorus (P) or boron (B).

[0017] An interlayer insulating film 14 is disposed on each of the upper gate conductive member 11a and the upper dummy conductive member 11b. An emitter surface electrode 15 is provided to cover the interlayer insulating film 14. The emitter surface electrode 15 is in physical contact with the emitter region 6 exposed between the interlayer insulating films 14. The interlayer insulating film 14 is a silicon oxide film (BPSG) doped with boron (B) and phosphorus (P). The interlayer insulating film 14 may be a silicon oxide film (PSG) doped with phosphorus (P), a non-doped SiO2 film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film (BSG) doped with boron (B), or a Si3N4 film. A laminate film of these may also be used. The emitter surface electrode 15 is formed of, for example, nickel silicide (NiSi x ) film, titanium nitride (TiN) film, titanium (Ti) film, aluminum (Al) film, or aluminum-silicon (Al-Si) film.

[0018] The bottom surface of the drift layer 3 is + A field stop layer (FS layer) 2 of the type is arranged, and a p +A molded collector region 1 is disposed on the bottom surface of the collector region 1. A collector backside electrode 17 is disposed on the bottom surface of the collector region 1. As the collector backside electrode 17, for example, a single layer film made of gold (Au) or a metal film laminated in this order of Ti, nickel (Ni), and Au can be used.

[0019] 3 and 4 are schematic cross-sectional views taken along the extension direction of the gate trench 7a and the dummy trench 7b, respectively. The emitter region 6, the contact region 25, the base region 5, and the accumulation layer 4 are omitted from FIGS. 3 and 4. As shown in FIG. 3, the upper gate conductive member 11a and the bottom gate conductive member 9a are insulated by a split insulating film 10a. A wiring layer 12a is provided on the upper surface of the upper gate conductive member 11a. A wiring layer 12c is provided on the upper surfaces of the bottom gate conductive member 9a exposed at one end of the gate trench 7a in the extension direction and the field insulating film 21 provided on the drift layer 3. The wiring layers 12a and 12c are connected to a gate surface electrode 16 electrically connected to a gate potential via contact holes 13a and 13c, respectively. As shown in FIG. 4, the upper dummy conductive member 11b and the bottom dummy conductive member 9b are insulated by a split insulating film 10b. A wiring layer 12b is provided on the upper surface of the upper dummy conductive member 11b. A wiring layer 12c is provided on the upper surface of the bottom dummy conductive member 9b exposed at one end in the extension direction of the dummy trench 7b and on the upper surface of the field insulating film 21 on the drift layer 3. The wiring layer 12b is connected to an emitter surface electrode 15 electrically connected to the emitter potential via a contact hole 13b. The wiring layer 12c is connected to a gate surface electrode 16 electrically connected to the gate potential via a contact hole 13c.

[0020] During operation of the IGBT according to the first embodiment, for example, the emitter front surface electrode 15 is held at ground potential, and a positive voltage is applied to the collector back surface electrode 17. When a positive voltage equal to or greater than a threshold is applied to the gate electrodes (9a, 11a), an inversion layer (channel) is formed on the side surface of the gate trench 7a in the base region 5, turning the IGBT on. The inversion layer is formed on the surface of the base region 5, which contacts the side surface of the gate trench 7a, which is the interface between the base region 5 and the gate insulating film 8a sandwiched between the base region 5 and the upper gate conductive member 11a. In the on-state, a current flows from the collector back surface electrode 17 to the emitter front surface electrode 15 via the collector region 1, the FS layer 2, the drift layer 3, the accumulation layer 4, the inversion layer in the base region 5, and the emitter region 6. When the voltage applied to the gate electrodes (9a, 11a) is less than the threshold, no inversion layer is formed in the base region 5, and therefore no current flows from the collector back surface electrode 17 to the emitter front surface electrode 15.

[0021] In the IGBT according to the first embodiment, the upper dummy conductive members 11b of the dummy trenches 7b are electrically connected to the emitter potential, so that no inversion layer is formed on the surface of the base region 5 that contacts the side surfaces of the dummy trenches 7b. This reduces the density of the gate trenches 7a where the IGBT channels are formed, making it possible to suppress an increase in gate charge capacitance Qg. Furthermore, split electrode structures are embedded in each of the trenches (7a, 7b). The bottom gate conductive members 9a of the gate trenches 7a and the bottom dummy conductive members 9b of the dummy trenches 7b are both electrically connected to the gate potential. This allows for easy screening of dielectric strength tests on the gate insulating film 8a and dummy insulating film 8b provided on the bottom surfaces of the trenches (7a, 7b), where electric field concentration is likely to occur.

[0022] The turn-on characteristics were evaluated for an example of the IGBT according to the first embodiment. FIG. 5 shows the turn-on waveform of the example. As shown in FIG. 5, the gate voltage V between the gate and emitter GE When the IGBT of the example is started by applying a gate current I G flows, charging the gate-emitter capacitance and VGE V GE When the threshold voltage is exceeded, the collector voltage V CE decreases, and the collector current I C begins to flow. Collector current I C When the current is as low as 15A, the collector voltage V CE The time rate of change dv / dt of the collector current I C Even if the current is 150A, the collector voltage V CE The time rate of change dv / dt of the collector voltage V CE 6 shows the potential distribution with respect to the depth distance from the top surface of the emitter region 6 to the bottom of the gate trench 7a around the gate trench 7a when the collector voltage V decreases in 50V intervals. As shown in FIG. 6, the potential rises from around the junction region between the emitter region 6 and the base region 5, becomes almost flat in the accumulation layer 4, and then increases near the bottom of the gate trench 7a in the drift layer 3. CE When the gate voltage V GE Moreover, the potentials around the emitter region 6, the base region 5 and the accumulation layer 4 do not change significantly and remain almost fixed.

[0023] FIG. 7 shows a conventional IGBT having trenches (7a, 7b) in which an integrated electrode structure is embedded, as a comparative example. As shown in FIG. 7, an integrated gate electrode 11c is provided inside the gate trench 7a via a gate insulating film 8a, and an integrated dummy electrode 11d is provided inside the dummy trench 7b via a dummy insulating film 8b. FIG. 8 shows the turn-on waveform of the comparative example. As shown in FIG. 8, the IGBT of the comparative example is started and the gate voltage V GE When the threshold voltage is exceeded, the collector voltage V CE decreases and the collector current I C begins to play. C When the current is as low as 15A, the collector voltage V CE The time rate of change dv / dt of I is almost constant and decreases smoothly. CIf the current is 150A, the collector voltage V CE The time rate of change dv / dt of is not constant in the comparative example, and a voltage tail T occurs. The cause of the voltage tail T is the gate-collector capacitance C GC As shown in Figure 8, the collector current I C is flowing, which increases turn-on losses.

[0024] Figure 9 shows the collector voltage V CE 9 shows the potential distribution around the gate trench 7a when the collector voltage V decreases in 50V intervals. As shown in FIG. 9, the potential distribution in the comparative example also increases near the bottom of the gate trench 7a, similar to the potential distribution in the example shown in FIG. 6, but the potential value is reduced compared to the example. In the comparative example, the dummy electrode 11d of the dummy trench 7b arranged next to the gate trench 7a is connected to the emitter potential, which lowers the potential near the bottom of the gate trench 7a. Also, as shown in FIG. 9, the collector voltage V CE When the gate voltage V drops from 550 V to 300 V, the potential mainly in the vicinity of the bottom of the gate trench 7a drops. GE It will not be lower than V in Figure 9. CE In the range of 250V to 50V, V CE As the potential near the bottom of the gate trench 7a decreases, GE The potential drops below 100 V, and a further drop in the potential also occurs in the n-type semiconductor region from the drift layer 3 to the accumulation layer 4. This large drop in potential in the n-type semiconductor region is due to the gate-collector capacitance C GC That is, as shown in Figure 8, the gate current I G The gate-collector capacitance C GC As a result, the time required for charging increases and a voltage tail T occurs.

[0025] As described above, in the first embodiment, split electrode structures are embedded in each of the trenches (7a, 7b). The upper gate conductive member 11a and the bottom gate conductive member 9a of the gate trench 7a are both electrically connected to the gate potential. The upper dummy conductive member 11b of the dummy trench 7b is electrically connected to the emitter potential, while the bottom dummy conductive member 9b is electrically connected to the gate potential. Therefore, the collector voltage V CE As the potential at the bottom of the gate trench 7a decreases, the potential at the bottom of the gate trench 7a also decreases. However, the potential near the bottom of the gate trench 7a is higher than the gate voltage V GE As a result, the potential drop in the n-type semiconductor region from the drift layer 3 to the accumulation layer 4 can be suppressed, and the collector voltage V CE It is possible to prevent the occurrence of the voltage tail T. In this way, in the IGBT according to the first embodiment, it is possible to reduce the turn-on loss and to perform screening of the gate insulating film.

[0026] (First Modification) As shown in FIG. 10, the IGBT according to the first modification of the first embodiment of the present invention includes stripe-shaped trenches (7a, 7b) arranged alternately in a plan view. The gate trench 7a has an integrated gate electrode 11c connected to a gate surface electrode 16 via a wiring layer 12c and a contact hole 13c. The dummy trench 7b has an upper dummy conductive member 11b and a bottom dummy conductive member 9b divided by a division insulating film 10b. The upper dummy conductive member 11b is connected to an emitter surface electrode 15 via a wiring layer 12b and a contact hole 13b. The bottom dummy conductive member 9b is connected to a gate surface electrode 16 via a wiring layer 12c and a contact hole 13c. As shown in FIG. 11, the trenches (7a, 7b) extend from the emitter region 6 through the base region 5 and the accumulation layer 4 to the drift layer 3. A gate electrode 11c is embedded inside the gate trench 7a via a gate insulating film 8a. Split dummy electrodes (9b, 11b) are buried inside the dummy trench 7b with a dummy insulating film 8b interposed therebetween. An interlayer insulating film 14 is disposed on each of the gate electrode 11c and the upper dummy conductive member 11b. The first modification differs from the first embodiment in that an integrated gate electrode 11c is buried in the gate trench 7a. Other configurations of the IGBT according to the first modification are the same as those of the first embodiment, and therefore redundant explanations will be omitted.

[0027] 12, at one end of the gate trench 7a in the extension direction, a wiring layer 12c is provided in physical contact with the upper surfaces of the gate electrode 11c and the field insulating film 21. The gate electrode 11c is connected to a gate surface electrode 16 electrically connected to a gate potential via the wiring layer 12c and a contact hole 13c. The gate electrode 11c embedded in the gate trench 7a is an integrated type, which simplifies the manufacturing process of the gate electrode structure. As a result, damage to the gate insulating film 8a can be reduced.

[0028] 4, the bottom dummy conductive member 9b embedded in the inner bottom of the dummy trench 7b is connected to the gate surface electrode 16 electrically connected to the gate potential via the wiring layer 12c and the contact hole 13c. This makes it possible to easily perform screening of a dielectric strength test on the gate insulating film 8a and the dummy insulating film 8b provided on the bottom surfaces of the trenches (7a, 7b) where electric field concentration is likely to occur.

[0029] 4, in the IGBT according to the first modification, the upper dummy conductive members 11b of the dummy trenches 7b are electrically connected to the emitter potential. Therefore, no inversion layer is formed on the surface of the base region 5 that contacts the side surfaces of the dummy trenches 7b. This reduces the density of the gate trenches 7a in which the channels of the IGBT are formed, making it possible to suppress an increase in the gate charge capacitance Qg.

[0030] In addition, the upper dummy conductive member 11b of the dummy trench 7b is electrically connected to the emitter potential, but the bottom dummy conductive member 9b is electrically connected to the gate potential. CE Even if the potential near the bottom of the gate trench 7a decreases, the potential near the bottom of the gate trench 7a is equal to the gate voltage V GE As a result, the potential drop in the n-type semiconductor region from the drift layer 3 to the accumulation layer 4 can be suppressed, and the collector voltage V CE Therefore, it is possible to prevent the occurrence of a voltage tail. In this way, the IGBT according to the first modification also makes it possible to reduce turn-on loss.

[0031] (Second Modification) As shown in FIG. 13, the IGBT according to the second modification of the first embodiment of the present invention includes trenches (7a, 7b) arranged alternately in a stripe pattern in a plan view. A gate electrode 11c of the gate trench 7a is connected to a gate surface electrode 16 via a wiring layer 12c and a contact hole 13c. The dummy trench 7b includes an upper buried insulating film 10c and a bottom dummy conductive member 9b. The bottom dummy conductive member 9b is connected to the gate surface electrode 16 via a wiring layer 12c and a contact hole 13c. As shown in FIG. 14, the trenches (7a, 7b) extend from the emitter region 6 through the base region 5 and the accumulation layer 4 to the drift layer 3. An integrated gate electrode 11c is buried inside the gate trench 7a via a gate insulating film 8a. An upper buried insulating film 10c is buried on the top of the dummy trench 7b via a dummy insulating film 8b, and a bottom dummy conductive member 9b is buried below the upper buried insulating film 10c. The lower surface of the upper buried insulating film 10c is located below the level of the lower surface of the base region 5. A TEOS oxide film, a high-resistance polysilicon film, or the like can be used as the upper buried insulating film 10c. An interlayer insulating film 14 is disposed on each of the gate electrode 11c and the upper buried insulating film 10c. The second modification differs from the first modification in that the upper buried insulating film 10c and the bottom dummy conductive member 9b are buried in the dummy trench 7b. The other configurations of the IGBT according to the second modification are the same as those of the first modification, so a duplicated description will be omitted.

[0032] As shown in FIG. 15, at one end of the dummy trench 7b in the extension direction, a wiring layer 12c is provided in physical contact with the top surfaces of the bottom dummy conductive member 9b and the field insulating film 21. The bottom dummy conductive member 9b is connected to a gate surface electrode 16 electrically connected to the gate potential via the wiring layer 12c and the contact hole 13c. The gate trench 7a is similar to the first modification shown in FIG. 12, and the embedded integrated gate electrode 11c is electrically connected to the gate potential. This simplifies the manufacturing process of the gate electrode structure and reduces damage to the gate insulating film 8a. Furthermore, it becomes possible to easily perform screening for a dielectric strength test on the gate insulating film 8a and dummy insulating film 8b provided on the bottom surfaces of the trenches (7a, 7b) where electric field concentration is likely to occur.

[0033] In the IGBT according to the second modification, the upper buried insulating film 10c of the dummy trench 7b is at a floating potential. Therefore, an inversion layer is not formed on the surface of the base region 5 that contacts the side surface of the dummy trench 7b. This reduces the density of the gate trenches 7a in which the channel of the IGBT is formed, making it possible to suppress an increase in the gate charge capacitance Qg. In addition, the bottom dummy conductive member 9b is electrically connected to the gate potential. Therefore, the collector voltage V CE Even if the potential near the bottom of the gate trench 7a decreases, the potential near the bottom of the gate trench 7a is equal to the gate voltage V GE As a result, the potential drop in the n-type semiconductor region from the drift layer 3 to the accumulation layer 4 can be suppressed, and the collector voltage V CE Therefore, it is possible to prevent the occurrence of a voltage tail. In this way, the IGBT according to the second modification also makes it possible to reduce turn-on loss.

[0034] (Second embodiment) As shown in FIG. 16 , the IGBT according to the second embodiment of the present invention includes trenches (7a, 7b) arranged alternately, similar to the first modification of the first embodiment. A gate electrode 11c is embedded inside the gate trench 7a with a gate insulating film 8a interposed therebetween, and split dummy electrodes (9b, 11b) are embedded inside the dummy trench 7b with a dummy insulating film 8b interposed therebetween. In the second embodiment, as shown in FIG. 16 , a p-type trench-bottom floating layer 20 is provided above the n-type drift layer 3. The trenches (7a, 7b) extend from the emitter region 6 through the base region 5 and the accumulation layer 4 to reach the trench-bottom floating layer 20. The upper surface of the trench-bottom floating layer 20 is located a distance S above the level of the lower surface of the upper dummy conductive member 11b of the dummy trench 7b. That is, the trench-bottom floating layer 20 and the upper dummy conductive member 11b overlap with each other at the distance S. 2 and 3 may be embedded in the gate trench 7a instead of the gate electrode 11c. The second embodiment differs from the first modification of the first embodiment in that a trench bottom floating layer 20 is provided above the drift layer 3. Other configurations of the IGBT according to the second embodiment are the same as those of the first modification of the first embodiment, and therefore redundant explanations will be omitted.

[0035] Without the p-type trench bottom floating layer, the collector voltage V CE The time rate of change dv / dt of the collector current I C The larger the collector current, the slower it becomes. To suppress noise generation, it is necessary to suppress the time rate of change dv / dt. C When the time rate of change dv / dt is small, if it is kept to a specified value, the collector current I CWhen is large, the time rate of change dv / dt is suppressed, and the turn-on loss increases. In the second embodiment, a p-type trench bottom floating layer 20 is provided that overlaps the upper dummy conductive member 11b of the dummy trench 7b at a distance S. At the time of turn-on, holes accumulate around the upper dummy conductive member 11b that is electrically connected to the emitter potential, and the trench bottom floating layer 20 is electrically connected to the emitter potential via the accumulated holes. As a result, the gate-collector capacitance C GC becomes constant, and the collector current I C Dependence on is reduced.

[0036] In this way, according to the IGBT of the second embodiment, the collector voltage V CE The collector current I with a time rate of change dv / dt C This reduces the dependence on the gate electrode 11c, thereby making it possible to suppress an increase in turn-on loss. Other effects of the IGBT according to the second embodiment are similar to those of the IGBT according to the first modification of the first embodiment. As described above, in the second embodiment, the integrated gate electrode 11c is used as the electrode structure embedded in the gate trench 7a, but this is not limited thereto. For example, the split gate electrode (9a, 11a) shown in FIG. 2 may be used as the electrode structure embedded in the gate trench 7a.

[0037] (Third embodiment) As shown in FIG. 17 , the IGBT according to the third embodiment of the present invention includes alternating stripe-shaped trenches (7a, 7b) arranged side by side in a plan view, similar to the second modification of the first embodiment. A dummy surface electrode 18 is disposed between the emitter surface electrode 15 and the gate surface electrode 16a, and a gate electrode pad 19 is disposed spaced apart from the gate surface electrode 16a. A gate electrode 11c in the gate trench 7a is connected to the gate surface electrode 16a via a wiring layer 12d and a contact hole 13d. A bottom dummy conductive member 9b in the dummy trench 7b is connected to the gate surface electrode 16a via a wiring layer 12e and a contact hole 13e. As shown in FIG. 18 , an integrated gate electrode 11c is buried inside the gate trench 7a via a gate insulating film 8a. An upper buried insulating film 10c is buried on top of the dummy trench 7b via a dummy insulating film 8b, and a bottom dummy conductive member 9b is buried below the upper buried insulating film 10c. Furthermore, as shown in FIG. 17 , the IGBT according to the third embodiment includes a diode 22 and a resistor 24. The diode 22 is disposed between the dummy surface electrode 18 and the gate surface electrode 16a in correspondence with each of the dummy trenches 7b. The resistor 24 is disposed between the gate surface electrode 16a and the gate electrode pad 19. The anode region 22a of the diode 22 is electrically connected to the gate surface electrode 16a via a contact hole 23a. The cathode region 22b is electrically connected to the dummy surface electrode 18 via a contact hole 23b. One end of the resistor 24 is electrically connected to the gate surface electrode 16a via a contact hole 23c, and the other end is electrically connected to the gate electrode pad 19 via a contact hole 23d. Other configurations of the IGBT according to the third embodiment are similar to those of the second modification of the first embodiment, and therefore, redundant description will be omitted.

[0038] As shown in FIG. 19, at one end of the gate trench 7a in the extension direction, a wiring layer 12d is provided in physical contact with the upper surfaces of the gate electrode 11c and the field insulating film 21. The interlayer insulating film 14 is composed of a first interlayer insulating film 14a covering the wiring layer 12d and a second interlayer insulating film 14b provided on the first interlayer insulating film 14a. The wiring layer 12d is electrically connected to the gate surface electrode 16a via a contact hole 13d that penetrates the first and second interlayer insulating films 14a and 14b. As shown in FIG. 20, at one end of the dummy trench 7b in the extension direction, a wiring layer 12e is provided in physical contact with the upper surfaces of the bottom dummy conductive member 9b and the field insulating film 21. The bottom dummy conductive member 9b is electrically connected to the dummy surface electrode 18 via a contact hole 13e that penetrates the first and second interlayer insulating films 14a and 14b.

[0039] As shown in FIG. 20 , the diode 22 is provided between the first and second interlayer insulating films 14a and 14b. The anode region 22a of the diode 22 is electrically connected to the gate surface electrode 16a through a contact hole 23a provided in the second interlayer insulating film 14b. The cathode region 22b is electrically connected to the dummy surface electrode 18 through a contact hole 23b provided in the second interlayer insulating film 14b. The resistive element 24 is provided on the upper surface of the field insulating film 21. One end and the other end of the resistive element 24 are electrically connected to the gate surface electrode 16a and the gate electrode pad 19 through contact holes 23c and 23d that penetrate the first and second interlayer insulating films 14a and 14b, respectively. The anode region 22a and the cathode region 22b of the diode 22 are formed using low-impurity-concentration doped polysilicon layers into which p-type impurities and n-type impurities are ion-implanted, respectively. A doped polysilicon layer is used for the resistive element 24, and the resistance value is controlled by the width of the doped polysilicon layer. Although the resistive element 24 is used to control the turn-on time, a wiring layer made of a doped polysilicon layer with a high impurity concentration may be disposed instead of the resistive element 24.

[0040] 21 schematically shows the connection of the gate electrode 11c and bottom dummy conductive member 9b of the trenches (7a, 7b) to a diode 22 and a resistor 24. As shown in Fig. 21, the gate electrode 11c of the gate trench 7a is electrically connected to the gate potential applied to the gate electrode pad 19 via the resistor 24. The bottom dummy conductive member 9b of the dummy trench 7b is electrically connected to the gate potential via the resistor 24 and the diode 22.

[0041] In Figures 22 and 23, the collector current I C 22 shows the turn-on and turn-off waveforms of the IGBT according to the third embodiment, with a collector voltage V of about 100 A. As an example, the gate electrode 11c of the gate trench 7a and the bottom dummy conductive member 9b of the dummy trench 7b are shown. As a comparative example, an IGBT having a dummy electrode 11d integrated into the dummy trench 7b as shown in FIG. 7 is used. As shown in FIG. 22, in the example, the collector voltage V CE The time rate of change dv / dt of the gate voltage V corresponding to the gate trench 7a in the example and the comparative example is decreasing almost constantly, but in the comparative example, it is not constant and a voltage tail T occurs. GE In the waveform of GE On the other hand, the gate voltage V GE In the waveform of , the bottom dummy conductive member 9b is connected to the diode 22, so the turn-on operation starts from 0V. As shown in FIG. 23, the collector voltage V CE With the rise of collector current I C In the example and comparative example corresponding to the gate trench 7a, the gate voltage V GE On the other hand, in the example corresponding to the dummy trench 7b, the gate voltage V GE The gate voltage V of the bottom dummy conductive member 9b rises sharply in a time period D from 0.03 μs to 0.07 μs after the cutoff, and then gradually drops. GEEven if the potential drops, the diode 22 is in a reverse bias state, so no current flows, and the potential around the dummy trench 7b does not drop. Even when the IGBT is in an off state, the potential around the dummy trench 7b is maintained, so when the IGBT is subsequently turned on, the gate current I G The gate voltage V shown in Figure 23 hardly flows, and the gate charge capacitance Qg can be reduced. GE The sudden rise in the gate voltage V is caused by a displacement current due to a sudden change in the potential around the dummy trench 7b. GE In order to prevent the gate voltage V from becoming too high in the time period D, it is necessary to determine the breakdown voltage of the diode 22 by controlling the impurity concentrations of the anode region 22a and the cathode region 22b. For example, GE In order to prevent the voltage drop from exceeding 20 V, the withstand voltage of the diode 22 should be set to about 35 V. Other effects of the IGBT according to the third embodiment are similar to those of the IGBT according to the second modification of the first embodiment.

[0042] (Other embodiments) Although the present invention has been described by the above disclosed embodiments, the descriptions and drawings forming part of this disclosure should not be understood as limiting the present invention. It should be understood that various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0043] In the above first and second embodiments, silicon (Si) is used as the material of the semiconductor substrate, but the semiconductor material is not limited thereto and may be a wide bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0044] As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined only by the invention-specifying matters related to the scope of the claims that are appropriate from the above explanation. [Explanation of symbols]

[0045] 1 Collector region 2. Field stop layer (FS layer) 3 Drift layer 4 Accumulation layer 5 Base Area 6 Emitter Area 7a Gate trench 7b Dummy Trench 8a Gate insulating film 8b Dummy insulating film 9a bottom gate conductive member (9a, 11a), 11c Gate electrode 9b Bottom dummy conductive member (9b, 11b), 11d Dummy electrodes 10a, 10b Dividing insulating film 10c Upper buried insulating film 11a Upper gate conductive member 11b Upper dummy conductive member 12a,12b,12c,12d,12e wiring layer 13a, 13b, 13c, 13d, 13e, 23a, 23b, 23c, 23d Contact holes 14, (14a, 14b) Interlayer insulating film 14a First interlayer insulating film 14b Second interlayer insulating film 15 Emitter surface electrode 16,16a Gate surface electrode 17 Collector back electrode 18 Dummy surface electrode 19 Gate electrode pad 20 Trench bottom floating layer 22 Diode 22a Anode region 22b Cathode region 24 Resistive element

Claims

1. a gate trench extending in a predetermined extension direction in a plan view; a first insulating film provided on a bottom surface and at least a part of a side surface of the gate trench; a bottom gate conductive member embedded in the gate trench via the first insulating film; a first dividing insulating film disposed on the bottom gate conductive member; an upper gate conductive member embedded in the gate trench via the first dividing insulating film; a gate surface electrode overlapping one end of the gate trench in the extension direction; a first contact hole electrically connecting the gate surface electrode and the bottom gate conductive member; a second contact hole electrically connecting the gate surface electrode and the upper gate conductive member; An insulated gate bipolar transistor comprising:

2. The second contact hole is provided separately from the first contact hole.

2. The insulated gate bipolar transistor according to claim 1.

3. a dummy trench extending in the extension direction in a plan view; a second insulating film provided on a bottom surface and at least a part of a side surface of the dummy trench; a bottom dummy conductive member buried in the dummy trench via the second insulating film; a second dividing insulating film provided on the bottom dummy conductive member; a third contact hole electrically connecting the bottom dummy conductive member to the gate surface electrode; Furthermore, The third contact hole is provided at a position adjacent to the first contact hole.

2. The insulated gate bipolar transistor according to claim 1.

4. The third contact hole is connected to the first contact hole.

4. The insulated gate bipolar transistor according to claim 3.

5. an upper dummy conductive member buried in the dummy trench via the second dividing insulating film; an emitter surface electrode; a fourth contact hole electrically connecting the upper dummy conductive member and the emitter surface electrode; Furthermore, The fourth contact hole is provided inward of the gate surface electrode in the extension direction in a plan view.

4. The insulated gate bipolar transistor according to claim 3.

6. In the extending direction, the second contact hole is located between the first contact hole and the fourth contact hole.

6. The insulated gate bipolar transistor according to claim 5.

7. The gate trenches and the dummy trenches are provided alternately.

4. The insulated gate bipolar transistor according to claim 3.

8. a drift layer of a first conductivity type; a second conductivity type base region provided on the drift layer; an emitter region of a first conductivity type provided on an upper surface of the base region and having a higher impurity concentration than the drift layer; a second conductivity type contact region having a higher impurity concentration than the base region, the second conductivity type contact region being provided on an upper surface of the base region to a depth deeper than the emitter region; an accumulation layer of a first conductivity type provided between the base region and the drift layer; Further equipped 2. The insulated gate bipolar transistor according to claim 1.

9. The emitter regions and the contact regions are alternately provided in the extension direction.

9. The insulated gate bipolar transistor according to claim 8.

10. a field stop layer of a first conductivity type provided on a lower surface of the drift layer and having a higher impurity concentration than the drift layer; a collector region of a second conductivity type provided on a lower surface of the field stop layer; a collector back surface electrode provided on a lower surface of the collector region; Further equipped 9. The insulated gate bipolar transistor according to claim 8.

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