Semiconductor device

Abstract

To configure a buffer circuit, an inverter circuit and the like by using only an n-channel TFT that uses an oxide semiconductor layer.SOLUTION: A buffer circuit, an inverter circuit and the like are configured by combining: a first transistor in which both of a source electrode and a drain electrode overlap a gate electrode; and a second transistor in which the source electrode overlaps the gate electrode and the drain electrode does not overlap the gate electrode. By configuring the second transistor as above, capacitance Cp can be reduced and large VA' can be obtained even when potential difference VDD-VSS is small.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] Thin film transistors (TFTs) are fabricated using semiconductor thin films formed on substrates with insulating surfaces. Thin-film transistors are used in devices such as ICs and electro-optical devices. It is widely used in electronic devices, especially in image display devices (liquid crystal display devices and EL display devices). It is used as an etching element.

[0004] Thin film transistors are used as switching elements in image display devices (liquid crystal display devices and EL display devices). The display device used in this way is called an active matrix display device, and its advantage is that the pixel part As a driving circuit for transmitting a signal to the The advantage is that it is possible to form circuits such as transistors and transistor paths using TFTs on the same insulator.

[0005] However, the manufacturing process of TFTs in active matrix display devices is complicated. This had the problem of high manufacturing costs. Therefore, if the manufacturing process becomes complicated, it becomes difficult to ensure a high yield. If there is a defect, it may cause a line defect in which a row of pixels does not work.

[0006] Patent Document 1 discloses a technology for forming pixel sections and driver circuits entirely from n-channel transistors. It has been done.

[0007] In addition, it is not limited to display devices, but also includes inverter circuits (logical negation circuits) and buffer circuits. By combining these techniques, various semiconductor integrated circuits such as LSI can be produced. The inverter circuit and buffer circuit are made up of a combination of n-channel and p-channel TFTs. It is composed of a CMOS circuit that combines [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-49333 Summary of the Invention [Problem to be solved by the invention]

[0009] Buffer circuits, inverter circuits, etc. are made using only n-channel TFTs with oxide semiconductor layers. One of the challenges is to create a [Means for solving the problem]

[0010] When configuring a buffer circuit or inverter circuit using only n-channel TFTs, When constructing a buffer circuit or an inverter circuit, a technique called a test trap is used. The output section used is shown in Figure 1(A).

[0011] In FIG. 1A, the gate electrode of the first transistor 301 is electrically connected to the control unit 304. The gate electrode of the second transistor 302 is also electrically connected to the control unit 304. In addition, the gate electrode of the second transistor 302 and one of the electrodes are electrically connected to each other. has a capacitance 303, and the other electrode of this capacitance is the source electrode of the second transistor 302 and is electrically connected thereto.

[0012] The bootstrap circuit is configured as the circuit shown in FIG. 1(A) so that OUT does not become smaller than VDD when the output becomes high. FIGS. 1(B) and 1( C) show how the potential of node A in FIG. 1(A) changes due to the bootstrap circuit. At this time, V ’ can be obtained by the following formula. A ’ can be obtained by the following equation.

[0013] [Equation]

[0014] When using a circuit as shown in FIG. 1(A), it is important to reduce the capacitance Cp. In particular, when the potential difference VDD-VSS is small, a very large capacitance C is required so that V ’ < VDD. When a circuit is configured using transistors with an oxide semiconductor, depending on the transistor structure, the capacitance Cp may increase. In a transistor with a large capacitance Cp structure, there are problems such as difficulty in operating the circuit, a small margin, and inability to obtain desired frequency characteristics (also referred to as f characteristics). A ’ < VDD. When using a transistor with an oxide semiconductor to form a circuit, depending on the transistor structure, the capacitance Cp may increase. In a transistor with a large capacitance Cp structure, there are problems such as difficulty in operating the circuit, a small margin, and inability to obtain desired frequency characteristics (also referred to as f characteristics). When using a transistor with an oxide semiconductor to form a circuit, depending on the transistor structure, the capacitance Cp may increase. In a transistor with a large capacitance Cp structure, there are problems such as difficulty in operating the circuit, a small margin, and inability to obtain desired frequency characteristics (also referred to as f characteristics). When using a transistor with an oxide semiconductor to form a circuit, depending on the transistor structure, the capacitance Cp may increase. In a transistor with a large capacitance Cp structure, there are problems such as difficulty in operating the circuit, a small margin, and inability to obtain desired frequency characteristics (also referred to as f characteristics). When using a transistor with an oxide semiconductor to form a circuit, depending on the transistor structure, the capacitance Cp may increase. In a transistor with a large capacitance Cp structure, there are problems such as difficulty in operating the circuit, a small margin, and inability to obtain desired frequency characteristics (also referred to as f characteristics). (also called f characteristics) cannot be obtained.

[0015] When using a transistor with an oxide semiconductor, if the source electrode overlaps the gate electrode and the drain electrode also overlaps the gate electrode, the capacitance Cp will increase. Therefore, if the transistor structure is such that both the source electrode and the drain electrode do not overlap the gate electrode, the on-current will decrease. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current is significantly reduced. When using a transistor with an oxide semiconductor, if the source electrode overlaps the gate electrode and the drain electrode also overlaps the gate electrode, the capacitance Cp will increase. Therefore, if the transistor structure is such that both the source electrode and the drain electrode do not overlap the gate electrode, the on-current will decrease. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current is significantly reduced. When using a transistor with an oxide semiconductor, if the source electrode overlaps the gate electrode and the drain electrode also overlaps the gate electrode, the capacitance Cp will increase. Therefore, if the transistor structure is such that both the source electrode and the drain electrode do not overlap the gate electrode, the on-current will decrease. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current is significantly reduced. When using a transistor with an oxide semiconductor, if the source electrode overlaps the gate electrode and the drain electrode also overlaps the gate electrode, the capacitance Cp will increase. Therefore, if the transistor structure is such that both the source electrode and the drain electrode do not overlap the gate electrode, the on-current will decrease. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current is significantly reduced. It will decrease.

[0016] In one embodiment of the present invention, the gate electrode of the second transistor 302 in the circuit of FIG. One end face is connected to the source electrode of the second transistor 302 and the drain electrode of the second transistor 302. The other end of the gate electrode is formed at a position overlapping the gap of the drain electrode. By configuring the second transistor in this way, the capacitance Cp Even if the potential difference VDD-VSS is small, V A ' can be taken larger.

[0017] One aspect of the present invention is a first transistor and a drain electrode of the first transistor electrically connected to the drain electrode of the first transistor. a second transistor having a source electrode connected to the first transistor, and a gate electrode of the second transistor and one of the first transistors; and a capacitor to which the electrode of the second transistor is electrically connected, and the other electrode of the capacitor is connected to the second transistor. The gate electrode of the first transistor is electrically connected to the source electrode of the second transistor. The source electrode and the drain electrode of the first transistor overlap through the second transistor. The gate electrode of the first transistor overlaps with the source electrode of the second transistor via the gate insulating layer. One end face of the gate electrode of the first transistor is connected to the source electrode of the second transistor. The gap between the drain electrodes of the first and second transistors overlaps the gap. The transistor is a semiconductor device characterized by being an n-channel transistor.

[0018] In addition, the parasitic capacitance of the second transistor 302 can be used in place of the capacitor 303. In this case, the capacitor 303 does not need to be provided separately.

[0019] In the case where the capacitor 303 is not provided, in one embodiment of the present invention, a second transistor whose source electrode is electrically connected to the drain electrode of the first transistor; The gate electrode of the first transistor is connected to the source electrode of the second transistor through the gate insulating layer. and the drain electrode of the second transistor overlaps with the gate electrode of the first transistor through the gate insulating layer. The source electrode of the second transistor overlaps with one end of the gate electrode of the second transistor. The surface overlaps with the gap between the source electrode of the second transistor and the drain electrode of the second transistor. The first transistor and the second transistor are n-channel transistors. The semiconductor device is characterized by the above.

[0020] In the above structure, the semiconductor layer of the first transistor and the semiconductor layer of the second transistor are It is preferable that the alloy contains at least indium (In) or zinc (Zn). Furthermore, it is preferable that the oxide semiconductor contains Zn. In addition, it contains gallium (Ga) as a stabilizer to reduce variations. It is also preferable to have tin (Sn) as a stabilizer. It is also preferable to have hafnium (Hf) as a stabilizer. It is preferable to have aluminum (Al) as the riser.

[0021] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0022] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. You can be there.

[0023] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0024] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having an atomic ratio or an oxide having a composition close to that. [Effects of the Invention]

[0025] Buffer circuits can be configured using only n-channel transistors, allowing for low-voltage This allows the semiconductor circuit to be driven with low power consumption. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 2] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] FIG. 10 is a diagram illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 5] FIG. 10 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 6] FIG. 10 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 7] FIG. 10 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 8] FIG. 10 illustrates a cross-sectional structure of a transistor used in calculation. [Figure 9] 1A to 1C illustrate a structure of an oxide material according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a structure of an oxide material according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate a structure of an oxide material according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0028] (Embodiment 1) In this embodiment, it corresponds to an output section used when configuring a buffer circuit or an inverter circuit. An example of the circuit and its configuration will be described with reference to FIGS. 1(A), 2(A), and 2(B). do.

[0029] The circuit shown in FIG. 1A includes a first transistor 301 and a drain a second transistor 302 having a source electrode electrically connected to the second electrode; The gate electrode of the capacitor 303 is electrically connected to one of the electrodes of the capacitor 303. The other electrode is electrically connected to the source electrode of the second transistor 302 .

[0030] 2B is a top view of the second transistor 302. FIG. 10 is a cross-sectional view corresponding to the dashed line AB in (B).

[0031] As shown in FIG. 2B, the drain electrode 315 of the second transistor The position of one end face of the gate electrode 310 of the gate electrode is set so as not to overlap with the gate electrode 310 of the gate electrode. The second transistor source electrode 314 and the second transistor drain electrode 315 The gap between the end face of the gate electrode 310 of the second transistor and the drain electrode 315 is The distance in the channel length direction at this point is expressed as Loff in Figure 2(B). The longer it is, the smaller the Cp of the capacitance 305 becomes.

[0032] As shown in FIG. 2B, the source electrode 314 of the second transistor The gate electrode 310 of the first transistor overlaps the gate electrode 310 of the second transistor. The distance in the channel length direction from the source electrode 314 to the source electrode 314 is Lov (also called overlap length). 2B. In addition, the source electrode 31 The protrusion of 4 (or the drain electrode 315) is called dW.

[0033] A manufacturing process of the second transistor 302 using an oxide semiconductor will be described below.

[0034] First, an insulating layer serving as a base layer is formed on the substrate 300 to a thickness of 50 nm to 300 nm, preferably 1 The substrate 300 is formed to a thickness of 00 nm or more and 200 nm or less. In addition to the substrate, a plastic substrate or the like that has heat resistance enough to withstand the processing temperature of this manufacturing process is also used. In addition, when the substrate does not need to be transparent, a metal such as a stainless steel alloy can be used. A substrate or a semiconductor substrate having an insulating layer on its surface may also be used.

[0035] The underlayer is made of aluminum nitride, aluminum oxynitride, silicon nitride, silicon oxide, or nitride. A laminated structure of one or more insulating layers selected from silicon oxide or silicon oxynitride. This has the function of preventing the diffusion of impurity elements from the substrate 300. The underlayer does not necessarily have to be provided.

[0036] Next, a layer of 100 nm or less is formed on the underlayer using sputtering, vacuum deposition, or plating. A conductive layer is formed to a thickness of 500 nm or less, preferably 200 nm or more and 300 nm or less, A resist mask is formed by a first photolithography process, and the conductive layer is selectively etched. The film is then removed to form the gate electrode 310.

[0037] The conductive layer for forming the gate electrode 310 is made of molybdenum (Mo), titanium (Ti), or titanium. W, Tantalum (Ta), Aluminum (Al), Copper (Cu), Chromium (Cr ), neodymium (Nd), scandium (Sc), or other metallic materials, or alloys containing these as the main components. The gold material can be used to form a single layer or a multilayer.

[0038] Since the conductive layer will be used as wiring, it is preferable to use low resistance materials such as Al and Cu. By using u, it is possible to reduce signal delay and achieve high image quality. It has low heat resistance and is prone to defects due to hillocks, whiskers, or migration. To prevent Al migration, Mo, Ti, W, and other metals are added to Al. It is preferable to use a metal material with a high melting point. Also, a material containing Al is used for the conductive layer. In this case, it is preferable to set the maximum process temperature in the subsequent steps to 380°C or less. It is recommended to keep the temperature below 350°C.

[0039] Next, a gate insulating layer 308 is formed on the gate electrode 310 to a thickness of preferably 5 nm to 300 nm. The gate insulating layer 308 is formed to a thickness of 10 nm or more and 200 nm or less. Silicon oxide nitride, silicon oxide nitride, aluminum oxide, aluminum oxide nitride , aluminum oxide nitride, tantalum oxide, gallium oxide, yttrium oxide, hafnium oxide Hafnium, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen was introduced Hafnium silicate, hafnium aluminate with nitrogen introduced, etc. can be used. The gate insulating layer can be formed by a plasma CVD method, a sputtering method, or the like. The layer 308 is not limited to a single layer, but may be a laminate of different layers.

[0040] Next, a method for forming an oxide semiconductor layer is performed so that hydrogen, a hydroxyl group, and moisture are not contained in the oxide semiconductor layer as much as possible. In order to do this, as a pretreatment for forming the oxide semiconductor layer, a base is heated in a preheating chamber of the sputtering equipment. The substrate 300 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 300 and the gate insulating layer 308. It is preferable to desorb and evacuate the impurities.

[0041] In this embodiment, an In—Sn—Zn—O film, which is an oxide semiconductor film, is formed to a thickness of 15 nm. Preferably, the atomic ratio is In:Sn:Zn=2:1:3, In:Sn:Zn=1 :2:2, In:Sn:Zn=1:1:1 or In:Sn:Zn=20:45:35 The In-Sn-Zn-O target shown in Fig. 1 was used. By forming an oxide semiconductor film using a Zn-O target, polycrystalline or CAAC( CAAC: Also known as C-Axis Aligned Crystal. It becomes.

[0042] The In-Sn-Zn-O film was prepared using a sputtering system with a volume ratio of argon to oxygen of 2:3. In this embodiment, the film is formed in a mixed atmosphere of In: An In-Sn-Zn-O target with an atomic ratio of Sn:Zn = 1:1:1 is used. The substrate heating temperature during film formation is set to 200°C.

[0043] To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage may be a turbomolecular pump with a cold trap added. The deposition chamber is evacuated using a gas pump, and contains hydrogen atoms, water (H2O), and other gases. Compounds containing carbon atoms (and more preferably compounds containing carbon atoms) are exhausted from the deposition chamber. The concentration of impurities contained in the formed oxide semiconductor layer can be reduced.

[0044] Next, a heat treatment is performed in a reduced pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. By the heat treatment, the impurity concentration in the oxide semiconductor film can be reduced.

[0045] The heat treatment is carried out in a reduced pressure or inert atmosphere, and then the temperature is maintained while the heat treatment is carried out in an acid atmosphere. It is preferable to switch to a chemical atmosphere and then carry out further heat treatment. When heat treatment is performed in an active atmosphere, the impurity concentration in the oxide semiconductor film can be effectively reduced. However, oxygen vacancies are also generated at the same time. This can be reduced by heat treatment in an oxidizing atmosphere.

[0046] In this embodiment, first, heat treatment is performed in a nitrogen atmosphere for 1 hour, and then the temperature is increased to 250° C. to 650° C. While maintaining the temperature, heat treatment is further carried out for 1 hour in an oxygen atmosphere.

[0047] Next, the oxide semiconductor film is processed by a second photolithography step to form an oxide semiconductor film. In this embodiment, the oxide semiconductor film is etched by dry etching. Etching is performed. BCl3 and Cl2 are used as etching gases. A dry etching device using a high density plasma source such as ECR or ICP is used above.

[0048] Next, a metal film is formed to form an electrode that functions as a source electrode or a drain electrode. The metal film is made of molybdenum, titanium, tantalum, tungsten, and aluminum. Metallic materials such as copper, chromium, neodymium, scandium, etc., or alloy materials containing these as the main components The metal film may have a single layer structure or a multilayer structure. Good too.

[0049] Next, the metal film is processed by a third photolithography process to form the source electrode 314 and The drain electrode 315 is formed by the photomask of the third photolithography process. Therefore, the source electrode 314 of the second transistor and the drain electrode 31 of the second transistor The position of the gate electrode 310 of the second transistor 302 is determined by the gate insulating layer 5. and the source electrode 314 of the second transistor is overlapped with the gate electrode of the second transistor. One end face of the electrode is connected to the source electrode 314 of the second transistor and the drain electrode 315 of the second transistor. It is formed to overlap the gap of the rain electrode 315 .

[0050] Next, a protective insulating film 320 is formed to cover the source electrode 314 and the drain electrode 315 . It is preferable that the protective insulating film 320 be an insulating film with good step coverage. The materials for 0 include silicon oxide film, gallium oxide film, aluminum oxide film, silicon oxynitride film, The insulating layer can be formed using a silicon film, an aluminum oxynitride film, or a silicon nitride oxide film. In this embodiment, a silicon oxide film that becomes the protective insulating film 320 is formed by sputtering. The silicon oxide film is formed by sputtering to a thickness of 300 nm. In a gas (typically argon) atmosphere, in an oxygen atmosphere, or in a mixed atmosphere of rare gas and oxygen The target can be silicon oxide or silicon. For example, silicon can be used as a target and sputtered in an atmosphere containing oxygen. By performing this process, a silicon oxide film can be formed.

[0051] In order to remove residual moisture in the deposition chamber during the deposition of the protective insulating film 320, an adsorption type It is preferable to use an air pump (such as a cryopump). The sputtering gas used for the deposition is free of impurities such as hydrogen, water, hydroxyl groups, and hydrides. It is preferable to use a high purity gas.

[0052] Then, the mixture is heated under a reduced pressure, an inert gas atmosphere, an oxygen gas atmosphere, or an ultra-dry air atmosphere. A second heat treatment is carried out under atmospheric pressure (preferably at 200°C or higher and 600°C or lower, for example, at 250°C or higher and 55°C or lower). When the second heat treatment is performed, a part of the oxide semiconductor layer (channel The temperature of the protective insulating film 320 is increased while the insulating film 320 is in contact with the oxygen-containing protective insulating film 320. Oxygen can be supplied to the oxide semiconductor layer 306 from the atmosphere. It is preferable that the following are not included.

[0053] Through the above steps, the second transistor 302 shown in FIGS. 2A and 2B is manufactured. can be done.

[0054] The first transistor 301 is formed by the photolithography process described above. The mask determines the positions of the source and drain electrodes of the first transistor 301. The source electrode and the drain electrode of the first transistor 301 are connected to the second transistor 302 via a gate insulating layer. The gate electrode of the first transistor 301 overlaps with the gate electrode of the first transistor 301.

[0055] In the second transistor 302 described in this embodiment, the top surface of the oxide semiconductor layer has a rectangular shape. However, the drain electrode 315 is not particularly limited to a U-shaped (C-shaped, U-shaped) Alternatively, the source electrode 314 may be shaped like a horseshoe or a square. This makes it possible to ensure a sufficient channel width even if the transistor area is small. This makes it possible to increase the amount of current that flows when the transistor is on (also called on-current). become.

[0056] (Embodiment 2) In this embodiment, an example in which the capacitor 303 shown in FIG. 1A is not provided will be described below.

[0057] Instead of the capacitance 303 shown in FIG. 1(A), a parasitic capacitance 323 is used as shown in FIG. This allows driving in a manner similar to that of the circuit shown in FIG.

[0058] The connection electrode 325 that functions as the source electrode of the second transistor 302 is a part of the parasitic capacitance. The surface of the region that functions as one electrode and overlaps with the gate electrode 310 of the second transistor 302 The capacity can be increased by widening the product, that is, by lengthening Lov.

[0059] The drain electrode of the second transistor is the same as that of the first embodiment. The gate electrode 310 of the drain electrode 302 is formed at a position where it does not overlap with the gate electrode 310 of the drain electrode 302. The distance between the electrodes 315 is Loff (also called the offset length).

[0060] The connection electrode 325 functions as a drain electrode of the first transistor 301 .

[0061] The gate electrode 330 of the first transistor 301 is connected to the source electrode 324 and the connecting electrode The source electrode 324 and the connection electrode 325 overlap with each other. The width of overlap with pole 330, Lov, is approximately the same.

[0062] In this embodiment, since it is not necessary to separately form the capacitor 303, the circuit is shorter than that in the first embodiment. The area occupied by the road can be reduced.

[0063] This embodiment mode can be freely combined with Embodiment Mode 1.

[0064] (Embodiment 3) The field-effect mobility of the first transistor 301 used in the circuit illustrated in FIG. 1 of Embodiment 1 is It is desirable that the value is high, and is greater than 10, preferably 30 or more, more preferably 50 or more. The second transistor 302 is a transistor having a field effect mobility of 100 . It is formed in the same process as the first transistor, and the source electrode overlaps the gate electrode. The power supply electrode and the gate electrode do not overlap, which reduces the potential difference between VDD and VSS. Even if V A In particular, semiconductors that can obtain high field-effect mobility If a material, specifically an In-Sn-Zn-O film, is used for the semiconductor layer, the on-current is reduced significantly. It's not a problem.

[0065] The field-effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured as However, the mobility is lower than the original mobility due to various reasons. There are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using this, we can theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. Can.

[0066] The following calculations are performed using a top-gate transistor structure. Even in a GaN-gate transistor, a comparable field-effect mobility can be obtained.

[0067] The intrinsic mobility of the semiconductor is μ0, and the measured field-effect mobility is μ. Assuming the existence of potential barriers (grain boundaries, etc.), this can be expressed by the following equation:

[0068]

number

[0069] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, if we assume that the potential barrier originates from defects, the Levinson model gives , which is expressed by the following formula:

[0070]

number

[0071] where e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the The dielectric constant, n is the number of carriers contained in the channel per unit area, C ox is per unit area capacitance, V g is the gate voltage, and t is the channel thickness. In the case of a semiconductor layer, the thickness of the channel can be considered to be the same as the thickness of the semiconductor layer. Drain current I d is expressed by the following formula:

[0072]

number

[0073] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, V d is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides gives It looks like this:

[0074]

number

[0075] The right side of number 5 is V g As can be seen from this equation, the vertical axis is ln(Id / Vg), The defect density N That is, the I d -V g From the characteristics, the defect density can be evaluated. As an oxide semiconductor, the ratio of indium (In), tin (Sn), and zinc (Zn) is I In the case of n:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 That's about it.

[0076] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in defective In-Sn-Zn oxide is 35 cm 2 / V However, the oxide semiconductor without defects inside the semiconductor and at the interface between the semiconductor and the insulating film The mobility of the conductor μ0 is 120 cm 2 It can be expected that / Vs.

[0077] However, even if there are no defects inside the semiconductor, the diffusion at the interface between the channel formation region and the gate insulating layer can occur. The transport properties of the transistor are affected by the disturbances from the gate insulating layer interface to the x The mobility μ1 at a distance of 1 μ m is expressed by the following equation:

[0078]

number

[0079] Here, D is the electric field in the gate direction, and B and G are constants. B and G are determined by actual measurements. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10 nm (depth of interface scattering). D increases (i.e., gate voltage increases). Since the second term in equation 6 increases, the mobility μ1 decreases.

[0080] A transistor that uses an ideal oxide semiconductor with no internal defects in the channel formation region The results of calculating the mobility μ2 of the device are shown in Figure 4. Using the Sentaurus Device simulation software, The band gap, electron affinity, dielectric constant, and thickness are set to 2.8 eV and 4.7 eV, respectively. These values ​​are for thin films formed by sputtering. This was obtained by measurement.

[0081] Furthermore, the work functions of the gate electrode, source electrode, and drain electrode are set to 5.5 electron volts. The gate insulating layer thickness was 100 nV, 4.6 eV, and 4.6 eV. The channel length and width were both 10 μm, and the drain Voltage V d is 0.1V.

[0082] As shown in Figure 4, the mobility is 100 cm at a gate voltage of just over 1 V. 2 / Vs or more peak However, if the gate voltage is further increased, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, it is necessary to flatten the semiconductor layer surface at the atomic level (Ato Micro Layer Flatness is desirable. Specifically, the average surface roughness (Ra) The thickness of the semi-conductor layer on the surface is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. A conductive layer may be formed.

[0083] For Ra, the centerline average roughness defined in JIS B0601 can be applied to the surface. It is a three-dimensional extension of the method, which is based on the averaging of the absolute values ​​of the deviations from the reference surface to the specified surface. This can be expressed as the "value obtained" and is defined by the following formula:

[0084]

number

[0085] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 ) (the rectangular area defined by the four points (x2, y2)), and Z0 is the average height of the measurement surface. Ra is the strength of the AFM (Atomic Force Microscope). It can be evaluated using the OPE.

[0086] The characteristics of a miniaturized transistor fabricated using an oxide semiconductor with such mobility are as follows: The results of the calculations are shown in Figures 5, 6, and 7. The surface structure is shown in Figure 8. The transistor shown in Figure 8 has an n-type oxide semiconductor layer. + Conductivity type of The semiconductor region 103a and the semiconductor region 103c are included. The resistivity of the body region 103c is 2 × 10 -3 Let it be Ωcm.

[0087] The transistor shown in FIG. 8A includes a base insulator 101 and a The insulating layer 102 is formed on a buried insulator 102 made of aluminum oxide so as to be etched away from the insulating layer 102 . The transistor is made up of a semiconductor region 103a, a semiconductor region 103c, and a channel The gate electrode 105 is formed in an intrinsic semiconductor region 103b. The width of 05 is 33 nm.

[0088] Between the gate electrode 105 and the semiconductor region 103b, there is a gate insulating layer 104. The gate electrode 105 is provided on both sides with sidewall insulators 106a and 106b. An insulator 107 is provided on the top of the gate electrode 105 to prevent short circuits between the gate electrode 105 and other wiring. The width of the sidewall insulator is set to 5 nm. The source electrode 108a and the drain electrode 108b are in contact with the transistor 103c. The channel width of the transistor is set to 40 nm.

[0089] The transistor shown in FIG. 8B has a base insulator 101 and a buried insulating film made of aluminum oxide. The semiconductor region 103a and the semiconductor region 103c are formed on the insulating layer 102. The intrinsic semiconductor region 103b sandwiched between the gate electrode 105 and the gate insulating layer 106 has a width of 33 nm. 104, the sidewall insulator 106a, the sidewall insulator 106b, the insulator 107, and the source electrode 10 8A in that it has a drain electrode 108a and a drain electrode 108b. do.

[0090] The difference between the transistor shown in FIG. 8A and the transistor shown in FIG. 8B is the sidewall insulator. The conductivity type of the semiconductor region under the sidewall insulator 106a and the sidewall insulator 106b is shown in FIG. In the transistor, the semiconductor region under the sidewall insulator 106a and the sidewall insulator 106b is n + The semiconductor region 103a and the semiconductor region 103c have the conductivity type of In the transistor shown in FIG. 8(B), it is the intrinsic semiconductor region 103b. In the semiconductor layer, the semiconductor region 103a (semiconductor region 103c) and the gate electrode 105 There is an area where there is no overlap of Loff. This area is called the offset area, and its width is L As is clear from the figure, the offset length is the length of the sidewall insulator 10 It is the same as the width of 6a (sidewall insulator 106b).

[0091] The first transistor 301 shown in FIG. 3 is a bottom gate type, but the transistor shown in FIG. That is, the semiconductor layer overlapping the gate electrode 105 in FIG. The body region 103b corresponds to the oxide semiconductor layer 326 in FIG. 3, and the n + The conductivity type of The semiconductor region 103a and the semiconductor region 103c are the source electrode 324 and the This corresponds to the contact portion between the connection electrode 325 and the oxide semiconductor layer 326. The interface state between the oxide semiconductor layer 326 and the protective insulating film 320 By reducing the interface state with the SiO2, high field-effect mobility was achieved, similar to the results shown in the calculations. It is possible to obtain

[0092] The other parameters used in the calculation are as described above. The simulation software, Sentaurus Device, was used. The drain current (Id, solid line) and mobility (μ The graph shows the gate voltage (Vg, the potential difference between the gate electrode and the source electrode) dependence of the drain The drain voltage (potential difference between the drain electrode and the source electrode) is set to +1V, and the on-state current Id is The degree μ is calculated assuming a drain voltage of +0.1V.

[0093] In Figure 5(A), the thickness of the gate insulating film is 15 nm, and in Figure 5(B), it is 10 nm. In Figure 5(C), the thickness is set to 5 nm.

[0094] FIG. 6 shows the structure of the transistor shown in FIG. 8(B) with the offset length Loff set to 5 nm. The gate voltage Vg dependence of the drain current Id (solid line) and mobility μ (dotted line) of the The drain current Id is calculated when the drain voltage is +1 V, and the mobility μ is calculated when the drain voltage is +0 The calculation was performed with a gate insulating film thickness of 15 nm. FIG. 6(B) shows the case where the thickness is 10 nm, and FIG. 6(C) shows the case where the thickness is 5 nm. do.

[0095] FIG. 7 shows the offset length Loff of the transistor having the structure shown in FIG. 8(B). Drain current Id (solid line) and mobility μ (dotted line) dependence on gate voltage for 5 nm The drain current Id is calculated by setting the drain voltage to +1 V, and the mobility μ is calculated by setting the drain voltage to +1 V. The calculation was performed with a voltage of +0.1V. Figure 7(A) shows the gate insulating film thickness of 15 nm. FIG. 7(B) shows the result of 10 nm, and FIG. 7(C) shows the result of 5 nm. is.

[0096] The peak of the mobility μ is 80 cm in Figure 5. 2 / Vs, but in Figure 6, 2 / Vs, 40cm in Figure 7 2 / Vs and the offset length Loff increase. The off-current also shows a similar trend. On the other hand, the on-current increases with increasing offset length Loff. The decrease with increasing the gate charge is much slower than the decrease in the off-state current.

[0097] (Fourth embodiment) In this embodiment, the c-axis is oriented and the crystal is triangular or triangular when viewed from the ab-plane, surface, or interface direction. The metal atoms are arranged in layers or in a combination of metal atoms and oxygen atoms along the c-axis. The molecules are arranged in layers, and the orientation of the a-axis or b-axis is different in the ab plane (the c-axis is the center). C-Axis Aligned Crystal (CAAC) This section explains oxides containing .

[0098] In a broad sense, oxides containing CAAC are non-single crystals that are not single crystals and are not uniform in size when viewed from the direction perpendicular to the ab plane. The atomic arrangement is triangular, hexagonal, equilateral triangular or equilateral hexagonal, and perpendicular to the c-axis direction. When viewed from the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0099] CAAC is not a single crystal, but it is not made up of only amorphous material. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it's impossible to tell for sure.

[0100] When the CAAC contains oxygen, a part of the oxygen may be replaced with nitrogen. The c-axis of each crystalline part that constitutes the CAAC is in a certain direction (for example, the substrate surface on which the CAAC is formed, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal of the ab plane of each crystal part is in a certain direction (e.g., the substrate surface on which the CAAC is formed, It may be oriented in a direction perpendicular to the surface of the AC.

[0101] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0102] An example of the crystal structure contained in CAAC will be described in detail with reference to FIGS. 9 to 11. Unless otherwise specified, the upward direction in FIGS. 9 to 11 is the c-axis direction, and the direction perpendicular to the c-axis direction is The plane is the ab plane. When we simply refer to the upper half and the lower half, we mean the upper half when the ab plane is used as the boundary. In Figure 9, the circled O represents a tetracoordinated O, and the double circled O represents a tetracoordinated O. The O in the figure indicates a three-coordinate O.

[0103] Figure 9(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as tetracoordinated oxygen atoms) adjacent to the In atom. In this case, there is one metal atom and one adjacent oxygen atom. The structure shown in Figure 9(A) is an octahedral structure, but it is a simple The upper and lower halves of Fig. 9(A) each have three There are four tetracoordinated O atoms. The small group shown in Figure 9(A) has a zero charge.

[0104] Figure 9(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as tricoordinates) adjacent to the Ga atom. The structure shows a structure with a tetracoordinate O and two adjacent tetracoordinate Os. The upper and lower halves of Figure 9(B) each contain one tetrahedral O atom. In addition, since In also takes five-coordinated positions, it can take the structure shown in Figure 9(B). The small group shown has a charge of 0.

[0105] FIG. 9(C) shows a structure having one tetracoordinated Zn and four tetracoordinated O atoms adjacent to the Zn. The upper half of Figure 9(C) contains one tetracoordinate O atom, and the lower half contains three tetracoordinate O atoms. Or, in Figure 9(C), there are three tetracoordinate O atoms in the upper half and one tetracoordinate O atom in the lower half. The small group shown in Figure 9(C) has a charge of 0.

[0106] FIG. 9(D) shows a structure having one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 9(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 9(D) has a charge of +1.

[0107] Figure 9(E) shows a small group containing two Zn atoms. The upper half of Figure 9(E) shows one tetrahedral group. The small group shown in Figure 9(E) has a charge becomes -1.

[0108] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0109] Here, we will explain the rules for combining these small groups. The three Os in the upper half of the In configuration each have three adjacent Ins downward, and the three in the lower half Each O has three adjacent In atoms in the upward direction. One O in the bottom half has one neighbor Ga below it, and one O in the bottom half has one neighbor Ga above it. The O atom in the upper half of the 4-coordinate Zn shown in Figure 9(C) has one neighboring O atom in the downward direction. Zn, and the three Os in the lower half each have three adjacent Zns in the upward direction. The number of tetrahedral O atoms above a metal atom is equal to the number of adjacent metal atoms below that O atom. Similarly, the number of tetrahedral O atoms below the metal atom and the number of neighboring metal atoms above the O atoms is equal. Since O is 4-coordinated, the number of neighboring metal atoms below is equal to the number of neighboring metal atoms above. The sum of the number of atoms is 4. Therefore, the number of 4-coordinated O atoms above the metal atom and the number of O atoms above another metal atom are When the sum of the number of tetracoordinated O atoms below the atom is 4, two small groups containing metal atoms are formed. The reason is as follows. For example, a hexacoordinated metal atom ( When In or Sn) is bonded through a tetracoordinate O in the lower half, there are three tetracoordinate O atoms. Therefore, either a five-coordinated metal atom (Ga or In) or a four-coordinated metal atom (Zn) It will be combined with

[0110] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinated oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0111] Figure 10(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 10(B) shows a large group consisting of three medium groups. C) shows the atomic arrangement when the layer structure of FIG. 10(B) is observed from the c-axis direction.

[0112] In FIG. 10(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the circle indicates that there are three tetrahedral O atoms in the upper and lower halves of Sn. Similarly, in FIG. 10(A), the upper and lower halves of In are There is one tetracoordinate O in each of them, which is shown as a circled 1. Similarly, in Figure 10 In (A), there is one tetracoordinate O in the bottom half and three tetracoordinate O in the top half. Zn with one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. This shows that:

[0113] In Fig. 10(A), the middle group, which is composed of the In-Sn-Zn-O system layer structure, is Sn has three tetrahedral O atoms in the upper half and three in the lower half, and one tetrahedral O atom in the upper half. In is bonded to the In in the upper and lower halves, and the In is bonded to the Z n, and three tetracoordinate O atoms bond to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one tetrahedral O in the upper half. It bonds to a small group consisting of 4, 4, and 4 through one 4-coordinate O in the lower half of this small group. Three O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0114] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6 67, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. As shown in (E), there is a small group containing two Zn atoms. For example, there is a small group containing Sn atoms. If there is one small group containing two Zn atoms for every group, the charges are canceled out. Therefore, the total charge of the layer structure can be set to zero.

[0115] Specifically, the large group shown in Figure 10(B) is repeated to form In-Sn-Zn -O system crystal (In2SnZn3O8) can be obtained. -Zn-O system layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be expressed by the composition formula:

[0116] For example, Figure 11(A) shows a model of the middle group consisting of an In-Ga-Zn-O system layer structure. A diagram is shown.

[0117] In FIG. 11(A), the middle group, which is composed of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to the Zn in the center, and one tetracoordinate O is bonded to the Zn via the three tetracoordinate O atoms in the lower half of the Zn. It bonds to Ga atoms in the upper and lower halves, respectively, and is bonded to one tetracoordinate O atom in the lower half of the Ga atom. The structure is such that three tetracoordinate O atoms are bonded to three In atoms in the upper and lower halves. Multiple medium groups combine to form large groups.

[0118] Figure 11(B) shows a large group consisting of three medium groups. 11(B) shows the atomic arrangement when the layer structure of FIG. 11(B) is observed from the c-axis direction.

[0119] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are Since the valence numbers are +3, +2, and +3 respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge is always 0.

[0120] The middle group, which is composed of an In-Ga-Zn-O layer structure, is shown in FIG. Not limited to the middle group, large-sized compounds with different arrangements of In, Ga, and Zn are also available. Groups can also be taken.

[0121] The CAAC described above can be obtained by the manufacturing process described in Embodiment 1. The CAAC has an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, and more preferably In addition, if the heating temperature during film formation is high, CA AC is likely to form.

[0122] This embodiment mode can be freely combined with other embodiment modes. [Explanation of symbols]

[0123] 101 Undercoat insulation 103 Semiconductor Area 104 Gate insulating layer 105 gate electrode 106 Sidewall insulator 107 Insulators 108 electrode 108a Source electrode 108b Drain electrode 300 boards 301 First transistor 302 Second Transistor 303 capacity 304 Control Unit 305 capacity 306 Oxide semiconductor layer 308 Gate insulating layer 314 Source electrode 315 Drain electrode 320 Protective insulating film 323 Parasitic capacitance 324 Source Electrode 325 connecting electrode 326 Oxide semiconductor layer 330 gate electrode

Claims

1. a first transistor and a second transistor each having a channel formation region including an oxide semiconductor; a semiconductor device having a function of controlling an output potential in accordance with a conduction state of the first transistor and a conduction state of the second transistor, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a second conductive film that functions as the other of the source electrode and the drain electrode of the first transistor and also functions as one of the source electrode and the drain electrode of the second transistor; a third conductive film functioning as the other of the source electrode and the drain electrode of the second transistor, a region where the second conductive film overlaps with a fourth conductive film functioning as a gate electrode of the second transistor is larger than a region where the second conductive film overlaps with a fifth conductive film functioning as a gate electrode of the first transistor; a region of the oxide semiconductor film having the channel formation region of the second transistor overlapping with the fourth conductive film is separated from a region of the oxide semiconductor film overlapping with the third conductive film in a plan view; the potential is output via the second conductive film. Semiconductor device.

2. a first transistor and a second transistor each having a channel formation region including an oxide semiconductor; a semiconductor device having a function of controlling an output potential in accordance with a conduction state of the first transistor and a conduction state of the second transistor, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a second conductive film that functions as the other of the source electrode and the drain electrode of the first transistor and also functions as one of the source electrode and the drain electrode of the second transistor; a third conductive film functioning as the other of the source electrode and the drain electrode of the second transistor, a region where the second conductive film overlaps with a fourth conductive film functioning as a gate electrode of the second transistor is larger than a region where the second conductive film overlaps with a fifth conductive film functioning as a gate electrode of the first transistor; a region of the oxide semiconductor film having the channel formation region of the second transistor overlapping with the fourth conductive film is separated from a region of the oxide semiconductor film overlapping with the third conductive film in a plan view; a first potential applied to the third conductive film is higher than a second potential applied to the first conductive film; the potential is output via the second conductive film. Semiconductor device.

3. a first transistor and a second transistor each having a channel formation region including an oxide semiconductor; a semiconductor device having a function of controlling an output potential in accordance with a conduction state of the first transistor and a conduction state of the second transistor, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a second conductive film that functions as the other of the source electrode and the drain electrode of the first transistor and also functions as one of the source electrode and the drain electrode of the second transistor; a third conductive film functioning as the other of the source electrode and the drain electrode of the second transistor, an upper surface of the first conductive film, an upper surface of the second conductive film, and an upper surface of the third conductive film each have a region in contact with a first insulating film; a region where the second conductive film overlaps with a fourth conductive film functioning as a gate electrode of the second transistor is larger than a region where the second conductive film overlaps with a fifth conductive film functioning as a gate electrode of the first transistor; a region of the oxide semiconductor film having the channel formation region of the second transistor overlapping with the fourth conductive film is separated from a region of the oxide semiconductor film overlapping with the third conductive film in a plan view; the potential is output via the second conductive film. Semiconductor device.

4. a first transistor and a second transistor each having a channel formation region including an oxide semiconductor; a semiconductor device having a function of controlling an output potential in accordance with a conduction state of the first transistor and a conduction state of the second transistor, a first conductive film functioning as one of a source electrode and a drain electrode of the first transistor; a second conductive film that functions as the other of the source electrode and the drain electrode of the first transistor and also functions as one of the source electrode and the drain electrode of the second transistor; a third conductive film functioning as the other of the source electrode and the drain electrode of the second transistor, an upper surface of the first conductive film, an upper surface of the second conductive film, and an upper surface of the third conductive film each have a region in contact with a first insulating film; a region where the second conductive film overlaps with a fourth conductive film functioning as a gate electrode of the second transistor is larger than a region where the second conductive film overlaps with a fifth conductive film functioning as a gate electrode of the first transistor; a region of the oxide semiconductor film having the channel formation region of the second transistor overlapping with the fourth conductive film is separated from a region of the oxide semiconductor film overlapping with the third conductive film in a plan view; a first potential applied to the third conductive film is higher than a second potential applied to the first conductive film; the potential is output via the second conductive film. Semiconductor device.

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