Semiconductor device, semiconductor package, and inverter system

Abstract

To provide a semiconductor device in which the warpage of a third semiconductor chip can be reduced.SOLUTION: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. By noncontact communication between different potentials in the third semiconductor chip, signals are exchanged between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first active element. The first semiconductor substrate includes a first surface. The first active element is formed on the first main surface. The second semiconductor chip includes a second semiconductor substrate and a second active element. The second semiconductor substrate includes a second main surface. The second active element is formed on the second main surface. The third semiconductor chip includes a third semiconductor substrate and a passive element. The third semiconductor substrate includes a third main surface. The passive element is formed over the third main surface. Each of the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate is formed of single-crystal silicon.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a semiconductor package, and an inverter system. [Background technology]

[0002] The semiconductor device described in JP 2023-157045 A (Patent Document 1) includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. The first semiconductor chip and the second semiconductor chip include a first circuit and a second circuit, respectively. The third semiconductor chip includes a transformer. The transformer transmits and receives signals between the first circuit and the second circuit through contactless communication between different potentials. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-157045 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described in Patent Document 1, the warpage of the third semiconductor chip is more likely to be large than that of the first semiconductor chip and the second semiconductor chip. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. Signals are transmitted and received between the first semiconductor chip and the second semiconductor chip through contactless communication between different potentials in the third semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first active element. The first semiconductor substrate has a first main surface. The first active element is formed on the first main surface. The second semiconductor chip includes a second semiconductor substrate and a second active element. The second semiconductor substrate has a second main surface. The second active element is formed on the second main surface. The third semiconductor chip includes a third semiconductor substrate and a passive element. The third semiconductor substrate has a third main surface. The passive element is formed above the third main surface. Each of the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate is formed of single crystal silicon. The interplanar spacing between two adjacent crystal planes parallel to the third main surface in the third semiconductor substrate is smaller than the interplanar spacing between two adjacent crystal planes parallel to the first main surface in the first semiconductor substrate and the interplanar spacing between two adjacent crystal planes parallel to the second main surface in the second semiconductor substrate. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, warpage of the third semiconductor chip can be reduced. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram of a semiconductor device DEV. [Figure 2] 10 is an explanatory diagram showing an example of signal transmission from a control circuit CC to a drive circuit DR. FIG. [Figure 3] FIG. 2 is a cross-sectional view of the semiconductor chip CHP1. [Figure 4] FIG. 2 is a cross-sectional view of a semiconductor chip CHP2. [Figure 5] FIG. 2 is a first plan view of the semiconductor chip CHP3. [Figure 6] FIG. 2 is a second plan view of the semiconductor chip CHP3. [Figure 7] FIG. 10 is a third plan view of the semiconductor chip CHP3. [Figure 8]FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 7. [Figure 9] 1A to 1C are manufacturing process diagrams of the semiconductor chip CHP1. [Figure 10] FIG. 10 is a cross-sectional view illustrating an ion implantation step S2. [Figure 11] FIG. 10 is a cross-sectional view illustrating a groove forming step S3. [Figure 12] FIG. 10 is a cross-sectional view illustrating an element isolation film forming step S4. [Figure 13] FIG. 10 is a cross-sectional view illustrating a gate insulating film forming step S5. [Figure 14] FIG. 10 is a cross-sectional view illustrating a gate electrode forming step S6. [Figure 15] FIG. 10 is a cross-sectional view illustrating an ion implantation step S7. [Figure 16] FIG. 10 is a cross-sectional view illustrating a sidewall spacer forming step S8. [Figure 17] FIG. 10 is a cross-sectional view illustrating an ion implantation step S9. [Figure 18] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S10. [Figure 19] FIG. 10 is a cross-sectional view illustrating a contact plug forming step S11. [Figure 20] FIG. 10 is a cross-sectional view illustrating the wiring layer forming step S12. [Figure 21] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S13. [Figure 22] FIG. 10 is a cross-sectional view illustrating a via plug forming step S14. [Figure 23] FIG. 10 is a cross-sectional view illustrating a wiring layer forming step S15. [Figure 24] 10 is a schematic graph showing the relationship between the stage of progress in the manufacturing process and the amount of warpage of the semiconductor chip CHP3. [Figure 25] 10 is a cross-sectional view of a semiconductor chip CHP3 included in a semiconductor device DEV according to a first modification. FIG. [Figure 26] FIG. 2 is a cross-sectional view of a semiconductor package PKG. [Figure 27] FIG. 2 is a schematic diagram of an inverter system INVS. DETAILED DESCRIPTION OF THE INVENTION

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) A semiconductor device (semiconductor device DEV) according to a first embodiment will be described.

[0010] (Configuration of semiconductor device DEV) The configuration of the semiconductor device DEV will be described below.

[0011] <Schematic configuration of semiconductor device DEV> The schematic configuration of the semiconductor device DEV will be described below.

[0012] Fig. 1 is a block diagram of a semiconductor device DEV. As shown in Fig. 1, the semiconductor device DEV has semiconductor chips CHP1, CHP2, and CHP3. The semiconductor chip CHP1 has a transmitting circuit TX1 and a receiving circuit RX2, and a control circuit CC is electrically connected to the transmitting circuit TX1 and the receiving circuit RX2. The semiconductor chip CHP2 has a driving circuit DR, a receiving circuit RX1, and a transmitting circuit TX2. The receiving circuit RX1 and the transmitting circuit TX2 are electrically connected to the driving circuit DR.

[0013] The semiconductor chip CHP3 has a transformer TR1, a transformer TR2, and lead-out wiring PL1 and lead-out wiring PL2.

[0014] The transformer TR1 has a transmitting coil CL1 and a receiving coil CL2. The transmitting coil CL1 has a coil CL11 and a coil CL12, and the receiving coil CL2 has a coil CL21 and a coil CL22. The transmitting coil CL1 and the receiving coil CL2 are electrically connected to a transmitting circuit TX1 and a receiving circuit RX1, respectively.

[0015] More specifically, one end of the coil CL11 is electrically connected to the transmitting circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the transmitting circuit TX1. One end of the coil CL21 is electrically connected to the receiving circuit RX1, and the other end of the coil CL21 is electrically connected to one end of the coil CL22 via the lead-out wiring PL1, and the other end of the coil CL22 is electrically connected to the receiving circuit RX1.

[0016] The transformer TR2 has a transmitting coil CL3 and a receiving coil CL4. The transmitting coil CL3 has coils CL31 and CL32, and the receiving coil CL4 has coils CL41 and CL42. The transmitting coil CL3 and the receiving coil CL4 are electrically connected to the transmitting circuit TX2 and the receiving circuit RX2, respectively.

[0017] More specifically, one end of the coil CL31 is electrically connected to the transmitting circuit TX2, the other end of the coil CL31 is electrically connected to one end of the coil CL32, and the other end of the coil CL32 is electrically connected to the transmitting circuit TX2. One end of the coil CL41 is electrically connected to the receiving circuit RX2, and the other end of the coil CL41 is electrically connected to one end of the coil CL42 via the lead-out wiring PL2, and the other end of the coil CL42 is electrically connected to the receiving circuit RX2.

[0018] In the semiconductor device DEV, a signal is transmitted from the control circuit CC to the drive circuit DR via a transmitter circuit TX1, a transformer TR1, and a receiver circuit RX1. Also, in the semiconductor device DEV, a signal is transmitted from the drive circuit DR to the control circuit CC via a transmitter circuit TX2, a transformer TR2, and a receiver circuit RX2.

[0019] FIG. 2 is an explanatory diagram showing an example of signal transmission from the control circuit CC to the drive circuit DR. As shown in FIG. 2, the control circuit CC inputs a signal SG1 to the transmitter circuit TX1. The signal SG1 is a square wave. The transmitter circuit TX1 modulates the signal SG1 to a signal SG2 and sends the signal SG2 to the transmitter coil CL1. When the signal SG2 flows to the transmitter coil CL1, a signal SG3 corresponding to the signal SG2 flows to the receiver coil CL2 due to induced electromotive force. The receiver circuit RX1 amplifies the signal SG3 and demodulates it to a signal SG4 (square wave), which it then outputs to the driver circuit DR. In this manner, signals are transmitted from the control circuit CC to the driver circuit DR. Note that signals are transmitted from the driver circuit DR to the control circuit CC in a similar manner. In this manner, in the semiconductor device DEV, signal transmission between the transmitter circuit TX1 and the receiver circuit RX1 and between the transmitter circuit TX2 and the receiver circuit RX2 are performed using a pulse communication method.

[0020] <Detailed configuration of semiconductor chip CHP1> The detailed configuration of the semiconductor chip CHP1 will be described below.

[0021] 3 is a cross-sectional view of the semiconductor chip CHP1. As shown in Fig. 3, the semiconductor chip CHP1 includes a semiconductor substrate SUB1, a gate insulating film GI1, a gate electrode GE1, a sidewall spacer SWS1, an isolation film ISL1, an interlayer insulating film ILD1a, a contact plug CP1, a plurality of interlayer insulating films ILD1b, a wiring layer WL1a, a via plug VP1, a plurality of wiring layers WL1b, and a passivation film PV1.

[0022] The semiconductor substrate SUB1 has a main surface MS1a and a main surface MS1b. The main surface MS1b is the surface opposite to the main surface MS1a. The main surface MS1a and the main surface MS1b are end surfaces in the thickness direction of the semiconductor substrate SUB1. The semiconductor substrate SUB1 is made of single crystal silicon. The main surface MS1a is configured, for example, by the (100) plane of the single crystal silicon. However, the crystal plane of the single crystal silicon that configures the main surface MS1a is not limited to this. Hereinafter, the "(klm) plane" refers to the crystal plane of the single crystal silicon expressed in Miller indices.

[0023] A source region SR1, a drain region DRA1, and a well region WR1 are formed in the semiconductor substrate SUB1. The source region SR1 and the drain region DRA1 are formed in the main surface MS1a. The source region SR1 and the drain region DRA1 are spaced apart from each other. The source region SR1 has a first portion SR1a and a second portion SR1b. The drain region DRA1 has a first portion DRA1a and a second portion DRA1b. The first portion SR1a is located closer to the drain region DRA1 than the second portion SR1b, and the first portion DRA1a is located closer to the source region SR1 than the second portion DRA1b.

[0024] The well region WR1 is formed in the main surface MS1a so as to surround the source region SR1 and the drain region DRA1. The conductivity type of the source region SR1 and the drain region DRA1 is a first conductivity type. The conductivity type of the well region WR1 is a second conductivity type. The second conductivity type is the opposite conductivity type to the first conductivity type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. The portion of the well region WR1 between the source region SR1 and the drain region DRA1 is sometimes referred to as the channel region of the well region WR1.

[0025] A gate insulating film GI1 is formed on the channel region of the well region WR1. The gate insulating film GI1 is formed of, for example, silicon oxide. A gate electrode GE1 is formed on the gate insulating film GI1. The gate electrode GE1 is formed of, for example, impurity-doped polycrystalline silicon. The source region SR1, the drain region DRA1, the well region WR1, the gate insulating film GI1, and the gate electrode GE1 constitute a transistor. This transistor constitutes a transmitting circuit TX1 and a receiving circuit RX2.

[0026] A trench TRN1 is formed in the main surface MS1a. The trench TRN1 surrounds the well region WR1 in a plan view (when the semiconductor substrate SUB1 is viewed along the normal direction of the main surface MS1a). The main surface MS1a is recessed toward the main surface MS1b at the trench TRN1. An element isolation film ISL1 is buried in the trench TRN1. The element isolation film ISL1 is made of, for example, silicon oxide. Adjacent transistors are electrically isolated by the element isolation film ISL1.

[0027] The sidewall spacers SWS1 are formed on the first portions SR1a and DRA1a so as to be in contact with the side surfaces of the gate insulating film GI1 and the gate electrode GE1. The sidewall spacers SWS1 are made of, for example, silicon nitride.

[0028] The interlayer insulating film ILD1a is formed on the main surface MS1a so as to cover the sidewall spacers SWS1 and the gate electrode GE1. The interlayer insulating film ILD1a is formed of, for example, silicon oxide. A contact hole CH1 is formed in the interlayer insulating film ILD1a. A contact plug CP1 is buried in the contact hole CH1. The contact plug CP1 is electrically connected to the source region SR1 (second portion SR1b), the drain region DRA1 (second portion DRA1b), or the gate electrode GE1. The contact plug CP1 is formed of, for example, tungsten.

[0029] The wiring layer WL1a is formed on the interlayer insulating film ILD1a. The wiring layer WL1a is electrically connected to the contact plug CP1. The wiring layer WL1a is made of, for example, aluminum or an aluminum alloy.

[0030] A plurality of interlayer insulating films ILD1b are stacked on the interlayer insulating film ILD1a. The interlayer insulating film ILD1b is formed of, for example, silicon oxide. The lowermost interlayer insulating film ILD1b covers the wiring layer WL1a. One wiring layer WL1b is formed on one interlayer insulating film ILD1b, and another interlayer insulating film ILD1b is formed on the interlayer insulating film ILD1b so as to cover the wiring layer WL1b. However, the uppermost wiring layer WL1b is not covered by the interlayer insulating film ILD1b. One wiring layer WL1a and another wiring layer WL1b above the one wiring layer WL1a are electrically connected by a via plug VP1. The via plug VP1 is embedded in a via hole VH1 formed in the interlayer insulating film ILD1b. The wiring layer WL1b is formed of, for example, aluminum or an aluminum alloy. The via plug VP1 is formed of, for example, tungsten.

[0031] The uppermost wiring layer WL1b has an electrode pad PD1. The electrode pad PD1 is electrically connected to the transistors (transmitter circuit TX1, receiver circuit RX2) through a plurality of wiring layers WL1b, via plugs VP1, wiring layers WL1a, and contact plugs CP1. A passivation film PV1 is formed on the uppermost interlayer insulating film ILD1b so as to cover the uppermost wiring layer WL1b. An opening is formed in the passivation film PV1. The electrode pad PD1 is exposed from the opening in the passivation film PV1. The passivation film PV1 is made of, for example, silicon nitride.

[0032] <Detailed configuration of the CHP2 semiconductor chip> The detailed configuration of the semiconductor chip CHP2 will be described below.

[0033] 3, the semiconductor chip CHP2 includes a semiconductor substrate SUB2, a gate insulating film GI2, a gate electrode GE2, a sidewall spacer SWS2, an element isolation film ISL2, an interlayer insulating film ILD2a, a contact plug CP2, a plurality of interlayer insulating films ILD2b, a wiring layer WL2a, a via plug VP2, a plurality of wiring layers WL2b, and a passivation film PV2.

[0034] The semiconductor substrate SUB2 has a main surface MS2a and a main surface MS2b. The main surface MS2b is the surface opposite to the main surface MS2a. The main surfaces MS2a and MS2b are end surfaces in the thickness direction of the semiconductor substrate SUB2. The semiconductor substrate SUB2 is made of single crystal silicon. The main surface MS2a is, for example, configured as a (100) plane of the single crystal silicon. However, the crystal plane of the single crystal silicon that configures the main surface MS2a is not limited to this.

[0035] A source region SR2, a drain region DRA2, and a well region WR2 are formed in the semiconductor substrate SUB2. The source region SR2 and the drain region DRA2 are formed in the main surface MS2a. The source region SR2 and the drain region DRA2 are spaced apart from each other. The source region SR2 has a first portion SR2a and a second portion SR2b. The drain region DRA2 has a first portion DRA2a and a second portion DRA2b. The first portion SR2a is located closer to the drain region DRA2 than the second portion SR2b, and the first portion DRA2a is located closer to the source region SR2 than the second portion DRA2b.

[0036] The well region WR2 is formed in the main surface MS2a so as to surround the source region SR2 and the drain region DRA2. The source region SR2 and the drain region DRA2 have a first conductivity type. The well region WR2 has a second conductivity type. The portion of the well region WR2 between the source region SR2 and the drain region DRA2 is sometimes referred to as the channel region of the well region WR2.

[0037] The gate insulating film GI2 is formed on the channel region of the well region WR2. The gate insulating film GI2 is formed of, for example, silicon oxide. The gate electrode GE2 is formed on the gate insulating film GI2. The gate electrode GE2 is formed of, for example, impurity-doped polycrystalline silicon. The source region SR2, the drain region DRA2, the well region WR2, the gate insulating film GI2, and the gate electrode GE2 constitute a transistor. This transistor constitutes the transmitter circuit TX2, the receiver circuit RX1, and the driver circuit DR.

[0038] A trench TRN2 is formed in the main surface MS2a. The trench TRN2 surrounds the well region WR2 in a plan view (when the semiconductor substrate SUB2 is viewed along the normal direction of the main surface MS2a). The main surface MS2a is recessed toward the main surface MS2b at the trench TRN2. An element isolation film ISL2 is embedded in the trench TRN2. The element isolation film ISL2 is made of, for example, silicon oxide. Adjacent transistors are electrically isolated by the element isolation film ISL2.

[0039] The sidewall spacers SWS2 are formed on the first portions SR2a and DRA2a so as to be in contact with the side surfaces of the gate insulating film GI2 and the gate electrode GE2. The sidewall spacers SWS2 are made of, for example, silicon nitride.

[0040] The interlayer insulating film ILD2a is formed on the main surface MS2a so as to cover the sidewall spacers SWS2 and the gate electrode GE2. The interlayer insulating film ILD2a is formed of, for example, silicon oxide. A contact hole CH2 is formed in the interlayer insulating film ILD2a. A contact plug CP2 is buried in the contact hole CH2. The contact plug CP2 is electrically connected to the source region SR2 (second portion SR2b), the drain region DRA2 (second portion DRA2b), or the gate electrode GE2. The contact plug CP2 is formed of, for example, tungsten.

[0041] The wiring layer WL2a is formed on the interlayer insulating film ILD2a. The wiring layer WL2a is electrically connected to the contact plug CP2. The wiring layer WL2a is made of, for example, aluminum or an aluminum alloy.

[0042] A plurality of interlayer insulating films ILD2b are stacked on the interlayer insulating film ILD2a. The interlayer insulating film ILD2b is formed of, for example, silicon oxide. The lowermost interlayer insulating film ILD2b covers the wiring layer WL2a. One wiring layer WL2b is formed on one interlayer insulating film ILD2b, and another interlayer insulating film ILD2b is formed on the interlayer insulating film ILD2b so as to cover the wiring layer WL2b. However, the uppermost wiring layer WL2b is not covered by the interlayer insulating film ILD2b. One wiring layer WL2a and another wiring layer WL2b above the one wiring layer WL2a are electrically connected by a via plug VP2. The via plug VP2 is embedded in a via hole VH2 formed in the interlayer insulating film ILD2b. The wiring layer WL2b is formed of, for example, aluminum or an aluminum alloy. The via plug VP2 is formed of, for example, tungsten.

[0043] The uppermost wiring layer WL2b has an electrode pad PD2. The electrode pad PD2 is electrically connected to transistors (transmitter circuit TX1, receiver circuit RX2, and driver circuit DR) via a plurality of wiring layers WL2b, via plugs VP2, wiring layers WL2a, and contact plugs CP2. A passivation film PV2 is formed on the uppermost interlayer insulating film ILD2b so as to cover the uppermost wiring layer WL2b. An opening is formed in the passivation film PV2. The electrode pad PD2 is exposed from the opening in the passivation film PV2. The passivation film PV2 is made of, for example, silicon nitride.

[0044] <Detailed configuration of the CHP3 semiconductor chip> The detailed configuration of the semiconductor chip CHP3 will be described below.

[0045] Fig. 5 is a first plan view of the semiconductor chip CHP3. Fig. 6 is a second plan view of the semiconductor chip CHP3. Fig. 7 is a third plan view of the semiconductor chip CHP3. Fig. 8 is a cross-sectional view taken along line VIII-VIII in Fig. 7. As shown in Figs. 5 to 8, the semiconductor chip CHP3 has a semiconductor substrate SUB3, an interlayer insulating film ILD3a, a wiring layer WL3a, a plurality of interlayer insulating films ILD3b, a plurality of wiring layers WL3b, via plugs VP3, and a passivation film PV3.

[0046] The semiconductor substrate SUB3 has a main surface MS3a and a main surface MS3b. The main surface MS3a is the surface opposite to the main surface MS3a. The main surface MS3a and the main surface MS3b are end surfaces in the thickness direction of the semiconductor substrate SUB3. The semiconductor substrate SUB3 is made of single crystal silicon. The main surface MS3a is configured, for example, as the (110), (111), (112), or (211) plane of the single crystal silicon. However, the crystal plane of the single crystal silicon that configures the main surface MS3a is not limited to this.

[0047] The interplanar spacing between two adjacent crystal planes parallel to the main surface MS3a of the semiconductor substrate SUB3 is smaller than the interplanar spacing between two adjacent crystal planes parallel to the main surface MS1a of the semiconductor substrate SUB1 and the interplanar spacing between two adjacent crystal planes parallel to the main surface MS2a of the semiconductor substrate SUB2. As long as this relationship is satisfied, it is possible to appropriately select the crystal plane of the single crystal silicon that forms the main surface MS1a, the crystal plane of the single crystal silicon that forms the main surface MS2a, and the crystal plane of the single crystal silicon that forms the main surface MS3a.

[0048] The interplanar spacing between two adjacent (110) planes is 3.84 Å, the interplanar spacing between two adjacent (111) planes is 3.14 Å, the interplanar spacing between two adjacent (112) planes is 2.22 Å, and the interplanar spacing between two adjacent (211) planes is 2.22 Å. On the other hand, the interplanar spacing between two adjacent (100) planes is 5.43 Å.

[0049] The Young's modulus of the semiconductor substrate SUB1 in a direction parallel to the main surface MS3a is greater than the Young's modulus of the semiconductor substrate SUB1 in a direction parallel to the main surface MS1a and the Young's modulus of the semiconductor substrate SUB2 in a direction parallel to the main surface MS2a. The Young's modulus of the single crystal silicon in a direction parallel to the (100) plane is 130 GPa. The Young's modulus of the single crystal silicon in a direction parallel to the (110) plane is 170 GPa, and the Young's modulus of the single crystal silicon in a direction parallel to the (111) plane is 189 GPa.

[0050] The interlayer insulating film ILD3a is formed on the main surface MS3a. Although not shown, a contact hole CH3 is formed in the interlayer insulating film ILD3a. A contact plug CP3 (not shown) is buried in the contact hole CH3. The contact plug CP3 is connected to the main surface MS3a. The interlayer insulating film ILD3a is made of, for example, silicon oxide. The contact plug CP3 is made of, for example, tungsten.

[0051] The wiring layer WL3a is formed on the interlayer insulating film ILD3a. Although not shown, the wiring layer WL3a is electrically connected to the contact plug CP3. The wiring layer WL3a is made of, for example, aluminum or an aluminum alloy.

[0052] A plurality of interlayer insulating films ILD3b are stacked on the interlayer insulating film ILD3a. The interlayer insulating film ILD3b is formed of, for example, silicon oxide. The lowermost interlayer insulating film ILD3b covers the wiring layer WL3a. One wiring layer WL3b is formed on one interlayer insulating film ILD3b, and another interlayer insulating film ILD3b is formed on the interlayer insulating film ILD3b so as to cover the wiring layer WL3b. However, the uppermost wiring layer WL3b is not covered by the interlayer insulating film ILD3b. One wiring layer WL3a and another wiring layer WL3b above the one wiring layer WL3a are electrically connected by a via plug VP3. The via plug VP3 is embedded in a via hole VH3 formed in the interlayer insulating film ILD3b. The wiring layer WL3b is formed of, for example, aluminum or an aluminum alloy. The via plug VP3 is formed of, for example, tungsten.

[0053] The uppermost wiring layer WL2b has an electrode pad PD3a, an electrode pad PD3b, an electrode pad PD3c, an electrode pad PD3d, an electrode pad PD3e, an electrode pad PD3f, an electrode pad PD3g, an electrode pad PD3h, an electrode pad PD3i, and an electrode pad PD3j.

[0054] The passivation film PV3 is formed on the uppermost interlayer insulating film ILD3b so as to cover the uppermost wiring layer WL3b. Openings are formed in the passivation film PV3. Electrode pads (electrode pads PD3a to PD3j) of the uppermost wiring layer WL3b are exposed through the openings in the passivation film PV3. The passivation film PV3 is made of, for example, silicon nitride.

[0055] The lowermost wiring layer WL3b has a transmitter coil CL1, a receiver coil CL4, and lead-out wiring PL2. The lowermost wiring layer WL3b further has wiring WL3ba, wiring WL3bb, wiring WL3bc, and wiring WL3bd. The transmitter coil CL1 and receiver coil CL4 are aligned along the first direction DR1 in a plan view (when the semiconductor chip CHP3 is viewed along the normal direction to the main surface MS3a).

[0056] The coils CL11 and CL12 are aligned along the first direction DR1 in plan view. The coils CL11 and CL12 are spirally wound in plan view. The coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL12 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL11 is connected to the outermost end of the coil CL12. From another perspective, the coils CL11 and CL12 have a serial aiding configuration.

[0057] The coils CL41 and CL42 are aligned along the first direction DR1 in plan view. The coils CL41 and CL42 are spirally wound in plan view. The coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL42 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL41 is connected to the outermost end of the coil CL42 via one end of the lead-out wiring PL2. From another perspective, the coils CL41 and CL42 are configured in a series mutually complementary manner.

[0058] The lead wiring PL2 extends in a second direction DR2, which is perpendicular to the first direction DR1.

[0059] The wiring WL3ba, wiring WL3bb, wiring WL3bc, and wiring WL3bd extend along the second direction DR2 in a plan view. One end of the wiring WL3ba in the second direction DR2 and one end of the wiring WL3bb in the second direction DR2 are adjacent to the coils CL11 and CL12, respectively. One end of the wiring WL3bc in the second direction DR2 and one end of the wiring WL3bd in the second direction DR2 are adjacent to the coils CL41 and CL42, respectively.

[0060] The wiring layer WL3a includes wirings WL3aa, WL3ab, WL3ac, and WL3ad. The wirings WL3aa, WL3ab, WL3ac, and WL3ad extend along the first direction DR1 in plan view.

[0061] One end and the other end of the wiring WL3aa in the first direction DR1 overlap one end of the wiring WL3ba and the innermost end of the coil CL11, respectively. One end and the other end of the wiring WL3ab in the first direction DR1 overlap one end of the wiring WL3bb and the innermost end of the coil CL12, respectively. One end and the other end of the wiring WL3ac in the first direction DR1 overlap one end of the wiring WL3bc and the innermost end of the coil CL41, respectively. One end and the other end of the wiring WL3ad in the first direction DR1 overlap one end of the wiring WL3bd and the innermost end of the coil CL42, respectively.

[0062] One end and the other end of the wiring WL3aa in the first direction DR1 are electrically connected to one end of the wiring WL3ba and the innermost end of the coil CL11 by via plugs VP3, respectively. One end and the other end of the wiring WL3ab in the first direction DR1 are electrically connected to one end of the wiring WL3bb and the innermost end of the coil CL12 by via plugs VP3, respectively. One end and the other end of the wiring WL3ac in the first direction DR1 are electrically connected to one end of the wiring WL3bc and the innermost end of the coil CL41 by via plugs VP3, respectively. One end and the other end of the wiring WL3ad in the first direction DR1 are electrically connected to one end of the wiring WL3bd and the innermost end of the coil CL42 by via plugs VP3, respectively.

[0063] The uppermost wiring layer WL3b further includes a receiver coil CL2, a transmitter coil CL3, a lead-out wiring PL1, and a guard ring GR. The lead-out wiring PL1 extends along the second direction DR2.

[0064] The receiver coil CL2 and the transmitter coil CL3 are aligned along the first direction DR1 in a plan view. The receiver coil CL2 and the transmitter coil CL3 overlap the transmitter coil CL1 and the receiver coil CL4, respectively, in a plan view. That is, the coils CL21 and CL22 face the coils CL11 and CL12, respectively, with an insulating layer (multiple interlayer insulating films ILD3b) therebetween, and the coils CL31 and CL32 face the coils CL41 and CL42, respectively, with an insulating layer (multiple interlayer insulating films ILD3b) therebetween. From another perspective, the coils CL21 and CL22 are magnetically coupled to the coils CL11 and CL12, respectively. Furthermore, the coils CL31 and CL32 are magnetically coupled to the coils CL41 and CL42, respectively.

[0065] The coils CL21 and CL22 are aligned along the first direction DR1 in plan view. The coils CL21 and CL22 are spirally wound in plan view. The coil CL21 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL22 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL21 is connected to the outermost end of the coil CL22 via one end of the lead-out wiring PL1. From another perspective, the coils CL21 and CL22 are configured in a series mutually complementary manner.

[0066] The coils CL31 and CL32 are aligned along the first direction DR1 in plan view. The coils CL31 and CL32 are spirally wound in plan view. The coil CL31 is wound counterclockwise from the innermost circumference to the outermost circumference. The coil CL32 is wound clockwise from the outermost circumference to the innermost circumference. The outermost end of the coil CL31 is connected to the outermost end of the coil CL32. From another perspective, the coils CL31 and CL32 are configured in a series mutually complementary configuration.

[0067] The electrode pads PD3a and PD3b are connected to the innermost ends of the coils CL21 and CL22, respectively. The electrode pads PD3c and PD3d are connected to the innermost ends of the coils CL31 and CL32, respectively.

[0068] The electrode pad PD3e is connected to one end of the lead-out wiring PL1. The electrode pad PD3f overlaps the other end of the lead-out wiring PL2 in a plan view. Although not shown, the electrode pad PD3f is electrically connected to the other end of the lead-out wiring PL2 by multiple wiring layers WL3b and via plugs VP3.

[0069] The electrode pads PD3g and PD3h overlap the other ends of the wiring WL2ba and WL2bb, respectively, in a plan view. Although not shown, the electrode pads PD3g and PD3h are electrically connected to the other ends of the wiring WL2ba and WL2bb, respectively, by multiple wiring layers WL2b and via plugs VP3. In this way, the electrode pads PD3g and PD3h are electrically connected to the transformer TR1 (transmitting coil CL1).

[0070] The electrode pads PD3i and PD3j overlap the other ends of the wiring WL2bc and WL2bd, respectively, in a plan view. Although not shown, the electrode pads PD3i and PD3j are electrically connected to the other ends of the wiring WL2bc and WL2bd, respectively, by multiple wiring layers WL2b and via plugs VP3. In this way, the electrode pads PD3i and PD3j are electrically connected to the transformer TR2 (receiving coil CL4).

[0071] The guard ring GR surrounds the receiver coil CL2 and the transmitter coil CL3 in a plan view. The electrode pad PD3e is connected to the guard ring GR. A reference potential is applied to the electrode pad PD3e. Therefore, the same reference potential is applied to the guard ring GR. A higher reference potential than that applied to the electrode pad PD3e is applied to the electrode pad PD3f.

[0072] <Method of manufacturing semiconductor chip CHP1> A method for manufacturing the semiconductor chip CHP1 will be described below.

[0073] 9 is a manufacturing process diagram of a semiconductor chip CHP1. As shown in FIG. 9, the manufacturing method of the semiconductor chip CHP1 includes a preparation step S1, an ion implantation step S2, a trench formation step S3, an element isolation film formation step S4, a gate insulating film formation step S5, a gate electrode formation step S6, an ion implantation step S7, a sidewall spacer formation step S8, and an ion implantation step S9. The manufacturing method of the semiconductor chip CHP3 further includes an interlayer insulating film formation step S10, a contact plug formation step S11, a wiring layer formation step S12, an interlayer insulating film formation step S13, a via plug formation step S14, a wiring layer formation step S15, and a passivation film formation step S16.

[0074] In the preparation step S1, a semiconductor substrate SUB1 is prepared. Fig. 10 is a cross-sectional view illustrating the ion implantation step S2. As shown in Fig. 10, in the ion implantation step S2, a well region WR1 is formed by ion implantation.

[0075] FIG. 11 is a cross-sectional view illustrating the groove forming step S3. As shown in FIG. 11, in the groove forming step S3, a groove TRN1 is formed in the main surface MS1a. In the groove forming step S3, first, a hard mask is formed on the main surface MS1a. The hard mask is, for example, a stacked film of an oxide film and a nitride film. Second, the hard mask is patterned. The hard mask is patterned by, for example, dry etching using a resist pattern formed on the hard mask. Third, dry etching is performed using the hard mask as a mask. In this way, the groove TRN1 is formed.

[0076] FIG. 12 is a cross-sectional view illustrating the element isolation film forming step S4. As shown in FIG. 12, in the element isolation film forming step S4, the element isolation film ISL1 is buried in the trench TRN1. In the element isolation film forming step S4, first, the constituent material of the element isolation film ISL1 is buried in the trench TRN1 by, for example, a CVD (Chemical Vapor Deposition) method. Second, the constituent material of the element isolation film ISL1 that protrudes from the trench TRN1 is removed by, for example, a CMP (Chemical Mechanical Polishing) method. At this time, the hard mask is also removed. In this manner, the element isolation film ISL1 is formed.

[0077] FIG. 13 is a cross-sectional view illustrating the gate insulating film forming step S5. As shown in FIG. 13, in the gate insulating film forming step S5, a gate insulating film GI1 is formed on the main surface MS1a, for example, by thermally oxidizing the main surface MS1a. FIG. 14 is a cross-sectional view illustrating the gate electrode forming step S6. As shown in FIG. 14, in the gate electrode forming step S6, a gate electrode GE1 is formed on the gate insulating film GI1. In the gate electrode forming step S6, first, a constituent material of the gate electrode GE1 is deposited on the gate insulating film GI1 by, for example, a CVD method. Second, the constituent material of the deposited gate electrode GE1 is patterned by etching using a resist pattern formed on the deposited gate electrode GE1 as a mask. In this manner, the gate electrode GE1 is formed.

[0078] FIG. 15 is a cross-sectional view illustrating the ion implantation step S7. In the ion implantation step S7, as shown in FIG. 15, first portions SR1a and DRA1a are formed by ion implantation. FIG. 16 is a cross-sectional view illustrating the sidewall spacer formation step S8. As shown in FIG. 16, in the sidewall spacer formation step S8, sidewall spacers SWS1 are formed on the main surface MS1a so as to contact the side surfaces of the gate insulating film GI1 and the gate electrode GE1. In the sidewall spacer formation step S8, first, a film of a material for the sidewall spacer SWS1 is formed by, for example, a CVD method so as to cover the gate insulating film GI1 and the gate electrode GE1. Second, the formed material for the sidewall spacer SWS1 is etched back, for example. In this manner, the sidewall spacer SWS1 is formed.

[0079] FIG. 17 is a cross-sectional view illustrating the ion implantation step S9. In the ion implantation step S9, as shown in FIG. 17, the second portion SR1b and the second portion DRA1b are formed by ion implantation. FIG. 18 is a cross-sectional view illustrating the interlayer insulating film formation step S10. As shown in FIG. 18, in the interlayer insulating film formation step S10, the interlayer insulating film ILD1a is formed on the main surface MS1a so as to cover the gate electrode GE1 and the sidewall spacers SWS1. In the interlayer insulating film formation step S10, first, a constituent material of the interlayer insulating film ILD1a is deposited by, for example, a CVD method so as to cover the gate electrode GE1 and the sidewall spacers SWS1. Second, the surface of the deposited interlayer insulating film ILD1a is planarized by, for example, a CMP method. In this manner, the interlayer insulating film ILD1a is formed.

[0080] FIG. 19 is a cross-sectional view illustrating the contact plug forming step S11. As shown in FIG. 19, in the contact plug forming step S11, a contact plug CP1 is buried in the interlayer insulating film ILD1a. In the contact plug forming step S11, first, a contact hole CH1 is formed by etching the interlayer insulating film ILD1a using a resist pattern formed on the interlayer insulating film ILD1a as a mask. Second, a constituent material of the contact plug CP1 is buried in the contact plug CP1 by, for example, a CVD method. Third, the constituent material of the contact plug CP1 that protrudes from the contact hole CH1 is removed by, for example, a CMP method. In this manner, the contact plug CP1 is formed.

[0081] FIG. 20 is a cross-sectional view illustrating the wiring layer forming step S12. As shown in FIG. 20, in the wiring layer forming step S12, a wiring layer WL1a is formed on an interlayer insulating film ILD1a. In the wiring layer forming step S12, first, a constituent material of the wiring layer WL1a is deposited on the interlayer insulating film ILD1a by, for example, sputtering. Second, a resist pattern is formed on the deposited constituent material of the wiring layer WL1a. Third, the constituent material of the wiring layer WL1a is etched using the resist pattern as a mask. In this manner, the wiring layer WL1a is formed.

[0082] FIG. 21 is a cross-sectional view illustrating the interlayer insulating film forming step S13. As shown in FIG. 21, in the interlayer insulating film forming step S13, an interlayer insulating film ILD1b is formed on the interlayer insulating film ILD1a so as to cover the wiring layer WL1a by the same method as in the interlayer insulating film forming step S10. FIG. 22 is a cross-sectional view illustrating the via plug forming step S14. As shown in FIG. 22, in the via plug forming step S14, a via hole VH1 is formed in the interlayer insulating film ILD1b by the same method as in the contact plug forming step S11, and a via plug VP1 is embedded in the via hole VH1. FIG. 23 is a cross-sectional view illustrating the wiring layer forming step S15. As shown in FIG. 23, in the wiring layer forming step S15, a wiring layer WL1b is formed on the interlayer insulating film ILD1b by the same method as in the wiring layer forming step S12. Thereafter, the interlayer insulating film forming step S13, the via plug forming step S14, and the wiring layer forming step S15 are sequentially repeated until the uppermost wiring layer WL1b is formed.

[0083] In the passivation film formation process S16, a passivation film PV1 is formed on the uppermost interlayer insulating film ILD1b so as to cover the uppermost wiring layer WL1b. In the passivation film formation process S16, first, a constituent material of the passivation film PV1 is formed on the uppermost interlayer insulating film ILD1b so as to cover the uppermost wiring layer WL1b. Second, a resist pattern is formed on the constituent material of the passivation film PV1. Third, the constituent material of the passivation film PV1 is etched using the resist pattern as a mask, thereby forming openings that expose the electrode pads PD1. As a result of the above, the structure of the semiconductor chip CHP1 shown in FIG. 3 is formed.

[0084] <Method of manufacturing semiconductor chips CHP2 and CHP3> A method for manufacturing the semiconductor chips CHP2 and CHP3 will be described below.

[0085] The manufacturing method of the semiconductor chip CHP2 is the same as the manufacturing method of the semiconductor chip CHP1. The manufacturing method of the semiconductor chip CHP3 is the same as the manufacturing method of the semiconductor chip CHP1. However, in the manufacturing method of the semiconductor chip CHP3, the ion implantation step S2, the trench formation step S3, the element isolation film formation step S4, the gate insulating film formation step S5, the gate electrode formation step S6, the ion implantation step S7, the sidewall spacer formation step S8, and the ion implantation step S9 are not performed.

[0086] <Effects of semiconductor device DEV> 24 is a schematic graph showing the relationship between the stage of progress in the manufacturing process and the amount of warpage in the semiconductor chip CHP3. As shown in FIG. 24, the amount of wafer warpage decreases each time a wiring layer is formed, but overall the amount of wafer warpage increases as the manufacturing process progresses. In the semiconductor chip CHP3, the area occupied by the wiring layers in a plan view is smaller than in the semiconductor chips CHP1 and CHP2, so the correction of warpage accompanying the formation of the wiring layers is weaker, and the amount of wafer warpage is likely to increase.

[0087] In this regard, in the semiconductor chip CHP3, the plane spacing between two adjacent crystal planes parallel to the main surface MS3a in the semiconductor substrate SUB3 is smaller than the plane spacing between two adjacent crystal planes parallel to the main surface MS1a in the semiconductor substrate SUB1 and the plane spacing between two adjacent crystal planes parallel to the main surface MS2a in the semiconductor substrate SUB2. As a result, in the semiconductor chip CHP3, the Young's modulus of the semiconductor substrate SUB1 in the direction parallel to the main surface MS3a is larger than the Young's modulus of the semiconductor substrate SUB1 in the direction parallel to the main surface MS1a and the Young's modulus of the semiconductor substrate SUB2 in the direction parallel to the main surface MS2a, and warpage is suppressed.

[0088] In the semiconductor chip CHP1 (semiconductor chip CHP2), transistors, which are active elements, are formed on the main surface MS1a (main surface MS2a), so it is preferable that the main surface MS1a (main surface MS2a) be a crystal plane with high electron mobility, such as the (100) plane. On the other hand, in the semiconductor chip CHP3, transistors are not formed on the main surface MS3a, and passive elements (transformers TR1 and TR2) are formed above the main surface MS3a, so it is not necessary for the main surface MS3a to be a crystal plane with high electron mobility. In this way, the semiconductor device DEV can maintain electrical characteristics while suppressing warpage of the semiconductor chip CHP3.

[0089] Increasing the thickness of the insulating layer between the transmitter coil CL1 and the receiver coil CL2 (between the transmitter coil CL3 and the receiver coil CL4) is an effective way to improve the dielectric strength of the semiconductor chip CHP3. However, increasing the thickness of this insulating layer (increasing the number of stacked interlayer insulating films ILD3b) increases warpage. In the semiconductor chip CHP3, because the Young's modulus of the semiconductor substrate SUB3 in the direction parallel to the main surface MS3a is high, warpage is unlikely to occur even if the thickness of this insulating layer is increased, and it is possible to improve the dielectric strength between the transmitter coil CL1 and the receiver coil CL2 (between the transmitter coil CL3 and the receiver coil CL4).

[0090] <Variation 1> 25 is a cross-sectional view of a semiconductor chip CHP3 included in the semiconductor device DEV according to Modification 1. As shown in FIG. 25, the semiconductor chip CHP3 may further include an epitaxial layer EPI. The epitaxial layer EPI may be formed on at least one of the main surface MS3a and the main surface MS3b. A polycrystalline silicon layer POL may be formed instead of the epitaxial layer EPI. A silicon oxide film SOF may be formed instead of the epitaxial layer EPI. The silicon oxide film SOF is, for example, a film obtained by oxidizing a polycrystalline silicon film. By forming the epitaxial layer EPI, the polycrystalline silicon layer POL, or the silicon oxide film SOF in this manner, the semiconductor substrate SUB3 is substantially thicker, thereby making it possible to further reduce warpage.

[0091] <Variation 2> In the above description, the transformer TR1 (transformer TR2) is configured with coils facing each other with an insulating layer interposed therebetween, but the transformer TR1 (transformer TR2) is not limited to this. For example, instead of the transmitter coil CL1 (transmitter coil CL3) and the receiver coil CL2 (receive coil CL4), the transformer TR1 (transformer TR2) may be configured with a capacitor configured with a pair of electrode plates facing each other with an insulating layer interposed therebetween.

[0092] (Second embodiment) A semiconductor package according to a second embodiment will be described below. The semiconductor package according to the second embodiment will be referred to as a semiconductor package PKG.

[0093] <Configuration of semiconductor package PKG> The configuration of the semiconductor package PKG will be described below.

[0094] 26 is a cross-sectional view of the semiconductor package PKG. As shown in Fig. 26, the semiconductor package PKG includes a lead frame LF, semiconductor chips CHP1, CHP2, and CHP3, bonding wires BW1 and BW2, and sealing resin MR.

[0095] The semiconductor chip CHP1 is disposed on the lead frame LF such that its main surface MS1b faces the lead frame LF with a bonding material CM interposed therebetween. Similarly, the semiconductor chip CHP2 is disposed on the lead frame LF such that its main surface MS2b faces the lead frame LF with a bonding material CM interposed therebetween, and the semiconductor chip CHP3 is disposed on the lead frame LF such that its main surface MS3b faces the lead frame LF with a bonding material CM interposed therebetween. The thicknesses of the semiconductor chip CHP1, the semiconductor chip CHP2, and the semiconductor chip CHP3 are preferably equal to one another. Note that the thicknesses of the semiconductor chip CHP1, the semiconductor chip CHP2, and the semiconductor chip CHP3 can be considered equal to one another if any two of them are within a range of ±10 percent of the other one.

[0096] It is preferable that the height positions of the electrode pads PD1 and PD2 and the electrode pads of the semiconductor chip CHP3 (electrode pads PD3a, PD3b, PD3c, PD3d, PD3g, PD3h, PD3i, and PD3j) are equal to one another. Note that the height positions of the electrode pads PD1 and PD2 and the electrode pads of the semiconductor chip CHP3 can be considered equal to one another if any two of them are within a range of ±30 μm from the other one.

[0097] The bonding wire BW1 is electrically connected at one end to the electrode pads (electrode pads PD3c, PD3d, PD3g, and PD3h) of the semiconductor chip CHP3, and at the other end to the electrode pad PD1. The bonding wire BW2 is electrically connected at one end to the electrode pads PD3a, PD3b, PD3i, and PD3j of the semiconductor chip CHP3, and at the other end to the electrode pad PD2. This allows the semiconductor package PKG to function as a semiconductor device DEV.

[0098] The sealing resin MR seals the lead frame LF, the bonding wires BW1 and BW2, the semiconductor chips CHP1, CHP2, and CHP3, with the terminals of the lead frame LF exposed from the sealing resin MF.

[0099] <Effects of semiconductor package PKG> The effects of the semiconductor package PKG will be explained below.

[0100] In the semiconductor chip CHP3, the Young's modulus of the semiconductor substrate SUB1 in the direction parallel to the main surface MS3a is greater than the Young's modulus of the semiconductor substrate SUB1 in the direction parallel to the main surface MS1a and the Young's modulus of the semiconductor substrate SUB2 in the direction parallel to the main surface MS2a, so there is no need to make the semiconductor chip CHP3 thicker than the semiconductor chips CHP1 and CHP2 that suppress warpage, and the thickness of the semiconductor chip CHP3 can be made equal to the thickness of the semiconductor chip CHP1 and the thickness of the semiconductor chip CHP2. Therefore, the semiconductor package PKG can reduce the thickness of the package.

[0101] In addition, in the semiconductor package PKG, the thickness of the semiconductor chip CHP3 can be made equal to the thickness of the semiconductor chip CHP1 and the thickness of the semiconductor chip CHP2, so that the height positions of the electrode pads PD1, PD2, and the electrode pads of the semiconductor chip CHP3 can be made equal to one another, which makes it possible to easily perform wire bonding using the bonding wires BW1 and BW2.

[0102] (Third embodiment) An inverter system according to a third embodiment will be described below, which will be referred to as inverter system INVS.

[0103] Fig. 27 is a schematic diagram of an inverter system INVS. As shown in Fig. 27, the inverter system INVS has an inverter circuit INVC and a semiconductor device DEV. The inverter circuit INVC has a power semiconductor element PWSE. The power semiconductor element PWSE is, for example, an IGBT (Insulated Gate Bipolar Transistor). However, the power semiconductor element PWSE is not limited to this.

[0104] The control terminal (gate electrode) of the power semiconductor element PWSE is connected to the drive circuit DR of the semiconductor device DEV (semiconductor chip CHP2), and the on / off of the power semiconductor element PWSE is controlled by a signal generated in the drive circuit DR, thereby performing the switching operation of the inverter circuit INVC.

[0105] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0106] BW1, BW2 bonding wires, CH1, CH2, CH3 contact holes, CHP1, CHP2, CHP3 semiconductor chips, CL1, CL3 transmitting coils, CL2, CL4 receiving coils, CL11, CL12, CL21, CL22, CL31, CL32, CL41, CL42 coils, CP1, CP2, CP3 contact plugs, DEV, DEV semiconductor device, DR drive circuit, DR1 first direction, DR2 second direction, DRA1a, DRA2a, SR1a, SR2a first portion, DRA1b, DRA2b, SR1b, SR2b second portion, DRA1, DRA2 drain regions, EPI epitaxial layer, GE1 gate electrode, GE2 gate electrode, GI1, GI2 gate insulating film, GR guard ring, ILD1a, ILD1b, ILD2b, ILD2a, ILD3a, ILD3b Interlayer insulating film, INVC inverter circuit, INVS inverter system, ISL1, ISL2 element isolation film, LF lead frame, MF, MR sealing resin, MS1b, MS1a, MS2a, MS2b, MS3a, MS3b main surface, PD1, PD2, PD3h, PD3j, PD3i, PD3f, PD3a, PD3b, PD3g, PD3c, PD3d, PD3e electrode pads, PL1 lead wiring, PL2 lead wiring, POL polycrystalline silicon layer, PV1, PV2, PV3 passivation film, PWSE power semiconductor element, RX1 receiver circuit, RX2 receiver circuit, S1 preparation process, S2 ion implantation process, S3 trench formation process, S4 element isolation film formation process, S5 gate insulating film formation process, S6 gate electrode formation process, S7 ion implantation process, S8 sidewall spacer formation process, S9 ion implantation process, S10 Interlayer insulating film forming process, S11 contact plug forming process, S12 wiring layer forming process, S13 interlayer insulating film forming process, S14 via plug forming process, S15 wiring layer forming process, S16 passivation film forming process, SG1, SG2, SG3, SG4 signal, SR1, SR2 source region, SUB1, SUB2, SUB3 semiconductor substrate, SOF silicon oxide film, SWS1, SWS2 sidewall spacer, TR1 transformer, TR2 transformer, TRN1, TRN2 trench, TX1, TX2 transmitter circuit, VH1, VH2, VH3 via hole, VP1, VP2,VP3 via plug, WL1b, WL1a, WL2b, WL2a, WL3b, WL3a wiring layers, WL2ba, WL2bb, WL2bc, WL2bd, WL3ba, WL3ab, WL3ad, WL3bd, WL3bc, WL3bb, WL3aa wiring, WR1, WR2 well area.

Claims

1. a first semiconductor chip; a second semiconductor chip; a third semiconductor chip; a signal is transmitted and received between the first semiconductor chip and the second semiconductor chip by non-contact communication between different potentials in the third semiconductor chip; the first semiconductor chip has a first semiconductor substrate and a first active element; the first semiconductor substrate has a first main surface; the first active element is formed on the first main surface, the second semiconductor chip has a second semiconductor substrate and a second active element; the second semiconductor substrate has a second main surface; the second active element is formed on the second main surface, the third semiconductor chip has a third semiconductor substrate and a passive element; the third semiconductor substrate has a third main surface; the passive element is formed above the third main surface, each of the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate is formed of single crystal silicon; a plane spacing between two adjacent crystal planes parallel to the third main surface in the third semiconductor substrate is smaller than a plane spacing between two adjacent crystal planes parallel to the first main surface in the first semiconductor substrate and a plane spacing between two adjacent crystal planes parallel to the second main surface in the second semiconductor substrate.

2. 2. The semiconductor device according to claim 1, wherein a crystal plane parallel to the third main surface of the third semiconductor substrate is different from a crystal plane parallel to the first main surface of the first semiconductor substrate and a crystal plane parallel to the second main surface of the second semiconductor substrate.

3. a crystal plane parallel to the first main surface of the first semiconductor substrate and a crystal plane parallel to the second main surface of the second semiconductor substrate are (100) planes, 3. The semiconductor device according to claim 2, wherein a crystal plane parallel to said third main surface of said third semiconductor substrate is a (111) plane or a (110) plane.

4. the first active element and the second active element are transistors, The semiconductor device according to claim 1 , wherein the passive element is a transformer for performing contactless communication between different potentials.

5. the transformer includes a first coil, a second coil, and an insulating layer; The semiconductor device according to claim 4 , wherein the first coil and the second coil are arranged opposite to each other with the insulating layer interposed therebetween, and are thereby magnetically coupled to each other.

6. the transformer has a first plate, a second plate, and an insulating layer; 5. The semiconductor device according to claim 4, wherein the first electrode plate and the second electrode plate are disposed opposite each other with the insulating layer interposed therebetween, and are thereby capacitively coupled to each other.

7. The semiconductor device according to claim 1 , wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip have the same thickness.

8. 8. The semiconductor device according to claim 7, wherein the thickness of the first semiconductor chip, the thickness of the second semiconductor chip, and the thickness of the third semiconductor chip are not less than 150 [mu]m and not more than 450 [mu]m.

9. the third semiconductor substrate has a fourth main surface that is the surface opposite to the third main surface, the third semiconductor chip further includes an epitaxial layer; 2. The semiconductor device according to claim 1, wherein said epitaxial layer is formed on at least one of said third main surface and said fourth main surface.

10. the third semiconductor substrate has a fourth main surface that is the surface opposite to the third main surface, the third semiconductor chip further includes a polycrystalline silicon layer; 2. The semiconductor device according to claim 1, wherein said polycrystalline silicon layer is formed on at least one of said third main surface and said fourth main surface.

11. the third semiconductor substrate has a fourth main surface that is the surface opposite to the third main surface, the third semiconductor chip further includes a silicon oxide film; 2. The semiconductor device according to claim 1, wherein said silicon oxide film is formed on at least one of said third main surface and said fourth main surface.

12. 2. The semiconductor device according to claim 1, wherein a Young's modulus of the third semiconductor substrate in a direction parallel to the third main surface is greater than a Young's modulus of the first semiconductor substrate in a direction parallel to the first main surface and a Young's modulus of the second semiconductor substrate in a direction parallel to the second main surface.

13. a first semiconductor chip; a second semiconductor chip; a third semiconductor chip; a first bonding wire; a second bonding wire; the first semiconductor chip has a first circuit and a first pad electrode electrically connected to the first circuit; the first circuit includes a first active element; the second semiconductor chip has a second circuit and a second pad electrode electrically connected to the second circuit; the second circuit includes a second active element; the third semiconductor chip has a transformer, and third and fourth pad electrodes electrically connected to the transformer; the transformer has an active element; the first bonding wire electrically connects the first pad electrode and the third pad electrode; the second bonding wire electrically connects the second pad electrode and the fourth pad electrode; A semiconductor package, wherein the height positions of the surfaces of the first pad electrode, the second pad electrode, the third pad electrode, and the fourth pad electrode are equal to one another.

14. an inverter circuit; a first semiconductor chip; a second semiconductor chip; a third semiconductor chip; the inverter circuit has a power semiconductor element, the first semiconductor chip has a first semiconductor substrate and a first circuit; the first semiconductor substrate has a first main surface; the first circuit includes a first active element; the first active element is formed on the first main surface, the second semiconductor chip has a second semiconductor substrate, a second circuit, and a third circuit; the second semiconductor substrate has a second main surface; the second circuit and the third circuit each include a second active element; the second active element is formed on the second main surface, the third semiconductor chip includes a third semiconductor substrate and a transformer; the third semiconductor substrate has a third main surface; the transformer has a passive element; the passive element is formed above the third main surface, a signal is transmitted from the first circuit to the second circuit by non-contact communication between different potentials in the transformer; the third circuit drives the power semiconductor device based on the signal transmitted to the second circuit; each of the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate is formed of single crystal silicon; an interplanar spacing between two adjacent crystal planes parallel to the third main surface in the third semiconductor substrate is smaller than an interplanar spacing between two adjacent crystal planes parallel to the first main surface in the first semiconductor substrate and an interplanar spacing between two adjacent crystal planes parallel to the second main surface in the second semiconductor substrate.

Images