Photoelectric conversion device and apparatus using photoelectric conversion device

Abstract

To provide a technique, in performing analog-to-digital (AD) conversion of pixel signals by amplifying the signals with different gains, which is advantageous for reducing noise generated in the AD conversion.SOLUTION: A photoelectric conversion device has: first pixels; an AD conversion circuit that performs AD conversion of signals from the first pixels; a reference signal generation circuit that generates a first reference signal in which voltage monotonously changes relative to time at a first rate of change, and a second reference signal in which voltage monotonously changes relative to time at a second rate of change smaller than the first rate of change; and a control circuit. The AD conversion circuit has a first comparison circuit to which two signals, namely, the signal from the first pixel and the first reference signal are input, and a second comparison circuit to which two signals, namely, the signal from the first pixel and the second reference signal are input. The control circuit applies first offset voltage between the signals input to the first comparison circuit, and applies second offset voltage between the signals input to the second comparison circuit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus using the photoelectric conversion device. [Background technology]

[0002] Patent Document 1 describes a photoelectric conversion device that simultaneously outputs pixel signals with different gains by providing two variable gain amplifiers and two signal processing circuits downstream of the variable gain amplifiers for one vertical output line. There are two comparison circuits for one pixel column. It is described that this configuration can expand the dynamic range. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-135815 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration described in Patent Document 1, there is a possibility that comparator circuits corresponding to different gains may change simultaneously, which may cause power supply fluctuations, and the fluctuations may propagate to other signal lines, causing noise in the analog-to-digital conversion of pixel signals.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a technique that is advantageous for reducing noise generated during analog-to-digital (AD) conversion when pixel signals are amplified by different gains and then converted into AD. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention is a photoelectric conversion device having a first pixel, a first analog-to-digital conversion circuit that performs analog-to-digital conversion on a signal from the first pixel, a reference signal generation circuit that generates a first reference signal whose voltage changes monotonically with time at a first rate of change and a second reference signal whose voltage changes monotonically with time at a second rate of change smaller than the first rate of change, and a control circuit, wherein the first analog-to-digital conversion circuit has a first comparison circuit to which two signals, the signal from the first pixel and the first reference signal, are input, and a second comparison circuit to which two signals, the signal from the first pixel and the second reference signal, are input, and the control circuit applies a first offset voltage between the signals input to the first comparison circuit and a second offset voltage between the signals input to the second comparison circuit prior to the analog-to-digital conversion, and sets the first offset voltage and the second offset voltage so that the product of the reciprocal of the first rate of change and the first offset voltage is smaller than the product of the reciprocal of the second rate of change and the second offset voltage. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technique that is advantageous for reducing noise generated during analog-to-digital (AD) conversion when pixel signals are amplified with different gains and then converted. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to the present invention. [Figure 2] 1 is a circuit diagram showing an example of the configuration of an analog-to-digital (AD) conversion circuit according to a first embodiment. [Figure 3] FIG. 2 is a drive timing chart of the AD conversion circuit according to the first embodiment. [Figure 4] FIG. 10 is a circuit diagram showing an example of the configuration of an AD conversion circuit according to a second embodiment. [Figure 5] FIG. 10 is a drive timing chart of the AD conversion circuit according to the second embodiment. [Figure 6]FIG. 10 is a circuit diagram showing an example of the configuration of an AD conversion circuit according to a third embodiment. [Figure 7] FIG. 10 is a drive timing chart of the AD conversion circuit according to the third embodiment. [Figure 8] 1A to 1C are diagrams illustrating application of a photoelectric conversion device according to an embodiment to equipment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the embodiments are not limited to image pickup devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measurement device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometry device (a device that measures the amount of incident light) can be used.

[0011] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0012] (First embodiment) The schematic configuration of the photoelectric conversion device of this embodiment will be described with reference to the block diagram of FIG. 1. The photoelectric conversion device 100 has a pixel array section 104 in which a plurality of unit pixels 101 are arranged in a matrix. The pixel array section 104 can include vertical signal lines 102 provided for each column of the unit pixels 101 and row control lines 103 provided for each row of the unit pixels 101. The photoelectric conversion device 100 can further include a vertical scanning circuit 105 that controls the row control lines 103 and a comparison circuit section 106 that compares pixel signals read from the vertical signal lines 102 with a reference signal, which will be described later. The photoelectric conversion device 100 can also include a counter circuit 109 and a memory circuit 107 that stores the count value of the counter circuit 109 based on the comparison result of the comparison circuit section 106.

[0013] The photoelectric conversion device may also include a reference signal generation circuit 108 that provides a reference signal serving as a reference for comparison to the comparison circuit unit 106, and a signal processing circuit 110 that processes the output of the memory circuit 107. The photoelectric conversion device 100 may further include a horizontal scanning circuit 111 for reading data from the memory, an output circuit 113 that can output the processing results of the signal processing circuit 110 to the outside, and a control circuit 112 that controls the entire device.

[0014] The unit pixel 101 may include a pixel circuit (not shown) that may include a photoelectric conversion element, a transfer transistor, a floating diffusion (hereinafter referred to as FD), a source follower circuit, and a selection transistor. The photoelectric conversion element can convert incident light into an electric charge corresponding to the amount of incident light. The transfer transistor can transfer the converted electric charge to the FD. The electric charge transferred to the FD can be read out from the pixel circuit as a pixel signal voltage (hereinafter referred to as pixel signal) via the source follower circuit and the selection transistor. The pixel circuit may also be configured to output a reset level voltage when the pixel circuit is reset.

[0015] The row control lines 103 can be provided for each row of the unit pixels 101 arranged in a matrix. The vertical scanning circuit 105 controls the row control lines 103 provided for each row to control the unit pixels 101 arranged in the row, thereby sequentially selecting the unit pixels 101 row by row. The vertical signal lines 102 can be provided for each column of the unit pixels 101 arranged in a matrix. The pixel signals of the unit pixels 101 in the row selected from the vertical scanning circuit 105 via the row control lines 103 are output to the vertical signal lines 102 and can be input to the comparison circuit unit 106.

[0016] The pixel signal readout operation includes two periods. The first period is an N signal output period in which a noise signal voltage (hereinafter referred to as an N signal) of a reset level when the unit pixel 101 is reset before the charge accumulated by incident light is transferred is read out. The other period is an S signal output period in which a photoelectric conversion signal voltage (hereinafter referred to as an S signal) including the N signal is read out after the charge accumulated by incident light is transferred. The N signal and S signal are output as pixel signals having voltages to the vertical signal line 102 in response to a control signal from the vertical scanning circuit 105. The N signal and S signal output to the vertical signal line 102 are then input to an analog-to-digital conversion circuit and converted into digital signals. The reset operation in the vertical scanning circuit 105 and the unit pixel 101 and the charge accumulation by incident light can be performed at predetermined timing under the control of the control circuit 112.

[0017] Next, analog-to-digital conversion will be described. Pixel signals output from the vertical signal lines 102 are input to a comparison circuit unit 106 of the analog-to-digital conversion circuit. A reference signal generation circuit 108 generates and outputs a reference signal during each period in which the N signal and the S signal are output. The reference signal is input in common to each of the comparison circuit units 106, which are made up of multiple column circuits including multiple comparison circuits provided for each column. Each of the multiple comparison circuits compares the pixel signal from the vertical signal line 102 with the reference signal generated by the reference signal generation circuit 108. Note that a configuration may be adopted in which two or more types of reference signals can be generated, and one of the multiple reference signals is selected and input to each comparison circuit.

[0018] The output signal of the counter circuit 109 is input to a memory circuit 107, which counts up the amount of time from the start time of the comparison operation performed by the comparison circuit unit 106 to the time the output of the comparison circuit changes. The comparison circuit unit 106 outputs a comparison result when the reference signal and the pixel signal match or one exceeds the other. At this timing, the count value is stored in the memory circuit 107. As a result, the analog S signal and N signal are analog-to-digital converted (hereinafter referred to as AD conversion) into digital signals based on their respective count values, and the digital signals can be stored in the memory circuit 107 for each pixel.

[0019] The values ​​held for each column in the memory circuit 107 are output to the signal processing circuit 110 in order, row by row, in accordance with a control signal output from the horizontal scanning circuit 111. The signal processing circuit 110 performs so-called correlated double sampling (CDS), for example, subtracting the N signal from the S signal for each pixel, to remove noise signals. The signals processed by the signal processing circuit 110 are read out to the outside by the output circuit 113 as image signals.

[0020] The control circuit 112 can control the timing and operation of the vertical scanning circuit 105, the reference signal generation circuit 108, the counter circuit 109, the signal processing circuit 110, and the horizontal scanning circuit 111. Note that the configuration described in this embodiment is merely an example. For example, the signal output to the vertical signal line 102 may be amplified by a column amplifier provided for each column and then input to the comparison circuit unit 106. Furthermore, although the counter circuit 109 is an up-counter that counts up, it may also be a down-counter. Furthermore, the memory circuit 107 may be configured to subtract the N signal from the S signal and store the difference between the S signal and the N signal.

[0021] Next, the circuit operation of the comparison circuit unit 106 according to this embodiment will be described in detail with reference to FIGS. 2 and 3. FIG. 2 shows an example of the configuration of the comparison circuit unit 106 according to this embodiment. In this embodiment, a pixel signal output to one vertical signal line 102 is simultaneously input to the negative input terminals of comparison circuits 203L and 203H, each having a differential pair of inputs, via an input capacitor 201AL and an input capacitor 201AH. Meanwhile, a reference signal VrampL is input to the positive input terminal of the comparison circuit 203L via an input capacitor 201BL, and a reference signal VrampH is input to the positive input terminal of the comparison circuit 203H via an input capacitor 201BH.

[0022] A feature of this configuration is that two adjacent comparison circuits 203L and 203H simultaneously receive an image signal from one vertical signal line 102 and compare it with different reference signals VrampH and VrampL. That is, for the same pixel signal, the amount of time from the start of comparison to the time the output of the comparison circuits 203L and 203H changes can be made different. Therefore, the same pixel signal is AD converted based on the respective amount of time, resulting in a configuration in which the same pixel signal is converted to different digital values ​​and read out. In other words, this means that it is now possible to read out the signal at different gains. Reading out the signal at different gains ensures a good S / N ratio. Furthermore, the dynamic range can be expanded.

[0023] In the following description, the input capacitance 201AL and the input capacitance 201AH are referred to as input capacitance 201A when they are not limited to either one, and the input capacitance 201BL and the input capacitance 201BH are referred to as input capacitance 201B when they are not limited to either one. Furthermore, the reference signal VrampL and the reference signal VrampH are referred to as reference signal Vramp when they are not limited to either one, and the comparison circuit 203L and the comparison circuit 203H are referred to as comparison circuit 203 when they are not limited to either one.

[0024] One of the drain or source of switch 202A, which can be configured as a MOS transistor, is connected to the negative input terminal of comparison circuit 203 to which input capacitor 201A is connected, and the other drain or source is connected to the output terminal of comparison circuit 203. Similarly, one of the drain or source of switch 202B is connected to the positive input terminal of comparison circuit 203 to which input capacitor 201B is connected, and the other drain or source is connected to the output terminal of comparison circuit 203.

[0025] The control signals φRES1 and φRES2 are control signals connected to the gates of the switches 202A and 202B. Prior to analog-to-digital conversion, the comparator circuits 203L and 203H are reset based on control signals transmitted from the control circuit 112. Details of the reset operation of the comparator circuits 203L and 203H will be described later with reference to FIG.

[0026] In this embodiment, the two comparison circuits 203L and 203H are controlled by different control signals φRES1 and φRES2, but they may be controlled by the same control signal. For the sake of explanation, the control signal φRES1 and the control signal φRES2 will be referred to as the control signal φRES when they are not limited to one of them.

[0027] Next, the comparison operation will be described with reference to a timing chart showing the comparison operation of the comparison circuit 203 constituting the comparison circuit unit 106 and the output of the comparison circuit. The N signal output period and S signal output period shown in Fig. 3(a) indicate periods in which the N signal and the S signal are read out and AD converted when the selected unit pixel 101 outputs the N signal and the S signal to the vertical signal line 102, respectively. Note that one frame of image can be read out by repeating this readout and AD conversion for the number of rows in one frame.

[0028] The vertical line signal potential PixSig indicates a pixel signal output from the same unit pixel 101. The vertical line signal potential PixSig indicates a change over time in the potential of the vertical signal line 102. Furthermore, the reference signal Vramp indicates a change over time in the potential of two types of reference signals, the reference signal VrampL and the reference signal VrampH.

[0029] Next, the comparison operation of the comparator circuit 203 will be described with reference to the timing chart of FIG. 3(a). First, before time t301, the reference signals VrampL and VrampH are changed from the potential Vp at the start of the read operation to potentials VL0 and VH0, respectively, which are lower than the potential Vp. In this embodiment, the potential VL0 is set to a voltage lower than the potential VH0. The absolute value of the amount of change in these two potentials is defined as an offset voltage ΔVoffset.

[0030] In FIG. 3(a), the offset voltage for the reference signal VrampL is shown as ΔVoffsetL (=Vp-VL0), and the offset voltage for the reference signal VrampH is shown as ΔVoffsetH (=Vp-VH0). In this example, the absolute values ​​of the two offset voltages have the relationship |Vp-VL0|>|Vp-VH0|. Next, the period from time t301 to time t302 is a period in which the reset operation of the comparator circuit 203 is performed by controlling φRES.

[0031] At time t301, the control signal φRES changes from L level to H level, and the switches 202A and 202B of the comparison circuit 203 are turned on. At this time, the two input terminals of the comparison circuit 203 are short-circuited to the output terminals, respectively, and the comparison circuit 203 is placed in a reset state. The potentials of the nodes to which one terminal of the input capacitance 201A or the input capacitance 201B and the input terminal of the comparison circuit 203 are connected are each at the reset potential, and the comparison circuit 203 is placed in a balanced state.

[0032] Subsequently, at time t302, the control signal φRES changes from H level to L level, turning off the switches 202A and 202B, thereby canceling the reset state. At this time, the difference between the voltage of the vertical signal line 102 connected to one end of the input capacitor 201A and the voltage of the negative input terminal of the comparator circuit 203, which is connected to the other end of the input capacitor 201A and in a balanced state, is held in the input capacitor 201A. Also, the difference between the offset voltage ΔVoffsetL applied to one end of the input capacitor 201BL and the voltage of the positive input terminal of the comparator circuit 203, which is connected to the other end of the input capacitor 201BL and in a balanced state, is held in the input capacitor 201BL. The difference between the offset voltage ΔVoffsetH applied to one end of the input capacitor 201BH and the voltage of the positive input terminal of the comparator circuit 203, which is connected to the other end of the input capacitor 201BH and in a balanced state, is held in the input capacitor 201BL.

[0033] That is, the reset potential of the comparator circuit 203 is set and held between the node at one end of the input capacitor 201A or the input capacitor 201B and the node to which the input terminal of the comparator circuit 203 is connected. That is, the input capacitor 201A holds a potential difference ΔV−(t302) between the voltage at the negative input terminal of the comparator circuit 203 at time t302 and the vertical signal line potential of the pixel at the reset level when the pixel is reset. Meanwhile, the input capacitor 201B holds a potential difference ΔV+(t302) between the voltage at the positive input terminal of the comparator circuit 203 and the reference signal Vramp at time t302. As described above, predetermined voltages can be set in the input capacitors 201A and 201B, respectively.

[0034] Hereinafter, time t is a variable, and the voltage difference between the negative input terminal of the comparator circuit 203 and the vertical signal line 102 is denoted as ΔV−(t), and the voltage difference between the positive input terminal of the comparator circuit 203 and the reference signal Vramp is denoted as ΔV+(t). The potential obtained by subtracting ΔV+(t302) from ΔV−(t302) at time t302, when the comparator circuit is reset, is defined as Vth (=ΔV−(t302)−ΔV+(t302)). After the reset state of the comparator circuit is released, the output of the comparator circuit changes when the difference between ΔV−(t) and ΔV+(t) becomes larger or smaller than Vth. This Vth is defined as the logical threshold. In other words, the potential difference between the vertical line signal potential PixSig and the reference signal Vramp at time t302 is referred to as the logical threshold ΔV (=PixSig−Vramp).

[0035] A reset operation sets a potential Vth, calculated by subtracting ΔV+(t302) from ΔV-(t302), across input capacitors 201A and 201B, respectively, connected to the two input terminals of the comparator circuit. In other words, after time t302, when the reset is released, the output of the comparator circuit changes when the difference between the vertical line signal potential PixSig and the reference signal Vramp becomes larger than the difference (=Vth) at time t302. Hereinafter, this timing is referred to as the output change timing. This reset operation of the comparator circuit is also referred to as auto-zero.

[0036] The logical threshold ΔV_L is defined as the difference between the vertical line signal potential PixSig and the reference signal Vramp_L from time t301 to time t302, and the logical threshold ΔV_H is defined as the difference between the vertical line signal potential PixSig and the reference signal Vramp_H during the same period.

[0037] It should be noted here that the logical thresholds ΔV_L and ΔV_H can be adjusted to desired values ​​by setting an offset voltage ΔVoffset. The logical thresholds can adjust the timing at which the output of the comparator circuit 203 changes. The method for setting the offset voltage ΔVoffset in this embodiment will be described in detail later. Next, from time t302 to time t303, the reference signal Vramp is reset to potential Vp. This is intended to ensure linearity of the output relative to the input vertical line signal potential by changing the output of the comparator circuit at a timing from time t303 to time t306 at which the linearity of the reference signal Vramp is ensured.

[0038] Specifically, the reference signal Vramp immediately after time t303 has poor linearity immediately after the potential starts to monotonically decrease from the constant potential Vp, but the linearity improves as time passes from time t303. In other words, the offset voltage allows the comparator circuit to perform comparison operations using the portion of the reference signal Vramp that has good linearity.

[0039] Subsequently, from time t303 to time t306, the reference signal Vramp monotonically decreases from the potential Vp, and a comparison is made between the vertical line signal potential of the N signal of the unit pixel 101 and the reference signal Vramp. At this time, the absolute value of the time change of the reference signal VrampL is defined as dVL / dt, and the absolute value of the time change of the reference signal VrampH is defined as dVH / dt, and dVL / dt is assumed to be greater than dVH / dt (dVL / dt>dVH / dt).

[0040] In this embodiment, the output of the comparator circuit 203 changes at the timing when the potential difference between the vertical line signal potential of the N signal and the reference signal Vramp becomes large with respect to the logical threshold value ΔV. That is, the output of the comparator circuit 203L changes at time t304, and the output of the comparator circuit 203H changes at time t305.

[0041] Here, the time amount Δta is the time amount from time t303 to time t304, and the time amount Δtb is the time amount from time t303 to time t305. Note that the counter circuit counts from time t303 to time t306 and outputs the counter value. The N signals input to the comparison circuits 203L and 203H are converted into digital signals based on the counter values ​​corresponding to the time amounts Δta and Δtb, respectively. These digital signals are held in the memory circuit 107. Note that this operation is referred to as AD conversion of the N signal.

[0042] Next, at time t306, the monotonically decreasing reference signal Vramp is reset to the potential Vp at the start of the readout operation, and the output of the comparator circuit 203 is also reset to its pre-change state. As mentioned above, the reason Vramp starts changing from the potential Vp is to allow the comparator circuit to perform a comparison operation at a timing when the linearity of the reference signal Vramp is good. In particular, ensuring linearity for low-luminance signals during the period from time t308 to time t311 (described later) when the vertical line signal potential of the S signal is compared with the reference signal Vramp is important for improving image quality.

[0043] Next, at time t307, the vertical line signal potential PixSig starts outputting an S signal based on the charge photoelectrically converted in the selected unit pixel 101. The N signal output period changes to the S signal output period, and the S signal output period begins. At this time, it is desirable to secure time from time t307 to time t308 for the vertical line signal potential PixSig to change from N signal output to S signal output and for the S signal output to stabilize.

[0044] Thereafter, from time t308 to time t311, the reference signal Vramp decreases monotonically, and a comparison operation is performed between the vertical line signal potential of the S signal of the unit pixel 101 and the reference signal Vramp. Then, at time t309, the output of the comparator circuit 203L changes, and at time t310, the output of the comparator circuit 203H changes.

[0045] Next, the amount of time from time t308 to time t309 is denoted as ΔTA. That is, the amount of time ΔTA is the amount of time corresponding to the S signal including the N signal component, and the difference between the amount of time ΔTA and the amount of time Δta corresponding to the N signal is the amount of time ΔtA. The amount of time ΔtA is the amount of time corresponding to the S signal not including the N signal component. Similarly, the amount of time from time t308 to time t310 is denoted as ΔTB. That is, the amount of time ΔTB is the amount of time corresponding to the S signal including the N signal component. The difference between the amount of time ΔTB and the amount of time Δtb corresponding to the N signal is the amount of time ΔtB, and the amount of time ΔtB is the amount of time corresponding to the S signal not including the N signal component.

[0046] The counter circuit counts from time t308 to time t311 and outputs the counter value. Therefore, the vertical line signal potential of the S signal input to the comparator circuits 203L and 203H is converted into a digital signal based on the counter value in accordance with the time amount ΔTA (=Δta+ΔtA) and the time amount ΔTB (=Δtb+ΔtB), and is held in the memory circuit 107.

[0047] Next, at time t311, the monotonically decreasing reference signal Vramp is reset to the potential Vp at the start of the read operation, and the comparator circuit 203 is reset to the state before the output change. In this manner, the N signal and the S signal are sequentially read. Next, the output change and timing control of the comparator circuit 203 during the N signal comparison operation from time t303 to t306 in this embodiment will be described.

[0048] A feature of this embodiment is that, in the comparison operation of the N signal, the output change timing of the comparison circuit 203L is made earlier than the output change timing of the comparison circuit 203H. That is, the time amount Δta is made shorter than the time amount Δtb (Δta<Δtb). This makes it possible to differentiate the output change timing of the comparison circuit 203 even in the comparison operation of the S signal from time t308 to time t311.

[0049] Next, the comparison operation of the S signal will be described. As shown in the example of FIG. 3(a), since the time change amount dVL / dt of the reference voltages VrampL and VrampH is greater than dVH / dt, the time amount ΔtA during the S signal output period is smaller than the time amount ΔtB (ΔtA<ΔtB). Therefore, the time amount ΔTA, which is the sum of the time amounts Δta and ΔtA, is smaller than the time amount ΔTB, which is the sum of the time amounts Δtb and ΔtB (ΔTA (=Δta+ΔtA)<ΔTB (=Δtb+ΔtB)). That is, as with the comparison operation of the N signal, in the comparison operation of the S signal, the output change timing of the comparison circuit 203L is earlier than the output change timing of the comparison circuit 203H.

[0050] Next, we will explain the case where the time amount Δta is greater than the time amount Δtb (Δta > Δtb). In this case, depending on the magnitude of the S signal, it is possible that comparison circuits 203L and 203H may simultaneously detect a change in their outputs. First, as described above, because dVL / dt is greater than dVH / dt in the time changes of reference voltages VrampL and VrampH, the time amount ΔtA is smaller than the time amount ΔtB (ΔtA < ΔtB). In this case, the difference between the time amounts ΔtA and ΔtB (i.e., ΔtB - ΔtA) is determined by the magnitude of the vertical line signal potential input to the comparison circuits.

[0051] If the change in vertical line signal potential during the S signal output period relative to the N signal output period is large, the difference between the time amounts ΔtA and ΔtB becomes large. Therefore, depending on the vertical line signal potential during the S signal output period relative to the N signal output period, the difference between the time amounts ΔtA and ΔtB (ΔtB - ΔtA) may be equal to the difference between the time amounts Δta and Δtb (Δta - Δtb). In other words, the sum of the time amounts Δta and ΔtA may be equal to the sum of the time amounts Δtb and ΔtB (i.e., ΔTA (= Δta + ΔtA) = ΔTB (= Δtb + ΔtB)).

[0052] When light is received with a luminance that indicates an S signal such that the above relationship holds, the output of comparison circuit 203L and the output of comparison circuit 203H change simultaneously during the S signal comparison operation. When the outputs of many comparison circuits change simultaneously, a large amount of current flows instantaneously. This causes fluctuations in the power supply voltage supplied to the circuit, resulting in circuit malfunctions and noise contamination of other signal lines, preventing accurate circuit operation. This can result in degradation of the image quality of the captured image.

[0053] Therefore, in this embodiment, the time amount Δta is always made smaller than the time amount Δtb, thereby creating a relationship Δta+ΔtA<Δtb+ΔtB, and the output change timing of the comparison circuit 203L and the comparison circuit 203H can be made different regardless of the vertical line signal potential.

[0054] Next, when ΔVoffsetL is set smaller than ΔVoffsetH as shown in FIG. 3B, the time amount Δta is also set smaller than the time amount Δtb. In this case, the time change amounts of the reference voltages VrampL and VrampH are dVL / dt larger than dVH / dt, so the relationship Δta+ΔtA<Δtb+ΔtB can be established. Therefore, the output change timings of the comparator circuits 203L and 203H can be made different regardless of the magnitude of the vertical line signal potential PixSig.

[0055] Let us consider the above-described time relationship in terms of the rate of change of the offset voltage and the reference signal over time. To simplify the explanation, consider that reference signals VrampL and VrampH change according to their respective time change rates from time 0. Comparator 203H compares with reference signal VrampH, and the set offset amount is VoffsetH. Comparator 203H compares with reference signal VrampL, and the set offset amount is VoffsetL. Let the time change rate dVL / dt of reference signal VrampL be a, and the time change rate dVH / dt of reference signal VrampH be b. In this case, the magnitude relationship of the time change rates is set as time change rate dVH / dt (= a) > time change rate dVH / dt (= b).

[0056] If we consider that the reference signal is displaced by the offset amount, the output of comparator 203H changes when VrampH becomes VoffsetH, which is assumed to be after time T1 has elapsed. Expressed as a formula, this occurs when VoffsetH=bT1. Similarly, the output of comparator 203L changes when time T2 has elapsed, when VoffsetL=aT2. Here, it can be seen that to achieve T1>T2, the relationship (VoffsetH / b)>(VoffsetL / a) must be established. In other words, the offset voltage must be set so that the product of the reciprocal of the time rate of change b (=dVH / dt) and the offset voltage VoffsetH is smaller than the product of the reciprocal of the time rate of change a (=dVL / dt) and the offset voltage VoffsetL.

[0057] As a result, it is possible to provide a photoelectric conversion device that can suppress simultaneous output changes of multiple comparator circuits and reduce noise during AD conversion when pixel signals are simultaneously read out at a plurality of different gains.

[0058] Note that this embodiment is characterized in that the output change timing of the comparison circuit 203L during AD conversion of the N signal is set earlier than the output change timing of the comparison circuit 203H. The configuration for this is not limited to setting the offset voltage ΔVoffset during the reset operation of the comparison circuit. It is sufficient to apply a predetermined offset voltage to the voltage between the start voltage of the reference signal and the reset voltage of the pixel signal during the reset operation of the comparison circuit. For example, the change timing may be controlled by applying an offset voltage to the pixel signal through voltage control on the vertical signal line 102.

[0059] In addition, in this embodiment, a monotonically decreasing reference signal is used for explanation. However, the reference signal may be a monotonically increasing reference signal. When the reference signal monotonically increases, the potentials VL0 and VH0 and the offset voltages ΔVoffsetL and ΔVoffsetH can be set to potentials higher than the potential Vp at the start of readout.

[0060] In this embodiment, in the AD conversion of the N signals of the rows that are simultaneously read out, the output change timing of the comparator circuit 203L is earlier than that of the comparator circuit 203H, which is effective in suppressing noise. However, as long as the above timing relationship is established for at least one unit pixel 101 of the rows that are simultaneously read out, the effects of this embodiment can be obtained.

[0061] (Second embodiment) A photoelectric conversion device 100 according to a second embodiment of the present invention will now be described. In this embodiment, as in the first embodiment, during the comparison operation of the N signal, the output of a comparison circuit that uses a reference signal with a large time change rate is changed faster than the output of a comparison circuit that uses a reference signal with a small time change rate. This makes it possible to prevent simultaneous changes in the output of the comparison circuit during the comparison operation of the S signal. Furthermore, by dispersing the timing of output changes during the comparison operation of the N signal in different comparison circuits that simultaneously perform comparison operations using reference signals with the same time change rate, it becomes possible to further reduce noise.

[0062] Differences between this embodiment and the first embodiment will be described below with reference to FIGS. 4 and 5. FIG. 4 shows an example of the configuration of the comparison circuit unit 106 in this embodiment. In this embodiment, a control signal φRES for resetting a comparison circuit corresponding to an arbitrary first unit pixel 101 and a comparison circuit corresponding to a second unit pixel 101 arranged in a different column from the first unit pixel 101 is provided. A pixel signal from the first unit pixel is input to a comparison circuit 203_1 of the comparison unit 106 via a vertical signal line 102-1. A pixel signal from the second unit pixel is input to a comparison circuit 203_2 via a vertical signal line 102-2.

[0063] A first pixel signal output from the first unit pixel 101 is input to a comparison circuit 203L_1 that is reset by a control signal φRES1 and a comparison circuit 203H_1 that is reset by a control signal φRES2. Reference signals VrampL and VrampH are input to the comparison circuit 203L_1 and comparison circuit 203H_1, respectively, and they compare the pixel signal. Furthermore, a second pixel signal output from the second unit pixel 101 is input to a comparison circuit 203L_2 that is reset by a control signal φRES3 and a comparison circuit 203H_2 that is reset by a control signal φRES4. Here, unless the following description is limited to any one of the above four comparison circuits, the four comparison circuits will be collectively referred to as the comparison circuit 203.

[0064] With the above configuration, it is possible to reset each comparison circuit 203 corresponding to the pixel signals of multiple unit pixels 101 arranged in different columns that are read out simultaneously with a different control signal φRES, and to set the logical threshold value ΔV at different timings.

[0065] Next, the comparison operation of the comparison circuit 203 constituting the comparison circuit section 106 in this embodiment will be described with reference to Fig. 5. The N signal output period and the S signal output period indicate periods during which the N signal and the S signal are read out from the first unit pixel 101 and the second unit pixel 101. In the figure, PixSig1 and PixSig2 indicate the time transition of the voltage on the vertical signal line 102 based on the pixel signals output from the first unit pixel 101 and the second unit pixel 101, respectively.

[0066] First, in the same manner as in the first embodiment, logical thresholds ΔVL_1 and ΔVH_1 are set in the comparator circuit 203L_1 and the comparator circuit 203H_1, and then logical thresholds ΔVL_2 and ΔVH_2 are set in the comparator circuit 203L_2 and the comparator circuit 203H_2.

[0067] First, the logic thresholds ΔVL_1 and ΔVH_1 of the comparator circuit 203L_1 and the comparator circuit 203H_1 are set. Before time t501, the reference signals VrampL_1 and VrampH_1 are transitioned from the voltages at the start of the read operation to VL0_1 and VH0_1, respectively. Then, from time t501 to time t502, the comparator circuit 203L_1 is reset by the control signal φRES1, and the comparator circuit 203H_1 is reset by the control signal φRES2. After the comparator circuit 203 is released from reset, similar to the first embodiment, the logic thresholds ΔVL_1 and ΔVH_1 are set in the two comparators 203L_1 and 203H_1.

[0068] Next, the logic thresholds ΔVL_2 and ΔVH_2 of the comparator circuits 203L_2 and 203H_2 are set. Therefore, between time t502 and time t503, the reference signals VrampL_2 and VrampH_2 are transitioned from the voltages at the start of the read operation to VL0_2 and VH0_2, respectively. Thereafter, between time t503 and time t504, the comparator circuit 203L_2 is reset by the control signal φRES3, and the comparator circuit 203H_2 is reset by the control signal φRES4. After the comparator circuit 203 is released from reset, similarly to the first embodiment, the logic thresholds ΔVL_2 and ΔVH_2 are set in the two comparator circuits 203L_2 and 203H_2.

[0069] In this embodiment, the control signals φRES1 and φRES2 transition at the same time, and the control signals φRES3 and φRES4 transition at the same time to reset the comparator circuit, but they may also transition at different times. Hereinafter, the offset voltage ΔVoffset is defined as in the first embodiment. The offset voltage for the reference signal VrampL determined by the voltage at time t502 is defined as ΔVoffsetL_1, and the offset voltage for the reference signal VrampH is defined as ΔVoffsetH_1. Similarly, the offset voltage for the reference signal VrampL determined by the voltage at time t504 is defined as ΔVoffsetL_2, and the offset voltage for the reference signal VrampH is defined as ΔVoffsetH_2.

[0070] Unlike the first embodiment, by providing different control signals φRES to the comparison circuits 203 that receive different pixel signals as input and resetting them in stages, it is possible to change the same reference signal Vramp and adjust ΔVoffset for each comparison circuit 203.

[0071] Next, the period from time t505 to time t510 is a comparison operation period for the N signal, during which a comparison operation is performed between the N signals from the first unit pixel 101 and the second unit pixel 101 and the reference signal Vramp. The outputs of the comparator circuit 203L_1 at time t506, the comparator circuit 203L_2 at time t507, the comparator circuit 203H_1 at time t508, and the comparator circuit 203H_2 at time t509 change according to their respective logic threshold values ​​ΔV.

[0072] Next, at time t511, the S signals of the first unit pixel and the second unit pixel are output to the vertical signal line 102. The period from time t512 to time t517 is a comparison operation period for the S signals, during which the respective S signals are compared with the reference signal Vramp.

[0073] The outputs of the comparator circuit 203L_1 at time t513, the comparator circuit 203L_2 at time t514, the comparator circuit 203H_1 at time t515, and the comparator circuit 203H_2 at time t516 change in accordance with the respective logic threshold values ​​ΔV.

[0074] Next, a description will be given of control of the output change timing of the comparison circuit 203 in the comparison operation of the N signal in this embodiment. In this embodiment, the output change timing during comparison of the N signal between the comparison circuits 203 that compare using reference signals with the same time change rate, i.e., between the comparison circuits 203L_1 and 203L_2 and between the comparison circuits 203H_1 and 203H_2, is made different.

[0075] In the comparison operation of the N signal, the comparators 203L_1 and 203L_2 are driven so that the output change timing of the comparators 203L_1 and 203L_2 is earlier than the output change timing of the comparators 203H_1 and 203H_2. By this driving, the inversion operations of the comparators for the same pixel and two different pixels can be performed at different timings.

[0076] In this regard, as in the first embodiment, the time rate of change of the reference signal VrampH is assumed to be a and b, with a>b. The offset voltage of the comparator circuit 203L_1 corresponding to the first unit pixel is assumed to be V1, and the offset voltage of the comparator circuit 203H_1 corresponding to the second unit pixel is assumed to be V2. The offset voltage of the comparator circuit 203L_2 corresponding to the second unit pixel is assumed to be V3, and the offset voltage of the comparator circuit 203H_2 corresponding to the second unit pixel is assumed to be V4. Then, the timing T1 at which the output of the comparator circuit 203L_1 changes is T1=(V1 / a), and the timing T2 at which the output of the comparator circuit 203H_1 changes is T2=(V2 / b). Similarly, the timing T3 at which the output of the comparator circuit 203L_2 changes is T3=(V3 / a), and the timing T4 at which the output of the comparator circuit 203H_2 changes is T4=(V4 / b). Regarding the relationship between the timings, by making T1 and T3 smaller than either T2 or T4, it is possible to prevent the comparator circuit from performing an inverted operation. This can be rephrased as follows.

[0077] The product of the reciprocal of the time change rate a and the offset voltage V1 and the product of the reciprocal of the time change rate a and the offset voltage V3 should be smaller than either the product of the reciprocal of the time change rate b and the offset voltage V2 or the product of the reciprocal of the time change rate b and the offset voltage V4. This allows the timing of the comparison operation of the N signal to be dispersed even in the comparison circuit 203, which uses the same reference signal for comparison when reading out the N signal and the S signal.

[0078] However, if the potential difference between the S signals of the first pixel signal and the second pixel signal is large, the comparator circuit 203 may change simultaneously during the comparison operation of the S signals. Specifically, if the potential difference between the S signals of the first pixel signal and the second pixel signal is larger than the difference caused by ΔVoffset or the time change rate of the reference signal Vramp, the outputs of the comparator circuit 203 may change simultaneously. Therefore, since the potential difference between the S signals of the first pixel and the second pixel signal is likely to be small in nearby pixels of the same color, it is desirable to configure nearby pixels of the same color to have different offset voltages ΔVoffset.

[0079] As in the first embodiment, in addition to the relationship ΔVoffsetL_1<ΔVoffset_H1, ΔVoffsetL_2<ΔVoffsetH_2 is set. This makes it possible to further suppress simultaneous changes in the output of the comparison circuit 203 in relation to the time rate of change of the reference signal. Furthermore, although this embodiment is configured to set two types of offset voltages for the comparison circuit 203 to be compared using reference signals with the same time rate of change, it is also possible to set three or more types. In this case, the timing of changes in the output of the comparison circuit is further dispersed.

[0080] Furthermore, this embodiment is characterized in that, during the comparison operation of the N signals, the output of the comparison circuit 203 that uses a reference signal with a large time change rate for comparison is changed faster than the output of any of the comparison circuits 203 that use a reference signal with a small time change rate for comparison. The means for achieving this is not limited to setting an offset voltage ΔVoffset for the reference signal. A similar effect can be obtained by setting an offset voltage on the vertical signal line. By using this embodiment, in addition to the effects of the first embodiment, it is possible to suppress simultaneous changes in multiple comparison circuits 203 during the comparison operation of the N signals.

[0081] (Third embodiment) A photoelectric conversion device 100 driven according to a third embodiment of the present invention will be described below. This embodiment is a modification of the gain amplification means in the second embodiment. In the first and second embodiments, by varying the time-varying reference signal Vramp between the N signal readout period and the S signal readout period, digital values ​​can be obtained with different gains in AD conversion. This embodiment illustrates a photoelectric conversion device in which vertical line signal potentials are amplified with different gains by a column amplifier and output.

[0082] The differences between this embodiment and the second embodiment will be described below with reference to Figures 6 and 7. Figure 6 shows an example of the comparison circuit unit 106 in this embodiment.

[0083] The first pixel signal and the second pixel signal output to the vertical signal line 102_1 and the vertical signal line 102_2 are respectively amplified at a low gain by a column amplifier 601L as an amplifier circuit and amplified at a high gain by a column amplifier 601H. Note that for the same pixel signal, when the column amplifier changes the amplification factor to a low value, the signal is referred to as being amplified at a low gain, and when the column amplifier changes the amplification factor to a high value, the signal is referred to as being amplified at a high gain. Hereinafter, the column amplifier 601L and the column amplifier 601H will be referred to as the column amplifier 601 when not limited to one of them.

[0084] The first pixel signal amplified by the column amplifier 601L is input to a comparison circuit 203L_1 that is reset and controlled by a control signal φRES1, and the first pixel signal amplified by the column amplifier 601H is input to a comparison circuit 203H_1 that is reset and controlled by a control signal φRES2.

[0085] Similarly, the second pixel signal amplified by the column amplifier 601L is input to a comparison circuit 203L_2 that is reset by a control signal φRES3, and the second pixel signal amplified by the column amplifier 601H is input to a comparison circuit 203H_2 that is reset by a control signal φRES4.

[0086] Unlike the second embodiment, a common reference signal Vramp is input to all of the comparison circuits 203, and the first and second pixel signals are compared with the reference signal Vramp, which has a common time change rate. However, what should be noted here is that with the above configuration, the same pixel signal is amplified with different gains and then input to different comparison circuits 203, making it possible to simultaneously output the same pixel signal with different gains, as in the second embodiment. Furthermore, with the configuration providing the control signals φRES1 to φRES4 as described above, it is also possible in this embodiment to reset the comparison circuits 203 connected to different unit pixels 101 at different timings.

[0087] 7 is a timing chart showing the comparison drive of the comparison circuit 203 constituting the comparison circuit unit 106 and the output of the comparison circuit in this embodiment. In the figure, vertical line signal potential PixSig is a pixel signal of the vertical signal line 102 output from the first and second unit pixels 101, and shows the time change of the potential multiplied by the gain of the column amplifier 601 to which each is connected.

[0088] The pixel signal of the first unit pixel 101 is amplified with a low gain to a voltage PixSigL_1, and amplified with a high gain to a voltage PixSigH_1. Similarly, the pixel signal of the second unit pixel 101 is amplified with a low gain to a voltage PixSigL_2, and amplified with a high gain to a voltage PixSigH_2.

[0089] The comparison operation of the comparator circuit 203 in this embodiment will be described below along the timing shown in Fig. 7. First, the reset operation of each comparator circuit 203 is performed.

[0090] First, the reference signal Vramp is transitioned from the voltage at the start of the read operation to the desired voltage VL0_1, and then the comparator circuit 203L_1 is reset by the control signal φRES1 from time t701 to time t702. Next, the reference signal Vramp is transitioned to voltage VL0_2, and then the comparator circuit 203L_2 is reset by the control signal φRES3 from time t703 to time t704.

[0091] Next, after the reference signal Vramp is transitioned to the voltage VH0_1, the comparator circuit 203H_1 is reset by the control signal φRES2 from time t705 to time t706. Finally, after the reference signal Vramp is transitioned to the voltage VH0_2, the comparator circuit 203H_2 is reset by the control signal φRES4 from time t707 to time t708.

[0092] The difference between the vertical line signal potential PixSig and the reference signal Vramp at the reset release time of these comparison circuits 203 is the logic threshold value ΔV of the corresponding comparison circuit 203. In the figure, ΔV_L1 indicates the logic threshold value ΔV of the comparison circuit 203L_1, ΔV_L2 indicates the logic threshold value ΔV of the comparison circuit 203L_2, ΔV_H1 indicates the logic threshold value ΔV of the comparison circuit 203H_1, and ΔV_H2 indicates the logic threshold value ΔV of the comparison circuit 203H_2.

[0093] Hereinafter, the offset voltage ΔVoffset is defined in the same manner as in the first and second embodiments. That is, the offset voltage determined at time t702 is ΔVoffsetL_1, at time t704 it is ΔVoffsetL_2, at time t706 it is ΔVoffsetH_1, and at time t708 it is ΔVoffsetH_2.

[0094] The comparison period between the N signal and the reference signal Vramp is from time t709 to time t714. The outputs of the comparator circuit 203L_1 at time t710, the comparator circuit 203L_2 at time t711, the comparator circuit 203H_1 at time t712, and the comparator circuit 203H_2 at time t713 change according to their respective ΔV.

[0095] The period from time t716 to time t721 is a comparison period between the S signal and the reference signal Vramp. The outputs of the comparator circuit 203L_1 at time t717, the comparator circuit 203L_2 at time t718, the comparator circuit 203H_1 at time t719, and the comparator circuit 203H_2 at time t720 change according to the magnitude relationship between the respective ΔV and the reference signal.

[0096] Next, a description will be given of the control of the output change timing of the comparator circuit 203 in the comparison operation of the N signal in this embodiment. In this embodiment, similar to the second embodiment, the output change timing of the N signal is made different between comparator circuits 203 that output with the same gain.

[0097] At this time, in the comparison operation of the N signal, the comparators 203L_1 and 203L_2 are driven so that the output change timings thereof become earlier than the output change timings of the comparators 203H_1 and 203H_2.

[0098] Specifically, since the reference signal Vramp is common in this embodiment, the above driving can be performed by making ΔVoffsetL_1 and ΔVoffsetL_2 smaller than both ΔVoffsetH_1 and ΔVoffsetH_2.

[0099] Incidentally, by amplifying the same pixel signal with different gains, the amount of time from the start of the comparison operation to the output change timing of the comparison circuit 203L is shorter than that of the comparison circuit 203H for the S signal of the same pixel, as in the second embodiment.

[0100] As a result, this driving method can achieve the same effects as in Embodiment 2. That is, by using this embodiment, not only can simultaneous changes in the comparator circuit outputs during the comparison operation of the S signal be suppressed, but simultaneous changes in the N signal outputs of many comparator circuits connected to simultaneously readout pixels can also be suppressed during the comparison operation of the N signal.

[0101] However, if the difference between the first pixel signal and the second pixel signal is large, the comparator circuit 203 may change simultaneously during the comparison operation of the S signal even in this driving mode. Specifically, the comparator circuit outputs may change simultaneously if the difference in output change timing caused by the difference in pixel signals is longer than the difference in output change timing of the comparator circuit 203 caused by the offset amount ΔVoffset and amplification by the column amplifier 601. For this reason, it is desirable to configure adjacent pixels of the same color to have different offset voltages ΔVoffset.

[0102] (Application of photoelectric conversion devices to equipment) Hereinafter, a device 1000 will be described that includes a semiconductor device 1100 including a package 1020 on which a semiconductor chip 1110 including a semiconductor integrated circuit is mounted, as shown in FIG. 8. The semiconductor chip 1110 is housed in the package 1020 and mounted on the device 1000. In the configuration shown in FIG. 8, the semiconductor chip 1110 includes a photoelectric conversion device according to the above-described embodiment. The semiconductor device 1100 can include a package 1020 that includes a base 1010 to which the semiconductor chip 1110 is fixed and a light-transmitting member 1030 such as glass that faces the semiconductor chip 1110. The package 1020 can include bonding members such as wires and bumps that connect inner leads provided on the base 1010 to terminals such as pad electrodes provided on the semiconductor chip 1110.

[0103] The device 1000 may include at least one of an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls a semiconductor chip 1110. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0104] The processing device 1060 processes an output signal from a photoelectric conversion device included in the semiconductor chip 1110. The processing device 1060 is a semiconductor device such as a CPU or ASIC for configuring an analog front-end AFE or a digital front-end DFE. For example, an image may be generated based on the event signal E. The display device 1070 is an EL display device or a liquid crystal display device that displays an information image obtained by the semiconductor chip 1110. The storage device 1080 is a magnetic device or a semiconductor device that stores the information image obtained by the semiconductor chip 1110. The storage device 1080 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0105] The mechanical device 1090 has a moving part or a propulsion part such as a motor or an engine. In the device 1000, a signal output from the semiconductor chip 1110 is displayed on the display device 1070, or transmitted to the outside by a communication device (not shown) included in the device 1000. For this purpose, the device 1000 may further include a storage device 1080 and a processing device 1060 in addition to the memory circuit and arithmetic circuit included in the semiconductor chip 1110. The mechanical device 1090 may be controlled based on the signal output from the semiconductor chip 1110.

[0106] The device 1000 is also suitable for electronic devices such as information terminals with imaging capabilities, such as smartphones, wearable devices, and cameras, such as interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras. The mechanical device 1090 in the camera can drive components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in the camera can move the optical device 1040 for vibration isolation.

[0107] Furthermore, the device 1000 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 1090 in the transportation equipment may be used as a moving device. The device 1000 as transportation equipment is suitable for transporting semiconductor chips 1110 or for assisting and / or automating driving by using an imaging function. The processing device 1060 for assisting and / or automating driving can perform processing for operating the mechanical device 1090 as a moving device based on information obtained by the semiconductor chip 1110. Alternatively, the device 1000 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0108] (Other embodiments) The disclosure of the present invention includes the following photoelectric conversion device, image processing circuit, photoelectric conversion device, and equipment to which the photoelectric conversion device is applied.

[0109] (Item 1) A first pixel; a first analog-to-digital conversion circuit that converts a signal from the first pixel into analog digital; a reference signal generating circuit that generates a first reference signal whose voltage changes monotonically with time at a first rate of change, and a second reference signal whose voltage changes monotonically with time at a second rate of change that is smaller than the first rate of change; A photoelectric conversion device having a control circuit, the first analog-to-digital conversion circuit includes a first comparison circuit to which two signals, the signal from the first pixel and the first reference signal, are input, and a second comparison circuit to which two signals, the signal from the first pixel and the second reference signal, are input; the control circuit, prior to the analog-to-digital conversion, applies a first offset voltage between the signals input to the first comparison circuit, applies a second offset voltage between the signals input to the second comparison circuit, and sets the first offset voltage and the second offset voltage so that a product of the reciprocal of the first rate of change and the first offset voltage is smaller than a product of the reciprocal of the second rate of change and the second offset voltage. A photoelectric conversion device characterized by: (Item 2) 2. The photoelectric conversion device according to item 1, wherein applying the first offset voltage includes offsetting the first reference signal by the first offset voltage, and applying the second offset voltage includes offsetting the second reference signal by the second offset voltage. (Item 3) 2. The photoelectric conversion device according to item 1, wherein applying the first offset voltage includes offsetting the signal from the first pixel input to the first comparison circuit with the first offset voltage, and applying the second offset voltage includes offsetting the signal from the first pixel input to the second comparison circuit with the second offset voltage. (Item 4) 4. The photoelectric conversion device according to any one of items 1 to 3, wherein the absolute value of the first offset voltage is smaller than the absolute value of the second offset voltage. (Item 5) a second pixel different from the first pixel; a second analog-to-digital conversion circuit that converts the signal from the second pixel into analog digital; the second analog-to-digital conversion circuit includes a third comparison circuit to which two signals, the signal from the second pixel and the first reference signal, are input, and a fourth comparison circuit to which two signals, the signal from the second pixel and the second reference signal, are input; the control circuit applies a third offset voltage between the signals input to the third comparison circuit and applies a fourth offset voltage between the signals input to the fourth comparison circuit prior to the analog-to-digital conversion; a product of the inverse of the first rate of change and the first offset voltage and a product of the inverse of the first rate of change and the third offset voltage are each smaller than either a product of the inverse of the second rate of change and the second offset voltage or a product of the inverse of the second rate of change and the fourth offset voltage; 2. The photoelectric conversion device according to item 1, (Item 6) 6. The photoelectric conversion device according to item 5, wherein applying the third offset voltage includes offsetting the first reference signal by the third offset voltage, and applying the fourth offset voltage includes offsetting the second reference signal by the fourth offset voltage. (Item 7) 6. The photoelectric conversion device according to item 5, wherein applying the third offset voltage includes offsetting the signal from the second pixel input to the third comparison circuit with the third offset voltage, and applying the fourth offset voltage includes offsetting the signal from the second pixel input to the fourth comparison circuit with the fourth offset voltage. (Item 8) 8. The photoelectric conversion device according to any one of items 5 to 7, wherein the absolute value of the third offset voltage is smaller than the absolute value of the fourth offset voltage. (Item 9) A first pixel; a second pixel different from the first pixel; a first analog-to-digital conversion circuit that converts a signal from the first pixel into analog digital; a second analog-to-digital conversion circuit that converts the signal from the second pixel into analog digital; a reference signal generating circuit that generates a reference signal whose voltage changes monotonically with respect to time; a control circuit; A photoelectric conversion device having a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit, the first amplifier circuit amplifies the signal from the first pixel by a first gain, the second amplifier circuit amplifies the signal from the first pixel by a second gain greater than the first gain, the third amplifier circuit amplifies the signal from the second pixel by the first gain, and the fourth amplifier circuit amplifies the signal from the second pixel by the second gain; the first analog-to-digital conversion circuit has a first comparison circuit to which two signals, the output signal of the first amplifier circuit and the reference signal, are input, and a second comparison circuit to which two signals, the output signal of the second amplifier circuit and the reference signal, are input; the second analog-to-digital conversion circuit has a third comparison circuit to which two signals, the output signal of the third amplifier circuit and the reference signal, are input, and a fourth comparison circuit to which two signals, the output signal from the fourth amplifier circuit and the reference signal, are input; the control circuit, prior to the analog-to-digital conversion, provides a first offset voltage between the signals input to the first comparison circuit, a second offset voltage between the signals input to the second comparison circuit, a third offset voltage between the signals input to the third comparison circuit, and a fourth offset voltage between the signals input to the fourth comparison circuit, and sets the first offset voltage, the third offset voltage, the second offset voltage, and the fourth offset voltage so that each of the first offset voltage and the third offset voltage is smaller than either of the second offset voltage and the fourth offset voltage. A photoelectric conversion device characterized by: (Item 10) A first pixel; a first analog-to-digital conversion circuit that converts a signal from the first pixel into analog digital; a reference signal generating circuit that generates a first reference signal whose voltage changes monotonically with time at a first rate of change, and a second reference signal whose voltage changes monotonically with time at a second rate of change that is smaller than the first rate of change; A photoelectric conversion device having a control circuit, the first analog-to-digital conversion circuit includes a first comparison circuit to which two signals, the signal from the first pixel and the first reference signal, are input, and a second comparison circuit to which two signals, the signal from the first pixel and the second reference signal, are input; the control circuit is configured to reset the first pixel prior to the analog-to-digital conversion, offset the first reference signal input to the first comparison circuit by a first offset voltage, and offset the second reference signal input to the second comparison circuit by a second offset voltage; during a period in which the analog-to-digital conversion is performed, the first comparison circuit compares a difference between the signal from the first pixel and the first reference signal with a first logic threshold corresponding to a difference between a reset level voltage of the first pixel and the first offset voltage, and the second comparison circuit compares a difference between the signal from the first pixel and the second reference signal with a second logic threshold corresponding to a difference between the reset level voltage of the first pixel and the second offset voltage; and set the first offset voltage and the second offset voltage so that a product of a reciprocal of the first rate of change and the first offset voltage is smaller than a product of a reciprocal of the second rate of change and the second offset voltage. A photoelectric conversion device characterized by: (Item 11) 11. The photoelectric conversion device according to item 10, wherein the absolute value of the first offset voltage is smaller than the absolute value of the second offset voltage. (Item 12) a second pixel different from the first pixel; a second analog-to-digital conversion circuit that converts the signal from the second pixel into analog digital; the second analog-to-digital conversion circuit includes a third comparison circuit to which two signals, the signal from the second pixel and the first reference signal, are input, and a fourth comparison circuit to which two signals, the signal from the second pixel and the second reference signal, are input; the control circuit is configured to reset the second pixel prior to the analog-to-digital conversion, offset the first reference signal input to the third comparison circuit by a third offset voltage, and offset the second reference signal input to the fourth comparison circuit by a fourth offset voltage; during a period of performing the analog-to-digital conversion, the third comparison circuit compares a difference between the signal from the second pixel and the first reference signal with a third logic threshold corresponding to a difference between a reset level voltage of the second pixel and the first offset voltage, and the fourth comparison circuit compares the difference between the signal from the second pixel and the second reference signal with a fourth logic threshold corresponding to a difference between the reset level voltage of the second pixel and the fourth offset voltage; and each of a product of the reciprocal of the first rate of change and the first offset voltage and a product of the reciprocal of the first rate of change and the third offset voltage is smaller than either a product of the reciprocal of the second rate of change and the second offset voltage or a product of the reciprocal of the second rate of change and the fourth offset voltage. 12. The photoelectric conversion device according to item 10 or 11, (Item 13) Item 13. The photoelectric conversion device according to item 12, wherein the absolute value of the first offset voltage and the absolute value of the third offset voltage are smaller than the absolute value of the second offset voltage and the absolute value of the fourth offset voltage. (Item 14) The photoelectric conversion device according to any one of items 1 to 13, and a processing device that processes an output signal from the photoelectric conversion device.

[0110] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0111] 100: photoelectric conversion device, 101: unit pixel, 102: vertical signal line, 103: control wiring, 104: pixel array section, 105: vertical scanning circuit, 106: comparison circuit, 107: memory circuit, 108: reference signal generation circuit, 109: counter circuit, 110: signal processing circuit, 111: horizontal scanning circuit, 112: control circuit, 113: output circuit, 201: input capacitance, 202: switch, 203: comparison circuit, 204: column memory, 601: column amplifier, φRES1, φRES2: control signal, VrampL, VrampH: reference signal, Voffset: offset voltage, PixSig: vertical signal line potential, ΔV_L, ΔV_H: logic threshold

Claims

1. A first pixel; a first analog-to-digital conversion circuit that performs analog-to-digital conversion on a signal from the first pixel; a reference signal generating circuit that generates a first reference signal whose voltage changes monotonically with time at a first rate of change, and a second reference signal whose voltage changes monotonically with time at a second rate of change that is smaller than the first rate of change; A photoelectric conversion device having a control circuit, the first analog-to-digital conversion circuit includes a first comparison circuit to which two signals, the signal from the first pixel and the first reference signal, are input, and a second comparison circuit to which two signals, the signal from the first pixel and the second reference signal, are input; the control circuit, prior to the analog-to-digital conversion, applies a first offset voltage between the signals input to the first comparison circuit, applies a second offset voltage between the signals input to the second comparison circuit, and sets the first offset voltage and the second offset voltage so that a product of the reciprocal of the first rate of change and the first offset voltage is smaller than a product of the reciprocal of the second rate of change and the second offset voltage. A photoelectric conversion device characterized by:

2. 2. The photoelectric conversion device according to claim 1, wherein applying the first offset voltage includes offsetting the first reference signal by the first offset voltage, and applying the second offset voltage includes offsetting the second reference signal by the second offset voltage.

3. 2. The photoelectric conversion device according to claim 1, wherein applying the first offset voltage includes offsetting the signal from the first pixel input to the first comparison circuit with the first offset voltage, and applying the second offset voltage includes offsetting the signal from the first pixel input to the second comparison circuit with the second offset voltage.

4. 2. The photoelectric conversion device according to claim 1, wherein the absolute value of the first offset voltage is smaller than the absolute value of the second offset voltage.

5. a second pixel different from the first pixel; a second analog-to-digital conversion circuit that converts the signal from the second pixel into an analog-to-digital conversion signal; the second analog-to-digital conversion circuit includes a third comparison circuit to which two signals, the signal from the second pixel and the first reference signal, are input, and a fourth comparison circuit to which two signals, the signal from the second pixel and the second reference signal, are input; the control circuit applies a third offset voltage between the signals input to the third comparison circuit and applies a fourth offset voltage between the signals input to the fourth comparison circuit prior to the analog-to-digital conversion; a product of the inverse of the first rate of change and the first offset voltage and a product of the inverse of the first rate of change and the third offset voltage are each smaller than either a product of the inverse of the second rate of change and the second offset voltage or a product of the inverse of the second rate of change and the fourth offset voltage; 2. The photoelectric conversion device according to claim 1.

6. 6. The photoelectric conversion device of claim 5, wherein applying the third offset voltage includes offsetting the first reference signal by the third offset voltage, and applying the fourth offset voltage includes offsetting the second reference signal by the fourth offset voltage.

7. 6. The photoelectric conversion device according to claim 5, wherein applying the third offset voltage includes offsetting the signal from the second pixel input to the third comparison circuit with the third offset voltage, and applying the fourth offset voltage includes offsetting the signal from the second pixel input to the fourth comparison circuit with the fourth offset voltage.

8. 6. The photoelectric conversion device according to claim 5, wherein the absolute value of the third offset voltage is smaller than the absolute value of the fourth offset voltage.

9. A first pixel; a second pixel different from the first pixel; a first analog-to-digital conversion circuit that performs analog-to-digital conversion on a signal from the first pixel; a second analog-to-digital conversion circuit that converts the signal from the second pixel into analog digital; a reference signal generating circuit that generates a reference signal whose voltage changes monotonically with respect to time; a control circuit; A photoelectric conversion device having a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit, the first amplifier circuit amplifies the signal from the first pixel by a first gain, the second amplifier circuit amplifies the signal from the first pixel by a second gain greater than the first gain, the third amplifier circuit amplifies the signal from the second pixel by the first gain, and the fourth amplifier circuit amplifies the signal from the second pixel by the second gain; the first analog-to-digital conversion circuit has a first comparison circuit to which two signals, the output signal of the first amplifier circuit and the reference signal, are input, and a second comparison circuit to which two signals, the output signal of the second amplifier circuit and the reference signal, are input; the second analog-to-digital conversion circuit has a third comparison circuit to which two signals, the output signal of the third amplifier circuit and the reference signal, are input, and a fourth comparison circuit to which two signals, the output signal of the fourth amplifier circuit and the reference signal, are input; the control circuit, prior to the analog-to-digital conversion, provides a first offset voltage between the signals input to the first comparison circuit, a second offset voltage between the signals input to the second comparison circuit, a third offset voltage between the signals input to the third comparison circuit, and a fourth offset voltage between the signals input to the fourth comparison circuit, and sets the first offset voltage, the third offset voltage, the second offset voltage, and the fourth offset voltage so that each of the first offset voltage and the third offset voltage is smaller than either of the second offset voltage and the fourth offset voltage. A photoelectric conversion device characterized by:

10. A first pixel; a first analog-to-digital conversion circuit that performs analog-to-digital conversion on a signal from the first pixel; a reference signal generating circuit that generates a first reference signal whose voltage changes monotonically with time at a first rate of change, and a second reference signal whose voltage changes monotonically with time at a second rate of change that is smaller than the first rate of change; A photoelectric conversion device having a control circuit, the first analog-to-digital conversion circuit includes a first comparison circuit to which two signals, the signal from the first pixel and the first reference signal, are input, and a second comparison circuit to which two signals, the signal from the first pixel and the second reference signal, are input; the control circuit is configured to reset the first pixel prior to the analog-to-digital conversion, offset the first reference signal input to the first comparison circuit by a first offset voltage, and offset the second reference signal input to the second comparison circuit by a second offset voltage; during a period in which the analog-to-digital conversion is performed, the first comparison circuit compares a difference between the signal from the first pixel and the first reference signal with a first logic threshold value corresponding to a difference between a reset level voltage of the first pixel and the first offset voltage; and the second comparison circuit compares a difference between the signal from the first pixel and the second reference signal with a second logic threshold value corresponding to a difference between the reset level voltage of the first pixel and the second offset voltage; and set the first offset voltage and the second offset voltage so that a product of the reciprocal of the first rate of change and the first offset voltage is smaller than a product of the reciprocal of the second rate of change and the second offset voltage. A photoelectric conversion device characterized by:

11. 11. The photoelectric conversion device according to claim 10, wherein the absolute value of the first offset voltage is smaller than the absolute value of the second offset voltage.

12. a second pixel different from the first pixel; a second analog-to-digital conversion circuit that converts the signal from the second pixel into an analog-to-digital conversion signal; the second analog-to-digital conversion circuit includes a third comparison circuit to which two signals, the signal from the second pixel and the first reference signal, are input, and a fourth comparison circuit to which two signals, the signal from the second pixel and the second reference signal, are input; the control circuit is configured to reset the second pixel prior to the analog-to-digital conversion, offset the first reference signal input to the third comparison circuit by a third offset voltage, and offset the second reference signal input to the fourth comparison circuit by a fourth offset voltage; during a period of performing the analog-to-digital conversion, the third comparison circuit compares a difference between the signal from the second pixel and the first reference signal with a third logic threshold value corresponding to a difference between a reset level voltage of the second pixel and the first offset voltage; and the fourth comparison circuit compares a difference between the signal from the second pixel and the second reference signal with a fourth logic threshold value corresponding to a difference between the reset level voltage of the second pixel and the fourth offset voltage; and each of a product of the reciprocal of the first rate of change and the first offset voltage and a product of the reciprocal of the first rate of change and the third offset voltage is smaller than either a product of the reciprocal of the second rate of change and the second offset voltage or a product of the reciprocal of the second rate of change and the fourth offset voltage.

11. The photoelectric conversion device according to claim 10.

13. 13. The photoelectric conversion device according to claim 12, wherein the absolute value of the first offset voltage and the absolute value of the third offset voltage are smaller than the absolute value of the second offset voltage and the absolute value of the fourth offset voltage.

14. The photoelectric conversion device according to any one of claims 1 to 13, and a processing device that processes an output signal from the photoelectric conversion device.

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