Photoelectric conversion device and apparatus

Abstract

To provide a technique advantageous for preventing an increase in the number of wires while dealing with acceleration of read-out of pixel signals.SOLUTION: A photoelectric conversion device comprises: at least two pixels; and a processing circuit including at least two comparison circuits that each perform a first operation to compare pixel signals from the at least two pixels with a threshold, at least two holding circuits that hold results of the first operations, and at least two setting units. Each of the at least two holding circuits holds the result of the first operation performed by the corresponding comparison circuit of the at least two comparison circuits. The results of the first operations are transferred from the at least two holding circuits to the corresponding setting unit of the at least two setting units through a common signal line. Each of the at least two setting units sets an operating state of the processing circuit according to the results of the first operations.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus using the photoelectric conversion device. [Background technology]

[0002] There is a technology in which an analog-to-digital (AD) converter is arranged for each column of pixels arranged in a matrix, and AD conversion is performed using a ramp signal. Patent Document 1 discloses an imaging device that performs AD conversion using two ramp signals that have different voltage changes over time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2013-251677 Summary of the Invention [Problem to be solved by the invention]

[0004] When simultaneously reading out and AD converting signals from multiple pixels to speed up AD conversion, using two ramp signals can lead to a further increase in the number of wirings. An object of the present invention is to provide a technology that is advantageous in suppressing an increase in the number of wirings while supporting faster readout of pixel signals. [Means for solving the problem]

[0005] One aspect of the present invention is characterized in that it comprises a processing circuit including at least two pixels, at least two comparison circuits each performing a first operation of comparing pixel signals from the at least two pixels with a threshold value, at least two holding circuits for holding a result of the first operation, and at least two setting units, wherein each of the at least two holding circuits holds a result of the first operation of a corresponding one of the at least two comparison circuits, the result of the first operation is transferred from the at least two holding circuits to a corresponding one of the at least two setting units via a common signal line, and each of the at least two setting units sets the operating state of the processing circuit according to the result of the first operation. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a technique that is advantageous in suppressing an increase in the number of wirings while responding to an increase in the speed of pixel signal readout. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of a photoelectric conversion device according to a first embodiment. [Figure 2] 10 is a comparison example of an AD converter using two ramp signals. [Figure 3] FIG. 2 is a diagram illustrating AD conversion. [Figure 4] FIG. 2 is a diagram illustrating AD conversion. [Figure 5] FIG. 2 is a diagram illustrating AD conversion according to the first embodiment. [Figure 6] 10 is a comparative example of a photoelectric conversion device. [Figure 7] FIG. 5 is a schematic diagram of a photoelectric conversion device according to a second embodiment. [Figure 8] FIG. 10 is a schematic diagram of a photoelectric conversion device according to a third embodiment. [Figure 9] FIG. 10 is a diagram illustrating AD conversion according to the third embodiment. [Figure 10] 10 shows an example in which the photoelectric conversion device according to the embodiment is applied to equipment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0009] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the embodiments are not limited to image pickup devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measurement device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometry device (a device that measures the amount of incident light) can be used.

[0010] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0011] Furthermore, while this specification describes an amplifier that outputs an amplified signal after inputting it, amplification is not necessarily limited to increasing the signal amplitude. In other words, amplification is a concept that includes signal attenuation, and the amplification factor of the amplifier may be less than 1. Furthermore, this specification describes an analog-to-digital converter (AD converter) that converts an analog signal into a digital signal, and the conversion rate from this analog signal to a digital signal can be treated as the amplification factor. In other words, when AD conversion is performed on an analog signal of the same signal level, if a digital signal with a larger value is generated, the amplification factor of the AD converter can be said to be higher than when a digital signal with a smaller value is generated.

[0012] (Embodiment 1) Prior to describing the first embodiment, AD conversion using two ramp signals whose voltages change at different time change rates as reference signals whose voltages change at different time change rates will be described with reference to the example of FIG. 2. A ramp signal is a reference signal whose voltage value changes over time. The change referred to here is not limited to a slope-like change, but also includes, for example, a change in voltage value that changes stepwise. In other words, it includes a change in voltage value in which either an increase or decrease is continuously occurring, or a change in voltage value that is continuously alternating between an increase or decrease and a halt in the change.

[0013] The photoelectric conversion device includes pixels 100, a pixel array 110 in which the pixels 100 are arranged in a matrix, a pixel scanning unit 120, and vertical signal lines 130. Furthermore, as components related to analog-to-digital (AD) conversion, the device includes a comparison circuit 140, a ramp generator 150, a determination result transfer line 210, a determination circuit 300, and a counter 360. The device may also include a horizontal scanning circuit 400 and an output unit including an output circuit 500 for outputting AD-converted data. The pixel 100 includes a photoelectric conversion unit including a photoelectric conversion element, a floating diffusion that converts the charge accumulated in response to light incident on the photoelectric conversion element into a potential, a transfer transistor that transfers the converted potential to the vertical signal line 130, and an amplification transistor.

[0014] The comparison circuit 140 has a comparator 160, a switching unit 170, and a selection unit 200. The switching unit 170 has a switch 180 and a switch 190. The selection unit 200 has a logic circuit 250. The determination circuit 300 has a holding circuit 320, a pulse generator 330, and a memory 340. The horizontal scanning circuit 400 has a horizontal transfer selection switch 420, a transfer memory 430, and a logic circuit 440. The ramp generator 150 outputs two ramp signals rampL and ramppH whose voltages change at different rates and have different slopes.

[0015] The counter 360 counts clocks and outputs a count signal cnt corresponding to the count value. Furthermore, control signals s2 and s3 are input to the selection unit 200, which selects either the ramp signal rampL or the ramp signal rampH during AD conversion. A control signal s1 for controlling the holding circuit 320 is supplied to the determination circuit 300, and transfer signals ATX and BTX for controlling the transfer memory 430 and a horizontal selection signal are supplied to the horizontal scanning circuit 400. The output of the comparator 160 is output to the determination circuit 300 via a comparator output line 310. The output of the memory 340 is output to an AD result output line 410.

[0016] Next, using FIG. 3, we will explain the AD conversion operation performed in the example of FIG. 2 when the pixel signal output from the pixel 100 to the vertical signal line 130 is at a level corresponding to low brightness. Between time t0 and time t2, the reset level potential of the pixel is AD converted. This AD change makes it possible to obtain a noise level signal. Note that the pixel 100 is initially in a reset state.

[0017] First, at time t0, control signal s2 is controlled to H level and control signal s3 is controlled to L level. When control signal s2 becomes H level, selection unit 200 enters a state in which selection is possible using control signal s3, and when control signal s3 becomes L level, switching unit 170 is controlled so that switch 180 is on and switch 190 is off. Ramp rampL is selected by control of switching unit 170 by selection unit 200. As a result, ramp signal rampL is input to the non-inverting input terminal of comparator 160.

[0018] At this time, the pixel 100 is reset, and the potential of the vertical signal line 130 is at a level equivalent to the reset level of the pixel 100. In other words, the potential of the vertical signal line 130 indicates the noise level. At this time, the potential of the non-inverting input terminal of the comparator 160 is greater than the potential of the inverting input terminal, so the output of the comparator 160 is at H level. After time t0, the potential of the ramp signal rampL decreases, and the count signal cnt counts up. At time t1, when the ramp signal rampL falls below the potential of the vertical signal line 130, the output of the comparator 160 transitions from H level to L level. In response to the output of the comparator 160, the pulse generator 330 generates a short one-shot pulse and supplies it to the memory 340.

[0019] The one-shot pulse writes the value of the count signal cnt of the counter 360 at time t1 to the memory 340. In this embodiment, the relationship between the ramp signal rampL and the potential of the vertical signal line 130 has been described as the output of the comparator 160 transitioning when the ramp signal rampL falls below the potential of the vertical signal line 130. However, the change in the ramp signal rampL can be reversed so that the output of the comparator 160 transitions when the ramp signal rampL exceeds the potential of the vertical signal line 130. For example, an amplifier that inverts and amplifies the signal of the vertical signal line 130 may be provided, and the output of this amplifier may be provided to the comparator 160. In this configuration, due to the inverting amplification by the amplifier, the voltage value of the signal input to the comparator 160 increases as more light enters the pixel. In such a case, the ramp signals rampL and ramppH may be signals that change so that their voltage value increases over time.

[0020] The count signal cnt written to the memory 340 is a count value corresponding to the magnitude of the analog signal. This count value becomes the data resulting from AD conversion using the ramp signal rampL relative to the reset level. At time t2, the ramp signal rampL and the count signal cnt are reset, and the output of the comparator 160 returns from L level to H level. The data resulting from AD conversion written at t1 is written from the memory 340 to the selected transfer memory 430 by the logic circuit 440, which receives the transfer signal BTX at time t2. The horizontal transfer selection switch 420 is controlled by the horizontal selection signal to select the transfer memory 430, and the selected data is transferred to the output circuit 500.

[0021] After that, at time t3, the control signal s3 switches to H level. This causes the selection unit 200 to control the switching unit 170 to turn off the switch 180 and turn on the switch 190. As a result, the ramp signal ramppH is input to the non-inverting input terminal of the comparator 160 via the switch 190. After time t3, the potential of the ramp signal ramppH decreases, during which time the counter 360 counts up and outputs the count value as the count signal cnt. When the ramp signal ramppH falls below the potential of the vertical signal line 130 at time t4, the output of the comparator 160 transitions to L level, causing the pulse generator 330 to generate a one-shot pulse. The one-shot pulse is supplied to the memory 340. As a result of this operation, the count signal cnt is written to the memory 340 at time t4.

[0022] The count signal cnt written to the memory 340 is a count value corresponding to the magnitude of the analog signal. This count value becomes the AD conversion result based on the ramp signal rampL relative to the reset level. At time t5, the control signal s3 goes low, the ramp signal rampL and the count signal cnt are reset, and the output of the comparator 160 returns from low to high. At time t5, the written AD conversion result is written from the memory 340 to the selected transfer memory 430 by the logic circuit 440 that has received the transfer signal BTX. In addition, the horizontal transfer selection switch 420 is controlled by the horizontal selection signal to select the transfer memory 430, and the selected data is transferred to the output circuit 500. When the control signal s3 returns to low at time t5, the ramp signal rampL is again input to the non-inverting input of the comparator 160.

[0023] At time t6, a pixel signal corresponding to the charge accumulated in a photoelectric conversion element of the photoelectric conversion unit of the pixel 100, such as a photodiode, in response to incident light is transferred to the vertical signal line 130. At this time, the potential of the vertical signal line 130 is set to a level corresponding to a low-luminance optical signal. At this timing, the potential of the ramp signal rampL is lowered to a predetermined reference potential, and the level of the vertical signal line 130 is determined. In this embodiment, the ramp signal can be selected depending on whether it is greater than or less than the reference potential (threshold value). Note that this threshold value is preferably set to a voltage whose amplitude is smaller than the voltage value reached at time t11 by the ramp signal rampL, whose potential changes from time t9 during AD conversion of the pixel signal, which will be described later.

[0024] In this specification, amplitude is considered to be the absolute value of the difference between the reference voltage and the actual voltage. In other words, in this embodiment, a voltage whose amplitude is smaller than the target voltage of the ramp signal rampL is a voltage whose amplitude is greater than the target voltage of the ramp signal rampL. Setting the threshold in this manner ensures AD conversion accuracy for pixel signals whose levels are close to the target voltage of the ramp signal rampL. If the threshold value is set to the same value as the target voltage of the ramp signal rampL, the ramp signal rampL may be selected in determining the level of the vertical signal line 130. However, if the amplitude of the vertical signal line 130 increases due to external noise or fluctuations in the power supply voltage during subsequent AD conversion, it may exceed the target voltage of the ramp signal rampL.

[0025] In this case, the output of the comparator 160 does not change, making it difficult to perform AD conversion correctly. By setting the threshold to a voltage whose amplitude is smaller than the ultimate voltage value of the ramp signal rampL, it is possible to determine that the ramp signal ramppH should be used for signal levels on the vertical signal line 130 that are close to the ultimate voltage value of the ramp signal rampL. This makes it possible to perform AD conversion appropriately even for signals whose levels are close to the ultimate voltage value of the ramp signal rampL.

[0026] 2, the incident light is of low luminance, so the potential of the vertical signal line 130 exceeds the reference potential determined by the ramp signal rampL, and the output of the comparator 160 becomes L level. At this time, the control signal s1 is set to H level during the period from time t6 to t7, thereby enabling the hold circuit 320 to write, and the L level determined by the comparator 160 is written to the hold circuit 320.

[0027] During the period from time t7 to t8, the logic circuit 440 that has received the transfer signal ATX writes the determination result into the transfer memory 430. At time t8, the ramp signal rampL is returned to the start level of the ramp signal rampL, and the output of the comparator 160 returns to the H level.

[0028] Then, by setting the control signal s2 to L level at time t9, the selection unit 200 can be put into a state where it is controlled by the output of the holding circuit 320. At this time, the determination result written to the holding circuit 320 can be reflected in the selection unit 200. During the period from time t6 to t7, an L level is written to the holding circuit 320. The selection unit 200 controls the switching unit 170 in response to the L level signal from the holding circuit 320, so that the switch 180 is turned on and the switch 190 is turned off. As a result, the ramp signal rampL can be input to the non-inverting input terminal of the comparator 160. At this time, the selection unit 200 selects the ramp signal and supplies it to the comparator, functioning as a setting unit that sets the operating state of the AD conversion.

[0029] After time t9, AD conversion of pixel signals corresponding to low-luminance incident light is performed. From time t9, the potential of the ramp signal rampL decreases, and the count signal cnt counts up. At time t10, the potential of the ramp signal rampL falls below the potential of the vertical signal line 130. At time t10, the comparator output transitions to the L level, and the AD conversion result based on the ramp signal rampL for the signal level is written to the memory 340. At time t11, the ramp signal rampL and the count signal cnt are reset.

[0030] After time t11, the AD conversion result written to the memory 340 at t10 is written to the transfer memory 430 selected by the logic circuit 440 that received the transfer signal BTX. The result of the comparison with the reference signal and the result of the AD conversion of the pixel signal, which were previously written to the transfer memory 430, are selected by the horizontal transfer selection switch 420 using a horizontal selection signal and are then horizontally transferred to the output circuit 500. The output circuit 500 performs processing such as "SN processing," which subtracts noise level data from pixel signal data, on the AD conversion result horizontally transferred from the transfer memory 430. After processing, a signal is output from the output circuit 500. At this time, the output circuit can perform different processing on the AD conversion result depending on the result of the comparison. This will be described later.

[0031] As described above, when the signal level of the pixel signal on the vertical signal line 130 corresponds to low brightness, the ramp signal rampL with a smaller slope is selected and used, thereby reducing random noise due to quantization errors and the like, and enabling highly accurate AD conversion.

[0032] Next, using FIG. 4, we will explain the AD conversion operation performed in FIG. 2 when the signal level output from the pixel 100 to the vertical signal line 130 is high luminance. The operation up to time t6, where the noise level is AD converted, is the same as that in FIG. 3. At time t6, a pixel signal corresponding to the charge accumulated in the photoelectric conversion unit of the pixel 100 in response to incident light is transferred to the vertical signal line 130. At this time, the potential of the vertical signal line 130 reaches a level corresponding to a high-luminance optical signal. At this timing, the potential of the ramp signal rampL is reduced to a predetermined reference potential, and the level of the vertical signal line 130 is determined. In this embodiment, the ramp signal can be selected depending on whether the potential is greater than or less than the reference potential.

[0033] 4, since the incident light is of high luminance, the reference potential of the ramp signal rampL exceeds the potential of the vertical signal line 130, and the output of the comparator 160 remains unchanged at H level. At this time, the control signal s1 is set to H level during the period from time t6 to t7, thereby enabling the hold circuit 320 to be written, and the H level determined by the comparator 160 is written to the hold circuit 320.

[0034] A ramp signal to be used when AD converting pixel signals is determined during a period from time t6 in which the signal level of the vertical signal line 130 is compared with a reference potential. The result written to the holding circuit 320 changes depending on the result of this determination. At time t8, the transfer signal ATX falls, and the determination result is stored in the transfer memory 430. At time t9, the control signal s2 is set to L level, thereby enabling the selection unit 200 to be controlled by the output of the holding circuit 320. A H level is written to the holding circuit 320. In response to the H level signal from the holding circuit 320, the selection unit 200 controls the switching unit 170, so that the switch 180 is turned off and the switch 190 is turned on. As a result, the ramp signal ramppH can be input to the non-inverting input terminal of the comparator 160.

[0035] From time t9, AD conversion is performed using the ramp signal ramppH. At time t10, the ramp signal ramppH falls below the potential of the vertical signal line, so that the comparator output of the comparator 160 transitions from H level to L level, and the pulse generator 330 generates a one-shot pulse in response to the transition of the output of the comparator 160. The one-shot pulse causes the value of the count signal cnt of the counter 360 to be written to the memory 340. After time t11, the AD conversion result written to the memory 340 at time t10 is written to the transfer memory 430 selected using the BTX signal and the logic circuit 440. The comparison result with the reference potential and the AD conversion result written to the transfer memory 430 may be horizontally transferred to the output circuit 500 by selecting the horizontal transfer selection switch 420 using a horizontal selection signal.

[0036] At this time, the output circuit 500 may perform "SN processing" to subtract noise level data from data corresponding to the pixel signal according to the determination result of the holding circuit 320. Furthermore, the signal may be output after processing such as applying a gain according to the ratio of the slopes of the ramp signals rampL and ramppH. In addition, it is also possible to perform processing such as correcting offset differences that occur due to differences in the start timing of operation between the ramp signals rampL and ramppH or differences in propagation delay.

[0037] As described above, when the signal level of the vertical signal line 130 corresponds to high brightness, the ramp signal rampH with a steeper slope is selected and used. As a result, although random noise in AD conversion due to quantization error and the like increases, the optical shot noise that appears on the vertical signal line 130 side becomes dominant, making it possible to shorten the readout time while minimizing the impact on the total random noise.

[0038] Next, this embodiment will be described with reference to FIG. 1. Here, the differences from FIG. 2 will be described. In the example of the photoelectric conversion device in FIG. 1, in order to read signals from the pixels 100 at high speed, a process of simultaneously reading out the pixels 100 arranged in two rows in the pixel array 110 is performed. To achieve this, two first comparison circuits 140-1 and second comparison circuits 140-2, and two first determination circuits 300-1 and second determination circuits 300-2 are vertically stacked in the column direction. Here, an example of simultaneously reading out two rows will be described, but the number of rows and columns and the number of simultaneously readout pixels are not limited.

[0039] In the following, when describing items with the same name and numbers such as "first" and "second," the numbers such as "first" and "second" may be omitted. Also, when describing items with branch numbers such as "300-1" and "300-1," the branch numbers "-1" and "-2" in the reference numbers may be omitted.

[0040] The first judgment circuit 300-1 and the second judgment circuit 300-2 are provided with a first serial transfer switch 350-1 and a second serial transfer switch 350-2. The judgment result transfer line 210 is shared by the two judgment circuits 300 and the two comparison circuits 140; in other words, the judgment result transfer line 210 is configured to be shared by multiple judgment circuits 300 and comparison circuits 140. Each of the two selection units 200 has a memory 215. Transfer signals ATX1, ATX2, BTX1, and BTX2 are input to the horizontal scanning circuit 400. The transfer signal ATX1 is input to the first comparison circuit 140-1 and the first judgment circuit 300-1. The transfer signal ATX2 is input to the second comparison circuit 140-2 and the second judgment circuit 300-2.

[0041] The serial transfer switches 350-1 and 350-2 connect the outputs of the holding circuits 320-1 and 320-2 to the decision result transfer line 210, respectively. The switches 350-1 and 350-2 are controlled by transfer signals ATX1 and ATX2, respectively. The memory 215-1 of the first selection unit 200-1 receives the decision result transfer line 210 as an input, and latches and stores the level of the decision result transfer line 210 at the falling edge of the transfer signal ATX1. The memory 215-2 of the second selection unit 200-2 receives the decision result transfer line 210 as an input, and latches and stores the level of the decision result transfer line 210 at the falling edge of the transfer signal ATX2. Reading of each memory 215 can be controlled by the logic circuit 250.

[0042] The first comparison circuit 140-1, the second comparison circuit 140-2, the first judgment circuit 300-1, and the second judgment circuit 300-2 can each be referred to as a circuit block. The judgment result transfer line 210 is shared between the circuit blocks. The judgment result transfer line 210 is also connected to the input of the transfer memory 430 of the horizontal scanning circuit 400. The signal on the judgment result transfer line 210 is stored in one of the transfer memories 430-1 to 430-4 selected by the transfer signal ATX1 or ATX2 and the logic circuit 440. The circuit 400 also has an output unit including the horizontal scanning circuit 400 and an output circuit 500 to output AD converted data. In this embodiment, the judgment circuit and the comparison circuit can be considered as processing circuits that process pixel signals.

[0043] Next, the operation of this embodiment will be described with reference to FIG. 5. Here, as explained in FIG. 3, the operation when the incident light is of low luminance will be explained. The operation from time t0 to t2 is the AD conversion period for the reset level by the ramp signal ramnpL, as in FIG. 3. The difference is that AD conversion is performed simultaneously for two pixels using the first comparison circuit 140-1 and first determination circuit 300-1, and the second comparison circuit 140-2 and second determination circuit 300-2, respectively.

[0044] At time t2, the vertical signal line potentials for the outputs from each of the two pixels and the AD conversion results based on rampL are transferred to and stored in the transfer memories 430-5 and 430-7 using the transfer signals BTX1 and BTX2. AD conversion for the reset level using the ramp signal ramppH is performed between times t3 and t5, and the AD conversion results are transferred to the transfer memories 430-6 and 430-8 using the transfer signals BTX1 and BTX2 at time t5. The comparison result with the reference potential and the AD conversion result data stored in the transfer memory 430 are transferred to the output circuit 500 using a horizontal selection signal. At this time, the output circuit 500 may perform "SN processing" in which noise level data is subtracted from data corresponding to the pixel signal based on the determination result of the holding circuit 320. Furthermore, the signal may be output after processing such as applying a gain depending on the ratio of the slopes of the ramp signals rampL and ramppH.

[0045] The period from time t6 to time t8 is a period in which the pixel signal level is compared with the magnitude of a reference signal, and the determination result is written to the first holding circuit 320-1 and the second holding circuit 320-2, as described with reference to FIG. 3. At this time, the signal levels of the two pixels are compared with the reference potential and determined. Between times t7 and t8, the determination results held in the first holding circuit 320-1 and the second holding circuit 320-2 are sequentially transferred to the determination result transfer line 210. Note that, in this embodiment, an example is described in which one of two ramp signals is selected in accordance with the reference potential as in the example of FIG. 3, but two or more reference potentials may be used and three or more slopes of the ramp signal may be provided.

[0046] Between t7 and t8, the transfer signals ATX1 and ATX2 sequentially go to H level. The determination results respectively held in the holding circuits 320-1 and 320-2 are sequentially transferred to the determination result transfer line 210 as the transfer signals ATX1 and ATX2 go to H level and the serial transfer switches 350-1 and 350-2 are sequentially turned on. The determination results are sequentially transferred from the two determination circuits 300 to the two comparison circuits 140 via the determination result transfer line 210 commonly wired.

[0047] During the period from time t7 to t8, the transferred judgment results are first stored in memory 215-1 and transfer memories 430-1 and 430-2 at the falling edge of transfer signal ATX1. Next, at the falling edge of ATX2, the results are stored in memory 215-2 and transfer memories 430-3 and 430-4. Here, an example has been given in which the falling edges of transfer signals ATX1 and ATX2 are used for storage, but the rising edges can also be used depending on the circuit configuration. Furthermore, because transfer signals ATX1 and ATX2 use the same judgment result transfer line 210, the timing at which they reach the H level is staggered so that the serial transfer switch 350 is not turned on at the same time.

[0048] Logic circuits 250-1 and 250-2 control switching unit 170 according to the determination results stored in memories 215-1 and 215-2 to select a ramp signal. The selected ramp signal is input to a comparator. AD conversion has been described using two pixels as an example. As shown in FIG. 1, a comparison circuit and a determination circuit are provided corresponding to each of the two pixels, so that an appropriate ramp signal can be selected and set for each of the two pixels according to the level of incident light.

[0049] In the present embodiment, an example has been described in which the serial transfer switch 350 is controlled using the transfer signals ATX1 and ATX2. However, the present invention is not limited to this configuration as long as the determination result data can be sequentially transferred to the memory 215 corresponding to the determination result and the transfer memory 430 and stored therein. By serially transferring the determination results in this manner, it becomes possible to reduce the number of determination result transfer lines 210 when multiple comparison circuits and determination circuits are provided in order to speed up the readout of pixel signals.

[0050] The period from time t9 is a period during which pixel signals from two pixels are AD converted using the ramp signal rampL selected based on the determination result. The determination circuit and comparison circuit can be considered processing circuits that perform AD conversion processing on pixel signals. As described above, in this embodiment, a ramp signal can be selected based on the magnitude of the pixel signal from among multiple ramp signals whose voltages change at different rates over time. As a result, the operating state of the processing circuit including the comparison circuit can be changed. The AD-converted data can be transferred and stored in transfer memories 430-5 and 430-7 by transfer signals BTX1 and BTX2. The data stored in the transfer memory 430 can then be output to the output circuit 500.

[0051] In addition to the need for high-speed pixel readout, miniaturization of pixel size also reduces the pitch between columns, which means that forming a circuit by sharing the pitch among multiple columns is advantageous in terms of securing layout area and reducing the number of signal lines in a multi-tiered circuit.

[0052] Furthermore, in this embodiment, multiple simultaneous determination results are not transferred all at once using the transfer signal ATX, but are transferred at separate timings using transfer signals ATX1 and ATX2. By performing memory write operations at separate transfer timings, it is possible to distribute the peak power generated at the memory write timing. This can reduce voltage fluctuations caused by peak currents in the shared power and GND wiring. It is also possible to suppress image quality degradation.

[0053] (Embodiment 2) Next, a second embodiment will be described. Prior to describing this embodiment, an example of simultaneous AD conversion of signals from four pixels 100 will be described with reference to FIG. 6. FIG. 6 is a schematic diagram of a multi-stage circuit. Here, the operation will be described using a four-stage example in which the pixels 100 arranged in four rows are simultaneously read and AD converted by circuits arranged in blocks in one column. In this example, AD conversion is also performed using ramp signals with two different time change rates. In a pixel array 110 in which a plurality of pixels are arranged in a matrix, pixel signals from four rows selected by a pixel scanning unit 120 are supplied to four comparison circuits 140 via vertical signal lines 130.

[0054] There are four comparison circuits, a first comparison circuit 140-1 to a fourth comparison circuit 140-4. Wiring for the ramp signal rampL and ramp signal ramppH from the ramp generator 150 is connected to each comparison circuit 140. Similarly, four determination circuits 300 are required, one for each pixel 100 to be simultaneously read out, so four determination circuits 300-1 to 300-4 are provided. A counter 360 is connected to each determination circuit 300 for AD conversion.

[0055] The four comparison circuits 140 are connected to the four decision circuits 300 via decision result transfer lines 210 and comparator output lines 310, which are outputs of the holding circuits 320. Furthermore, AD result output lines 410 and decision result transfer lines 210 are connected between the four decision circuits 300-1 to 300-4 and the horizontal scanning circuit 400. The horizontal scanning circuit 400 horizontally transfers the received AD conversion results and decision results in sequence to the output circuit 500. The output circuit 500 can perform data processing according to the decision results. The processed data signals can be output to the outside.

[0056] Here, simultaneous readout from four pixels requires four comparison circuits and four decision circuits, so a total of eight lines are wired in each column between the comparison circuits and the decision circuits: four decision result transfer lines 210 and four comparator output lines 310. Also, a total of eight lines are wired in each column between the four decision circuits and the horizontal scanning circuit: four decision result transfer lines 210 and four AD result output lines 410. Simultaneous readout of four pixels has been described here as an example. When reading eight pixels simultaneously, a total of 16 lines are wired in each column, and the number of lines in the column increases in proportion to the number of pixels being read out simultaneously.

[0057] FIG. 7 is a schematic diagram of a multi-stage circuit according to this embodiment. It shows an example of four stages, the same as FIG. 6. The differences from the example of FIG. 6 will now be described. In this embodiment, by serially transferring the determination results, the number of determination result transfer lines 210 connecting the four first comparison circuits 140-1 to the fourth comparison circuit 140-4 and the four first determination circuits 300-1 to the fourth determination circuits 300-4 can be reduced to one. Furthermore, the number of comparator output lines 310 can be reduced to four. A total of five wires are wired within one column. Furthermore, the connection lines between the four determination circuits 300 and the horizontal scanning circuit 400 are one determination result transfer line 210 and four AD result output lines, for a total of five wires, wired within one column. Therefore, the number of wires within the column is reduced compared to the total of eight in the conventional example.

[0058] In this example, simultaneous reading of four pixels is used as an example, but in the case of simultaneous reading of eight pixels, a total of nine wires are wired within the column, which is reduced from the total of 16 in the conventional example. In this way, the greater the number of simultaneously read pixels, the greater the effect of reducing the number of wires within the column in this embodiment.

[0059] (Embodiment 3) The photoelectric conversion device of this embodiment will be described with reference to FIG. 8 . The photoelectric conversion device includes the pixel array 110 shown in the first embodiment. In this configuration, the vertical signal line 130 of the pixel array 110 is connected to one electrode of an input capacitance 132 in a column amplifier 131. The other electrode of the input capacitance 132 is connected to an amplifier 134 and a feedback capacitance 133 of the amplifier 134. A selection unit 200 is also arranged in the column amplifier 131, and the selection unit 200 includes a memory 215 and a logic circuit 250, as in the first embodiment. The selection unit 200 switches the capacitance value of the feedback capacitance 133, which determines the amplification factor of the amplifier 134, using switches 180 and 190 of a switching unit 170. The selection unit 200 functions as a setting unit that sets the amplification factor. In this embodiment, the amplifier 134 is an inverting amplifier.

[0060] The amplifier 134 inverts and amplifies the vertical signal potential from the vertical signal line 130 and outputs it as an image signal 135. The potential of the image signal 135 is indicated by the image signal potential (dashed line). The image signal 135 is input to the comparison circuit 140. In this embodiment, the comparison circuit 140 compares the image signal 135 with a ramp signal rampH generated by a ramp generator 150. The comparison result is input from the comparison circuit 140 to the determination circuit 300 via a comparator output line 310. The column amplifier 131 including the amplifier 134, the comparison circuit 140, and the determination circuit 300 can be said to be processing circuits that perform AD conversion processing of pixel signals. The other configurations are the same as those of the first embodiment.

[0061] Next, the operation of this embodiment will be described with reference to FIG. 9. Here, the AD conversion operation performed in FIG. 8 when the signal level of the image signal output from the pixel 100 to the vertical signal line 130 is high luminance will be described. Between time t0 and time t2, the reset level potential of the pixel is AD converted. This AD conversion makes it possible to obtain data equivalent to the noise level signal. Note that the pixel 100 is initially in a reset state.

[0062] In this embodiment, the column amplifier gain is set to four times to amplify the reset level potential. First, at time t0, the feedback capacitance 133, which determines the column amplifier gain, is selected by the selection unit 200 to provide a four-time gain. At this time, the pixel 100 is reset, and the potential of the vertical signal line 130 is at a level equivalent to the reset level of the pixel 100. In other words, the potential of the vertical signal line 130 indicates the noise level.

[0063] The vertical signal line 130 is input to an amplifier 134, which is an inverting amplifier, via an input capacitor 132. An image signal 135, which is an output signal of the amplifier 134, is connected to a non-inverting input terminal of a comparator 160. A ramp signal rampH is input to an inverting input terminal of the comparator 160. At time t0, the potential of the non-inverting input terminal of the comparator 160 is higher than the potential of the inverting input terminal, so the output of the comparator 160 becomes H level. After time t0, the potential of the ramp signal rampH increases over time. At this time, the count signal cnt counts up as the ramp signal rampH increases. At time t1, when the ramp signal rampH exceeds the potential of the image signal 135, the output of the comparator 160 transitions from H level to L level. In response to the output of the comparator 160, the pulse generator 330 generates a short-duration one-shot pulse and supplies it to a memory 340.

[0064] The one-shot pulse causes the value of the count signal cnt of the counter 360 at time t1 to be written to the memory 340. In this embodiment, the relationship between the ramp signal ramppH and the potential of the image signal 135 has been described as such that the output of the comparator 160 transitions when the ramp signal ramppH exceeds the potential of the image signal 135. However, the change in the ramp signal ramppH can be reversed so that the output of the comparator 160 transitions when the potential falls below that of the image signal 135.

[0065] For example, the amplifier 134 may be a non-inverting amplifier, and the image signal on the vertical signal line 130 may be input to the non-inverting amplifier. The output of this amplifier may be provided to the comparator 160. In this configuration, due to the non-inverting amplification by the amplifier, the voltage value of the signal input to the comparator 160 decreases as more light is incident on the pixel. In such a case, the ramp signal rampH may be a signal that changes so that its voltage value decreases over time.

[0066] The count signal cnt written to the memory 340 is a count value corresponding to the magnitude of the analog value of the image signal 135. This count value becomes data resulting from AD conversion by the ramp signal ramppH with respect to a reset level amplified by the column amplifier 131 at an amplification factor of 4. At time t2, the ramp signal ramppH and the count signal cnt are reset, and the output of the comparator 160 returns from L level to H level. Also at time t2, the written data resulting from AD conversion is written from the memory 340 to the selected transfer memory 430 by the logic circuit 440 that has received the transfer signal BTX. Also, the horizontal transfer selection switch 420 is controlled by a horizontal selection signal to select the transfer memory 430, and the selected data is transferred to the output circuit 500.

[0067] At time t3, a pixel signal corresponding to the charge accumulated in a photoelectric conversion element of the photoelectric conversion unit of the pixel 100, for example, a photodiode, in response to incident light is transferred to the vertical signal line 130. In this embodiment, the operation will be described assuming that the pixel signal is at a high brightness level. Therefore, the potential of the vertical signal line 130 is at a level corresponding to a high-brightness optical signal. The pixel signal is amplified by the column amplifier 131 and input to the comparison circuit 140. It is assumed that the amplification factor of the column amplifier is set to 4 at time t3.

[0068] At time t4, the potential of the ramp signal ramppH is increased to a predetermined reference potential indicated by a solid line, and a determination operation is performed in which the potential is compared with the potential of the image signal 135 indicated by a dashed line. In this embodiment, the amplification factor of the column amplifier 131 can be selected depending on whether the reference potential is greater or less than a reference potential (threshold value). Note that this threshold value is preferably set to a voltage whose amplitude is smaller than the voltage value that the ramp signal ramppH, whose potential changes from time t7, reaches at time t9 during AD conversion of the pixel signal, which will be described later. According to this embodiment, the operating state of the processing circuit, including the amplification factor of the column amplifier, can be changed.

[0069] In this specification, the amplitude is considered to be the absolute value of the difference between the reference voltage value for the change and the changed voltage value. In other words, in this embodiment, a voltage having an amplitude smaller than the target voltage value of the ramp signal ramppH is a voltage having a voltage value smaller than the target voltage value of the ramp signal ramppH. By setting the threshold value in this manner, it is possible to ensure the AD conversion accuracy for pixel signals at levels near the target voltage value of the ramp signal ramppH.

[0070] If the threshold voltage is set to the same value as the target voltage of the ramp signal ramppH, the amplitude of the image signal 135 may exceed the target voltage of the ramp signal ramppH during subsequent AD conversion if it increases due to external noise or fluctuations in the power supply voltage. In this case, the output of the comparator 160 does not change, making it difficult to perform AD conversion correctly. By setting the threshold voltage to a voltage whose amplitude is smaller than the target voltage of the ramp signal ramppH, it is possible to change the column amplifier amplification factor to 1 for signal levels of the image signal 135 near the target voltage of the ramp signal ramppH and make a judgment. This allows AD conversion to be performed appropriately even for signals with levels near the target voltage of the ramp signal ramppH.

[0071] 9, since the incident light is high in brightness, the potential of the image signal 135 exceeds the reference potential determined by the ramp signal rampH, and the output of the comparator 160 becomes H level. At this time, the control signal s1 is set to H level during the period from time t4 to t5, thereby enabling the hold circuit 320 to be written, and the H level determined by the comparator 160 is written to the hold circuit 320.

[0072] During the period from time t4 to t5, an H level is written to the holding circuit 320. The values ​​written to the two holding circuits 320 are transferred to the memory 215 of the selection unit 200 in turn by transfer signals ATX1 and ATX2 from time t5 to t6. Then, by setting the control signal s2 to an L level at time t6, the selection unit 200 can be put into a state controlled by the output of the holding circuit 320. In this example, the incident light is set to high intensity, so the switch 180 is turned on and the switch 190 is turned off. As a result, the amplification factor of the column amplifier 131 is changed from 4x to 1x.

[0073] During the period from time t5 to time t6, the logic circuit 440 that has received the transfer signal ATX1 or ATX2 writes the determination result into the transfer memory 430.

[0074] In the description of this embodiment, the gain of the column amplifier 131 is exemplified by 4x and 1x, but the gain is not limited to this. A plurality of thresholds may be provided to set a selected gain from the plurality of gains. In this embodiment, the gain of the column amplifier 131 is changed to 1, so that the non-inverting input terminal of the comparator 160 can receive the image signal 135, which is the pixel signal from the vertical signal line 130 inverted and amplified by an gain of 1. Furthermore, as shown in FIG. 8 , a comparison circuit and a determination circuit are provided corresponding to each of the two pixels, so that an appropriate gain of the column amplifier can be selected and set for each of the two pixels depending on the level of incident light.

[0075] After time t7, AD conversion of pixel signals corresponding to high-luminance incident light is performed. From time t7, the potential of the ramp signal ramppH increases, and the count signal cnt counts up. At time t8, the potential of the ramp signal ramppH exceeds the potential of the image signal 135. At time t8, the comparator output transitions to the L level, and the AD conversion result based on the ramp signal ramppH for the signal level is written to the memory 340. At time t9, the ramp signal rampL and the count signal cnt are reset. After time t9, the information written to the memory 340 is processed in the same manner as in the first embodiment.

[0076] <Examples of photoelectric conversion device applications> Hereinafter, a device 1000 will be described that includes a semiconductor device 1100 including a package 1020 on which a semiconductor chip 1110 including a semiconductor integrated circuit is mounted, as shown in FIG. 10 . The semiconductor chip 1110 is housed in the package 1020 and mounted on the device 1000. In the configuration shown in FIG. 10 , the semiconductor chip 1110 includes a photoelectric conversion device according to the above-described embodiment. The semiconductor device 1100 can include a package 1020 that includes a base 1010 to which the semiconductor chip 1110 is fixed, and a light-transmitting member 1030 such as glass that faces the semiconductor chip 1110. The package 1020 can include bonding members such as wires and bumps that connect inner leads provided on the base 1010 to terminals such as pad electrodes provided on the semiconductor chip 1110.

[0077] The device 1000 may include at least one of an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls a semiconductor chip 1110. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0078] The processing device 1060 processes an output signal from a photoelectric conversion device included in the semiconductor chip 1110. The processing device 1060 is a semiconductor device such as a CPU or ASIC for configuring an AFE analog front end or a DFE digital front end. For example, when an event is detected, an image may be generated based on the imaging signal. The display device 1070 is an EL display device or a liquid crystal display device that displays an information image obtained by the semiconductor chip 1110. The storage device 1080 is a magnetic device or a semiconductor device that stores the information image obtained by the semiconductor chip 1110. The storage device 1080 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0079] The mechanical device 1090 has a moving part or a propulsion part such as a motor or an engine. In the device 1000, the signal output from the semiconductor chip 1110 is displayed on the display device 1070, or transmitted to the outside by a communication device (not shown) included in the device 1000. For this purpose, the device 1000 may further include a storage device 1080 and a processing device 1060 in addition to the memory circuit and arithmetic circuit included in the semiconductor chip 1110. The mechanical device 1090 may be controlled based on the signal output from the semiconductor chip 1110.

[0080] The device 1000 is suitable for electronic devices such as information terminals with a photographing function, such as smartphones, wearable devices, and cameras, such as interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras. The mechanical device 1090 in the camera may be a device that can drive components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in the camera may be a device that can move the optical device 1040 for vibration isolation.

[0081] Furthermore, the device 1000 may be transportation equipment such as a vehicle or a ship. The mechanical device 1090 in the transportation equipment may be used as a moving device. The device 1000 as transportation equipment is suitable for transporting semiconductor chips 1110 or for assisting and / or automating driving by using a photographing function. The processing device 1060 for assisting and / or automating driving can perform processing for operating the mechanical device 1090 as a moving device based on information obtained by the semiconductor chip 1110. Alternatively, the device 1000 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0082] (Other embodiments) The disclosure of the present specification includes the following photoelectric conversion device and equipment using the photoelectric conversion device. (Item 1) at least two pixels; a processing circuit including at least two comparison circuits each performing a first operation of comparing pixel signals from the at least two pixels with a threshold, at least two holding circuits each holding a result of the first operation, and at least two setting units; each of the at least two holding circuits holds a result of the first operation of a corresponding one of the at least two comparing circuits; a result of the first operation is transferred from the at least two holding circuits to a corresponding one of the at least two setting units via a common signal line; each of the at least two setting units sets an operation state of the processing circuit according to a result of the first operation; A photoelectric conversion device characterized by: (Item 2) setting the operating state includes setting a reference signal selected from a plurality of reference signals whose voltages change at different change rates over time; the at least two comparison circuits perform a second operation of comparing the pixel signal with the selected reference signal; 2. The photoelectric conversion device according to item 1, (Item 3) 3. The photoelectric conversion device according to item 1 or 2, wherein the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix. (Item 4) 4. The photoelectric conversion device according to item 3, wherein the number of different rows is 2, 4, or 8. (Item 5) 5. The photoelectric conversion device according to any one of items 1 to 4, wherein the results of the first operation held in the at least two holding circuits are transferred to the signal line in sequence. (Item 6) a counter and a memory for storing a count value of the counter; 3. The photoelectric conversion device according to item 2, characterized in that in the second operation, the count value counted during the period until the selected reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory. (Item 7) 7. The photoelectric conversion device according to any one of items 1 to 6, further comprising an output section, wherein the result of the first operation is supplied to the output section via the signal line. (Item 8) the processing circuit further includes an amplifier that amplifies the pixel signal by a set amplification factor; 2. The photoelectric conversion device according to item 1, wherein the setting of the operating state includes setting the amplification factor. (Item 9) 9. The photoelectric conversion device according to item 8, wherein the at least two comparison circuits perform a second operation of comparing the pixel signal with a reference signal whose voltage changes over time. (Item 10) 10. The photoelectric conversion device according to item 8 or 9, wherein the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix. (Item 11) 11. The photoelectric conversion device according to item 10, wherein the number of different rows is 2, 4, or 8. (Item 12) 12. The photoelectric conversion device according to any one of items 8 to 11, wherein the results of the first operation held in the at least two holding circuits are transferred to the signal line in sequence. (Item 13) a counter and a memory for storing a count value of the counter; Item 10. The photoelectric conversion device according to item 9, characterized in that in the second operation, the count value counted during the period until the reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory. (Item 14) 14. The photoelectric conversion device according to any one of items 8 to 13, further comprising an output section, wherein the result of the first operation is supplied to the output section via the signal line. (Item 15) The photoelectric conversion device according to any one of items 1 to 14, and a processing device that processes an output signal from the photoelectric conversion device.

[0083] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0084] 100: pixel, 110: pixel array, 120: pixel scanning unit, 130: vertical signal line, 131: column amplifier, 132: input capacitance, 133: feedback capacitance, 134: amplifier, 135: image signal, 140: comparison circuit, 150: ramp generator, 160: comparator, 170: switching unit, 180: switch, 190: switch, 200: selection unit, 210: decision result transfer line, 215: memory, 250: logic circuit, 300: decision circuit, 310: comparator output line, 320: holding circuit, 330: pulse generator, 340: memory, 350: serial transfer switch, 360: counter, 400: horizontal scanning circuit, 410: AD result output line, 420: horizontal transfer selection switch, 430: transfer memory, 440: logic circuit, 500: output circuit

Claims

1. at least two pixels; a processing circuit including at least two comparison circuits each performing a first operation of comparing pixel signals from the at least two pixels with a threshold value, at least two holding circuits each holding a result of the first operation, and at least two setting units; each of the at least two holding circuits holds a result of the first operation of a corresponding one of the at least two comparing circuits; a result of the first operation is transferred from the at least two holding circuits to a corresponding one of the at least two setting units via a common signal line; each of the at least two setting units sets an operation state of the processing circuit according to a result of the first operation; A photoelectric conversion device characterized by:

2. setting the operating state includes setting a reference signal selected from a plurality of reference signals whose voltages change at different change rates over time; the at least two comparison circuits perform a second operation of comparing the pixel signal with the selected reference signal; 2. The photoelectric conversion device according to claim 1.

3. 2. The photoelectric conversion device according to claim 1, wherein the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix.

4. 3. The photoelectric conversion device according to claim 2, wherein the number of different rows is 2, 4, or 8.

5. 2. The photoelectric conversion device according to claim 1, wherein the results of the first operation held in the at least two holding circuits are transferred to the signal line in order.

6. a counter and a memory for storing a count value of the counter; The photoelectric conversion device according to claim 2, characterized in that in the second operation, the count value counted during the period until the selected reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory.

7. 2. The photoelectric conversion device according to claim 1, further comprising an output section, wherein the result of the first operation is supplied to the output section via the signal line.

8. the processing circuit further includes an amplifier that amplifies the pixel signal by a set amplification factor; 2. The photoelectric conversion device according to claim 1, wherein the setting of the operating state includes setting the amplification factor.

9. 9. The photoelectric conversion device according to claim 8, wherein the at least two comparison circuits perform a second operation of comparing the pixel signal with a reference signal whose voltage changes over time.

10. 9. The photoelectric conversion device according to claim 8, wherein the at least two pixels are arranged in different rows in a pixel array in which a plurality of pixels are arranged in a matrix.

11. 11. The photoelectric conversion device according to claim 10, wherein the number of different rows is 2, 4, or 8.

12. 9. The photoelectric conversion device according to claim 8, wherein the results of the first operation held in the at least two holding circuits are transferred to the signal line in order.

13. a counter and a memory for storing a count value of the counter; The photoelectric conversion device according to claim 9, characterized in that in the second operation, the count value counted during the period until the reference signal exceeds or falls below the magnitude of the pixel signal is stored in the memory.

14. 9. The photoelectric conversion device according to claim 8, further comprising an output section, wherein the result of the first operation is supplied to the output section via the signal line.

15. The photoelectric conversion device according to any one of claims 1 to 14, and a processing device that processes an output signal from the photoelectric conversion device.

Images