Solar cell and photovoltaic module

Abstract

To provide a solar cell and a photovoltaic module that can improve photovoltaic conversion efficiency.SOLUTION: The back surface of a semiconductor substrate 1 includes alternating N-type conductive regions 2 and P-type conductive regions 3, a first passivation layer 5 is provided on the P-type conductive region 3 side away from the semiconductor substrate 1, and the length of the first passivation layer 5 along a first direction is greater than the length of the P-type conductive region 3 along the first direction, and a second passivation layer 6 is provided on the N-type conductive region 2 side away from the semiconductor substrate 1, and the length of the second passivation layer 6 along the first direction is smaller than the length of the N-type conductive region 2 along the first direction, the first direction is a direction parallel to a plane in which the semiconductor substrate 1 is located. A first doped conductive layer 7 is provided on the first passivation layer 5 side away from the semiconductor substrate 1, and a second doped conductive layer 8 is provided on the second passivation layer 6 side away from the semiconductor substrate 1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application relates to the field of photovoltaic technology, and in particular to solar cells and photovoltaic modules. [Background technology]

[0002] As the energy crisis and environmental pollution worsen, humanity's demand for renewable energy is growing. Solar energy, with its advantages of safety, pollution-free, and unrestricted geographical location, is the most widely applied and promising of the various renewable energies. Among the various technologies for effectively utilizing solar energy, photovoltaics is undoubtedly one of the most promising. Among the many new solar cells, back-contact solar cells, also known as interdigitated back contact (IBC) solar cells, are a type of back-contact solar cell. The greatest feature of IBC solar cells is that both the emitter and base electrodes are located on the back surface of the cell, reducing light shading. Compared to solar cells with shaded light-receiving surfaces, IBC cells have higher short-circuit currents and higher photoelectric conversion efficiencies.

[0003] IBC cells maximize the utilization of incident photons by eliminating the loss caused by the shielding of the electrode grid lines because the front surface is unshielded. Accordingly, p+ and n+ regions must be formed interdigitally on the back surface of the cell, and a gap region must be formed between the p+ and n+ regions to separate them and prevent short-circuiting. However, the back surface structure of conventional IBC cells limits the improvement of the cell's photoelectric conversion efficiency. Therefore, how to improve the photoelectric conversion efficiency of IBC cells remains a current problem to be solved. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a solar cell and a solar power generation module, which can improve the light utilization rate of the non-light-receiving side of the solar cell and reduce parasitic absorption of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present application provides a solar cell, the solar cell including a semiconductor substrate, a first passivation layer, a second passivation layer, a first doped conductive layer, a second doped conductive layer, a first electrode, and a second electrode; the semiconductor substrate includes a front surface and a back surface disposed opposite to each other, the back surface of the semiconductor substrate has alternating N-type conductive regions and P-type conductive regions, the first passivation layer is disposed on a side of the P-type conductive regions away from the semiconductor substrate, and a length of the first passivation layer along a first direction is greater than a length of the P-type conductive regions along the first direction, the second passivation layer is disposed on a side of the N-type conductive regions away from the semiconductor substrate, and a length of the second passivation layer along the first direction is smaller than a length of the N-type conductive regions along the first direction, the first direction being a direction parallel to a plane in which the semiconductor substrate is located; the first doped conductive layer is disposed on a side of the first passivation layer away from the semiconductor substrate; the second doped conductive layer is disposed on a side of the second passivation layer away from the semiconductor substrate; the first electrode forms an ohmic contact with the first doped conductive layer; The second electrode forms an ohmic contact with the second doped conductive layer.

[0006] In a second aspect, an embodiment of the present application provides a photovoltaic module, the photovoltaic module including a cover plate, an encapsulant layer, and a solar cell string, the solar cell string including a plurality of solar cells according to the first aspect. [Effects of the Invention]

[0007] Compared with the prior art, the technical solution of the present application has at least the following beneficial effects:

[0008] In the solar cell of the present application, the back surface of the semiconductor substrate has alternating N-type conductive regions and P-type conductive regions, the N-type conductive regions are doped with an N-type element, the P-type conductive regions are doped with a P-type element, a first passivation layer is provided on the P-type conductive region on a side facing away from the semiconductor substrate, and a first doped conductive layer is provided on the first passivation layer on a side facing away from the semiconductor substrate, a first passivation contact structure can be formed on the P-type conductive region, and the length of the first passivation layer in the first direction is greater than the length of the P-type conductive region in the first direction, allowing the size of the first passivation contact structure to be increased, thereby increasing the reflection area of ​​the first passivation contact structure in the P-type conductive region for front-on incident light, allowing the front-on incident light to be reflected into the semiconductor substrate and absorbed by the semiconductor substrate for use, and increasing the number of reflections of the reflected light on the back surface of the solar cell, improving the light utilization rate on the back surface of the solar cell and thereby improving the photoelectric conversion efficiency of the solar cell. A second passivation layer is provided on the N-type conductivity region on a side facing away from the semiconductor substrate, and a second doped conductive layer is provided on the second passivation layer on a side facing away from the semiconductor substrate, and a second passivation contact structure can be formed on the N-type conductivity region, and the length of the second passivation layer in the first direction is smaller than the length of the N-type conductivity region in the first direction, allowing the size of the second passivation contact structure on the N-type conductivity region to be reduced, thereby reducing parasitic absorption of light in the second passivation contact structure and improving the photoelectric conversion efficiency of the solar cell. Furthermore, the N-type conductivity region and the P-type conductivity region of the present application are designed with passivation contact structures of different sizes, which can reduce the carrier recombination rate at the lateral boundary between the N-type conductivity region and the P-type conductivity region, reducing the electrode contact resistance between the first electrode and the second electrode on the back surface, thereby further improving the photoelectric conversion efficiency of the solar cell. The present application designs the size of the passivation contact structures in different regions on the back surface of the solar cell, which can improve the light utilization efficiency of the back surface of the solar cell, reduce the parasitic absorption of the solar cell, and reduce the carrier recombination rate in different regions on the back surface of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a structural schematic diagram of a solar cell provided in an embodiment of the present application. [Figure 2] 1 is a scanning electron microscope photograph of a P-type conductive region having a first passivation layer in a solar cell provided by an example of the present application. [Figure 3] 1 is a scanning electron microscope photograph of an N-type conductive region having a second passivation layer in a solar cell provided by an example of the present application. [Figure 4] 1 is a structural schematic diagram of a P-type conductive region having a first passivation layer in a solar cell provided by an embodiment of the present application; FIG. [Figure 5] 1 is a structural schematic diagram of an N-type conductive region having a second passivation layer in a solar cell provided by an embodiment of the present application; [Figure 6] FIG. 2 is another structural schematic diagram of a solar cell provided in an embodiment of the present application. [Figure 7] 1 is a manufacturing flowchart of a solar cell provided by an embodiment of the present application. [Figure 8] 1 is a structural schematic diagram of a solar cell provided by an embodiment of the present application after an N-type conductive region and a P-type conductive region are formed. [Figure 9] 1 is a structural schematic diagram of a solar cell provided by an embodiment of the present application after a first passivation layer and a second passivation layer are formed; FIG. [Figure 10] 1 is a structural schematic diagram of a solar cell after a texture structure and a front passivation layer are formed, according to an embodiment of the present application; FIG. [Figure 11] 1 is a structural schematic diagram of a solar cell provided by an embodiment of the present application after a first doped conductive layer and a second doped conductive layer are formed; FIG. [Figure 12] 1 is a schematic structural diagram of a solar cell provided in an embodiment of the present application after a third passivation layer is formed. [Figure 13] 1 is a structural schematic diagram of a photovoltaic module provided by an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0010] The present application will now be further described with reference to the figures and examples.

[0011] In order to better understand the technical solution of the present application, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings.

[0012] It should be clear that the described embodiments are only some of the embodiments of the present application, not all of the embodiments, and all other embodiments that a person skilled in the art can obtain based on the embodiments of the present application without any creative work shall fall within the scope of protection of the present application.

[0013] The terms used in the examples of this application are for the purpose of describing particular examples only and are not intended to limit this application. As used in the examples and claims of this application, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

[0014] It should be understood that the term "and / or" used herein is only a relational relationship that describes related objects, and indicates that three types of relationships may exist. For example, A and / or B can indicate three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the text generally indicates that the related objects before and after it are in an "or" relationship.

[0015] In the related art, the backside process in the fabrication of IBC cells involves forming interdigitated p+ and n+ regions by phosphorus and boron diffusion. Specifically, boron diffusion is first performed on the backside of a silicon substrate to form an n+-doped layer, followed by localized laser light removal of a portion of the n+-doped layer. Phosphorus diffusion is then performed in the removed n+-doped layer to form a p+-doped layer. Etching and pickling are then performed to form a gap region between the n+ and p+-doped layers. The gap region is typically trench-shaped and is used to prevent recombination problems at the contact area between the n+ and p+-doped layers. Currently, a passivation contact structure on the backside of an IBC cell can reduce the carrier recombination rate on the non-light-receiving side of the IBC cell and improve the photoelectric conversion efficiency of the IBC cell. Common passivation structures include a tunnel passivation contact structure and a heteropassivation contact structure. However, the conventional passivation contact structure has a low light utilization rate on the non-light-receiving side of the IBC cell, and there is a relatively large parasitic absorption in the passivation contact region, which is disadvantageous for improving the photoelectric conversion efficiency of the solar cell.

[0016] In view of this, an embodiment of the present application provides a solar cell. Referring to FIGS. 1 to 3, the solar cell includes a semiconductor substrate 1, a first passivation layer 5, a second passivation layer 6, a first doped conductive layer 7, a second doped conductive layer 8, a first electrode 12, and a second electrode 13; The semiconductor substrate 1 includes a front surface and a back surface arranged opposite to each other, and the back surface of the semiconductor substrate 1 has alternating N-type conductive regions 2 and P-type conductive regions 3, a first passivation layer 5 is arranged on the side of the P-type conductive region 3 facing away from the semiconductor substrate 1, and the length of the first passivation layer 5 along a first direction is greater than the length of the P-type conductive region 3 along the first direction, and a second passivation layer 6 is arranged on the side of the N-type conductive region 2 facing away from the semiconductor substrate, and the length of the second passivation layer 6 along the first direction is smaller than the length of the N-type conductive region 2 along the first direction, and the first direction is a direction parallel to the plane in which the semiconductor substrate 1 is located. The first doped conductive layer 7 is provided on the side of the first passivation layer 5 that is away from the semiconductor substrate 1, the second doped conductive layer 8 is provided on the side of the second passivation layer 6 that is away from the semiconductor substrate 1, the first electrode 12 forms ohmic contact with the first doped conductive layer 7, and the second electrode 13 forms ohmic contact with the second doped conductive layer 8.

[0017] In the above technical solution, the back surface of the semiconductor substrate 1 has alternating N-type conductive regions 2 and P-type conductive regions 3, the N-type conductive regions 2 being doped with an N-type element, and the P-type conductive regions 3 being doped with a P-type element, a first passivation layer 5 being formed on a side of the P-type conductive region 3 facing away from the semiconductor substrate 1, and a first doped conductive layer 7 being formed on the side of the first passivation layer 5 facing away from the semiconductor substrate 1, so that a first passivation contact structure can be formed on the P-type conductive region 3, and the length of the first passivation layer 5 in the first direction is greater than the length of the P-type conductive region 3 in the first direction, so that the size of the first passivation contact structure can be increased, thereby increasing the reflective area of ​​the first passivation contact structure for front-incident light, allowing the front-incident light to be reflected multiple times into the semiconductor substrate 1 and absorbed by the semiconductor substrate 1 for utilization, and thereby increasing the number of reflections of the reflected light on the back surface of the solar cell, improving the light utilization rate on the back surface of the solar cell and thereby improving the photoelectric conversion efficiency of the solar cell. A second passivation layer 6 is provided on the side of the N-type conductivity region 2 facing away from the semiconductor substrate 1, and a second doped conductive layer 8 is provided on the side of the second passivation layer 6 facing away from the semiconductor substrate 1, thereby forming a second passivation contact structure in the N-type conductivity region 2. The length of the second passivation layer 6 along the first direction is smaller than the length of the N-type conductivity region 2 along the first direction, thereby reducing the size of the second passivation contact structure in the N-type conductivity region 2. This reduces parasitic absorption of light in the second passivation contact structure and improves the photoelectric conversion efficiency of the solar cell. Furthermore, the N-type conductivity region 2 and the P-type conductivity region 3 of the present application are designed with passivation contact structures of different sizes, which reduces the carrier recombination rate at the lateral boundary between the N-type conductivity region 2 and the P-type conductivity region 3 and reduces the electrode contact resistance between the first electrode 12 and the second electrode 13 on the back surface, thereby further improving the photoelectric conversion efficiency of the solar cell.The present application designs the size of the passivation contact structures in different regions on the back surface of the solar cell, which can improve the light utilization efficiency of the back surface of the solar cell, reduce the parasitic absorption of the solar cell, and reduce the carrier recombination rate in different regions on the back surface of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0018] In this application, the P-type conductivity region 3 refers to a region formed of a highly doped P-type semiconductor material, and the N-type conductivity region 2 refers to a region formed of a highly doped N-type semiconductor material. The P-type conductivity region 3 and the N-type conductivity region 2 are interdigitated on the back surface of the semiconductor substrate 1, and their main functions are to separate and collect carriers. The P-type conductivity region 3 is for collecting holes, and the N-type conductivity region 2 is for collecting electrons. They transfer the collected carriers to the back surface electrode of the semiconductor substrate 1, respectively, and form a path with an external load. Therefore, the P-type conductivity region 3 and the N-type conductivity region 2 must not be in direct contact with each other; otherwise, the collected carriers will come into direct contact with each other on the back surface of the semiconductor substrate 1, forming a short circuit and preventing effective carrier collection. Therefore, a "groove-shaped" separation region 4 is usually formed between the P-type conductivity region 3 and the N-type conductivity region 2.

[0019] In addition, the semiconductor substrate 1 generally has a front surface and a back surface, and the front surface of the semiconductor substrate 1 may refer to the light-receiving surface, i.e., the surface that is irradiated with sunlight, and the back surface of the semiconductor substrate 1 refers to the surface opposite to the front surface.

[0020] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer) or may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) may be, for example, one of a polycrystalline silicon substrate, a single-crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the examples of the present application are not limited to the specific type of the semiconductor substrate 1. When the semiconductor substrate 1 is an N-type substrate, the doping element may be a Group V element such as phosphorus (P), arsenic (As), or tellurium (Te). The N-type semiconductor substrate 1 and the P-type conductive region 3 form a PN junction, and the N-type semiconductor substrate 1 and the N-type conductive region 2 form an N-N+ Hi-Low junction. When the semiconductor substrate 1 is a P-type substrate, the doping element may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type semiconductor substrate 1 and the N-type conductive region 2 form a PN junction, and the P-type semiconductor substrate 1 and the P-type conductive region 3 form a P-P+ Hi-Low junction.

[0021] In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, and specifically may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, but is not limited thereto.

[0022] In some embodiments, FIG. 4 is a structural schematic diagram of a P-type conductive region having a first passivation layer 5 in a solar cell. Referring to FIG. 4, the P-type conductive region 3 includes a first surface 31 and a second surface 32 that are arranged opposite to each other, and at least a portion of the first passivation layer 5 includes a first sub-passivation surface a and a first sub-passivation surface b that are arranged opposite to each other, and the first surface 31, the second surface 32, the first sub-passivation surface a, and the first sub-passivation surface b are all perpendicular to the first direction, and the first sub-passivation surface The surface a protrudes relative to the first surface 31, and / or the first sub-passivation surface b protrudes relative to the second surface 32, thereby increasing the size of the first passivation contact structure in the P-type conductive region 3 and increasing the reflective area of ​​the first passivation contact structure in the P-type conductive region 3 for front-incident light, allowing the front-incident light to be reflected into the semiconductor substrate 1 and absorbed by the semiconductor substrate 1 for utilization, thereby increasing the number of reflections of the reflected light on the back surface of the solar cell, improving the light utilization rate on the back surface side of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0023] In some embodiments, referring to FIG. 4 , the distance H1 between the first sub-passivation surface a and the first surface 31 is 1 μm to 300 μm, and may be, for example, 1 μm, 5 μm, 10 μm, 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, or 300 μm. Naturally, other values ​​within the above range are also possible and are not limited thereto. If the distance between the first sub-passivation surface a and the first surface 31 is less than 1 μm, the reflection area of ​​the first passivation contact structure in the P-type conductive region 3 for front-incident light is relatively small, which is unfavorable for improving the light utilization efficiency of the back surface of the solar cell. If the distance between the first sub-passivation surface a and the first surface 31 is greater than 300 μm, the carrier recombination efficiency between the P-type conductive region 3 and the N-type conductive region 2 is increased, which is unfavorable for improving the photoelectric conversion efficiency of the solar cell. Preferably, the distance between the first sub-passivation surface a and the first surface 31 is 50 μm to 200 μm.

[0024] 4, in some embodiments, the distance H2 between the first sub-passivation surface b and the second surface 32 is 1 μm to 300 μm, and may be, for example, 1 μm, 5 μm, 10 μm, 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, or 300 μm, and may be any other value within the above range, without limitation. If the distance H2 between the first sub-passivation surface b and the second surface 32 is less than 1 μm, the first passivation contact structure formed by the first passivation layer 5 and the first doped conductive layer 7 in the P-type conductive region 3 has a relatively small reflection area for front-incident light, which is disadvantageous for improving the light utilization efficiency of the back surface of the solar cell. If the distance between the first sub-passivation surface b and the second surface 32 is greater than 300 μm, the recombination efficiency of carriers in the P-type conductivity region 3 and the N-type conductivity region 2 will increase, which is detrimental to improving the photoelectric conversion efficiency of the solar cell. Preferably, the distance between the first sub-passivation surface b and the second surface 32 is 50 μm to 200 μm.

[0025] In some embodiments, FIG. 5 is a structural schematic diagram of an N-type conductive region having a second passivation layer in a solar cell. Referring to FIG. 5, the N-type conductive region 2 includes a third surface 21 and a fourth surface 22 arranged opposite each other, and the second passivation layer 6 includes a second sub-passivation surface a and a second sub-passivation surface b arranged opposite each other, wherein the third surface 21, the fourth surface 22, the second sub-passivation surface a, and the second sub-passivation surface b are all perpendicular to the first direction, and the second sub-passivation surface a is recessed relative to the third surface 21, and / or the second sub-passivation surface b is recessed relative to the fourth surface 22, which can reduce the size of the second passivation contact structure, which is advantageous for reducing parasitic absorption of light in the solar cell, reducing light loss, and improving the photoelectric conversion efficiency of the solar cell.

[0026] 5, in some embodiments, the distance H3 between the second sub-passivation surface a and the third surface 21 is 1 μm to 100 μm, and may be, for example, 1 μm, 5 μm, 10 μm, 20 μm, 50 μm, 60 μm, 70 μm, 81 μm, 90 μm, or 100 μm, or may be any other value within the above range, and is not limited thereto. If the distance between the second sub-passivation surface a and the third surface 21 is less than 1 μm, the area of ​​the second doped conductive layer 8 in the N-type conductive region becomes large, which increases parasitic absorption of light in the N-type conductive region and is detrimental to improving the photoelectric conversion efficiency of the solar cell. If the distance between the second sub-passivation surface a and the third surface 21 is greater than 100 μm, the size of the second passivation contact structure formed by the second passivation layer 6 and the second doped conductive layer 8 in the N-type conductive region 2 will be too small, increasing the ohmic contact resistance between the second electrode 13 and the second doped conductive layer 8. This limits the transfer of carriers in the N-type conductive region 2 to the second electrode 13, which is detrimental to improving the photoelectric conversion efficiency of the solar cell. Furthermore, by shading a larger portion of the light-irradiated region, the effective light absorption area will be reduced, which is detrimental to improving the photoelectric conversion efficiency of the solar cell. At the same time, it is also detrimental to reducing carrier recombination in the N-type conductive region 2, which affects the passivation effect of the solar cell. Preferably, the distance between the second sub-passivation surface a and the third surface 21 is 50 μm to 100 μm.

[0027] 5, in some embodiments, the distance H4 between the second sub-passivation surface b and the fourth surface 22 is 1 μm to 100 μm, and may be, for example, 1 μm, 5 μm, 10 μm, 20 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, or 100 μm, or may be any other value within the above range, and is not limited thereto. If the distance between the second sub-passivation surface a and the fourth surface 22 is less than 1 μm, the area of ​​the second doped conductive layer 8 in the N-type conductive region becomes large, which increases parasitic absorption of light in the N-type conductive region and is detrimental to improving the photoelectric conversion efficiency of the solar cell. If the distance between the second sub-passivation surface b and the fourth surface 22 is greater than 100 μm, the size of the second passivation contact structure formed by the second passivation layer 6 and the second doped conductive layer 8 in the N-type conductive region 2 will be too small, increasing the ohmic contact resistance between the second electrode 13 and the second doped conductive layer 8. This limits the transfer of carriers in the N-type conductive region 2 to the second electrode 13, which is detrimental to improving the photoelectric conversion efficiency of the solar cell. Furthermore, by shading a larger portion of the light-irradiated region, the effective light absorption area will be reduced, which is detrimental to improving the photoelectric conversion efficiency of the solar cell. At the same time, it is also detrimental to reducing carrier recombination in the N-type conductive region 2, which affects the passivation effect of the solar cell. Preferably, the distance between the second sub-passivation surface b and the fourth surface 22 is 50 μm to 100 μm.

[0028] In some embodiments, the first passivation layer 5 and the second passivation layer 6 are tunneling layers, and the materials of the first passivation layer 5 and the second passivation layer 6 include, but are not limited to, dielectric materials with tunneling properties, such as silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polycrystalline silicon.

[0029] In some embodiments, the thickness of the first passivation layer 5 is 1 nm to 5 nm, and specifically may be 1 nm, 2 nm, 2.6 nm, 3 nm, 3.5 nm, 4 nm, or 5 nm, etc., and of course may be other values ​​within the above range, and is not limited here.

[0030] In some embodiments, the thickness of the second passivation layer 6 is 1 nm to 5 nm, and specifically may be 1 nm, 2 nm, 2.6 nm, 3 nm, 3.5 nm, 4 nm, or 5 nm, etc., and of course may be other values ​​within the above range, and is not limited here.

[0031] In some embodiments, the surface of the P-type conductive region 3 facing away from the semiconductor substrate 1 is a smooth surface, which can improve the light reflectivity of the P-type conductive region 3, improve the passivation effect of the solar cell, and reduce the carrier recombination rate in the P-type conductive region 3, thereby improving the photoelectric conversion efficiency of the solar cell.

[0032] In some embodiments, the surface of the N-type conductive region 2 facing away from the semiconductor substrate 1 is rough, which can increase light scattering and light capture in the N-type conductive region 2, reduce light loss, and improve the light absorption efficiency of the solar cell.

[0033] In some embodiments, still referring to FIG. 1 , the solar cell further includes an isolation region 4 disposed between the N-type conductivity region 2 and the P-type conductivity region 3, and has a first side surface 14 between the isolation region 4 and the P-type conductivity region 3, the first side surface 14 being a smooth surface that can improve the light reflectivity of the back surface of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0034] In some embodiments, the solar cell further includes an isolation region 4 disposed between the N-type conductivity region 2 and the P-type conductivity region 3, and has a second side surface 15 between the isolation region 4 and the N-type conductivity region 2, the second side surface 15 being a rough surface, which can increase light scattering and light capture in the N-type conductivity region 2, reduce light loss, and improve the light absorption efficiency of the solar cell.

[0035] In some embodiments, referring to FIG. 1, the isolation region 4 has a textured structure, which can effectively reduce the reflectivity of the surface of the semiconductor substrate 1 and increase light absorption, thereby improving the photoelectric conversion efficiency of the cell.

[0036] In some embodiments, the width of the separation region 4 is 1 μm to 300 μm, and specifically may be 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, or 300 μm, etc., and may of course be other values ​​within the above range and is not limited thereto. As can be understood, having the width of the separation region 4 within the above range is advantageous for reducing the recombination rate of carriers in the N-type conductivity region 2 and the P-type conductivity region 3 and improving the photoelectric conversion efficiency of the solar cell.

[0037] In some embodiments, the projection of the first passivation layer 5 on the surface on which the semiconductor substrate 1 is located at least partially overlaps with the projection of said first side surface 14 on the surface on which the semiconductor substrate 1 is located.

[0038] In some embodiments, S1 represents the overlapping area between the projection of the first passivation layer 5 on the surface of the semiconductor substrate 1 and the projection of the first side surface 14 on the surface of the semiconductor substrate 1, and S2 represents the area of ​​the projection of the first side surface 14 on the surface of the semiconductor substrate 1. S1 / S2 is (0.2 to 0.99):1, and may be, for example, 0.2:1, 0.3:1, 0.5:1, 0.6:1, 0.8:1, 0.9:1, or 0.99:1. Naturally, other values ​​within the above range are also possible and are not limited thereto. Having S1 / S2 within the above range ensures that the length of the first passivation layer 5 along the first direction is longer than the length of the P-type conductive region 3 along the first direction. This increases the reflective area of ​​the first passivation contact structure formed on the P-type conductive region 3 for front-side incident light, improving the light utilization efficiency of the backside of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0039] In some embodiments, the projected area of ​​the second passivation layer 6 on the surface where the semiconductor substrate 1 is located is S3, and the projected area of ​​the N-type conductive region 2 on the surface where the semiconductor substrate 1 is located is S4. S3 / S4=(1.01-1.90):1, specifically, may be 1.01:1, 1.1:1, 1.3:1, 1.5:1, 1.6:1, 1.8:1, or 1.9:1, etc., and may be other values ​​within the above range, without limitation. Having S3 / S4 within the above limited range can ensure that the length of the second passivation layer 6 in the first direction is shorter than the length of the N-type conductive region 2 in the first direction, thereby reducing parasitic absorption of light in the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0040] In some embodiments, the thickness of the first doped conductive layer 7 is equal to or greater than the thickness of the second doped conductive layer 8, which can improve the passivation effect on the back surface of the solar cell, reduce the carrier recombination rate in the solar cell, and further reduce the parasitic absorption of light in the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0041] In some embodiments, the thickness of the first doped conductive layer 7 is 50 nm to 500 nm, and specifically may be 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, 350 nm, 400 nm, or 500 nm, etc., and of course may be other values ​​within the above range and are not limited here.

[0042] In some embodiments, the thickness of the second doped conductive layer 8 is 50 nm to 300 nm, and specifically may be 50 nm, 100 nm, 150 nm, 180 nm, 200 nm, 240 nm, 280 nm, or 300 nm, etc., and of course may be other values ​​within the above range and are not limited here.

[0043] In some embodiments, still referring to FIG. 1 , the length of the first doped conductive layer 7 along the first direction is greater than the length of the P-type conductive region 3 along the first direction, which can increase the size of the first passivation contact structure in the P-type conductive region 3, increase the reflective area for front-incident light, and improve the light utilization efficiency of the back surface of the solar cell.

[0044] In some embodiments, the material of the first doped conductive layer 7 includes semiconductor materials such as polycrystalline silicon, microcrystalline silicon, and silicon carbide, and the doping element in the first doped conductive layer 7 includes at least one of boron (B), aluminum (Al), and gallium (Ga).

[0045] In some embodiments, the length of the second doped conductive layer 8 along the first direction is smaller than the length of the N-type conductive region 2 along the first direction, thereby reducing the area of ​​the second doped conductive layer 8 in the N-type conductive region 2 and reducing the parasitic absorption of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0046] In some embodiments, the material of the second doped conductive layer 8 includes semiconductor materials such as polycrystalline silicon, microcrystalline silicon, and silicon carbide, and the doping element in the second doped conductive layer 8 includes at least one of phosphorus (P), arsenic (As), and tellurium (Te).

[0047] 1 , in some embodiments, the solar cell further includes a textured structure 10 provided on the front surface of the semiconductor substrate 1, and a front passivation layer 11 provided on the surface of the textured structure 10. As can be seen, providing the textured structure 10 on the front surface of the semiconductor substrate 1 can reduce the reflection of sunlight on the front surface of the semiconductor substrate 1, improve the absorption rate of sunlight on the front surface of the semiconductor substrate 1, and improve the photoelectric conversion efficiency of the solar cell.

[0048] In some embodiments, the front passivation layer 11 may include, but is not limited to, a single oxide layer or a multi-layer structure, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. Of course, other types of passivation layers may also be used, and the present invention is not limited to the specific material of the front passivation layer 11. The front passivation layer 11 can provide good passivation and reflection reduction effects for the semiconductor substrate 1, thereby improving the conversion efficiency of the cell.

[0049] In some embodiments, FIG. 6 is another structural schematic diagram of a solar cell provided in the examples of the present application. Referring to FIG. 6, the solar cell further includes a third passivation layer 9, which covers the first doped conductive layer 7 and the second doped conductive layer 8.

[0050] In some embodiments, the third passivation layer 9 includes one or a combination of a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide / silicon nitride stack. Obviously, other types of passivation layers may be used for the third passivation layer 9, and the present application does not limit the specific material of the third passivation layer 9. For example, in another embodiment, the third passivation layer 9 may be a stack of silicon dioxide and silicon nitride. The third passivation layer 9 can provide a good passivation effect for the semiconductor substrate 1, contributing to improving the cell conversion efficiency.

[0051] In some embodiments, and still referring to FIG. 6 , a first electrode 12 is provided on the surface of the third passivation layer 9, forming an ohmic contact with the first doped conductive layer 7, and a second electrode 13 is provided on the surface of the third passivation layer 9, forming an ohmic contact with the second doped conductive layer 8.

[0052] The present application further provides a method for manufacturing the solar cell described above. FIG. 7 shows a flowchart of the manufacturing of a solar cell provided by an embodiment of the present application. As shown in FIG. 7, the manufacturing method of the solar cell includes the following steps: providing a semiconductor substrate 1 including opposed front and back surfaces; forming an N-type conductive region 2 and a P-type conductive region 3 on the back surface of a semiconductor substrate 1; forming a first passivation layer 5 on a surface of the P-type conductive region 3 facing away from the semiconductor substrate 1, the length of the first passivation layer 5 in a first direction being greater than the length of the P-type conductive region 3 in the first direction, and forming a second passivation layer 6 on a surface of the N-type conductive region 2 facing away from the semiconductor substrate 1, the length of the second passivation layer 6 in the first direction being less than the length of the N-type conductive region 2 in the first direction, the first direction being a direction parallel to a plane in which the semiconductor substrate is located; forming a first doped conductive layer (7) on a surface of the first passivation layer (5) facing away from the semiconductor substrate (1); forming a second doped conductive layer 8 on a surface of the second passivation layer 6 facing away from the semiconductor substrate 1; forming a first electrode 12 on the surface of the first doped conductive layer 7 and a second electrode 13 on the surface of the second doped conductive layer 8.

[0053] In step S100, a semiconductor substrate 1 is provided, which includes a front surface and a back surface disposed opposite to each other. In some embodiments, the front surface of semiconductor substrate 1 corresponds to the front surface of the cell, which is the surface facing the sun (i.e., the light-receiving surface), and the back surface of semiconductor substrate 1 corresponds to the back surface of the cell, which is the surface facing away from the sun (i.e., the non-light-receiving surface).

[0054] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) may be, for example, one of a polycrystalline silicon substrate, a single-crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the examples of the present application are not limited to the specific type of the semiconductor substrate 1.

[0055] In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, and specifically may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, but is not limited thereto.

[0056] In step S200, a P-type conductive region 3 and an N-type conductive region 2 are formed on the back surface of the semiconductor substrate 1, resulting in a structure as shown in FIG.

[0057] In this step, in order to manufacture N-type conductive regions 2 and P-type conductive regions 3 alternately arranged on the back surface of the semiconductor substrate 1, a diffusion process is performed on each of the back surfaces of the semiconductor substrate 1, but the present application is not limited to the specific process of the diffusion process.

[0058] In some embodiments, after step S200, the step of polishing the surface of the P-type conductive region 3 facing away from the semiconductor substrate 1 is further included in order to obtain a P-type conductive region 3 having a smooth surface.

[0059] In some embodiments, after step S200, the method further includes a step of texturing the surface of the N-type conductive region 2 facing away from the semiconductor substrate 1 to obtain an N-type conductive region 2 having a rough surface.

[0060] In step S300, a first passivation layer 5 is formed on the surface of the P-type conductive region 3 facing away from the semiconductor substrate 1, and the length of the first passivation layer 5 along the first direction is greater than the length of the P-type conductive region 3 along the first direction. A second passivation layer 6 is formed on the surface of the N-type conductive region 2 facing away from the semiconductor substrate 1, and the length of the second passivation layer 6 along the first direction is less than the length of the N-type conductive region 2 along the first direction. The resulting structure is as shown in FIG. 9. The first direction is a direction parallel to the plane in which the semiconductor substrate is located. In some embodiments, before step S300, the solar cell manufacturing method of the present application further includes the following steps: forming a textured structure 10 on the front surface of the semiconductor substrate 1 by a texturing process, and forming a front passivation layer 11 on the surface of the textured structure 10, and the resulting structure is as shown in FIG. 10.

[0061] As shown in FIG. 10, in the present application, a texturing process is performed on the front surface of the semiconductor substrate 1 to form a pyramidal texture structure 10, thereby reducing the reflection of sunlight on the front surface of the semiconductor substrate 1 and improving the absorption rate of sunlight on the front surface of the semiconductor substrate 1, thereby improving the photoelectric conversion efficiency of the solar cell.

[0062] In some embodiments, the front passivation layer 11 may include, but is not limited to, a single oxide layer or a multi-layer structure, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. Of course, other types of passivation layers may also be used, and the present application does not limit the specific material of the front passivation layer 11. The front passivation layer 11 can provide good passivation and reflection reduction effects for the semiconductor substrate 1, thereby improving the conversion efficiency of the cell.

[0063] In some embodiments, the thickness of the front passivation layer 11 ranges from 40 nm to 100 nm, and may be, for example, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, and of course may be other values ​​within the above range, and is not limited thereto.

[0064] In some embodiments, the manufacturing method of the present application further includes the following step: forming a reflection reduction layer (structure not shown) on the surface of the front passivation layer 11 to reduce light reflection on the front surface of the cell.

[0065] In some embodiments, the reflection reduction layer may be, for example, a silicon oxynitride layer or an aluminum oxide / silicon nitride stacked structure, but this application is not limited thereto. Taking a silicon oxynitride layer as an example, the presence of silicon oxynitride can effectively reduce light reflection and improve light transmittance. By controlling the film thickness, the reflectance can be adjusted to achieve the desired reflection reduction effect. Furthermore, NH4, the raw material for silicon oxynitride, decomposes into H atoms during the reaction process. The H atoms penetrate into the semiconductor substrate 1 at high temperatures and bond with dangling bonds on the surface to provide passivation. In some embodiments, the first passivation layer 5 and the second passivation layer 6 are tunnel layers, and the materials for the first passivation layer 5 and the second passivation layer 6 include, but are not limited to, dielectric materials with tunneling properties, such as silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, and intrinsic polycrystalline silicon.

[0066] In some embodiments, the surfaces of the P-type conductive region 3 and the N-type conductive region 2 facing away from the semiconductor substrate 1 can be oxidized using any one of ozone oxidation, high-temperature thermal oxidation, and nitric acid oxidation to obtain the first passivation layer 5 and the second passivation layer 6.

[0067] In some embodiments, the thickness of the first passivation layer 5 is 1 nm to 5 nm, and specifically may be 1 nm, 2 nm, 2.6 nm, 3 nm, 3.5 nm, 4 nm, or 5 nm, etc., and of course may be other values ​​within the above range, and is not limited here.

[0068] In some embodiments, the thickness of the second passivation layer 6 is 1 nm to 5 nm, and specifically may be 1 nm, 2 nm, 2.6 nm, 3 nm, 3.5 nm, 4 nm, or 5 nm, etc., and of course may be other values ​​within the above range, and is not limited here.

[0069] In step S400, a first doped conductive layer 7 is formed on the surface of the first passivation layer 5 on the side facing away from the semiconductor substrate 1.

[0070] In some embodiments, the material of the first doped conductive layer 7 includes semiconductor materials such as polycrystalline silicon, microcrystalline silicon, and silicon carbide, and the doping element in the first doped conductive layer 7 includes at least one of boron (B), aluminum (Al), and gallium (Ga).

[0071] In some embodiments, the thickness of the first doped conductive layer 7 is in the range of 50 nm to 300 nm, and may be, for example, 50 nm, 60 nm, 100 nm, 150 nm, 180 nm, 200 nm, 250 nm, or 300 nm, and of course may be other values ​​within the above range, and is not limited here.

[0072] In step S500, a second doped conductive layer 8 is formed on the surface of the second passivation layer 6 facing away from the semiconductor substrate 1, and the resulting structure is as shown in FIG.

[0073] In some embodiments, the material of the second doped conductive layer 8 includes semiconductor materials such as polycrystalline silicon, microcrystalline silicon, and silicon carbide, and the doping element in the second doped conductive layer 8 includes at least one of phosphorus (P), arsenic (As), and tellurium (Te).

[0074] In some embodiments, the thickness of the second doped conductive layer 8 is in the range of 50 nm to 500 nm, and may be, for example, 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, 350 nm, 400 nm, or 500 nm, and of course may be other values ​​within the above range, and is not limited here.

[0075] In some embodiments, the solar energy manufacturing method further includes the following steps: forming a third passivation layer 9 on the surface of the first doped conductive layer 7 and the second doped conductive layer 8, and the third passivation layer 9 covers the first doped conductive layer 7 and the second doped conductive layer 8, and the resulting structure is as shown in FIG. 12.

[0076] In some embodiments, the third passivation layer 9 includes one or a combination of a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide / silicon nitride stack. Naturally, other types of passivation layers may be used for the third passivation layer 9. The present application does not limit the specific material of the third passivation layer 9. For example, in other embodiments, the third passivation layer 9 may be a stack of silicon dioxide and silicon nitride. The third passivation layer 9 can provide a good passivation effect for the semiconductor substrate 1, contributing to improving the cell conversion efficiency.

[0077] In some embodiments, the third passivation layer 9 may be deposited using plasma enhanced chemical vapor deposition, although of course other methods such as organic chemical vapor deposition may also be used.

[0078] In some embodiments, the thickness of the third passivation layer 9 ranges from 10 nm to 100 nm, and may be, for example, 10 nm, 20 nm, 30 nm, 42 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, and of course may be other values ​​within the above range, and is not limited here.

[0079] In step S600, a first electrode 12 is formed on the surface of the first doped conductive layer 7, and a second electrode 13 is formed on the surface of the second doped conductive layer 8 to obtain a solar cell, the structural schematic diagram of which is as shown in FIG.

[0080] Specifically, in this step, a metallization process is performed on the surfaces of the first doped conductive layer 7 and the second doped conductive layer 8 to obtain a first electrode 12 on the surface of the first doped conductive layer 7 and a second electrode 13 on the surface of the second doped conductive layer 8, where the first electrode 12 and the second electrode 13 correspond to the P-type conductive region 3 and the N-type conductive region 2, respectively. The first electrode 12 and the second electrode 13 are manufactured by screen printing and then sintered, so that the first electrode 12 and the N-type conductive region 2 form ohmic contacts, and the second electrode 13 and the P-type conductive region 3 form ohmic contacts, or the first electrode 12 and the P-type conductive region 3 form ohmic contacts, and the second electrode 13 and the N-type conductive region 2 form ohmic contacts. Of course, the first electrode 12 and the second electrode 13 may also be formed on the back surface of the battery using at least one of a metal evaporation method and a plating method.

[0081] In the embodiments of the present application, the specific materials of the first electrode 12 and the second electrode 13 are not limited. For example, when the first electrode 12 forms an ohmic contact with the P-type conductive region 3 and the second electrode 13 forms an ohmic contact with the N-type conductive region 2, the first electrode 12 is a silver electrode or a silver / aluminum electrode, and the second electrode 13 is a silver electrode. For example, a silver paste may be printed on the underside of the third passivation layer 9 corresponding to the N-type conductive region 2, and a silver paste or a silver / aluminum paste doped with a small amount of aluminum may be printed on the underside of the third passivation layer 9 corresponding to the P-type conductive region 3, followed by sintering and firing each paste through the third passivation layer 9. The formed silver electrode or silver / aluminum electrode forms an ohmic contact with the P-type conductive region 3, and the formed silver electrode forms an ohmic contact with the N-type conductive region 24.

[0082] In this specification, unless otherwise specified, the processing steps may be performed in the order described or in a different order from the order described. In the examples of the present application, the order of steps for manufacturing a solar cell is not limited, and may be adjusted according to the actual manufacturing process.

[0083] An embodiment of the present application provides a photovoltaic module 1000, which includes a cell string in which the solar cells are electrically connected to form a cell string.

[0084] Specifically, referring to FIG. 13, a photovoltaic module 1000 includes a first cover plate 200 , a first sealing glue layer 300 , a solar cell string, a second sealing glue layer 400 and a second cover plate 500 .

[0085] In some embodiments, a solar cell string includes a plurality of the solar cells 100 connected by conductive bands, and the solar cells 100 may be connected to each other by partial stacking or joining.

[0086] In some embodiments, the first cover plate 200, the second cover plate 500 may be a transparent or opaque cover plate, for example, a glass cover plate, a plastic cover plate.

[0087] Both sides of the first sealing glue layer 300 contact and bond with the first cover plate 200 and the battery string, respectively, and both sides of the second sealing glue layer 400 contact and bond with the second cover plate 500 and the battery string, respectively. In addition, each of the first sealing glue layer 300 and the second sealing glue layer 400 may be an ethylene-vinyl acetate copolymer (EVA) glue film, a polyethylene-octene elastomer (POE) glue film, or a polyethylene terephthalate (PET) glue film.

[0088] The photovoltaic module 1000 may employ a complete side sealing method, i.e., a sealing tape is used to completely cover and seal the sides of the photovoltaic module 1000, to prevent the photovoltaic module 1000 from shifting during the lamination process.

[0089] The photovoltaic module 1000 further includes an edge sealing member, which is fixed to and seals a portion of the edge of the photovoltaic module 1000. The edge sealing member can be fixed to and seal an edge near a corner of the photovoltaic module 1000. The edge sealing member can be high-temperature resistant tape. The high-temperature resistant tape has relatively good high-temperature resistance and will not decompose or fall off during the lamination process, ensuring reliable sealing of the photovoltaic module 1000. Both ends of the high-temperature resistant tape are fixed to the second cover plate 500 and the first cover plate 200, respectively. Both ends of the high-temperature resistant tape can be bonded to the second cover plate 500 and the first cover plate 200, respectively, and the center of the high-temperature resistant tape can achieve positional restriction relative to the side edges of the photovoltaic module 1000, preventing misalignment during lamination of the photovoltaic module 1000.

[0090] The above are only preferred embodiments of the present application, and do not limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included within the protection scope of the present application. [Explanation of symbols]

[0091] 1 - semiconductor substrate, 2 - N-type conductive region, 21 - third surface, 22 - fourth surface, 3 - P-type conductive region, 31 - first surface, 32 - second surface, 4 - isolation region, 5 - first passivation layer, 6 - second passivation layer, 7 - first doped conductive layer, 8 - second doped conductive layer, 9 - third passivation layer, 10 - textured structure, 11 front passivation layer, 12 - first electrode, 13 - second electrode, 14 - first side surface, 15 - second side surface, 1000 - photovoltaic module, 100 - solar cell, 200 - first cover plate, 300 - first sealing glue layer, 400 - second sealing glue layer, 500 - second cover plate.

Claims

1. A solar cell, The solar cell includes a semiconductor substrate, a first passivation layer, a second passivation layer, a first doped conductive layer, a second doped conductive layer, a first electrode, and a second electrode; the semiconductor substrate includes opposed front and back surfaces, the back surface of the semiconductor substrate having alternating N-type and P-type conductivity regions; the first passivation layer is provided on a side of the P-type conductive region that is away from the semiconductor substrate, and a length of the first passivation layer along a first direction is greater than a length of the P-type conductive region along the first direction; the second passivation layer is provided on a side of the N-type conductive region that is away from the semiconductor substrate, the length of the second passivation layer along the first direction is smaller than the length of the N-type conductive region along the first direction, and the first direction is a direction parallel to a plane in which the semiconductor substrate is located; the first doped conductive layer is disposed on a side of the first passivation layer away from the semiconductor substrate; the second doped conductive layer is disposed on a side of the second passivation layer away from the semiconductor substrate; the first electrode forms an ohmic contact with the first doped conductive layer; The second electrode forms an ohmic contact with the second doped conductive layer.

2. the P-type conductive region includes a first surface and a second surface provided opposite to each other, and at least a portion of the first passivation layer includes a first sub-passivation surface (a) and a first sub-passivation surface (b) provided opposite to each other, and the first surface, the second surface, the first sub-passivation surface (a), and the first sub-passivation surface (b) are all perpendicular to the first direction; 2. The solar cell of claim 1, wherein the first sub-passivation surface (a) protrudes relative to the first surface and / or the first sub-passivation surface (b) protrudes relative to the second surface.

3. The solar cell of claim 2, characterized in that the distance between the first sub-passivation surface (a) and the first surface is 1 μm to 300 μm, and / or the distance between the first sub-passivation surface (b) and the second surface is 1 μm to 300 μm.

4. the N-type conductive region includes a third surface and a fourth surface provided opposite to each other, the second passivation layer includes a second sub-passivation surface (a) and a second sub-passivation surface (b) provided opposite to each other, and the third surface, the fourth surface, the second sub-passivation surface (a) and the second sub-passivation surface (b) are all perpendicular to the first direction; 2. The solar cell of claim 1, wherein the second sub-passivation surface (a) is recessed relative to the third surface and / or the second sub-passivation surface (b) is recessed relative to the fourth surface.

5. The solar cell of claim 4, characterized in that the distance between the second sub-passivation surface (a) and the third surface is 1 μm to 100 μm, and / or the distance between the second sub-passivation surface (b) and the fourth surface is 1 μm to 100 μm.

6. 2. The solar cell according to claim 1, wherein the surface of the P-type conductive region facing away from the semiconductor substrate is a smooth surface, and / or the surface of the N-type conductive region facing away from the semiconductor substrate is a rough surface.

7. the solar cell further includes an isolation region between the N-type conductivity region and the P-type conductivity region, and has a first side surface between the isolation region and the P-type conductivity region, the first side surface being a smooth surface; and / or 2. The solar cell of claim 1, further comprising a second side surface between the isolation region and the N-type conductivity region, the second side surface being a rough surface.

8. 8. The solar cell according to claim 7, wherein the projection of the first passivation layer on the surface on which the semiconductor substrate is located at least partially overlaps the projection of the first side surface on the surface on which the semiconductor substrate is located.

9. The solar cell according to claim 7, characterized in that, when an area where a projection of the first passivation layer on the surface on which the semiconductor substrate is located overlaps with a projection of the first side surface on the surface on which the semiconductor substrate is located is defined as S1, and an area of ​​the projection of the first side surface on the surface on which the semiconductor substrate is located is defined as S2, the solar cell satisfies S1 / S2=(0.2 to 0.99):

1.

10. The solar cell according to claim 1, characterized in that, when the area of ​​the projection of the second passivation layer on the surface on which the semiconductor substrate is located is S3 and the area of ​​the projection of the N-type conductive region on the surface on which the semiconductor substrate is located is S4, the relationship S3 / S4 = (1.01 to 1.90): 1 is satisfied.

11. the thickness of the first doped conductive layer is between 50 nm and 500 nm; and / or 2. The solar cell according to claim 1, wherein the second doped conductive layer has a thickness of 50 nm to 300 nm.

12. a length of the first doped conductive layer along the first direction is greater than a length of the P-type conductive region along the first direction; 2. The solar cell according to claim 1, wherein the length of the second doped conductive layer along the first direction is smaller than the length of the N-type conductive region along the first direction.

13. A photovoltaic module, The photovoltaic module includes a cover plate, an encapsulant layer, and a solar cell string, and the solar cell string includes a plurality of solar cells according to any one of claims 1 to 12.

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