Method for manufacturing depletion-type high electron mobility transistor

Abstract

To provide a method for manufacturing a depletion-type high electron mobility transistor.SOLUTION: A method for manufacturing a depletion-type high electron mobility transistor includes the steps of (a) providing a semiconductor substrate including a channel layer and a barrier layer overlying the channel layer, (b) isolating a mesa, (c) forming a dielectric layer over the semiconductor substrate, (d) forming a first field plate over the dielectric layer, (e) forming a second field plate over the first field plate, (f) patterning the first field plate and the second field plate to expose locations corresponding to the source opening, the gate opening, and the drain opening in the dielectric layer, (g) patterning the dielectric layer to expose locations corresponding to the source opening and the drain opening in the semiconductor substrate, and (h) patterning and forming an ohmic contact metal layer to cover the locations corresponding to the source opening and the drain opening in the semiconductor substrate, and alloying the ohmic contact metal layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for fabricating a transistor, and in particular, but not exclusively, to a method for fabricating a depletion-mode high electron mobility transistor. [Background technology]

[0002] In the semiconductor industry, high-voltage switching transistors, such as high electron mobility transistors (HEMTs), junction field effect transistors (JFETs), or power metal oxide semiconductor field effect transistors (MOSFETs), are often used as semiconductor switching elements for high-voltage, high-power devices. High electron mobility transistors have advantages such as high power density, high breakdown voltage, high output voltage, and high switching frequency, which minimize damage to devices even in high-voltage operating environments, and are gradually becoming more widely used.

[0003] Specifically, the excellent characteristics of high electron mobility transistors are largely dependent on the material properties of GaN, such as the bandgap, high critical electric field, and high carrier mobility. In addition, due to the inherent polarization effect of GaN, the AlGaN / GaN heterostructure induces the formation of two-dimensional electron gases (2DEG) at the interface without doping, allowing AlGaN / GaN HEMTs to operate with high current output and have very low on-resistance.

[0004] In practice, high electron mobility transistors can be configured as enhancement mode semiconductor devices (E-mode) with a positive threshold voltage, or as depletion mode high electron mobility transistors (D-mode) with a negative threshold voltage. Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional fabrication methods for depletion-mode high electron mobility transistors, the ohmic contact metal layer is typically fabricated first because the process temperature for the ohmic contact metal layer is typically high and can easily affect nitride deposition. However, the subsequent low-pressure chemical vapor deposition (LPCVD) process used to form the nitride dielectric layer must be free of metal contamination. Therefore, conventional fabrication methods do not allow the ohmic contact metal layer to be fabricated before the nitride deposition process. This limits the placement of the dielectric layer and increases the complexity and difficulty of patterning / etching. For example, precise control of patterning / etching requires the use of specialized etching processes. Furthermore, care must be taken to avoid over-etching underlying layers or contaminating the electrode metal during the process to avoid subsequent device leakage and failure. Special etching processes include atomic layer etching (ALE), which sequentially removes thin layers of material through self-limiting reactions. However, this process is expensive, technically challenging, and time-consuming.

[0006] In view of the above problems, the present inventors believe that the current process temperature for the ohmic contact metal layer can be reduced to 600°C or below, thereby reducing the impact on the deposition of the nitride dielectric layer. Therefore, the present inventors propose a method for fabricating a depletion-mode high electron mobility transistor in which a nitride dielectric layer is first formed and then an ohmic contact metal layer is formed. Specifically, the nitride dielectric layer is formed using an LPCVD process or a plasma-enhanced chemical vapor deposition (PECVD) process in a timely manner. This eliminates the need to consider the risk of metal contamination during the steps of forming multiple nitride dielectric layers, providing greater flexibility in the fabrication method. At the same time, by utilizing the characteristics of different epitaxial growth or deposition processes, the present invention allows for more efficient and simple patterning of transistors in subsequent fabrication processes. [Means for solving the problem]

[0007] Therefore, one aspect of the present invention provides a method for manufacturing a depletion-mode high electron mobility transistor, the method comprising the steps of: (a) providing a semiconductor substrate including a channel layer and a barrier layer overlying the channel layer, (b) isolating a mesa, (c) forming a dielectric layer over the semiconductor substrate, (d) forming a first field plate over the dielectric layer, (e) forming a second field plate over the first field plate, (f) patterning the first field plate and the second field plate to expose locations corresponding to source, gate, and drain openings in the dielectric layer, (g) patterning the dielectric layer to expose locations corresponding to the source and drain openings in the semiconductor substrate, and (h) patterning and forming an ohmic contact metal layer to cover locations corresponding to the source and drain openings in the semiconductor substrate, and alloying the ohmic contact metal layer.

[0008] According to one embodiment of the present invention, the manufacturing method further includes the steps of: (i) patterning a metal layer to cover the ohmic contact metal layer at positions corresponding to the source opening and the drain opening and to cover the dielectric layer at positions corresponding to the gate opening, and (j) patterning a protection layer to expose the metal layer at positions corresponding to the source opening and the drain opening.

[0009] According to one embodiment of the present invention, the protective layer comprises silicon nitride and has a thickness of 1500 to 3500 angstroms.

[0010] According to one embodiment of the present invention, the semiconductor substrate further comprises a cap layer on the barrier layer.

[0011] According to one embodiment of the present invention, in step (b), the mesa isolation comprises an isolation implantation step.

[0012] According to one embodiment of the present invention, in step (c), the formation of the dielectric layer is performed using a low-pressure chemical vapor deposition (LPCVD) process.

[0013] According to one embodiment of the present invention, the dielectric layer comprises silicon nitride and has a thickness of 450 to 750 angstroms.

[0014] According to one embodiment of the present invention, in step (d), the first field plate is formed using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0015] According to one embodiment of the present invention, in step (e), forming the second field plate uses a plasma-assisted chemical vapor deposition process.

[0016] According to one embodiment of the present invention, the first field plate includes silicon nitride and has a thickness of 1500 to 3500 angstroms.

[0017] According to one embodiment of the present invention, the second field plate includes silicon nitride and has a thickness of 2500 to 4000 angstroms.

[0018] According to one embodiment of the present invention, step (d) further includes forming an etch stop layer on the first field plate.

[0019] According to one embodiment of the present invention, the etching stop layer is formed using a low pressure chemical vapor deposition process at a temperature below 800°C.

[0020] According to one embodiment of the present invention, the etching stop layer includes silicon nitride and has a thickness of 75 to 150 angstroms.

[0021] According to one embodiment of the present invention, in step (h), the process temperature for forming and alloying the ohmic contact metal layer is 300 to 600°C.

[0022] In the method for manufacturing a depletion-mode high electron mobility transistor provided by the present invention, various dielectric layers (including the aforementioned dielectric layer, first field plate, etch stop layer, and second field plate) can be fabricated before the ohmic contact metal layer, making the configuration of the manufacturing process more flexible. Based on this, the present invention further utilizes the characteristics of different epitaxial growth or deposition processes to more efficiently and simply pattern the transistor in the subsequent manufacturing process without using special processes of the prior art.

[0023] To make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the following description is given with reference to the drawings. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a flowchart of a method for fabricating a depletion-mode high electron mobility transistor according to one embodiment of the present invention. [Figure 2] 1 is a flowchart of a method for fabricating a depletion-mode high electron mobility transistor according to one embodiment of the present invention. [Figure 3] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 4A] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 4B] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 4C] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 5] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 6A] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 6B] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 7] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 8A] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 8B] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 8C]1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 8D] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 8E] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 8F] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 9A] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 9B] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 9C] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 10A] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 10B] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 10C] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 10D] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 11A] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 11B] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 11C] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; [Figure 12] 1A-1D are schematic cross-sectional views illustrating a depletion-mode high electron mobility transistor structure at different stages of fabrication according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0025] According to common practice, the various features and components in the drawings are not drawn to scale, but are drawn in a manner that best suits the purpose of presenting the specific features and components relevant to the present invention. Furthermore, the same or similar reference numerals are used to represent similar components and elements in different drawings.

[0026] To provide a more detailed and complete description of the present invention, the following provides illustrative descriptions of embodiments and specific examples of the present invention, but these are not the only ways to implement or operate the specific examples of the present invention. In this specification and the appended claims, unless the context dictates otherwise, the terms "a," "an," and "the" may be interpreted as plural. Furthermore, unless otherwise specified in this specification and the appended claims, "disposed on something" may be considered to be attached or otherwise in direct or indirect contact with some surface. The identity of the surface must be determined based on the context of the specification, the meaning of the paragraph, and common knowledge in the technical field to which the present invention pertains.

[0027] Although the numerical ranges and parameters specifying the present invention are approximations, the relevant numerical values ​​in the specific examples are presented as precisely as possible. However, any numerical values ​​necessarily contain standard deviations resulting from the inherent nature of each testing method. As used herein, the term "about" typically means that the actual value is within ±10%, 5%, 1%, or 0.5% of a particular numerical value or range. Alternatively, the term "about" indicates that the actual value is within an acceptable standard error of the mean, as would be expected by one of ordinary skill in the art to which the present invention pertains. Thus, unless otherwise specified, the numerical values ​​and parameters disclosed in this specification and the appended claims are approximations that can be varied as necessary. At the very least, these numerical values ​​and parameters should be interpreted as meaning values ​​obtained using the indicated number of significant digits and ordinary rounding techniques.

[0028] <Terminology> As used herein, the term "high electron mobility transistor" may refer to an enhancement-mode semiconductor device (E-mode) or a depletion-mode high electron mobility transistor (D-mode). The depletion-mode high electron mobility transistor may have a normally-on structure with a negative threshold voltage or a normally-off structure with a positive threshold voltage. Meanwhile, the "semiconductor material" of the present invention may include chemical compounds of multiple elements, including, but not limited to, GaN, which may belong to one or more elements of different groups in the chemical periodic table. These compounds include pairs consisting of elements from Group 13 (i.e., the group including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl)) and Group 15 (i.e., the group including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi)), or pairs consisting of elements from Group 14 (i.e., the group including elements such as carbon (C), silicon (Si), germanium (Ge), and tin (Sn)), such as silicon carbide (SiC) or silicon germanium alloys. Groups 13 through 15 of the periodic table are sometimes referred to as Groups III, IV, and V, respectively.

[0029] As used herein, the term "exposure" means that the surface of an object is not completely covered and may have one or more openings or hole / groove structures formed on the surface of the object, but the specific definition should be determined based on the meaning of the context / paragraph of the specification and common knowledge in the field of technology to which the present invention belongs.

[0030] As used herein, the term "suitable epitaxial growth or deposition process" includes, but is not limited to, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), atomic layer deposition (ALD), molecular layer deposition (MLD), plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, and the like, or combinations thereof.

[0031] As used herein, the term "photoresist" refers to a photosensitive material commonly used in the fabrication of integrated circuits and semiconductor devices. After exposure or irradiation with ultraviolet light, deep ultraviolet light, electron beams, ion beams, X-rays, etc., it develops different solubility, allowing a user to draw a desired pattern on the surface of an object. Photoresists are divided into positive photoresists and negative photoresists. After exposure and development, positive photoresists produce the same pattern as the reticle, while negative photoresists produce an inverted pattern.

[0032] As used herein, the term "mask / reticle" refers to a light-shielding device commonly used in the fabrication of integrated circuits and semiconductor devices, which defines a pattern on the surface of an object during the manufacturing process and is used in combination with photoresist to perform patterning.

[0033] As used herein, the term "lift-off process" refers to using a negative photoresist where you want to create a metal area, forming the metal after going through a light irradiation process, and then using an etching method to dissolve the sacrificial layer and peel off other metal deposits that are not needed to create the metal area.

[0034] As used herein, the term "suitable etching process" includes, but is not limited to, dry etching and wet etching. Dry etching includes physical bombardment methods such as reactive ion etching (RIE) and inductively coupled plasma (ICP), while wet etching is a chemical solution etching method well known in the art to which the present invention pertains.

[0035] The following description of the present invention will enable those skilled in the art to easily understand the necessary technical contents of the present invention, and various modifications and adaptations may be made to the present invention to adapt to different uses and situations without departing from the spirit and scope of the present invention. Other embodiments also fall within the scope of the claims of the present invention. [Example]

[0036] 1 and 2 are flow charts of methods for fabricating depletion-mode high electron mobility transistors according to some embodiments of the present invention, and FIGS. 3 to 12 are cross-sectional views of high electron mobility transistor structures at different stages of the fabrication method.

[0037] First, referring to FIG. 1 , one aspect of the present invention provides a method for manufacturing a depletion-mode high electron mobility transistor, substantially including the following steps: Step S100: Prepare a semiconductor substrate; Step S102: Isolate a mesa; Step S104: Form a dielectric layer on the semiconductor substrate; Step S106: Form a first field plate on the dielectric layer; Step S108: Form a second field plate on the first field plate; Step S110: Pattern the first and second field plates to expose positions corresponding to the source, gate, and drain openings in the dielectric layer; Step S112: Pattern the dielectric layer to expose positions corresponding to the source and drain openings in the semiconductor substrate; Step S114: Pattern and form an ohmic contact metal layer to cover positions corresponding to the source and drain openings in the semiconductor substrate, and alloy the ohmic contact metal layer. Step S106 may further include Step S107 of forming an etching stop layer on the first field plate while forming the first and second field plates.

[0038] 2, a method for manufacturing a depletion-mode high electron mobility transistor according to an embodiment of the present invention further includes the following steps: Step S116: Patterning a metal layer to cover the ohmic contact metal layer at positions corresponding to the source and drain openings and to cover the dielectric layer at positions corresponding to the gate opening; Step S118: Patterning a protection layer to expose the metal layer at positions corresponding to the source and drain openings.

[0039] 3 shows the semiconductor substrate 100 provided in step S100. Please refer to FIGS. 1 and 3 together. According to some embodiments of the present invention, the semiconductor substrate 100 is an epitaxially grown layer based on an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) high electron mobility transistor. Specifically, the semiconductor substrate 100 includes a channel layer 108 and a barrier layer 110 disposed on the channel layer 108. A heterogeneous material interface exists between the channel layer 108 and the barrier layer 110, allowing a two-dimensional electron gas region to form near the interface in the channel layer 108. The two-dimensional electron gas region can form a conductive channel of free electrons when a bias is applied, thereby achieving the purpose of electrically connecting, for example, a source electrode and a drain electrode. Furthermore, the material of the channel layer 108 is undoped or unintentionally doped GaN, and the thickness of the channel layer 108 is 50 to 400 nm, for example, the following values ​​or values ​​within a range between any two of these: 150 nm, 170 nm, 190 nm, 210 nm, 230 nm, 250 nm, 270 nm, 290 nm, 310 nm, 330 nm, 350 nm, 370 nm, 390 nm, or 400 nm. The material of the barrier layer 110 is undoped or unintentionally doped Al. x Ga 1-x N, where x is in the range of about 0.1 to about 1, and the thickness of the barrier layer 110 is 10 to 40 nm, such as the following values ​​or values ​​within a range between any two of these: 10, 15, 20, 25, 30, 35, or 40 nm.

[0040] According to a preferred embodiment of the present invention, the semiconductor substrate 100 has a layer structure, from bottom to top, of a substrate 102, a nucleation layer 104, a buffer layer 106, a channel layer 108, and a barrier layer 110. According to a more preferred embodiment, a cap layer (not shown) may be further included on the barrier layer 110, with the cap layer having a thickness of 0 to 3.0 nm, e.g., 0 nm, 0.5 nm, 1.0 nm, 0.5 nm, 2.0 nm, 2.5 nm, or 3.0 nm. The substrate 102 includes a wafer made of high-quality single-crystal silicon semiconductor material, such as sapphire, GaN, GaAs, crystalline silicon, any polymorph of silicon carbide (SiC) (including wurtzite), AlN, InP, or a similar substrate material for semiconductors, which must be insulated. The nucleation layer 104 may contain undoped or unintentionally doped AlN compounds. The buffer layer 106 is provided to compensate for mismatch between the layers and comprises undoped, unintentionally doped, or carbon doped GaN.

[0041] 4A-4C illustrate the structural changes that occur when mesas are isolated on semiconductor substrate 100 using a specific mask and / or photoresist in step S102. Please refer to FIGS. 1 and 4A-4C together. First, photoresist 1 is applied to semiconductor substrate 100, and an appropriate etching process is used to etch down to buffer layer 106 of semiconductor substrate 100. The photoresist 1 is then removed to obtain semiconductor substrate 200 with the mesa isolation step completed. This allows active regions M to be defined in semiconductor substrate 200 so that elements can operate independently without affecting each other. More specifically, the depth D1 etched down to buffer layer 106 of semiconductor substrate 100 is 1500-4500 Å, for example, 1500 Å, 2000 Å, 2500 Å, 3000 Å, 3500 Å, or 4000 Å. According to one embodiment of the present invention, the mesa isolation step may further include an isolation implantation step, which is a method of doping a transistor by accelerating specific types of ions in an electric field, to change the resistance of the layer and facilitate the achievement of the above-mentioned active region definition. Specifically, the isolation implantation process may be performed after the subsequent high-temperature process is completed. More specifically, it may be performed after the high-temperature process is completed and before the alloying process.

[0042] FIG. 5 shows a structure in which a dielectric layer 112 is formed on a semiconductor substrate 100 in step S104. Please refer to FIGS. 1 and 5 together. Here, the dielectric layer 112 is formed on a semiconductor substrate 200 using an appropriate epitaxial growth or deposition process, and preferably, the dielectric layer 112 is formed using an LPCVD process. Without being bound by any particular theory, forming the dielectric layer 112 using the LPCVD process in step S104 can effectively prevent contamination with metals from other processes. According to a preferred embodiment of the present invention, the thickness of the dielectric layer 112 is 450 to 750 Å, for example, the following values ​​or values ​​within any two ranges thereof: 450 Å, 500 Å, 550 Å, 600 Å, 650 Å, 700 Å, or 750 Å, preferably 550 Å. The material of the dielectric layer 112 is silicon nitride (SiN). x (where x is about 0.1 to 1).

[0043] FIG. 6A shows a structure in which first field plate 114 is formed on dielectric layer 112 in step S106. Please refer to FIGS. 1 and 6A together. Here, first field plate 114 is formed on dielectric layer 112 using an appropriate epitaxial growth or deposition process. Preferably, first field plate 114 is formed using a process different from that in step S104, such as a PECVD process. According to a preferred embodiment of the present invention, the thickness of first field plate 114 is 1500 to 3500 Å, for example, the following values ​​or values ​​within a range between any two of these values: 1500 Å, 1700 Å, 1900 Å, 2100 Å, 2300 Å, 2500 Å, 2700 Å, 2900 Å, 3100 Å, 3300 Å, or 3500 Å, preferably 2500 Å. The material of first field plate 114 is silicon nitride (SiN). x (where x is about 0.1 to 1).

[0044] According to a preferred embodiment of the present invention, after step S106, as shown in FIGS. 1 and 6B, the method may further include step S107 of forming an etching stop layer 116 on the first field plate 114. Specifically, this step is a step of forming the etching stop layer 116 on the first field plate 114 using an appropriate epitaxial growth or deposition process. Preferably, the etching stop layer 116 is formed using a process different from that of step S106, such as an LPCVD process. Without being bound by any particular theory, the LPCVD process in this step may be performed at a lower temperature to avoid damage to other layers below the etching stop layer 116. According to a preferred embodiment of the present invention, the temperature is less than 800° C., for example, less than 800, less than 750, less than 700, or less than 650° C. According to a preferred embodiment of the present invention, the thickness of the etching stop layer 118 is 75 to 150 Å, for example, the following values ​​or values ​​within a range between any two of these values: 75 Å, 85 Å, 95 Å, 105 Å, 115 Å, 125 Å, 135 Å, 145 Å, or 150 Å. Also, the material of the etching stop layer 118 is silicon nitride (SiN). x (where x is about 0.1 to 1).

[0045] FIG. 7 shows the second field plate 118 formed on the first field plate 114 (or on the etching stop layer 116) in step S108. Please refer to FIGS. 1 and 7 together. Here, the second field plate 118 is formed on the first field plate 114 (or on the etching stop layer 116) using an appropriate epitaxial growth or deposition process, and preferably, the second field plate 118 is formed using a process different from that in step S107, such as a PECVD process. According to a preferred embodiment of the present invention, the thickness of the second field plate 116 is 2500 to 4000 Å, for example, the following values ​​or values ​​within a range between any two of these values: 2500 Å, 2700 Å, 2900 Å, 3100 Å, 3300 Å, 3500 Å, 3700 Å, 3900 Å, or 4000 Å, preferably 3500 Å. The material of the second field plate 116 is silicon nitride (SiN).x (where x is between about 0.1 and 1). Without being bound by any particular theory, first field plate 114 and second field plate 118 can improve the breakdown voltage by making the electric field distribution uniform in the channel layer of a depletion-mode high electron mobility transistor.

[0046] 8A-8F illustrate the structural changes that occur after patterning the first field plate 114 and the second field plate 118 in step S110. Please refer to FIGS. 1 and 8A-8F together. First, referring to 8A-8C, the second field plate 118 is patterned using a specific mask and / or photoresist (photoresist 2 shown in FIG. 8A) and an appropriate etching process. Photoresist 2 is then removed to obtain the layer structure of the patterned second field plate 118. According to a preferred embodiment of the present invention, the etching stop layer 116 is formed using an LPCVD process, and the second field plate 118 is formed using a PECVD process. Without being bound by any particular theory, due to the different characteristics of the deposition processes of the two, a selective etching effect can be achieved simply by adjusting the process parameters of the etching process, and the etching process is stopped at the etching stop layer 116, preventing over-etching of the first field plate 114.

[0047] Next, refer to FIGS. 8D to 8F. Here, using a specific mask and / or photoresist (such as photoresist 3 shown in FIG. 8D) and an appropriate etching process, first field plate 114 is patterned to expose the dielectric layer 112 at locations corresponding to source opening 10, gate opening 11, and drain opening 12, and then photoresist 3 is removed. According to a preferred embodiment of the present invention, the length Ls of source opening 10 is 12 to 17 μm, e.g., 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, or 17 μm, preferably 15 μm. According to another preferred embodiment of the present invention, the length Lg of gate opening 11 is 1.0 to 2.5 μm, e.g., 1.0 μm, 1.5 μm, 2.0 μm, or 2.5 μm, preferably 1.5 μm. According to another preferred embodiment of the present invention, the length Ld of the drain opening 12 is 15 to 25 μm, for example, the following value or a value within a range between any two of these: 15 μm, 17 μm, 19 μm, 21 μm, 23 μm, or 25 μm. According to another preferred embodiment of the present invention, the length Lgs between the source opening 10 and the gate opening 11 is 2.0 to 3.5 μm, for example, the following value or a value within a range between any two of these: 2.0 μm, 2.5 μm, 3.0 μm, or 3.5 μm, preferably 3.0 μm. According to another preferred embodiment of the present invention, the length Lgd between the drain opening 12 and the gate opening 11 is 15 to 25 μm, for example, the following value or a value within a range between any two of these: 15 μm, 20 μm, or 25 μm, preferably 20 μm. According to a preferred embodiment of the present invention, dielectric layer 112 is formed using an LPCVD process, and first field plate 114 is formed using a PECVD process. Without being bound by any particular theory, due to the different characteristics of the deposition processes of the two, a selective etching effect can be achieved by simply adjusting the process parameters of the etching process, and the etching process is stopped at dielectric layer 112.

[0048] 9A to 9C show the structural changes that occur when the dielectric layer 112 is patterned using a specific mask and / or photoresist in step S112. Please refer to FIG. 1 and FIGS. 9A to 9C together. First, a specific photoresist 4 is used, and then an appropriate etching process is used to etch the dielectric layer 112 downward from the predetermined locations where the source and drain will be formed to the barrier layer 110, thereby forming corresponding source openings 10 and drain openings 12 on the semiconductor substrate 200, and then the photoresist 4 is removed.

[0049] 10A to 10C show the structural change state in step S114, in which an ohmic contact metal layer 120 is patterned and formed on the source opening 12 and the drain opening 14, and the ohmic contact metal layer 120 is alloyed. Please refer to FIG. 1 and FIGS. 10A to 10C together. Here, the ohmic contact metal layer 120 is formed using an appropriate mask and / or photoresist (two photoresists 5 and 6 made of different materials, as shown in FIG. 10A) and an appropriate epitaxial growth or deposition process, and then the photoresists 5 and 6 are removed to achieve the purpose of forming the ohmic contact metal layer 120 exclusively in the source opening 12 and the drain opening 12. According to a preferred embodiment of the present invention, photoresist 6 is provided on photoresist 5, and photoresist 6 covers a larger area of ​​the semiconductor substrate than photoresist 5. Without being bound by any particular theory, such a configuration allows the photoresist to have an overhang structure, which can effectively separate the ohmic contact metal layer 120 formed in the source opening 10 / drain opening 12 and the ohmic contact metal layer 120 formed on the photoresist.

[0050] Further, an alloying process is used to alloy the ohmic contact metal layer 120 formed in the source opening 10 and the drain opening 12 to form the source and drain, respectively, thereby forming ohmic contacts in the high electron mobility transistor. According to a preferred embodiment of the present invention, since the bottom surfaces of the source opening 10 and the drain opening 12 expose the channel layer 108, the alloying process can be performed at a process temperature substantially lower than that of known techniques, preferably 300 to 600°C, for example, at the following values ​​or values ​​within a range between any two of these values: 300°C, 350°C, 400°C, 450°C, 500°C, 550°C, or 600°C. According to another preferred embodiment of the present invention, the formation of the ohmic contact can also be improved by forming a highly doped n-type gallium nitride layer (not shown) on the bottom surfaces of the source opening 10 and the drain opening 12, respectively, with a carrier concentration of preferably 10 19 cm -3 More preferably, the carrier concentration is increased to 10 by molecular beam epitaxy (MBE). 20 cm -3 Without being bound by any particular theory, the alloying process may be replaced or simplified, or a lower alloying process temperature, such as 300-400°C, may be employed. More specifically, according to a preferred embodiment, after step S102 (mesa isolation), a suitable etching process is first used to form corresponding source and drain openings 10 and 12 on the semiconductor substrate 200 by etching downward from the predetermined locations where the source and drain will be formed to the channel layer 108, and then an n-type gallium nitride layer is formed by molecular beam epitaxy. According to some embodiments of the present invention, the ohmic contact metal layer 120 may be made of any suitable conductive material capable of forming an ohmic contact or other conductive interface, preferably titanium (Ti), aluminum (Al), nickel (Ni), tantalum (Ta), molybdenum (Mo), or gold (Au).

[0051] 11A and 11B illustrate the structural change resulting from patterning metal layer 122 in step S116. Please refer to FIG. 2, 11A, and 11B together. In this step, metal layer 122 is patterned to cover the portions of ohmic contact metal layer 120 corresponding to source opening 10 and drain opening 12, the portion of dielectric layer 112 corresponding to gate opening 11, part of etching stop layer 116, and part of second field plate 118. Specifically, metal layer 122 is formed using an appropriate mask and / or photoresist (two photoresists 7 and 8 of different materials, as shown in FIG. 11A) and an appropriate epitaxial growth or deposition process, and then the photoresists 7 and 8 are removed using a lift-off process to achieve the goal of patterning and forming metal layer 122. According to a preferred embodiment of the present invention, the photoresists 7 and 8 have the same structure as photoresists 5 and 6 shown in FIG. 10A, and an overhang structure can also be formed.

[0052] Specifically, the metal layer 122 covers a portion of the dielectric layer 112 corresponding to the gate opening 11 to form a gate, and also covers portions of the ohmic contact metal layer 120 corresponding to the source opening 10 and the drain opening 12, a portion of the etching stop layer 116, and a portion of the second field plate 118, although the specific size of the covered area is not limited by the present invention. According to one embodiment of the present invention, the gate protrusion length Lgo is 0.5 to 1.0 μm, for example, 0.5 μm, 0.75 μm, or 1.0 μm, or a value between any two of these values, preferably 0.75 μm. According to another embodiment of the present invention, the source protrusion length Lso is 0.3 to 1.0 μm, for example, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, or 1.0 μm, or a value between any two of these values, preferably 0.5 μm. According to another embodiment of the present invention, the drain protrusion length Ldo is 0.5 to 1.0 μm, for example, 0.5 μm, 0.75 μm, or 1.0 μm, preferably 0.75 μm. Without being bound by any particular theory, the metal layer 122 covers the ohmic contact metal layer 120 at locations corresponding to the source opening 10 and the drain opening 12, thereby thickening the source and drain and preventing series resistance in a depletion-mode high electron mobility transistor. According to some embodiments of the present invention, the metal layer 122 can be made of any conductive material capable of biasing and controlling a semiconductor device, preferably nickel (Ni) / gold (Au) or zirconium (Zr) / gold (Au).

[0053] FIG. 12 illustrates the structural change state formed by patterning the protective layer 124 in step S118. Please refer to FIGS. 2 and 12 together. Here, the protective layer 124 is formed using an appropriate mask and / or photoresist (not shown) and an appropriate epitaxial growth or deposition process, and then the mask / photoresist is removed to selectively expose the protective layer 124 at positions corresponding to the source opening 10 and the drain opening 12 of the metal layer 122. According to a preferred embodiment of the present invention, the thickness of the protective layer 124 is 1500 to 3500 Å, for example, the following values ​​or values ​​within any two ranges thereof: 1500 Å, 1700 Å, 1900 Å, 2100 Å, 2300 Å, 2500 Å, 2700 Å, 2900 Å, 3100 Å, 3300 Å, or 3500 Å. The material of the protective layer 124 is silicon dioxide (SiO ). x Or silicon nitride SiN x (where x is about 0.1 to 1), and preferably silicon nitride.

[0054] According to some embodiments of the present invention, after carrying out the above steps, a passivation layer (not shown) can be preferably patterned and provided. The passivation layer can be formed through a suitable epitaxial growth or deposition process, and patterned in combination with a specific mask and photoresist, and made of organic / inorganic dielectric material, preferably SiO2, SiON, etc. x or SiN x (x is about 0.1 to 1).

[0055] In summary, in the method for manufacturing a depletion-mode high electron mobility transistor provided by the present invention, the various dielectric layers (including the aforementioned dielectric layer, first field plate, etching stop layer, and second field plate) can be formed before the ohmic contact metal layer, eliminating the problem of limiting the choice of epitaxial or deposition process by forming them later than the ohmic contact metal layer. This makes it possible to more appropriately utilize the characteristics of different epitaxial growth or deposition processes, thereby achieving the effect of accurately controlling selective etching in subsequent processes without using expensive, complicated, and technically difficult processes.

[0056] Although the present invention has been described in detail above, the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. That is, those skilled in the art may make equivalent modifications and adaptations without departing from the spirit and scope of the present invention, which should fall within the protection scope of the present invention. [Explanation of symbols]

[0057] 100, 200 Semiconductor substrate 10 Source opening 1, 2, 3, 4, 5, 6, 7, 8 Photoresist 11 Gate opening 12 Drain opening 102 Base material 104 Nucleation layer 106 Buffer Layer 108 Channel Layer 110 Barrier Layer 112 Dielectric layer 114 First Field Plate 116 Etching suppression layer 118 Second Field Plate 120 Ohmic contact metal layer 122 Metal layer 124 Protective layer D1 Depth Ls, Lg, Ld, Lgs, Lgd, Lso, Lgo, Ldo length S100~S118 steps

Claims

1. (a) providing a semiconductor substrate including a channel layer and a barrier layer overlying the channel layer; (b) isolating the mesa; (c) forming a dielectric layer over the semiconductor substrate; (d) forming a first field plate over the dielectric layer; (e) forming a second field plate over the first field plate; (f) patterning the first field plate and the second field plate to expose locations corresponding to source, gate, and drain openings in the dielectric layer; (g) patterning the dielectric layer to expose locations of the semiconductor substrate corresponding to the source and drain openings; and (h) patterning an ohmic contact metal layer to cover the semiconductor substrate at positions corresponding to the source opening and the drain opening, and alloying the ohmic contact metal layer; 2. A method for manufacturing a depletion-mode high electron mobility transistor, comprising:

2. (i) patterning and forming a metal layer to cover the ohmic contact metal layer at positions corresponding to the source opening and the drain opening and to cover the dielectric layer at a position corresponding to the gate opening; and (j) patterning a protection layer to expose portions of the metal layer corresponding to the source opening and the drain opening; The method of claim 1 , comprising:

3. 3. The method of claim 2, wherein the protective layer comprises silicon nitride and has a thickness of 1500 to 3500 angstroms.

4. The method of claim 1 , wherein the semiconductor substrate further comprises a cap layer over the barrier layer.

5. 2. The method of claim 1, wherein in step (b), isolating the mesa comprises an isolation implantation step.

6. 2. The manufacturing method according to claim 1, wherein in step (c), the dielectric layer is formed using a low-pressure chemical vapor deposition (LPCVD) process.

7. 2. The method of claim 1, wherein the dielectric layer comprises silicon nitride and has a thickness of 450 to 750 Angstroms.

8. 2. The manufacturing method of claim 1, wherein in step (d), the first field plate is formed using a plasma-enhanced chemical vapor deposition (PECVD) process.

9. 9. The manufacturing method of claim 8, wherein in step (e), the second field plate is formed using the plasma-assisted chemical vapor deposition process.

10. The method of claim 1 , wherein the first field plate comprises silicon nitride and has a thickness of 1500 to 3500 angstroms.

11. The method of claim 1 , wherein the second field plate comprises silicon nitride and has a thickness of 2500 to 4000 angstroms.

12. The method of claim 1 , wherein step (d) can further include forming an etch stop layer over the first field plate.

13. The method of claim 12 , wherein the etching stop layer is formed using a low-pressure chemical vapor deposition process at a temperature of less than 800° C.

14. The method of claim 13, wherein the etch stop layer comprises silicon nitride and has a thickness of 75 to 150 angstroms.

15. 2. The manufacturing method according to claim 1, wherein in step (h), the process temperature for forming and alloying the ohmic contact metal layer is 300 to 600°C.

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