Efficient energy recovery in nanosecond pulser circuit

Abstract

To provide a nanosecond pulser circuit and a method for creating high voltage pulses, performing efficient energy recovery in a nanosecond pulser circuit that achieves fast rise times and / or fast fall times for high voltage pulses.SOLUTION: A nanosecond pulser circuit 100 includes: a high voltage power supply; a nanosecond pulser 105 that is electrically coupled with the high voltage power supply and that switches voltage from the high voltage power supply at high frequencies; a transformer T1 that has a primary side and a secondary side, the nanosecond pulser being electrically coupled with the primary side of the transformer; and an energy recovery circuit 110 that is electrically coupled with the secondary side of the transformer. In some embodiments, the energy recovery circuit includes: an inductor 115 that is electrically coupled with the nanosecond pulser; a crowbar diode 130 that is arranged in parallel with the secondary side of the transformer; and a second diode 120 that is arranged in series with the inductor and that is arranged to conduct current from a load to the nanosecond pulser.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to efficient energy recovery in nanosecond pulser circuits. [Background technology]

[0002] It is difficult to generate high voltage pulses with fast rise and / or fall times. For example, to achieve fast rise and / or fall times (e.g., less than about 50 ns) for high voltage pulses (e.g., greater than about 5 kV), the slope of the rise and / or fall of the pulse must be very steep (e.g., greater than 10 ns). -11 V / s). Such steep rise and / or fall times are very difficult to produce, especially in circuits driving capacitive loads. Such pulses can be particularly difficult to generate compactly using standard electrical components, and / or with pulses that have variable pulse widths, voltages, and repetition rates, and / or in applications with capacitive loads, such as plasma. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made to solve the problems in the prior art described above. [Means for solving the problem]

[0004] Some embodiments include a nanosecond pulser circuit. In some embodiments, the nanosecond pulser circuit may include a high-voltage power supply, a nanosecond pulser electrically coupled to the high-voltage power supply and configured to switch voltage from the high-voltage power supply at a high frequency, a transformer having a primary side and a secondary side, the nanosecond pulser electrically coupled to the primary side of the transformer, and an energy recovery circuit electrically coupled to the secondary side of the transformer. In some embodiments, the energy recovery circuit includes an inductor electrically coupled to the high-voltage power supply, a crowbar diode disposed in parallel with the secondary side of the transformer, and a second diode disposed in series with the inductor and configured to conduct current from the load to the high-voltage power supply.

[0005] In some embodiments, the energy recovery inductor has an inductance greater than about 50 μH.

[0006] In some embodiments, the nanosecond pulser switches the voltage from the high voltage power supply at a frequency greater than about 100 kHz. In some embodiments, the nanosecond pulser switches the voltage from the high voltage power supply at a frequency between about 0 kHz and about 500 kHz. In some embodiments, the nanosecond pulser circuit delivers a voltage greater than about 5 kV to the load.

[0007] In some embodiments, the energy recovery circuit comprises a switch. In some embodiments, the energy recovery circuit further comprises a high voltage switch in series with the second diode and the inductor. In some embodiments, the high voltage switch switches a voltage greater than about 5 kV.

[0008] In some embodiments, the load comprises a capacitive load.In some embodiments, the load comprises a plasma deposition chamber.

[0009] In some embodiments, the high voltage power supply provides DC power at voltages greater than 500V, 750V, 1 kV, 1.5 kV, and the like.

[0010] Some embodiments include a circuit comprising: a storage capacitor; a switching circuit coupled to the storage capacitor and outputting a waveform having a voltage greater than about 1 kV and a frequency greater than about 1 kHz; a transformer having a primary side and a secondary side, wherein the switching circuit may be electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the secondary side of the transformer (e.g., via an energy recovery diode) and the storage capacitor. In some embodiments, the energy recovery circuit comprises an inductor electrically coupled to the high voltage power supply and a second diode disposed in series with the inductor and configured to conduct current from the load to the high voltage power supply.

[0011] In some embodiments, the energy recovery circuit comprises a crowbar diode placed in parallel with the secondary transformer.

[0012] In some embodiments, the inductor comprises an inductance greater than about 50 μH.

[0013] In some embodiments, the switching circuit includes a nanosecond pulser. In some embodiments, the switching circuit comprises an RF driver. In some embodiments, the RF driver includes any of a half-bridge driver, a full-bridge driver, high frequency solid-state switch(es), an RF generator, a tube-based RF generator, or a tube-based RF generator.

[0014] In some embodiments, the circuit further comprises a bias compensation circuit including a bias compensation diode arranged in parallel with the bias compensation switch, and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

[0015] Some embodiments include a method for generating high voltage pulses, the method including: opening a bias compensation switch in a bias compensation circuit with a pulser switch closed and coupling the bias compensation circuit to a secondary side of a transformer; closing a pulser switch of a nanosecond pulser to generate a pulse and coupling the nanosecond pulser to a primary side of the transformer and a DC power source, the pulse having a voltage greater than 1 kV on the secondary side of the transformer; opening an energy recovery switch in an energy recovery circuit with the pulser switch closed, the energy recovery circuit coupled to the secondary side of the transformer and the DC power source; pausing for a period of less than about 100 nanoseconds; closing the pulser switch of the nanosecond pulser; and opening the energy recovery switch in the energy recovery circuit with the pulser switch closed.

[0016] In some embodiments, the energy recovery circuit includes an inductor and a diode connected in series with the energy recovery switch.

[0017] In some embodiments, the energy recovery switch includes a plurality of switches arranged in series, the switches having a plurality of voltage sharing resistors, each voltage sharing resistor of the plurality of voltage sharing resistors positioned across a corresponding one of the plurality of switches.

[0018] In some embodiments, the bias compensation circuit comprises a bias compensation diode arranged in parallel with the bias compensation switch, and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

[0019] Some embodiments include a method for generating high voltage pulses, the method including the steps of: before a burst of pulses, opening a bias compensation switch in a bias compensation circuit coupled to a nanosecond pulser through a transformer, the bias compensation circuit coupled to a secondary side of the transformer; during the burst of pulses, repeatedly opening and closing a pulser switch of the nanosecond pulser to generate a plurality of pulses in the burst of pulses, the nanosecond pulser coupled to a primary side of the transformer and to a DC power source, the opening and closing of the pulser switch occurring at a pulse repetition frequency greater than about 1 kHz, and the closing of the pulser switch generating pulses at a voltage greater than 1 kV on the secondary side of the transformer; during the burst of pulses, repeatedly opening and closing an energy recovery switch in an energy recovery circuit, such that the energy recovery switch closes when the pulser switch is open and opens when the pulser switch is closed, coupling the energy recovery circuit to the secondary side of the transformer and the DC power source; and after the burst of pulses, closing the bias compensation switch in the bias compensation circuit.

[0020] In some embodiments, the method may further include pausing for a period of less than about 100 microseconds, opening the bias compensation switch before the second burst of pulses, opening and closing the pulser switch during the second burst of pulses, opening and closing the energy recovery switch during the second burst of pulses, and closing the bias compensation switch after the second burst.

[0021] In some embodiments, the energy recovery circuit includes an inductor and a diode connected in series with the energy recovery switch.

[0022] In some embodiments, the energy recovery switch includes a plurality of switches arranged in series, the plurality of switches having a plurality of voltage sharing resistors, each voltage sharing resistor of the plurality of voltage sharing resistors disposed across a corresponding switch of the plurality of switches.

[0023] In some embodiments, the bias compensation circuit comprises a bias compensation diode arranged in parallel with the bias compensation switch, and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

[0024] Some embodiments include a nanosecond pulser circuit comprising: a high voltage power supply; a nanosecond pulser electrically coupled to the high voltage power supply and configured to switch voltage from the high voltage power supply at a high frequency; a transformer having a primary side and a secondary side; and an energy recovery circuit arranged in parallel with the primary side of the transformer. In some embodiments, the energy recovery circuit comprises a switch, an inductor, a first diode arranged in series with the switch and the inductor and arranged to conduct current from the switch to the inductor when the switch is closed, and a second diode arranged to conduct current from a point in the nanosecond pulser circuit between the switch and the first diode to a point in the nanosecond pulser circuit between the high voltage power supply and the nanosecond pulser when the switch is closed.

[0025] Some embodiments include a nanosecond pulser circuit comprising: a high voltage power supply; a nanosecond pulser electrically coupled to the high voltage power supply and configured to switch a voltage from the high voltage power supply at a high frequency; a transformer having a primary side and a secondary side, the nanosecond pulser electrically coupled to the primary side of the transformer; and an energy recovery circuit electrically coupled to the secondary side of the transformer in parallel with the primary side of the transformer. In some embodiments, the energy recovery circuit comprises an inductor electrically coupled to the high voltage power supply; a crowbar diode disposed in parallel with the secondary side of the transformer; and a second diode disposed in series with the inductor and configured to conduct current from a load to the high voltage power supply.

[0026] In some embodiments, the inductor comprises an inductance of less than about 1000 nH. In some embodiments, the nanosecond pulser switches the voltage from the high voltage power supply at a frequency greater than about 100 kHz. In some embodiments, the nanosecond pulser switches the voltage from the high voltage power supply at a frequency between about 0 kHz and about 500 kHz. In some embodiments, the nanosecond pulser circuit supplies a voltage greater than about 5 kV to the load. In some embodiments, the secondary side of the transformer is coupled to a capacitive load. In some embodiments, the secondary side of the transformer is coupled to one or more electrodes that generate or manipulate the plasma. In some embodiments, the energy recovery circuit comprises a switch.

[0027] These exemplary embodiments are mentioned not to limit or define the disclosure, but to provide examples to aid in understanding the disclosure. Additional embodiments are set forth in the Detailed Description, and further explanation is found therein. Advantages offered by one or more of the various embodiments may be further understood by studying this specification or by practicing one or more of the embodiments presented.

[0028] Some embodiments include a high voltage, high frequency switching circuit including: a high voltage switching power supply having a voltage greater than 1 kV and generating pulses at a frequency greater than 10 kHz (or any frequency), a transformer having a primary side and a secondary side, an output electrically coupled to the secondary side of the transformer, and a primary sink electrically coupled to the primary side of the transformer and connected in parallel with the high voltage switching power supply, the primary sink including at least one resistor for discharging a load coupled to the output.

[0029] In some cases, the resistance of the primary sink has a value less than about 400 ohms.

[0030] In some embodiments, the high voltage, high frequency switching power supply provides for higher peak power embodiments, with the primary sink configured to dissipate an average power greater than about 1 kilowatt, hi some embodiments, the primary sink configured to dissipate an average power between 30 W and 30 kW.

[0031] In some embodiments, the primary sink comprises at least one inductor connected in series with at least one resistor.

[0032] In some embodiments, the primary sink includes a switch connected in series with at least one resistor.

[0033] In some embodiments, the output is coupled to a plasma load that is generally capacitive.

[0034] In some embodiments, the output is coupled to a plasma load comprising a dielectric barrier discharge.

[0035] In some embodiments, the resistance is greater than 100 kW.

[0036] In some embodiments, the resistor in the primary sink comprises a resistor R and the output is

number

number

[0037] In some embodiments, the load is capacitive, having a capacitance of less than 50 nF, and the capacitance of the load does not hold a charge for more than 1 μs.

[0038] In some embodiments, the load is capacitive in nature and the high voltage, high frequency switching circuitry rapidly charges the load capacitance and discharges the load capacitance.

[0039] In some embodiments, the output generates a negative bias voltage relative to the plasma and ground on the electrode, substrate, or wafer that is greater than -2 kV when the high-voltage switching power supply is not providing the high-voltage pulses. In some embodiments, the bias voltage may be positive.

[0040] In some embodiments, the output can generate high voltage pulses having voltages greater than 1 kV and frequencies greater than 10 kHz with pulse fall times less than about 400 ns, 40 ns, 4 ns, etc.

[0041] Some embodiments include a high voltage, high frequency switching circuit, including: a high voltage switching power supply generating pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz; a transformer having a primary side and a secondary side; an output electrically coupled to the secondary side of the transformer; a high voltage switching power supply generating pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz; and a primary sink electrically coupled to the primary side of the transformer and arranged in parallel with the output of the high voltage switching power supply, the primary sink including at least one resistor discharging a load coupled to the output coupled to the secondary side of the transformer and at least one inductor arranged in series with the at least one resistor.

[0042] In some embodiments, the primary sink includes a switch connected in series with at least one resistor and / or at least one inductor.

[0043] In some embodiments, the output is capable of generating high voltage pulses having a voltage greater than 1 kV, a frequency greater than 10 kHz, and a pulse fall time less than about 400 ns.

[0044] In some embodiments, the primary sink is configured to dissipate greater than about 1 kilowatt of power.

[0045] In some embodiments, a high voltage switching power supply comprises a power supply, at least one switch, and a step-up transformer.

[0046] In some embodiments, the primary sink handles peak power in excess of 10 kW.

[0047] In some embodiments, the resistance of the resistor in the primary sink is less than about 400 ohms.

[0048] In some embodiments, the primary sink includes an inductor and a resistor, and the inductance L of the inductor and the resistance R of the resistor are set to satisfy L / R≈tp, where tp is the pulse width of the pulse.

[0049] In some embodiments, the resistor of the primary sink comprises a resistor R and the output is

number

number

[0050] In some embodiments, a high voltage switching power supply establishes an electrical potential within the plasma that is used to accelerate ions to the surface.

[0051] In some embodiments, the output generates a negative potential difference of greater than −2 kV from the electrode or substrate (or wafer and plasma) relative to ground when the high voltage switching power supply is not providing a high voltage pulse.

[0052] Some embodiments include a high-voltage, high-frequency switching circuit. In some embodiments, the high-voltage, high-frequency switching circuit includes a high-voltage switching power supply generating pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz, a transformer having a primary side and a secondary side, an output electrically coupled to the secondary side of the transformer, and a primary sink electrically coupled to the primary side of the transformer and arranged in parallel with the output of the high-voltage switching power supply, the primary sink including at least one resistor, at least one inductor, and a switch arranged in series. In some embodiments, the output is capable of generating high-voltage pulses having a voltage greater than 1 kV at a frequency greater than 10 kHz and a pulse fall time less than about 400 ns, and the output is electrically coupled to a plasma-type load.

[0053] In some embodiments, the plasma-type load may be modeled as having a capacitive element of less than 20 nF, 10 nF, 100 pF, 10 pF, 1 pF, 0.5 pF, etc.

[0054] In some embodiments, the plasma-type load is designed to accelerate ions onto a surface.

[0055] In some embodiments, a high voltage, high frequency switching power supply establishes the potential for accelerating ions to the surface.

[0056] In some embodiments, the plasma type is generally capacitive in nature.

[0057] In some embodiments, the plasma-type load comprises a dielectric barrier discharge.

[0058] In some embodiments, the high voltage, high frequency switching power supply provides peak power in excess of 100 kW.

[0059] In some embodiments, a high voltage switching power supply comprises a power supply, at least one switch, and a step-up transformer.

[0060] These exemplary embodiments are mentioned not to limit or define the disclosure, but to provide examples to aid in understanding the disclosure. Additional embodiments are set forth in the Detailed Description, and further explanation is found therein. Advantages offered by one or more of the various embodiments may be further understood by studying this specification or by practicing one or more of the embodiments presented. [Brief explanation of the drawings]

[0061] These and other features, aspects, and advantages of the present disclosure will be better understood by reading the following detailed description in conjunction with the accompanying drawings. [Figure 1] FIG. 1 is a circuit diagram of a nanosecond pulser system with an energy recovery circuit driving a capacitive load, according to some embodiments. [Figure 2] 2 is a diagram showing waveforms of voltages and currents in the circuit diagram shown in FIG. 1. [Figure 3] FIG. 1 is a circuit diagram of a nanosecond pulser system including a nanosecond pulser with an energy recovery circuit having an energy recovery switch, according to some embodiments. [Figure 4] FIG. 1 is a circuit diagram of a nanosecond pulser system including a passive bias compensation circuit with an energy recovery circuit, according to some embodiments. [Figure 5] FIG. 1 is a circuit diagram of a nanosecond pulser system including an active bias compensation circuit with an energy recovery circuit according to some embodiments. [Figure 6] FIG. 1 is a circuit diagram of a nanosecond pulser system including an active bias compensation circuit with an energy recovery circuit, according to some embodiments. [Figure 7] FIG. 1 is a circuit diagram of an RF driver system including an RF driver, an active bias compensation circuit, and an energy recovery circuit, according to some embodiments. [Figure 8] FIG. 1 is a diagram of voltage and current waveforms in a nanosecond pulser system. [Figure 9]FIG. 1 is a schematic diagram of a spatially variable wafer bias system according to some embodiments. [Figure 10] FIG. 1 is a circuit diagram of a nanosecond pulser system with an energy recovery circuit according to some embodiments. [Figure 11] FIG. 1 shows voltage and current waveforms in a nanosecond pulser system. [Figure 12] FIG. 1 is a circuit diagram of a nanosecond pulser system with an energy recovery circuit driving a capacitive load, according to some embodiments. [Figure 13] FIG. 1 shows voltage and current waveforms in a nanosecond pulser system. [Figure 14] FIG. 1 is a block diagram of a high voltage switch with isolated power according to some embodiments. [Figure 15] FIG. 1 is a block diagram of a process for operating a nanosecond pulser system with an active energy recovery circuit and an active bias compensation circuit, according to some embodiments. [Figure 16] FIG. 1 illustrates an exemplary computing system for performing functions to facilitate implementation of the embodiments described herein. [Figure 17] FIG. 1 is a schematic diagram of a spatially variable wafer bias system according to some embodiments. [Figure 18] FIG. 1 is a circuit diagram of an RF driver system including an RF driver, an active bias compensation circuit, and an energy recovery circuit, according to some embodiments. [Figure 19] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, according to some embodiments. [Figure 20] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, according to some embodiments. [Figure 21] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, according to some embodiments. [Figure 22] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, according to some embodiments. [Figure 23]FIG. 1 is a diagram of a waveform generated by a nanosecond pulser system. [Figure 24] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, a bias compensation circuit, and a plasma load, according to some embodiments. [Figure 25] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, a bias compensation circuit, and a plasma load, according to some embodiments. [Figure 26] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, a bias compensation circuit, and a plasma load, according to some embodiments. [Figure 27] FIG. 1 is a circuit diagram of a nanosecond pulser system with a primary sink, a bias compensation circuit, and a plasma load, according to some embodiments. [Figure 28] FIG. 1 is a diagram of a waveform generated by a nanosecond pulser system. DETAILED DESCRIPTION OF THE INVENTION

[0062] Some embodiments include a nanosecond pulser system that uses an energy recovery circuit to recover energy from a load (e.g., a capacitive load). In some embodiments, the nanosecond pulser system may include a high-voltage, high-frequency nanosecond pulser that may drive, for example, a plasma deposition system, a plasma etching system, a plasma sputtering system, an electron beam system, an ion beam system, or the like.

[0063] In some embodiments, an energy recovery circuit may recover charge from a load to charge an energy storage capacitor. For example, the energy recovery circuit may recover energy or charge stored in various circuit elements, including capacitors and inductors. These elements may include, for example, stray or parasitic capacitance, inductance, etc., that may normally be dissipated or wasted. The energy recovery circuit may recover energy by, for example, acting to recharge the energy storage capacitor and / or inductor. This energy may be available and / or reused by the circuit.

[0064] FIG. 1 is a circuit diagram of a nanosecond pulser system 100 including a nanosecond pulser stage 101 with an energy recovery circuit 110, a transformer T1, a lead stage 103, a DC bias circuit 104, and a load stage .

[0065] In some embodiments, the load stage 106 may represent an idealized or effective circuit of a semiconductor processing chamber, such as a plasma deposition tool, semiconductor manufacturing tool, or plasma sputtering tool. The capacitance C2 may represent, for example, the capacitance of an electrostatic chuck on which a semiconductor process wafer rests. The chuck may include, for example, a dielectric material (e.g., aluminum oxide or other ceramic material and a conductor encased within the dielectric material). For example, the capacitor C1 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0066] Capacitor C3 may represent, for example, the sheath capacitance between the plasma and the wafer. Resistor R6 may represent, for example, the sheath resistance between the plasma and the wafer. Inductor L2 may represent, for example, the sheath inductance between the plasma and the wafer. Current source I2 may represent, for example, the ion current flowing through the sheath. For example, capacitor C1 or capacitor C3 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0067] Capacitor C9 may represent, for example, the capacitance in the plasma between the chamber wall and the top surface of the wafer. Resistor R7 may represent, for example, the resistance in the plasma between the chamber wall and the top surface of the wafer. Current source I1 may represent, for example, the ion current in the plasma. For example, capacitor C1 or capacitor C9 may have a small capacitance (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0068] In some embodiments, the plasma voltage may be the voltage measured from ground to circuit point 123, the wafer voltage may be the voltage measured from ground to circuit point 122 and represent the voltage at the surface of the wafer, the chucking voltage is the voltage measured from ground to circuit point 121, the electrode voltage is the voltage measured from ground to a circuit point labeled 124 (e.g., on the electrode), and the input voltage is the voltage measured from ground to circuit point 125.

[0069] In this example, the DC bias circuit 104 does not include bias compensation. The DC bias circuit 104 includes, for example, an offset supply voltage V5 that can bias the output voltage either positively or negatively. In some embodiments, the offset supply voltage V5 can be adjusted to change the potential between the wafer voltage and the chuck voltage. In some embodiments, the offset supply voltage V5 can have a kV voltage of approximately ±5 kV, ±4 kV, ±3 kV, ±2 kV, ±1 kV, etc.

[0070] In some embodiments, bias capacitor C12 can isolate (or separate) the DC bias voltage from other circuit elements. Bias capacitor C12 can, for example, allow a potential shift from one portion of the circuit to another. In some embodiments, this potential shift may ensure that the electrostatic force holding the wafer in place on the chuck remains below a voltage threshold. Resistor R2 may isolate the DC bias supply from the high voltage pulse output from nanosecond pulser stage 101.

[0071] Bias capacitor C12 may have a capacitance of, for example, less than about 100 pF, 10 pF, 1 pF, 100 μF, 10 μF, 1 μF, etc. Resistor R2 may have a high resistance, for example, about 1 kOhm, 10 kOhm, 100 kOhm, 1 Mohm, 10 Mohm, 100 Mohm, etc.

[0072] Resistor R13 may represent, for example, the resistance of a lead or transmission line connecting the output of the high voltage power supply system to an electrode (e.g., load stage 106). Capacitor C1 may represent, for example, the stray capacitance of a lead or transmission line.

[0073] In some embodiments, the nanosecond pulser stage 101 may generate pulses with high pulse voltages (e.g., voltages greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), high frequencies (e.g., frequencies greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), fast rise times (e.g., rise times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1000 ns, etc.), fast fall times (e.g., fall times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1000 ns, etc.), and / or short pulse widths (e.g., pulse widths less than about 1000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0074] For example, nanosecond pulser stage 101 may include all or any portion of any device described in U.S. patent application Ser. No. 14 / 542,487, entitled "High Voltage Nanosecond Pulser," which is incorporated herein by reference for all purposes; or all or any portion of any device described in U.S. patent application Ser. No. 14 / 635,991, entitled "Galvanically Isolated Output Variable Pulse Generator Disclosure," which is incorporated herein by reference for all purposes; or all or any portion of a device described in U.S. patent application Ser. No. 14 / 798,154, entitled "High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency," which is incorporated herein by reference for all purposes.

[0075] In some embodiments, nanosecond pulser stage 101 may include one or more nanosecond pulsers coupled in any number of ways.

[0076] In some embodiments, the nanosecond pulser stage 101 may include a DC power supply that provides a consistent DC voltage switched by switch S6 and supplies switched power to the transformer T1. The DC power supply may include a voltage source V5 and an energy storage capacitor C7. If the transformer T1 has a turns ratio of 1:10, the transformer may generate 10 kV across the load C1.

[0077] In some embodiments, if the capacitance of the load (e.g., capacitances C3 and C9) is small compared to the capacitance of the energy storage capacitor C7, a doubling of the voltage may occur at the input of the transformer. For example, if the energy storage capacitor C7 provides 500V, 1 kV may be measured at the input of the transformer T1.

[0078] Switch S6 may include one or more solid-state switches, such as an IGBT, a MOSFET, a SiC-MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc. Switch S6 may be switched based on signals from a controller labeled Sig6+ and Sig6−.

[0079] In some embodiments, the nanosecond pulser stage 101 may include a snubber circuit, which may include a snubber resistor R3 and a snubber capacitor C5 arranged in parallel with a snubber diode D4. The snubber circuit may also include stray inductance. In some embodiments, the snubber resistor R3 and / or the snubber diode D4 may be arranged between the collector of the switch S6 and the primary winding of the transformer T1. The snubber diode D4 may be used to snub overvoltages during switching. A large-capacitance and / or high-speed capacitor C5 may be coupled to the emitter side of the switch S6. A freewheeling diode D2 may also be coupled to the emitter side of the switch S1. Various other components not shown may be included. One or more switches and / or circuits may be arranged in parallel or in series.

[0080] In some embodiments, switch S6 may switch very fast so that the switched voltage does not become the full voltage (e.g., the voltage of energy storage capacitor C7 and / or voltage source V5). In some embodiments, a gate resistor coupled to switch S6 may be set with a short turn-on pulse.

[0081] In some embodiments, nanosecond pulser stage 101 may include a freewheeling diode D2. In some embodiments, freewheeling diode D2 may be used in combination with an inductive load so that energy stored in the inductive load can be dissipated in a resistive element of the circuit after switch S6 is opened, causing current to continue flowing in the same direction through the inductor. If freewheeling diode D2 were not included, this could result in a large reverse voltage across switch S6, for example.

[0082] In some embodiments, the nanosecond pulser stage 101 may include a stray inductance L1 and / or a stray resistance R1. The stray inductance L1 may be, for example, less than about 10 nH, 100 nH, 1000 nH, 10,000 nH, etc. The stray resistance R1 may be, for example, less than about 1 ohm, 100 mOhm, 10 mOhm, etc.

[0083] In some embodiments, the energy recovery circuit 110 may be electrically coupled to the secondary side of the transformer T1 and / or the energy storage capacitor C7. The energy recovery circuit 110 may include, for example, a diode 130 (e.g., a crowbar diode) across the secondary side of the transformer T1. The energy recovery circuit 110 may include, for example, an energy recovery diode 120 and an energy recovery inductor 115 (arranged in series) to allow current to flow from the secondary side of the transformer T1 to charge the energy storage capacitor C7. The energy recovery diode 120 and the energy recovery inductor 115 may be electrically connected to the secondary side of the transformer T1 and the energy storage capacitor C7. In some embodiments, the energy recovery circuit 110 may include the diode 130 and / or an inductor 140 electrically coupled to the secondary side of the transformer T1. The inductor 140 may represent stray inductance and / or may include the stray inductance of the transformer T1.

[0084] In some embodiments, the energy recovery inductor 115 may include any type of inductor, such as, for example, a ferrite inductor, an air core inductor, etc. In some embodiments, the energy recovery inductor 115 may have an inductance greater than about 10 μH, 50 μH, 100 μH, 500 μH, etc. In some embodiments, the energy recovery inductor 115 may have an inductance between about 1 μH and about 100 mH.

[0085] When the nanosecond pulser is turned on, current may charge the load stage 106 (e.g., charging capacitor C3, capacitor C2, or capacitor C9). Some current may flow through the energy recovery inductor 115, for example, when the voltage on the secondary side of transformer T1 rises above the charging voltage of energy storage capacitor C7. When the nanosecond pulser is turned off, current may flow from a capacitor in the load stage 106 (e.g., capacitor C1) through the energy recovery inductor 115 until the voltage across the energy recovery inductor 115 becomes zero, thereby charging energy storage capacitor C7. Diode 130 may prevent the capacitor in the load stage 106 from ringing with inductance in the load stage 106 or the DC bias circuit 104.

[0086] Energy recovery diode 120 may also prevent charge from flowing from energy storage capacitor C7 to a capacitor within load stage 106, for example.

[0087] The value of the energy recovery inductor 115 may be selected to control the current fall time. In some embodiments, the energy recovery inductor 115 may have an inductance value between 1 μH and 600 μH. In some embodiments, the energy recovery inductor 115 may have an inductance value greater than 50 μH. In some embodiments, the energy recovery inductor 115 may have an inductance less than approximately 50 μH, 100 μH, 150 μH, 200 μH, 250 μH, 300 μH, 350 μH, 400 μH, 500 μH, etc.

[0088] For example, if energy storage capacitor C7 supplies 500V, 1 kV will be measured at the input of transformer T1 (e.g., by voltage doubling, as described above). The 1 kV at transformer T1 may be divided among the components of energy recovery circuit 110 when switch S6 is open. If the values ​​are appropriately selected (e.g., inductor L3 has a smaller inductance than the inductance of energy recovery inductor 115), the voltage across energy recovery diode 120 and energy recovery inductor 115 may be greater than 500V. Current may then flow through energy recovery diode 120 and / or charge energy storage capacitor C7. Current may also flow through diode D3 and inductor L6. Once energy storage capacitor C7 is charged, current may no longer flow through diode D3 and energy recovery inductor 115.

[0089] In some embodiments, the energy recovery circuit 110 may transfer energy (or charge) from the load stage 106, for example, on a fast time scale (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1000 ns, etc.). The stray resistance of the energy recovery circuit may be such that the pulse across the load stage 106 has a fast fall time t fThe stray resistance of the energy recovery circuit 110 may be low to ensure that the resistance is less than about 1 ohm, 100 mOhms, 10 mOhms, etc. In some embodiments, the resistive dissipation of energy from the load stage 106 may be low, such as less than about 60%, 70%, 80%, or 90%.

[0090] Any number of the components shown in FIG. 1 may or may not be required, such as diode 135 or diode 130 or inductor 140, for example.

[0091] In some embodiments, a diode may be placed between voltage source V1 and the point where energy recovery circuit 110 connects to voltage source V1 and / or energy storage capacitor C7. The diode may be positioned, for example, to allow current to flow from voltage source V1 to energy storage capacitor C7, but not to allow current to flow from the energy recovery circuit to energy storage capacitor C7.

[0092] FIG. 2 shows voltage and current waveforms within the nanosecond pulser system 100 shown in FIG. 1. Waveform 205 represents the voltage across the load stage 106 measured at a point labeled 124 (e.g., on the electrode) within the nanosecond pulser system 100. Waveform 220 represents the voltage at a point labeled 122 (e.g., on the wafer). Waveform 215 represents the current through the energy recovery inductor 115. Waveform 215 shows the current through the energy recovery inductor 115 when the nanosecond pulser stage 101 is turned on (e.g., as shown by the rising edge of the light blue waveform). When the nanosecond pulser stage 101 is turned off, the current through the energy recovery inductor 115 continues to rise to a maximum before falling. When the voltage across the energy recovery inductor 115 reaches zero, the current through the energy recovery inductor 115 should stop, but in this example, the nanosecond pulser stage 101 turns on again before the voltage across the energy recovery inductor 115 reaches zero.

[0093] In some embodiments, although the potential at point labeled 121 in FIG. 1 is shown as negative, the chucking potential can also be positive.

[0094] 3 is a circuit diagram of a nanosecond pulser system 300 including a nanosecond pulser stage 101 with an active energy recovery circuit 111 having an energy recovery switch S5 according to some embodiments. The energy recovery switch S5 may be switched based on signals from a controller labeled Sig5+ and Sig5-.

[0095] 3, the active energy recovery circuit 111 may include an energy recovery switch S5 that can be used to control the flow of current through the energy recovery inductor 115. In some embodiments, the energy recovery switch S5 may include a freewheeling diode disposed across the energy recovery switch. The energy recovery switch S5 may be disposed in series with the energy recovery inductor 115, for example. In some embodiments, the energy recovery switch S5 may be opened or closed based on a signal from a switching input V5. In some embodiments, the switching input V5 may close the energy recovery switch when switch S1 is open and / or is no longer pulsing, allowing current to flow back from the load stage 106 to the high-voltage load C7. In some embodiments, the switching input V5 may open the energy recovery switch when switch S1 is closed and / or is pulsing, preventing current from flowing to the high-voltage load C7.

[0096] 3 is shown in series with the energy recovery diode 120 and the energy recovery inductor 115 and is disposed between the secondary side of the transformer T1 and both the energy recovery diode 120 and the energy recovery inductor 115. In some embodiments, both the energy recovery diode 120 and the energy recovery inductor 115 may be disposed between the energy recovery switch S5 and the secondary side of the transformer T1. In some embodiments, the energy recovery switch S5 may be disposed between the energy recovery diode 120 and the energy recovery inductor 115. The energy recovery diode 120, the energy recovery inductor 115, and the energy recovery switch S5 may be disposed in any order.

[0097] Energy recovery switch S5 may include a high voltage switch, such as high voltage switch 1400, for example.

[0098] In some embodiments, the load stage 106 may be charged by the nanosecond pulser stage 101 while the energy recovery switch S5 is open. For example, it may be beneficial to remove charge from the load stage 106, such as on a fast time scale (e.g., less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1000 ns, etc.). To remove charge from the load stage 106, the energy recovery switch S5 may be closed.

[0099] FIG. 4 is a circuit diagram of a nanosecond pulser system 400 including a passive bias compensation circuit 114 along with an energy recovery circuit 110, according to some embodiments.

[0100] In this example, the passive bias compensation circuit 114 is a passive bias compensation circuit and may include a bias compensation diode 405 and a bias compensation capacitor 410. The bias compensation diode 405 may be placed in series with the offset supply voltage V5. The bias compensation capacitor 410 may be placed across either or both of the offset supply voltage V5 and resistor R2. The bias compensation capacitor 410 may have a capacitance between 100 nF and less than 100 μF, for example, about 100 μF, 50 μF, 25 μF, 10 μF, 2 μF, 500 nF, or 200 nF.

[0101] In some embodiments, bias compensation diode 405 can conduct currents between 10 A and 1 kA at frequencies between 10 Hz and 500 kHz.

[0102] In some embodiments, bias capacitor C12 can allow for a voltage offset between the output of nanosecond pulser stage 101 (e.g., position labeled 125) and the voltage on the electrode (e.g., position labeled 124). In operation, the electrode may be at, for example, a DC voltage of −2 kV during a burst (a burst may include multiple pulses), while the output of the nanosecond pulser alternates between +6 kV during a pulse and 0 kV between pulses.

[0103] The bias capacitor C12 may be, for example, 100 nF, 10 nF, 1 nF, 100 μF, 10 μF, 1 μF, etc. Resistor R2 may have a high resistance, for example, a resistance value on the order of about 1 kOhm, 10 kOhm, 100 kOhm, 1 Mohm, 10 Mohm, 100 Mohm, or the like.

[0104] In some embodiments, bias compensation capacitor 410 and bias compensation diode 405 can allow a voltage offset between the output of nanosecond pulser stage 101 (e.g., labeled 125) and the voltage on the electrode (e.g., labeled 124) to be established and reach a required equilibrium at the beginning of each burst. For example, charge is transferred from capacitor C12 to bias compensation capacitor 410 at the beginning of each burst over a number of pulses (e.g., on the order of about 5-100 pulses) to establish the correct voltage in the circuit.

[0105] In some embodiments, the pulse repetition frequency (e.g., the frequency of the pulses within a burst) may be between 200 kHz and 800 MHz, such as 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 80 MHz. In some embodiments, the burst repetition frequency (e.g., the frequency of the burst) may be about 10 kHz, 50 Hz, 100 kHz, 500 kHz, 1 MHz, etc., such as 400 kHz.

[0106] The energy recovery circuit 110 may or may not include an energy recovery switch, as shown in FIG.

[0107] FIG. 5 is a circuit diagram of a nanosecond pulser system 500 including an active bias compensation circuit 134 along with an energy recovery circuit 110, according to some embodiments.

[0108] The active bias compensation circuit 134 may include any bias and / or bias compensation circuit known in the art. For example, the active bias compensation circuit 134 may include any bias and / or bias compensation circuit described in U.S. patent application Ser. No. 16 / 523,840, entitled "NANOSECOND PULSER BIAS COMPENSATION," which is incorporated herein in its entirety for all purposes.

[0109] In some embodiments, the active bias compensation circuit 134 of the nanosecond pulser system 500 shown in FIG. 5 may include a bias capacitor C7, a blocking capacitor C12, a blocking diode D8, a bias compensation switch S8 (e.g., a high voltage switch), an offset supply voltage V5, a resistor R2, and / or a resistor R4. In some embodiments, switch S8 may include a high voltage switch, such as high voltage switch 1400 shown in FIG. 14. The bias compensation switch S8 may be switched based on signals from a controller labeled Sig8+ and Sig8−.

[0110] In some embodiments, the offset supply voltage V5 may include a DC voltage source capable of biasing the output voltage either positively or negatively. In some embodiments, capacitor C12 may isolate / isolate the offset supply voltage V5 from other circuit elements. In some embodiments, the active bias compensation circuit 134 may allow for potential shifting of power from one part of the circuit to another. In some embodiments, the active bias compensation circuit 134 may be used to maintain a constant chucking force between the process wafer and the electrostatic chuck. Resistor R2 may, for example, protect / isolate the DC bias supply from the driver. As another example, resistor R2 may be used to protect the DC power supply V5 from overcurrent faults.

[0111] In some embodiments, bias compensation switch S8 may be open while nanosecond pulser stage 101 is not actively generating pulses above 10 kHz or providing bursts of pulses, and may be closed when nanosecond pulser stage 101 is not pulsing. While closed, bias compensation switch S8 may allow current in a direction that would otherwise be blocked by blocking diode D8, for example. By shunting this current, the bias between the wafer and the chuck may be less than 2 kV, which may be within an acceptable range.

[0112] In some embodiments, the load stage 106 may be coupled to an active bias compensation circuit 134. In some embodiments, the energy recovery circuit 110 may or may not include an energy recovery switch, as shown in FIG.

[0113] FIG. 6 is a circuit diagram of a nanosecond pulser system 600 including an active bias compensation circuit 134 with an active energy recovery circuit 111, according to some embodiments.

[0114] FIG. 7 is a circuit diagram of a matchless driver system 700 including an RF driver 705, an active bias compensation circuit 134, and an energy recovery circuit 110, according to some embodiments.

[0115] In this example, the matchless driver system 700 may include an RF driver 705 instead of the nanosecond pulser stage 101. The RF driver 705 may be, for example, a half-bridge driver or a full-bridge driver. The RF driver 705 may include a voltage source V1, which may be a DC voltage source (e.g., a capacitive source, an AC / DC converter, etc.). In some embodiments, the RF driver 705 may include four switches S1, S2, S3, and S4. In some embodiments, the RF driver 705 may include multiple switches S1, S2, S3, and S4 arranged in series or parallel. These switches S1, S2, S3, and S4 may include any type of solid-state switch, such as, for example, an IGBT, a MOSFET, a SiC-MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc. These switches S1, S2, S3, and S4 may be switched at a high frequency and / or generate high voltage pulses. These frequencies may include, for example, frequencies of approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, and the like.

[0116] Each of switches S1, S2, S3, and S4 may be coupled in parallel with a respective diode D1, D2, D3, and D4, and may include stray inductances represented by inductors L1, L2, L3, and L4. In some embodiments, the inductances of inductors L1, L2, L3, and L4 may be equal. In some embodiments, the inductances of inductors L1, L2, L3, and L4 may be less than approximately 50 nH, 100 nH, 150 nH, 500 nH, 1000 nH, etc. The combination of a switch (S1, S2, S3, or S4) and a respective diode (D1, D2, D3, or D4) may be coupled in series with the respective inductor (L1, L2, L3, or L4). Inductors L3 and L4 are connected to ground. Inductor L1 is connected to switch S4 and resonant circuit 710. And, inductor L2 is connected to switch S3 and the other side of resonant circuit 710.

[0117] Switches S1, S2, S3, and S4 may include high voltage switches, such as high voltage switch 1400 shown in FIG.

[0118] In some embodiments, the RF driver 705 may be coupled to a resonant circuit 710. The resonant circuit 710 may include a resonant inductor L5 and / or a resonant capacitor C2 coupled to a transformer T1. The resonant circuit 710 may include a resonant resistor R5, which may include, for example, stray resistance of any leads between the RF driver 705 and the resonant circuit 710 and / or any components in the resonant circuit 710, such as the transformer T1, the capacitor C2, and / or the inductor L5. In some embodiments, the resonant resistor R5 includes only stray resistance of wires, traces, or circuit elements. While the inductance and capacitance of other circuit elements may affect the drive frequency, the drive frequency can be largely set by the selection of the resonant inductor L5 and / or the resonant capacitor C2. Further refinement and / or adjustment may be required to achieve an appropriate drive frequency taking into account stray inductance and capacitance. Additionally, the rise time of the transformer T1 can be adjusted by changing L5 and / or C2, provided the following conditions are met:

number

[0119] In some embodiments, a larger inductance value for L5 may result in a slower or shorter rise time. These values ​​may also affect the burst envelope. As shown in Figure 17, each burst may include a transient pulse and a steady pulse. The transient pulse within each burst may be set by L5 and / or the Q of the system until the full voltage is reached during the steady pulse.

[0120] The switch in the RF driver 705 adjusts the resonant frequency, f resonant When switched at , the output voltage at transformer T1 is amplified. In some embodiments, the resonant frequency may be approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0121] In some embodiments, resonant capacitor C2 may include the stray capacitance of transformer T1 and / or a physical capacitor. In some embodiments, resonant capacitor C2 may have a capacitance of approximately 10 μF, 1 μF, 100 nF, 10 nF, etc. In some embodiments, resonant inductor L5 may include the stray inductance of transformer T1 and / or a physical inductor. In some embodiments, resonant inductor L5 may have an inductance of approximately 50 nH, 100 nH, 150 nH, 500 nH, 1000 nH, etc. In some embodiments, resonant resistor R5 may have a resistance of approximately 10 ohms, 25 ohms, 50 ohms, 100 ohms, 150 ohms, 500 ohms, etc.

[0122] In some embodiments, resonant resistor R5 may represent the stray resistance of wires, traces, and / or transformer windings in a physical circuit, and may have a resistance of approximately 10 mOhms, 50 mOhms, 100 mOhms, 200 mOhms, 500 mOhms, etc.

[0123] In some embodiments, transformer T1 may comprise a transformer such as that disclosed in U.S. Patent Application No. 15 / 365,094, entitled "High Voltage Transformer," which is incorporated herein for all purposes. In some embodiments, the output voltage of resonant circuit 710 may be changed by changing the duty cycle (e.g., the "on" time or the time the switches are conducting) of switches S1, S2, S3, and / or S4. For example, a longer duty cycle results in a higher output voltage, and a shorter duty cycle results in a lower output voltage. In some embodiments, the output voltage of resonant circuit 710 may be changed or adjusted by adjusting the duty cycle of switching in RF driver 705.

[0124] For example, the duty cycle of the switches can be adjusted by changing the duty cycle of signal Sig1 that opens or closes switch S1, changing the duty cycle of signal Sig2 that opens or closes switch S6, changing the duty cycle of signal Sig3 that opens or closes switch S3, and changing the duty cycle of signal Sig4 that opens or closes switch S4. Adjusting the duty cycle of switches S1, S2, S3, or S4 can, for example, control the output voltage of resonant circuit 710.

[0125] In some embodiments, each switch S1, S2, S3, or S4 of resonant circuit 710 may be switched independently or in conjunction with one or more other switches. For example, signal Sig1 may be the same signal as signal Sig3. As another example, signal Sig2 may be the same signal as signal Sig4. As another example, each signal may be independent, and each switch S1, S2, S3, or S4 may be controlled independently or separately.

[0126] In some embodiments, the resonant circuit 710 may be coupled to a half-wave rectifier 715, which may include a blocking diode D7.

[0127] The active bias compensation circuit 134 may include the active bias compensation circuit described in conjunction with FIG.

[0128] The matchless driver system 700 does not include a conventional matching network, such as a 50 ohm matching network, an external matching network, or a stand-alone matching network. In some embodiments, the matchless driver system 700 does not require a 50 ohm matching network to adjust the switching power applied to the wafer chamber. In some embodiments, the matchless driver system 700 can include a variable output impedance RF generator without a conventional matching network, allowing for rapid changes in the power drawn by the plasma chamber. Typically, this adjustment of the matching network takes at least 100 μs to 200 μs. In some embodiments, the change in power can occur within one or two RF cycles, e.g., 2.5 μs to 5.0 μs at 400 kHz.

[0129] In this example, the energy recovery circuit 110 may be disposed on or electrically coupled to the secondary side of the transformer T1. The energy recovery circuit 110 may include, for example, a diode 130 (e.g., a crowbar diode) across the secondary side of the transformer T1. The energy recovery circuit 110 may include, for example, an energy recovery diode 120 and an energy recovery inductor 115 (arranged in series) to allow current to flow from the secondary side of the transformer T1 to charge the energy storage capacitor C7 and to allow current to flow to the load stage 106. The energy recovery diode 120 and the energy recovery inductor 115 may be electrically connected to the secondary side of the transformer T1 and coupled to the energy storage capacitor C7. In some embodiments, the energy recovery circuit 110 may include the diode 130 and / or the inductor 140 electrically coupled to the secondary side of the transformer T1. The energy recovery inductor 115 may represent and / or include stray inductance of the transformer T1.

[0130] When the nanosecond pulser is turned on, current may charge a capacitor in the load stage 106 (e.g., charging capacitor C3, capacitor C2, or capacitor C9). Some current may flow through the energy recovery inductor 115, for example, when the voltage on the secondary side of transformer T1 rises above the charging voltage of energy storage capacitor C7. When the nanosecond pulser is turned off, current may flow from a capacitor in the load stage 106 (e.g., capacitor C1) through the energy recovery inductor 115 to charge energy storage capacitor C7 until the voltage across the energy recovery inductor 115 becomes zero. Diode 130 may prevent the capacitor in the load stage 106 from ringing with the inductance in the load stage 106 or the active bias compensation circuit 134.

[0131] Energy recovery diode 120 may, for example, prevent charge from flowing from energy storage capacitor C7 to a capacitor within load stage 106.

[0132] The value of the energy recovery inductor 115 may be selected to control the current fall time, and in some embodiments, the energy recovery inductor 115 may have an inductance value between 1 μH and 500 μH.

[0133] In some embodiments, the energy recovery circuit 110 may include a switch that can be used to control the flow of current through the energy recovery inductor 115. The switch may be placed, for example, in series with the energy recovery inductor 115. In some embodiments, when switch S1 is open and / or is no longer pulsing, the switch may be closed to allow current to flow back from the load stage 106 to the energy storage capacitor C7.

[0134] The switches of the energy recovery circuit 110 may include, for example, a high voltage switch such as the high voltage switch 1400 shown in FIG.

[0135] 8 shows voltage and current waveforms within matchless driver system 700. Waveform 805 represents the voltage on the wafer measured at the location labeled 124 (e.g., on the electrode). Waveform 810 represents the voltage to load stage 106 measured at the location labeled 122 (e.g., on the wafer). Waveform 815 represents the current through energy recovery diode 120.

[0136] 9 is a schematic diagram of a spatially variable wafer bias system 900 according to some embodiments. The spatially variable wafer bias system 900 may include a first high voltage pulser 925 coupled to a first energy recovery circuit 926 and a second high voltage pulser 930 coupled to a second energy recovery circuit coupled to a plasma chamber 935. Either or both of the first energy recovery circuit 926 and the second energy recovery circuit 931 may include all or some of the components of the energy recovery circuit 110 or the active energy recovery circuit 111.

[0137] In this example, a first high-voltage pulser 925 is coupled to a first energy recovery circuit 926 and a first bias capacitor 915, and / or a second high-voltage pulser 930 is coupled to a second energy recovery circuit 931 and a second bias capacitor 921.

[0138] A first electrode 950 and a second electrode 955 may be disposed within the plasma chamber 935. In this example, the first electrode 950 is disk-shaped and is disposed within a central opening of the second electrode 955. A first high-voltage pulser 925 is electrically coupled to the first electrode 950, and a second high-voltage pulser 930 is electrically coupled to the second electrode 955. In some embodiments, a stray coupling capacitance 965 may exist between the first high-voltage pulser 925 and the second high-voltage pulser 930. The stray coupling capacitance 965 may be, for example, less than about 100 pF, about 1 nF, or about 10 nF.

[0139] In some embodiments, either or both of the first high voltage pulser 925 and the second high voltage pulser 930 may be coupled to a bias circuit, such as, for example, the DC bias circuit 104, the passive bias compensation circuit 114, or the active bias compensation circuit 134.

[0140] In some embodiments, the energy storage capacitor C7 of the first nanosecond pulser 925 may be coupled to a first DC power supply, and the energy storage capacitor C7 of the second nanosecond pulser 930 may be coupled to a second DC power supply.

[0141] In some embodiments, the energy storage capacitor C7 of the first nanosecond pulser 925 and the energy storage capacitor C7 of the second nanosecond pulser 930 may be combined with a single DC power supply.

[0142] In some embodiments, both the first nanosecond pulser 925 and the second nanosecond pulser 930 may be coupled to the same energy storage capacitor, which may be coupled to a DC power source.

[0143] In some embodiments, switch S6 may be turned on for a different period of time than switch S7. The amount of time the switches are closed may correspond to the voltages applied to the respective electrodes. Each switch may be turned on for a different period of time to provide different voltages to different electrodes.

[0144] Either or both of the first nanosecond pulser 925 and the second nanosecond pulser 930 may include a passive bias compensation circuit 114 , an active bias compensation circuit 134 , or a DC bias circuit 104 .

[0145] FIG. 10 is a circuit diagram of a nanosecond pulser system 1000 with an energy recovery circuit 110 according to some embodiments. In this example, the nanosecond pulser system 1005 is similar to the nanosecond pulser system 100, except that the nanosecond pulser stage 101 switches the other polarity of the energy storage capacitor C7. When switch S6 is open, the charge on capacitor C1 can flow through the energy recovery circuit 110 to charge the high-voltage energy storage capacitor C7. When the charge on capacitor C1 becomes less than the charge on the high-voltage energy storage capacitor C7, no current flows through the energy recovery circuit 110. In some embodiments, the DC bias circuit 104 may be replaced with a passive bias compensation circuit 114 or an active bias compensation circuit 134. In some embodiments, the energy recovery circuit 110 may be replaced with an active energy recovery circuit 111.

[0146] In some embodiments, a nanosecond pulser (or switch) is included to switch the ground side (see, e.g., FIG. 1) or the positive side of power supply V1 and / or C7 (see, e.g., FIG. 10). Either arrangement may be used. Figures showing one arrangement may be interchangeable with the other arrangement.

[0147] FIG. 11 illustrates voltage and current waveforms within the nanosecond pulser system 1000 shown in FIG. 10. Waveform 1105 represents the current through the energy recovery inductor 115. Waveform 1110 represents the voltage to the load stage 106 measured at location label 124 (e.g., on the electrode). Waveform 1115 represents the wafer voltage measured at the location labeled 122 (e.g., on the wafer). As shown, when the pulse is turned off, current flows through the energy recovery inductor 115, which charges the high-voltage energy storage capacitor C7. In this example, the capacitive load is 500 pF and the energy recovery inductor 115 is 10 μH.

[0148] 12 is a circuit diagram of a nanosecond pulser system 1200 in which the energy recovery circuit 110 drives a capacitive load 1205, according to some embodiments. In this example, the nanosecond pulser system 1200 is similar to the nanosecond pulser system 100 without the DC bias circuit 104, and is driving the capacitive load 1205. The capacitive load 1205 may include any type of load, such as a plasma load, multiple grids, multiple electrodes, etc.

[0149] Figure 13 shows the voltage and current waveforms within the nanosecond pulser system 1200 shown in Figure 12. Waveform 1305 represents the voltage across the capacitive load 1205, and waveform 1310 represents the current through the energy recovery inductor 115. As shown, when the pulse is turned off, current flows through the energy recovery inductor 115, charging the high-voltage energy storage capacitor C7. In this example, the load C1 is 500 pF and the energy recovery inductor 115 is 10 μH.

[0150] 14 is a block diagram of a high-voltage switch 1400 with isolated power, according to some embodiments. The high-voltage switch 1400 may include multiple switch modules 1405 (collectively or individually 1405, and individually 1405A, 1405B, 1405C, and 1405D) capable of switching voltage from a high-voltage source 1460 with fast rise times and / or high frequencies and / or variable pulse widths. Each switch module 1405 may include a switch 1410, such as, for example, a solid-state switch.

[0151] In some embodiments, the switch 1410 may be electrically coupled to a gate driver circuit 1430, which may include a power supply 1440 and / or an isolated fiber trigger 1445 (also referred to as a gate trigger or switch trigger). For example, the switch 1410 may include a collector, an emitter, and a gate (or a drain, a source, and a gate), and the power supply 1440 may drive the gate of the switch 1410 via the gate driver circuit 1430. The gate driver circuit 1430 may be separate from other components of the high-voltage switch 1400, for example.

[0152] In some embodiments, the power supply 1440 may be isolated using, for example, an isolation transformer. The isolation transformer may include a low-capacitance transformer. The low capacitance of the isolation transformer may, for example, allow the power supply 1440 to charge on a fast time scale without requiring a large current. The isolation transformer may have, for example, a capacitance of less than about 100 pF. As another example, the isolation transformer may have a capacitance of less than about 30-100 pF. In some embodiments, the isolation transformer may provide voltage isolation up to 1 kV, 5 kV, 10 kV, 25 kV, 50 kV, etc.

[0153] In some embodiments, the isolation transformer may have low stray capacitance. For example, the isolation transformer may have a stray capacitance of less than about 1000 pF, 100 pF, 10 pF, etc. In some embodiments, the low capacitance may minimize electrical coupling to low-voltage components (e.g., sources of input control power) and / or reduce EMI generation (e.g., electrical noise generation). In some embodiments, the transformer stray capacitance of the isolation transformer may include the capacitance measured between the primary and secondary windings.

[0154] In some embodiments, the isolation transformer may be a DC / DC converter or an AC / DC transformer. In some embodiments, the transformer may include, for example, a 110V AC transformer. In either case, the isolation transformer may provide power that is isolated from other components within the high voltage switch 1400. In some embodiments, the isolation may be galvanic, such that conductors on the primary side of the isolation transformer do not pass through or contact any conductors on the secondary side of the isolation transformer.

[0155] In some embodiments, the transformer may include a primary winding tightly wound or wound around a transformer core. In some embodiments, the primary winding may include a conductive sheet wrapped around the transformer core. In some embodiments, the primary winding may include one or more windings.

[0156] In some embodiments, the secondary winding may be wound on the core as far away from the core as possible. For example, the bundle of windings making up the secondary winding may be wound through the center of the opening in the transformer core. In some embodiments, the secondary winding may include one or more windings. In some embodiments, the bundle of windings making up the secondary winding may have a cross-section that is, for example, circular or square, to minimize stray capacitance. In some embodiments, insulation (e.g., oil or air) may be disposed between the primary winding, the secondary winding, or the transformer core.

[0157] In some embodiments, keeping the secondary winding away from the transformer core may have several advantages. For example, stray capacitance between the isolation transformer primary and the isolation transformer secondary may be reduced. As another example, a high voltage standoff between the isolation transformer primary and the isolation transformer secondary may be allowed for to prevent corona and / or breakdown from forming during operation.

[0158] In some embodiments, the spacing between the isolation transformer primary side (e.g., primary winding) and the isolation transformer secondary side (e.g., secondary winding) can be approximately 0.1 inches, 0.5 inches, 1 inch, 5 inches, or 10 inches. In some embodiments, a typical spacing between the isolation transformer core and the isolation transformer secondary side (e.g., secondary winding) can be approximately 0.1 inches, 0.5 inches, 1 inch, 5 inches, or 10 inches. In some embodiments, the gap between the windings may be filled with the lowest possible dielectric material, such as, for example, vacuum, air, any insulating gas or liquid, or a solid material with a dielectric constant less than 3.

[0159] In some embodiments, power supply 1440 may include any type of power supply capable of providing high voltage standoff (isolation) or having low capacitance (e.g., less than about 1000 pF, 100 pF, 10 pF, etc.) In some embodiments, the controlled voltage power supply may provide 1420 V AC or 240 V AC at 60 Hz.

[0160] In some embodiments, each power supply 1440 may be inductively electrically coupled to a single controlled voltage power supply. For example, power supply 1440A may be electrically coupled to the power supply through a first transformer, power supply 1440B may be electrically coupled to the power supply through a second transformer, power supply 1440C may be electrically coupled to the power supply through a third transformer, and power supply 1440D may be electrically coupled to the power supply through a fourth transformer. For example, any type of transformer capable of providing voltage isolation between the various power supplies may be used.

[0161] In some embodiments, the first transformer, the second transformer, the third transformer, and the fourth transformer may include different secondary windings around a single transformer core. For example, the first transformer may include a first secondary winding, the second transformer may include a second secondary winding, the third transformer may include a third secondary winding, and the fourth transformer may include a fourth secondary winding. Each of these secondary windings may be wound on a single transformer core. In some embodiments, the first secondary winding, the second secondary winding, the third secondary winding, the fourth secondary winding, or the primary winding may include a single winding or multiple windings wound around a transformer core.

[0162] In some embodiments, power supply 1440A, power supply 1440B, power supply 1440C, and / or power supply 1440D may not share a return reference ground or a local ground.

[0163] For example, the isolated fiber trigger 1445 may be isolated from other components of the high voltage switch 1400. The isolated fiber trigger 1445 may include a fiber optic receiver that allows each switch module 1405 to float relative to other switch modules 1405 and / or other components of the high voltage switch 1400, while still allowing active control of the gates of each switch module 1405, for example.

[0164] In some embodiments, for example, the return reference ground or local ground or common ground of each switch module 1405 may be isolated from one another using, for example, an isolation transformer.

[0165] By electrically isolating each switch module 1405 from a common ground, for example, multiple switches can be placed in a series configuration for cumulative high voltage switching. In some embodiments, some delay in the timing of the switch modules can be tolerated or designed in. For example, each switch module 1405 may be configured or rated to switch 1 kV, the switch modules may be electrically isolated from each other, and / or the timing of closing each switch module 1405 need not be perfectly synchronized for a period defined by the capacitance of the snubber capacitor and / or the voltage rating of the switch.

[0166] In some embodiments, electrical isolation can provide many advantages. For example, one possible advantage may include minimizing jitter between switches and / or allowing for arbitrary switch timing. For example, each switch 1410 may have a switch transition jitter of less than about 500 ns, 50 ns, 20 ns, 5 ns, etc.

[0167] In some embodiments, electrical isolation between two components (or circuits) may mean a very high resistance between the two components and / or may mean a small capacitance between the two components.

[0168] Each switch 1410 may include any type of solid-state switch device, such as, for example, an IGBT, a MOSFET, a SiC-MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc. The switches 1410 may be capable of switching high voltages (e.g., greater than about 1 kV) at high frequencies (e.g., 1 kHz or greater), at high speeds (e.g., repetition rates greater than about 500 kHz), and / or with fast rise times (e.g., rise times less than about 25 ns), and / or long pulse lengths (e.g., greater than about 10 ms). In some embodiments, each switch is designed to individually switch 1,200 V to 1,700 V, but can combine to switch 4,800 V to over 6,800 V (for four switches). Switches with various other voltage ratings may also be used.

[0169] There are several advantages to using a large number of low-voltage switches rather than a small number of high-voltage switches. For example, low-voltage switches generally have higher performance; they switch faster than high-voltage switches, have faster transition times, and potentially have higher switching efficiency. However, the larger the number of switches, the greater the need for precision in switch timing.

[0170] The high-voltage switch 1400 shown in Figure 14 includes four switch modules 1405. While four are shown in this figure, any number of switch modules 1405 may be used, e.g., 2, 8, 12, 16, 20, 24, etc. For example, if each switch in each switch module 1405 is rated at 1200V and 16 switches are used, the high-voltage switch can switch up to 19.2kV. As another example, if each switch in each switch module 1405 is rated at 1700V and 16 switches are used, the high-voltage switch can switch up to 27.2kV.

[0171] In some embodiments, the high voltage switch 1400 may switch voltages greater than 5 kV, 10 kV, 14 kV, 20 kV, 25 kV, and the like.

[0172] In some embodiments, the high-voltage switch 1400 may include a high-speed capacitor 1455. The high-speed capacitor 1455 may include, for example, one or more capacitors arranged in series and / or parallel. These capacitors may include, for example, one or more polypropylene capacitors. The high-speed capacitor 1455 may store energy from the high-voltage source 1460.

[0173] In some embodiments, high-speed capacitor 1455 may have a low capacitance, such as about 1 μF, about 5 μF, between about 1 μF and about 5 μF, between about 100 nF and about 1000 nF, or the like.

[0174] In some embodiments, the high-voltage switch 1400 may or may not include a crowbar diode 1450. The crowbar diode 1450 may include multiple diodes arranged in series or parallel, which may be useful, for example, for driving an inductive load. In some embodiments, the crowbar diode 1450 may include one or more Schottky diodes, such as silicon carbide Schottky diodes. The crowbar diode 1450 may, for example, sense whether the voltage from the switch of the high-voltage switch exceeds a certain threshold. If the threshold is exceeded, the crowbar diode 1450 may shunt power from the switch module to ground. The crowbar diode may, for example, allow an AC path to dissipate energy stored in an inductive load after switching. This may, for example, prevent large inductive voltage spikes. In some embodiments, the crowbar diode 1450 may have a low inductance, for example, 1 nH, 10 nH, 100 nH, or the like. In some embodiments, the crowbar diode 1450 may have a low capacitance, for example, 100 pF, 1 nF, 10 nF, 100 nF, etc.

[0175] In some embodiments, the crowbar diode 1450 may not be used, for example, if the load 1465 is primarily resistive.

[0176] In some embodiments, each gate driver circuit 1430 may generate jitter of less than about 1000 ns, 100 ns, 10.0 ns, 5.0 ns, 3.0 ns, 1.0 ns, etc. In some embodiments, each switch 1410 may have a minimum switch-on time (e.g., less than about 10 μs, 1 μs, 500 ns, 100 ns, 50 ns, 10.5 ns, etc.) and a maximum switch-on time (e.g., greater than 25 s, 10 s, 5 s, 1 s, 500 ms, etc.).

[0177] In some embodiments, during operation, each high voltage switch may be switched on and / or off within 1 ns of each other.

[0178] In some embodiments, each switch module 1405 may have the same or substantially the same (±5%) stray inductance. Stray inductance may include any inductance within the switch module 1405 that is not associated with inductors such as leads, diodes, resistors, switches 1410, and / or circuit board traces. The stray inductance within each switch module 1405 may include a low inductance, such as an inductance of less than about 300 nH, 100 nH, 10 nH, 1 nH, etc. The stray inductance between each switch module 1405 may include a low inductance, such as an inductance of less than about 300 nH, 100 nH, 10 nH, 1 nH, etc.

[0179] In some embodiments, each switch module 1405 may have the same or substantially the same (±5%) stray capacitance. The stray capacitance may include any capacitance within the switch module 1405 that is not associated with a capacitor, such as capacitance in leads, diodes, resistors, switches 1410, and / or circuit board traces. The stray capacitance within each switch module 1405 may include low capacitance, such as, for example, less than about 1000 pF, 100 pF, or 10 pF. The stray capacitance between each switch module 1405 may include low capacitance, such as, for example, less than about 1000 pF, 100 pF, or 10 pF.

[0180] Imperfections in voltage sharing can be addressed, for example, with passive snubber circuits (e.g., snubber diodes 1415, snubber capacitors 1420, and / or freewheeling diodes 1425). For example, slight differences in when each switch 1410 turns on or off, or differences in inductance or capacitance, can cause voltage spikes. These spikes can be mitigated by various snubber circuits (e.g., snubber diodes 1415, snubber capacitors 1420, and / or freewheeling diodes 1425).

[0181] The snubber circuit may include, for example, a snubber diode 1415, a snubber capacitor 1420, a snubber resistor 1416, and / or a freewheeling diode 1425. In some embodiments, the snubber circuit may be placed together in parallel with the switch 1410. In some embodiments, the snubber capacitor 1420 may have a low capacitance, such as, for example, a capacitance of less than about 100 pF.

[0182] In some embodiments, the high voltage switch 1400 may be electrically coupled to or include a load 1465 (e.g., a resistive, capacitive, or inductive load). The load 1465 may have a resistance of, for example, 50 ohms to 500 ohms. Alternatively or additionally, the load 1465 may be an inductive load or a capacitive load.

[0183] In some embodiments, the energy recovery circuit 110 or the active energy recovery circuit 111 can reduce the energy consumption of the high-voltage nanosecond pulser system and / or the voltage required to drive a given load at the same energy output capacity as a system without the energy recovery circuit. For example, for the same energy output capacity as a system without the energy recovery circuit, the energy consumption can be reduced by 10%, 15%, 20%, 25%, 30%, 40%, 45%, 50%, etc., or more.

[0184] In some embodiments, diode 130, diode 135, and / or energy recovery diode 120 may comprise high voltage diodes.

[0185] 15 is a block diagram of a process 1500 for operating a nanosecond pulser system with an active energy recovery circuit and an active bias compensation circuit, according to some embodiments. Process 1500 may include additional blocks. Blocks shown in process 1500 may be removed, replaced, skipped, or performed in any order.

[0186] Process 1500 may be performed, for example, using nanosecond pulser system 600 having active energy recovery circuit 111 and active bias compensation circuit 134 or similar circuitry.

[0187] In some embodiments, a nanosecond pulser may be used to generate multiple bursts, each burst containing multiple pulses. The pulses may be generated by switching the nanosecond pulser on and off. The pulse width of each pulse may vary, for example, from 10 seconds to 10 nanoseconds. The frequency of the pulses may vary, for example, from 10 kHz to 1 MHz, e.g., 400 kHz. Each burst may contain a set number of pulses. Each burst may have a burst width that defines the time to complete the multiple pulses.

[0188] Process 1500 may begin at block 1505 with initializing and setting a counter n to 1. Counter n counts the number of pulses in a given burst.

[0189] In block 1510, a bias compensation switch (eg, switch S8) may be opened.

[0190] At block 1515, a nanosecond pulser switch (eg, switch S6) may be closed.

[0191] In block 1520, the energy recovery switch (eg, switch S5) may be opened.

[0192] In some embodiments, blocks 1510, 1515, and 1520 may occur substantially simultaneously or within 10 ns or 100 ns, etc. In some embodiments, blocks 1515 and 1520 may occur substantially simultaneously.

[0193] At block 1525, process 1500 may pause (e.g., pulse) for a time that defines the pulse width of each pulse. In some embodiments, the pulse width of a pulse may define the voltage of the pulse at a load, such as a capacitive load, by defining the amount of time the load is charged to a particular voltage. The output voltage at a capacitive load generated by the pulse may depend, for example, on the amount of time the nanosecond pulser switch is closed and, therefore, on the amount of time the pulse charges the capacitive load. Thus, the output voltage at the load of the pulse may be defined by the voltage pause time to the maximum output voltage of the nanosecond pulser, or some multiple of the maximum output voltage of the nanosecond pulser if the pulse is applied to an inductor and / or capacitor that generates some voltage ring. The voltage pause may be, for example, from about 10 ns to about 500 ns, or from about 50 ns to about 200 ns, or 500 ns, 73.75 ns, 27 ns, 16 ns, or 12.5 ns.

[0194] At block 1530, a nanosecond pulser switch (eg, switch S6) may be opened.

[0195] In block 1535, an energy recovery switch (eg, switch S5) may be closed.

[0196] In some embodiments, blocks 1530 and 1535 may occur substantially simultaneously.

[0197] At block 1540, it may be determined whether counter n is equal to the desired number of pulses N. While there is no limit to the number of pulses in a burst, the desired number of pulses N may be, for example, between 5 and 1000. In some embodiments, the pulses may be performed continuously; thus, N may be nearly infinite. If counter n is not equal to the desired number of pulses N (i.e., fewer pulses than the desired number occurred in the burst), process 1500 proceeds to block 1545.

[0198] At block 1545, process 1500 may pause for a period of time that may, in part, define the pulse frequency (e.g., a pulse pause). For example, the duration of the pulse pause may be less than 500 ns, 250 ns, 100 ns, 50 ns, 10 ns, 5 ns, etc. The pulse pause period may include, for example, any duration.

[0199] At block 1550, counter n is incremented and the portion of process 1500 may repeat by proceeding to block 1515 to create additional pulses. If at block 1540 counter n is equal to the desired number of pulses N (i.e., the desired number of pulses has been created), process 1500 proceeds to block 1555. At block 1555, a bias compensation switch (e.g., switch S8) may be closed.

[0200] At block 1560, process 1500 pauses for a period defining the amount of time between bursts (e.g., burst pause). The period of the burst pause may be as small as 1 ms or as long as 20 seconds, for example. For example, the pulse pause may include a time between 2.5 microseconds (at a pulse frequency of 200 Hz) and 100 ms. As another example, the pulse pause may be from 10 ms to several hours. Any other period may be used. After the period has elapsed, process 1500 may return to block 1505, where counter n is initialized, and process 1500 may be repeated to produce additional bursts with additional pulses.

[0201] When the nanosecond pulser switch is closed, the energy recovery switch is open, and the bias compensation switch is open, a high voltage pulse (eg, greater than 1 kV) may be generated at circuit location 124 .

[0202] In some embodiments, the pulse pause period may be shorter than the burst pause period.

[0203] In some embodiments, blocks 1520 and 1535 may be eliminated from process 1500. In such embodiments, the energy recovery switch is not used, and a high voltage pulse (e.g., greater than 1 kV) may be generated at circuit location 124 when the nanosecond pulser switch is closed and the bias compensation switch is open.

[0204] In some embodiments, the blocks of process 1500 may be implemented using a controller (or processor), such as, for example, the computing system 1600 shown in Figure 16. The controller may communicate with, for example, switch S6 via Sig6+ and Sig6-, bias compensation switch S8 via Sig8+ and Sig8-, and / or energy recovery switch S5 via Sig5+ and Sig5-. The controller may provide signals to open and close the nanosecond pulser switch, the energy recovery switch, and / or the bias compensation switch.

[0205] The computing system 1600 shown in Figure 16 may be used to implement any of the embodiments of the present invention. For example, the computing system 1600 may be used to implement the process 1500. As another example, the computing system 1600 may be used to perform any of the calculations, identifications, and / or determinations described herein. The computing system 1600 includes hardware elements that may be electrically coupled via (or may communicate in other ways, as appropriate) a bus 1605. The hardware elements may include one or more processors 1610, including, without limitation, one or more general-purpose processors and / or one or more special-purpose processors (such as digital signal processing chips, graphics acceleration chips, and / or the like), one or more input devices 1615, including, without limitation, a mouse, keyboard, and / or the like, and one or more output devices 1620, including, without limitation, a display device, printer, and / or the like.

[0206] Computing system 1600 may further include (and / or communicate with) one or more storage devices 1625, which may include, but are not limited to, local and / or network-accessible storage and / or solid-state storage devices, such as, but not limited to, disk drives, drive arrays, optical storage devices, random access memory (“RAM”) and / or read-only memory (“ROM”), which may be programmable, flash-updateable, and / or the like. Computing system 1600 may include a communications subsystem 1630, which may include, without limitation, a modem, a network card (wireless or wired), an infrared communications device, a wireless communications device and / or chipset (such as a Bluetooth device, an 802.6 device, a Wi-Fi device, a WiMax device, a cellular communications facility, etc.), and / or the like. Communications subsystem 1630 may enable data exchange with a network (such as the networks described below, by way of example) and / or any other device described herein. In many embodiments, the computing system 1600 will further include a working memory 1635, which may include a RAM or ROM device, as described above.

[0207] Computing system 1600 may also include software elements shown as currently residing in working memory 1635, including other code, such as an operating system 1640 and / or one or more application programs 1645, which may include computer programs of the present invention and / or may be designed to implement methods of the present invention and / or configure systems of the present invention, as described herein. For example, one or more of the procedures described with respect to the methods described above may be implemented as code and / or instructions executable by a computer (and / or a processor within a computer). Sets of these instructions and / or code may be stored on a computer-readable storage medium, such as storage device(s) 1625 described above.

[0208] In some cases, the storage medium may be incorporated within or in communication with computing system 1600. In other embodiments, the storage medium may be provided separately from computing system 1600 (e.g., on a removable medium such as a compact disc) and / or in an installation package, such that the storage medium can be used to program a general-purpose computer with the instructions / code stored thereon. These instructions may be in the form of executable code that can be executed by computing system 1600 and / or may be in the form of source and / or installable code that, when compiled and / or installed on computing system 1600 (e.g., using any of a variety of commonly available compilers, installation programs, compression / decompression utilities, etc.), is then in the form of executable code.

[0209] 17 is a schematic diagram of a spatially variable wafer bias system 1700 according to some embodiments. The spatially variable wafer bias system 1700 may include a first high-voltage pulser 1725, a second high-voltage pulser 1730, a first energy recovery circuit 1726, and a second energy recovery circuit 1731. Both the first energy recovery circuit 1726 and the second energy recovery circuit 1731 are coupled to a single energy storage capacitor C7. In some embodiments, the energy recovery circuit 1726 or the energy recovery circuit 1731 may each include one or more diodes and / or inductors coupled to the secondary side of the respective transformer. In some embodiments, the energy recovery circuit 1726 or the energy recovery circuit 1731 may include a switch (e.g., as described above) to allow current to flow through the energy recovery circuit after each pulse.

[0210] 18 is a circuit diagram of an RF driver system 1800 including an RF driver 1805, an active bias compensation circuit 134, and an energy recovery circuit 110, according to some embodiments. In this example, the RF driver system 1800 is similar to the Matchless RF system 700, with the RF driver 705 and resonant circuit 710 replaced by the RF driver 1805. The RF driver 705 shown in FIG. 7 includes a full-wave rectifier and the resonant circuit 710 replaced by the RF driver 1805.

[0211] In some embodiments, the RF driver 1805 may include multiple high frequency solid state switch(es), an RF generator, a tube-based RF generator, or a tube-based RF generator.

[0212] The RF driver system 1800 may not include a conventional matching network, such as a 50 ohm matching network, an external matching network, or a standalone matching network. In some embodiments, the RF driver system 1800 does not require a 50 ohm matching network to adjust the switching power applied to the wafer chamber. A conventional RF generator without a matching network can quickly change the power drawn by the plasma chamber. Typically, this adjustment of the matching network takes at least 100 μs to 200 μs. In some embodiments, the power change can occur within one or two RF cycles, such as 2.5 μs to 5.0 μs at 400 kHz.

[0213] In some embodiments, the RF driver 1805 may operate at frequencies such as approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, and the like.

[0214] Either or both of the first nanosecond pulser 1725 and the second nanosecond pulser 1730 may include a passive bias compensation circuit 114 , an active bias compensation circuit 134 , or a DC bias circuit 104 .

[0215] 19 is a circuit diagram of a nanosecond pulser system 1900 according to some embodiments. The nanosecond pulser system 1900 includes a nanosecond pulser 105, a primary sink 1906, a transformer T1, and a load stage 1915.

[0216] In some embodiments, the nanosecond pulser 105 may generate pulses with high pulse voltages (e.g., voltages greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), high frequencies (e.g., frequencies greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), fast rise times (e.g., rise times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1000 ns, etc.), fast fall times (e.g., fall times less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1000 ns, etc.), and / or short pulse widths (e.g., pulse widths less than about 1000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0217] For example, the nanosecond pulser 105 may include all or any portion of any device described in U.S. patent application Ser. No. 14 / 542,487, entitled "High Voltage Nanosecond Pulser," which is incorporated herein by reference for all purposes; or all or any portion of the device described in U.S. patent application Ser. No. 14 / 635,991, entitled "Galvanically Isolated Output Variable Pulse Generator Disclosure," which is incorporated herein by reference for all purposes; or all or any portion of the device described in U.S. patent application Ser. No. 14 / 798,154, entitled "High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency," which is incorporated herein by reference for all purposes.

[0218] In some embodiments, the nanosecond pulser 105 includes a switch S1 coupled to a power source C7 (e.g., an energy storage capacitor that may be coupled to the power source) that may provide a consistent DC voltage that is switched by the switch S1 and provides switched power to the transformer T1. The switch S1 may include one or more solid-state switches, such as, for example, an IGBT, a MOSFET, a SiC-MOSFET, a SiC junction transistor, a FET, a SiC switch, a GaN switch, a photoconductive switch, etc. In some embodiments, a gate resistor coupled to the switch S1 may be set with a short turn-on pulse.

[0219] In some embodiments, resistor R8 and / or resistor R5 may represent stray resistance within nanosecond pulser 105. In some embodiments, inductor L3 and / or inductor L1 may represent stray inductance within nanosecond pulser 105.

[0220] In some embodiments, the nanosecond pulser 105 may include a snubber circuit including both a snubber resistor R1 and a snubber inductor L3, which may be arranged in parallel with a snubber diode D2. The snubber circuit may also include a snubber capacitor C5. In some embodiments, the snubber resistor R1, the snubber inductor L3, and / or the snubber diode D2 may be arranged between the collector of the switch S1 and the primary winding of the transformer T1. The snubber diode D2 may be used to snub out overvoltages during switching. A large-capacity, high-speed capacitor C5 may be coupled to the emitter side of the switch S1. A freewheeling diode D1 may also be coupled to the emitter side of the switch S1. Various other components not shown may also be included.

[0221] In some embodiments, a freewheeling diode D1 may be used in combination with an inductive load to dissipate energy stored in the inductor after switch S1 is opened by forcing current to continue flowing in the same direction through the inductor, causing the energy to be dissipated in resistive elements in the circuit, which, if not used, could result in a large reverse voltage across switch S1, for example.

[0222] In some embodiments, primary sink 1906 may be arranged in parallel with switch S1 (and the snubber circuit). Primary sink 1906 may include, for example, a sink diode D6, a resistor R2, and a sink inductor L6 arranged in series. In some embodiments, resistor R2 may include one or more resistors having a resistance of approximately 100 ohms. In some embodiments, sink inductor L6 may include one or more inductors having an inductance of approximately 100 μH. In some embodiments, resistor R2 may include multiple resistors arranged in parallel and / or in series. In some embodiments, sink inductor L6 may comprise multiple inductors arranged in parallel and / or in series.

[0223] In some embodiments, sink diode D6 may be positioned to direct current from transformer T1 to ground.

[0224] In some embodiments, a sink diode D6, a resistor R2, and a sink inductor L6 are arranged in parallel with the transformer T1.

[0225] In some embodiments, resistor R2 and sink inductor L6 are located on the primary side of transformer T1.

[0226] The use of a primary sink to achieve high-frequency, high-voltage pulses with fast rise / fall times and / or short pulse widths may constrain the selection of circuit elements (e.g., R2 and L6) in the resistive output stage. The primary sink may be selected to accommodate high average power, high peak power, fast rise times, and / or fast fall times. For example, the average power rating may be greater than about 10 W, 50 W, 100 W, 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc.; the peak power rating may be greater than about 1 kW, 10 kW, 100 kW, 1 MW, etc.; and / or the rise and fall times may be less than 1000 ns, 100 ns, 10 ns, or 1 ns.

[0227] High average and / or peak power requirements can result from both the need to dissipate the energy stored in the load stage 1915 quickly and / or at a high frequency. For example, if the load stage 1915 is capacitive in nature (as shown in FIG. 1, with capacitance C12) and has a capacitance of 1 nF that requires discharging in 20 ns, and the primary sink can be purely resistive (e.g., a minimum value of L6), the primary sink may have a resistance of approximately 12.5 mOhms. If the high voltage pulses applied to the load are 20 kV and 100 ns long, each pulse must dissipate approximately 2 J during the 100 ns pulse width (e.g., E=t p V p 2 / R), dissipating an additional 0.2 J and draining stored energy from a 1 nF capacitive load (e.g., E =1 / 2t p CV s 2 ), in the formula, t p is the pulse width, V is the pulse voltage, R2 is the resistance of the primary sink, C is the capacitance of the load, and V p is the voltage on the primary side of the transformer, V S is the voltage on the transformer secondary and E is the energy. When operating at 10 kHz, the total energy dissipation per pulse will be 2.2 J and the average power dissipation into the primary sink will be 22 kW. The peak power loss in the primary sink during the pulse will be about 20 mW and can be calculated from Power=V2 / R.

[0228] High frequency and high voltage operation, combined with the need for low resistance in, for example, the primary sink, leads to instances where the peak and / or average power in the primary sink is high. Standard pull-down resistors (e.g., around 5 volts) used in TTL-type electrical circuits and data acquisition-type circuits typically operate at well below 1 W in both average and peak power dissipation.

[0229] In some embodiments, the ratio of power dissipated by primary sink 1906 compared to the total power dissipated by load stage 1915 may be, for example, 10%, 20%, 30%, or more. In typical low-voltage electronic circuits, pull-down resistors dissipate less than 1% of the power they consume, and typically much less.

[0230] The requirements for fast turn - on time and fast turn - off time can potentially impose constraints on both the stray inductance and stray capacitance within the primary sink. In the above example, in order to discharge a 1nF capacitive load in approximately 20ns, the series stray inductance within the primary sink needs to be within a range such as less than about 1000nH, 500nH, 300nH, 100nH, 30nH, etc. In some embodiments, L6 / R2 < tf. In some embodiments, the L / R time is, for example, less than 10% of the capacitive energy stored in the load capacitance, so that the primary sink does not waste significant additional energy due to its stray capacitance, and the stray capacitance of the primary sink may be less than 100pF. Since the primary sink requires high heat dissipation, it tends to be physically large, and it is difficult to achieve both this low stray inductance and stray capacitance. Generally, in this design, a number of discrete components (such as resistors, etc.) need to be used to perform a fair amount of parallel and series operations, and the components are closely grouped and away from the ground plane, which can significantly increase the stray capacitance.

[0231] In some embodiments, the load stage 1915 may include a dielectric barrier discharge device. The load stage 1915 in dielectric barrier discharge may be capacitance - dominant. In some embodiments, the load may be modeled as a purely capacitive load CL, for example, like dielectric barrier discharge. For example, when the power supply P is turned on, the capacitive load CL is charged, and when the power supply P is turned off, the charge of the capacitive load CL can be drained through the resistor R. Further, due to the requirements of high voltage and / or high frequency and / or fast turn - off time, the primary sink may need to rapidly discharge a significant amount of charge from the capacitive load CL, which may be different from the case of low - voltage applications (e.g., standard 5V logic levels and / or low - voltage data pulsers).

[0232] For example, a typical dielectric barrier discharge device may have a capacitance of about 10 pF and / or may be driven to about 20 kV with a rise time of about 20 ns and / or a fall time of about 20 ns. In some embodiments, the desired pulse width is 80 ns long. To match the fall time with the rise time, resistor R2 may be about 12.5 ohms to provide the desired fall time. Various other values ​​for circuit element resistor R2 may be used depending on the load and / or other circuit elements and / or the required rise time, fall time, and / or pulse width, etc.

[0233] In some embodiments, for a capacitive load, or a load with an effective capacitance C (e.g., capacitance C), the characteristic pulse fall time may be designated tf and the pulse rise time may be designated tr. In some embodiments, the rise time tr may be set by the specifications of the driving power supply. In some embodiments, the pulse fall time tf may be made to approximately match the pulse rise time tr by selecting resistor R2,

number

[0234] In some embodiments, the power dissipated in resistor R2 during a pulse having pulse width tp and drive voltage V is given by P=V2 / R. The fall time tf is determined by the resistance R (e.g.,

number

[0235] In some embodiments, resistor R2 may include a series and / or parallel stack of resistors having a desired resistance and power rating. In some embodiments, resistor R2 may include resistors having resistances less than about 2,000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 25 ohms, 10 ohms, 1 ohm, 0.5 ohms, 0.25 ohms, etc., and having average power ratings greater than about 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc., and having peak power ratings greater than about 1 kW, 10 kW, 100 kW, 1 MW, etc.

[0236] Using the example above, if tp=80 ns, V=500 kV, and resistor R2 is 12.5 kOhms, each pulse applied to the load can dissipate 16 mJ if the capacitance in the load is fully charged. When the pulse is turned off, the charge from the load is dissipated in resistor R2. When operated at 100 kHz, resistor R2 dissipates 1.6 kW. If resistor R2 were selected to produce a tf of 10 ns, the power dissipated in resistor R2 would be 3.2 kW. In some embodiments, the high voltage pulse width can extend up to 500 ns. With tf=20 ns at 500 ns, resistor R2 would dissipate 10 kW.

[0237] In some embodiments, the power dissipated in resistor R2 may be considered large if it exceeds 10% or 20% of the power consumed in load stage 1915.

[0238] If a fast fall time tf is required, the power dissipation can be large, for example, about one-third of the total power consumed. For example, if resistor R2 includes resistor R2 connected in series with sinking inductor L6, sinking inductor L6 can, for example, reduce the power flowing into resistor R while voltage V is present and / or speed up the fall time beyond the time set by RC damping.

[0239] For example, the time constant L6 / R2 can be set to be approximately the same as the pulse width tp, e.g., L6 / R2≈tp. This can, for example, reduce energy dissipation and / or shorten the fall time tf (e.g., decrease tf). In some embodiments, R2≈C / tf≈C / tr, assuming one wants tf to match tr. In this application, this disclosure, and / or claims, the symbol "≈" means within a factor of 10.

[0240] In some embodiments, the transformer T1 may be part of the nanosecond pulser 105.

[0241] 20 is a circuit diagram of a nanosecond pulser system 2000 according to some embodiments. The nanosecond pulser system 2000 includes a nanosecond pulser 105, a primary sink 2006, a transformer T1, and a load stage 1915.

[0242] In some embodiments, primary sink 2006 may include a sink switch S2 instead of or in addition to sink diode D6. In some embodiments, sink switch S2 may be placed in series with sink inductor L6 and / or sink resistor R2.

[0243] In some embodiments, sink switch S2 may be closed, for example, when load capacitance C2 is dumped through sink resistor R2 and / or sink inductor L6. For example, sink switch S2 may be switched on and / or off to dump charge from load capacitance C2 after each pulse. During each pulse, for example, sink switch S2 may be open. At the end of each pulse, sink switch S2 may be closed to dump the load capacitance into resistor R2. For example, sink switch S2 may be closed when switch S1 is open and / or open when switch S1 is closed.

[0244] In some embodiments, sink switch S2 may include high voltage switch 1400 described in FIG.

[0245] 21 is a circuit diagram of a nanosecond pulser system 2100, according to some embodiments. The nanosecond pulser system 2100 includes a nanosecond pulser 2105, a primary sink 2106, a transformer T1, and a load stage 1915.

[0246] In some embodiments, nanosecond pulser 2105 may include diode D9 positioned between sink switch S2 and primary sink 2106. Diode D9 may be positioned to allow current to flow through switch S1 toward transformer T1 and limit current flow from transformer T1 toward switch S1.

[0247] Primary sink 2106 may include the components of primary sink 1906 except for sink diode D6. In some embodiments, primary sink 2106 may include sink diode D6 and / or sink switch S2.

[0248] 22 is a circuit diagram of a nanosecond pulser system 2200 according to some embodiments. The nanosecond pulser system 2200 includes a nanosecond pulser 105, a primary sink 2206, a transformer T1, and a load stage 1915.

[0249] In some embodiments, primary sink 2206 may include a sink switch S2 and a sink diode D6. In some embodiments, sink switch S2 may be placed in series with sink inductor L6 and / or sink resistor R2. In some embodiments, a crowbar diode D8 may be included across sink switch S2.

[0250] In some embodiments, sink switch S2 may be closed, for example, when load capacitance C2 is dumped through sink resistor R2 and / or sink inductor L6. For example, sink switch S2 may be switched on and / or off to dump charge from load capacitance C2 after each pulse. During each pulse, for example, sink switch S2 may be open. Alternatively, sink switch S2 may be closed at the end of each pulse to dump the load capacitance into resistor R2. For example, sink switch S2 may be closed when switch S1 is open and / or open when switch S1 is closed.

[0251] FIG. 23 shows a waveform 2305 representing the voltage at the input to transformer T1 and a waveform 2310 representing the voltage at load stage 1915 when using nanosecond pulser system 2100 shown in FIG.

[0252] 24 illustrates a nanosecond pulser system 2400 according to some embodiments. The nanosecond pulser system 2400 includes the nanosecond pulser 105, the primary sink 1906, a transformer T1, a bias compensation circuit 2410, and a load stage 2415.

[0253] In some embodiments, bias compensation circuit 2410 may include a high-voltage switch S3 coupled across bias compensation diode D8 and arranged in series with offset power supply V1 and bias compensation resistor R9. In some embodiments, high-voltage switch S3 may include multiple switches arranged in series to collectively open and close the high voltage. For example, high-voltage switch S3 may include high-voltage switch 1400 described in FIG. 14. In some embodiments, high-voltage switch S3 may be opened or closed based on signals Sig3+ and Sig3−.

[0254] The high-voltage switch S3 may be coupled in series with either or both of an inductor L9 and a resistor R11. The inductor L9 may limit the peak current through the high-voltage switch S3. The inductor L9 may have an inductance of less than about 100 μH, such as, for example, about 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, or 1 μH. The resistor R11 may, for example, shift power losses to the primary sink. The resistor R11 may have a resistance of, for example, less than about 1000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 10 ohms, or the like.

[0255] In some embodiments, the high-voltage switch S3 may include a snubber circuit, which may include a resistor R9, a snubber diode D8, a snubber capacitor C15, and a snubber resistor R10.

[0256] In some embodiments, resistor R8 may represent a stray resistance of the offset power supply voltage V1. Resistor R8 may have a high resistance value, for example, about 10 kOhms, 100 kOhms, 1 MOhms, 10 MOhms, 100 MOhms, 1 GOhms, etc.

[0257] In some embodiments, bias compensation capacitor C8 may have a capacitance between 100 nF and less than 100 μF, such as, for example, about 100 μF, 50 μF, 25 μF, 10 μF, 2 μF, 500 nF, 200 nF, etc.

[0258] In some embodiments, bias compensation capacitor C8 and bias compensation diode D8 may allow a voltage offset between the output of nanosecond pulser 105 (e.g., labeled 125) and the voltage on the electrode (e.g., labeled 124) to be established and reach a required equilibrium at the beginning of each burst. For example, charge is transferred from capacitor C12 to capacitor C8 at the beginning of each burst over multiple pulses (e.g., about 5-100) to establish the correct voltage in the circuit.

[0259] In some embodiments, bias capacitor C12 may allow for a voltage offset between the output of nanosecond pulser 105 (e.g., labeled 125) and the voltage on the electrode (e.g., labeled 124). In operation, the electrode is at a DC voltage of, for example, −2 kV during the burst, while the output of the nanosecond pulser alternates between +6 kV during the pulse and 0 kV between pulses.

[0260] Bias capacitor C12 may have a capacitance on the order of, for example, 100 nF, 10 nF, 1 nF, 100 μF, 10 μF, or 1 μF. Resistor R9 may have a high resistance, for example, on the order of, for example, 1 kOhm, 10 kOhm, 100 kOhm, 1 MOhm, 10 MOhm, or 100 MOhm.

[0261] Bias compensation circuit 2410 may include any number of other elements or be arranged in any number of ways.

[0262] In some embodiments, high-voltage switch S3 may be open while nanosecond pulser 105 is pulsing and closed when nanosecond pulser 105 is not pulsing. When high-voltage switch S3 is closed, for example, current may short out bias compensation diode D8. By shorting this current, the bias between the wafer and the chuck may be less than 2 kV (or another voltage value), which may be within an acceptable range. In some embodiments, bias compensation diode D8 may conduct a current between 10 A and 1 kA at a frequency between 10 Hz and 10 kHz.

[0263] In some embodiments, the high voltage switch S3 may include the high voltage switch 1400 described in FIG.

[0264] In some embodiments, the load stage 2415 may represent an idealized or effective circuit of a semiconductor processing chamber, such as a plasma deposition tool, semiconductor manufacturing tool, plasma sputtering tool, etc. Capacitance C2 may represent, for example, the capacitance of a chuck on which the wafer rests. The chuck may include, for example, a dielectric material. For example, capacitor C1 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0265] Capacitor C3 may represent, for example, the sheath capacitance between the plasma and the wafer. Resistor R6 may represent, for example, the sheath resistance between the plasma and the wafer. Inductor L2 may represent, for example, the sheath inductance between the plasma and the wafer. Current source I2 may represent, for example, the ion current flowing through the sheath. For example, capacitor C1 or capacitor C3 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0266] Capacitor C9 may represent, for example, a capacitance in the plasma between the chamber wall and the top surface of the wafer. Resistor R7 may represent, for example, a resistance in the plasma between the chamber wall and the top surface of the wafer. Current source I1 may represent, for example, an ion current in the plasma. For example, capacitor C1 or capacitor C9 may have a small capacitance (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0267] As used herein, plasma voltage is the voltage measured from ground to circuit point 123, wafer voltage is the voltage measured from ground to circuit point 122 and may represent the voltage at the surface of the wafer, chucking voltage is the voltage measured from ground to circuit point 121, electrode voltage is the voltage measured from ground to circuit point 124, and input voltage is the voltage measured from ground to circuit point 125.

[0268] 25 illustrates a nanosecond pulser system 2500 according to some embodiments. The nanosecond pulser system 2500 includes a nanosecond pulser 105, a primary sink 2006, a transformer T1, a bias compensation circuit 2410, and a load stage 2415.

[0269] 26 illustrates a nanosecond pulser system 2600 according to some embodiments. The nanosecond pulser system 2600 includes a nanosecond pulser 2105, a primary sink 1906, a transformer T1, a bias compensation circuit 2410, and a load stage 2415.

[0270] 27 illustrates a nanosecond pulser system 2700 according to some embodiments. The nanosecond pulser system 2700 includes a nanosecond pulser 105, a primary sink 2206, a transformer T1, a bias compensation circuit 2410, and a load stage 2415.

[0271] FIG. 28 shows a waveform 2805 of the voltage at the input to transformer T1, a waveform 2810 of the voltage at the chuck (point labeled 121), and a waveform 2815 of the voltage at the wafer (point labeled 122) when using the nanosecond pulser system 2700.

[0272] Although in some embodiments the chucking potential is shown as negative, the chucking potential may be positive.

[0273] In some embodiments, primary sink 1906, primary sink 2006, or primary sink 2206 can reduce the energy consumption of the high voltage nanosecond pulser system and / or the voltage required to drive a given load. For example, energy consumption can be reduced by 10%, 15%, 20%, 25%, 30%, 40%, 45%, 50%, etc., or more.

[0274] In some embodiments, diode D9 and / or diode D6 may comprise high voltage diodes.

[0275] Unless otherwise specified, the term "substantially" means within 5% or 10% of the stated value, or within manufacturing tolerances. Unless otherwise specified, the term "about" means within 5% or 10% of the stated value, or within manufacturing tolerances.

[0276] The term "or" is inclusive.

[0277] Numerous specific details are described herein to provide a thorough understanding of claimed subject matter. However, those skilled in the art will understand that claimed subject matter may be practiced without these specific details. In other instances, methods, apparatuses, or systems known to those skilled in the art have not been described in detail so as not to obscure claimed subject matter.

[0278] Embodiments of the methods disclosed herein may be performed in operation of such a computing device. The order of the blocks presented in the above examples may be changed, e.g., the blocks may be reordered, combined, and / or divided into sub-blocks. Certain blocks or processes may be performed in parallel.

[0279] Use of "adapted to" or "configured to" herein is intended as open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0280] Furthermore, the use of "based on" is intended to be open and inclusive in the sense that a process, step, calculation, or other action that is "based on" one or more recited conditions or values ​​may in fact be based on additional conditions or values ​​other than the recited conditions or values. Headings, lists, and numbering provided herein are for ease of description and are not intended to be limiting.

[0281] While the subject matter of the present invention has been described in detail with reference to specific embodiments thereof, it will be understood that those skilled in the art, upon gaining the foregoing understanding, may readily make modifications, variations, and equivalents to such embodiments. Accordingly, it should be understood that the present disclosure has been presented for purposes of illustration and not limitation, and is not intended to exclude modifications, variations, and / or additions to the subject matter that would be readily apparent to those skilled in the art. [Explanation of symbols]

[0282] 100, 600, 1000, 1200, 2000, 2100, 2200, 2400, 2500, 2600, 2700 nanosecond pulser system 101 nanosecond pulsar stage 103 Lead Stage 104 DC bias circuit 106 Load Stages 110 Energy Recovery Circuit 111 Active Energy Recovery Circuit 114 Passive Bias Compensation Circuit 115 Energy Recovery Inductor 120 Energy Recovery Diode 130, 135 Diodes 134 Active bias compensation circuit 405 bias compensation diode 410 Bias compensation capacitor 700 Matchless Driver System 705 RF Driver 710 resonant circuit 900 Wafer Bias System 921 Second bias capacitor 925 High Voltage Pulser 926 First Energy Recovery Circuit 930 Second High-Voltage Pulser 931 Second Energy Recovery Circuit 935 Plasma Chamber 950 First electrode 955 Second electrode 1205 Capacitive load 1400 High Voltage Switch 1405 Switch Module 1410 Switch 1415 snubber diode 1420 snubber capacitor 1425 Freewheeling Diode 1440 Power supply 1445 Isolated Fiber Trigger 1450 Clover Diode 1600 Computing Systems 1625 Storage Device 1630 Communications Subsystem 1635 Working Memory 1640 Operating System 1645 Application Program 1700 Spatially Variable Wafer Bias System 1725 First high-voltage pulser 1726 First Energy Recovery Circuit 1730 Second High-Voltage Pulser 1731 Second Energy Recovery Circuit 1800 RF Driver System 1805 RF Driver 1906, 2006, 2106, 2206 Primary sink 1915, 2415 load stages 2105 nanosecond pulsar 2410 Bias Compensation Circuit C5 snubber capacitor C7 Energy Storage Capacitor C12 bias capacitor D2 Freewheeling diode D4 snubber diode D7 Blocking diode L1 stray inductance R1 floating resistor R3 snubber resistor R5 resonant resistance S1, S6 switches S5 Energy Recovery Switch T1 transformer

Claims

1. 1. A nanosecond pulser circuit, comprising: A high voltage power supply; a nanosecond pulser electrically coupled to the high voltage power supply for switching voltage from the high voltage power supply at a high frequency; a transformer having a primary side and a secondary side, the nanosecond pulser being electrically coupled to the primary side of the transformer; an energy recovery circuit electrically coupled to the secondary side of the transformer, the energy recovery circuit comprising: an energy recovery inductor electrically coupled to the high voltage power supply; a crowbar diode arranged in parallel with the secondary side of the transformer; a second diode disposed in series with the energy recovery inductor and positioned to conduct current from a load through the energy recovery inductor to the high voltage power supply.

2. 10. The nanosecond pulser circuit of claim 1, wherein said energy recovery inductor has an inductance greater than about 50 [mu]H.

3. 10. The nanosecond pulser circuit of claim 1, wherein said nanosecond pulser switches voltage from said high voltage power supply at a frequency of about 400 kHz.

4. 10. The nanosecond pulser circuit of claim 1, wherein the nanosecond pulser circuit delivers a voltage of greater than 5 kV to a load.

5. 2. The nanosecond pulser circuit of claim 1, wherein the load comprises a capacitive load.

6. 10. The nanosecond pulser circuit of claim 1, wherein the load comprises a plasma deposition chamber.

7. 2. The nanosecond pulser circuit of claim 1, wherein said energy recovery circuit further comprises a high voltage switch connected in series with said second diode and said energy recovery inductor.

8. 8. The nanosecond pulser circuit of claim 7, wherein said high voltage switch switches voltages in excess of 5 kV.

9. 2. The nanosecond pulser circuit of claim 1, wherein said high voltage power supply provides DC power at a voltage exceeding 1 kV.

10. A circuit comprising: A storage capacitor; a switching circuit connected to the storage capacitor, the switching circuit outputting a waveform with a voltage greater than 1 kV and a frequency greater than 1 kHz; a transformer having a primary side and a secondary side, the switching circuit being electrically coupled to the primary side of the transformer; an energy recovery circuit electrically coupled to the secondary side of the transformer and the storage capacitor, the energy recovery circuit comprising: an energy recovery inductor electrically coupled to the high voltage power supply; a second diode disposed in series with the energy recovery inductor and arranged to conduct current from a load through the energy recovery inductor to the high voltage power supply.

11. 11. The circuit of claim 10, wherein the energy recovery circuit comprises a crowbar diode disposed in parallel with the secondary side of the transformer.

12. The circuit of claim 10 wherein the switching circuit comprises a nanosecond pulser.

13. 11. The circuit of claim 10, wherein the switching circuit comprises an RF driver operating at a frequency greater than about 400 kHz.

14. 14. The circuit of claim 13, wherein the RF driver comprises either a half-bridge driver or a full-bridge driver.

15. 11. The circuit of claim 10, further comprising a bias compensation circuit, the bias compensation circuit including: a bias compensation diode arranged in parallel with the bias compensation switch; and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

16. 11. The circuit of claim 10, wherein the energy recovery inductor comprises an inductance greater than 50 μH.

17. A method for generating a high voltage pulse, comprising: with the pulser switch closed, opening a bias compensation switch in the bias compensation circuit to couple the bias compensation circuit to a secondary side of the transformer; generating a pulse with a pulser switch of a nanosecond pulser closed, the nanosecond pulser coupled to a primary side of a transformer and a DC power supply, the pulse having a voltage greater than 1 kV at a secondary side of the transformer; with the pulser switch closed, opening an energy recovery switch in an energy recovery circuit, the energy recovery circuit being coupled to the secondary side of the transformer and the DC power source; pausing for a period of less than about 100 nanoseconds; closing a pulser switch of the nanosecond pulser; and opening the energy recovery switch in the energy recovery circuit while closing the pulser switch.

18. 18. The method of claim 17, wherein the energy recovery circuit includes an inductor and a diode connected in series with the energy recovery switch.

19. 18. The method of generating high-voltage pulses of claim 17, wherein the energy recovery switch includes a plurality of switches having a plurality of voltage sharing resistors arranged in series, such that each voltage sharing resistor of the plurality of voltage sharing resistors is disposed across a corresponding one of the plurality of switches.

20. 18. The method of generating a high-voltage pulse according to claim 17, wherein the bias compensation circuit comprises a bias compensation diode arranged in parallel with the bias compensation switch, and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

21. A method for generating a high voltage pulse, comprising: before the burst of pulses, opening a bias compensation switch in a bias compensation circuit coupled to the nanosecond pulser through a transformer, the bias compensation circuit being coupled to a secondary side of the transformer; repeatedly opening and closing a pulser switch of a nanosecond pulser during the burst of pulses to generate a plurality of pulses within the burst of pulses, the nanosecond pulser being coupled to a primary side of the transformer and to a DC power source, the opening and closing of the pulser switch occurring at a pulse repetition frequency greater than about 1 kHz, and the closing of the pulser switch generating pulses of a voltage greater than 1 kV on a secondary side of the transformer; repeatedly opening and closing an energy recovery switch in an energy recovery circuit during the burst of pulses, closing the energy recovery switch when the pulser switch is open and opening the energy recovery switch when the pulser switch is closed, coupling the energy recovery circuit to the secondary side of the transformer and to the DC power source; and closing a bias compensation switch in the bias compensation circuit after the burst of pulses.

22. pausing for a period of less than about 100 microseconds; opening the bias correction switch prior to a second burst of pulses; opening and closing the pulser switch during the second burst of pulses; opening and closing the energy recovery switch during the second burst; 22. The method of claim 21, further comprising the step of: closing the bias correction switch after the second burst.

23. 22. The method of claim 21, wherein the energy recovery circuit includes an inductor and a diode connected in series with the energy recovery switch.

24. 22. The method of generating high-voltage pulses of claim 21, wherein the energy recovery switch includes a plurality of switches arranged in series and having a plurality of voltage sharing resistors, such that each voltage sharing resistor of the plurality of voltage sharing resistors is disposed across a corresponding one of the plurality of switches.

25. 22. The method of claim 21, wherein the bias compensation circuit includes a bias compensation diode arranged in parallel with the bias compensation switch, and a DC power supply arranged in series with the bias compensation diode and the bias compensation switch.

26. A method for generating a high voltage pulse, comprising: before a first burst of pulses, opening a bias compensation switch in a bias compensation circuit connected to the nanosecond pulser via a transformer, the bias compensation circuit being connected to a secondary side of the transformer; During the first burst of pulses, repeatedly opening and closing a pulser switch of a nanosecond pulser to generate a plurality of pulses within the burst of pulses, the nanosecond pulser being coupled to a primary side of the transformer and to a DC power source, the opening and closing of the pulser switch occurring at a pulse repetition frequency greater than about 1 kHz, and the closing of the pulser switch producing pulses of voltage greater than 1 kV on a secondary side of the transformer; closing a bias compensation switch in the bias compensation circuit after the burst of pulses; pausing for a period of less than about 100 microseconds; opening the bias compensation switch before a second burst of pulses; opening and closing the pulser switch during the second burst of pulses; and c. closing the bias correction switch after the second burst.

27. 27. The method of generating high voltage pulses of claim 26, further comprising the step of repeatedly opening and closing an energy recovery switch in the energy recovery circuit during the first burst of pulses such that an energy recovery switch closes when the pulser switch is open and an energy recovery switch opens when the pulser switch is closed, the energy recovery circuit being coupled to the secondary side of the transformer and the DC power source.

28. 28. The method of claim 27, further comprising opening and closing the energy recovery switch during the second burst of pulses.

29. A high voltage, high frequency switching circuit, a high voltage switching power supply that generates pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz; a transformer having a primary side and a secondary side; an output electrically coupled to the secondary side of the transformer; a primary sink electrically coupled to a primary side of the transformer and connected in parallel with the high voltage switching power supply, the primary sink including at least one resistor for discharging a load coupled to the output.

30. 30. The high voltage, high frequency switching circuit of claim 29, wherein the primary sink is configured to dissipate an average power greater than about 1 kilowatt.

31. 30. The high voltage, high frequency switching circuit of claim 29, wherein the primary sink comprises at least one inductor connected in series with the at least one resistor.

32. 30. The high voltage, high frequency switching circuit of claim 29, wherein the primary sink includes a switch connected in series with the at least one resistor.

33. 30. The high voltage, high frequency switching circuit of claim 29, wherein the output is coupled to a plasma load that is generally capacitive.

34. 30. The high voltage, high frequency switching circuit of claim 29, wherein the output is coupled to a plasma load comprising a dielectric barrier discharge.

35. 30. The high voltage, high frequency switching circuit of claim 29, wherein the resistance of the resistor in the primary sink has a value less than about 400 ohms.

36. 30. The high voltage, high frequency switching circuit of claim 29, wherein the high voltage, high frequency switching power supply provides a peak power in excess of 100 kW.

37. The resistance in the primary sink comprises a resistor R, and the output is [Equation 1] where t ｆ 30. The high voltage, high frequency switching circuit of claim 29, wherein: is the pulse fall time.

38. 30. The high voltage, high frequency switching circuit of claim 29, wherein the load is capacitive with a capacitance of less than 50 nF, and the capacitance of the load does not hold a charge for more than 10 μs.

39. 30. The high voltage, high frequency switching circuit of claim 29, wherein the load is capacitive in nature and the high voltage, high frequency switching circuit rapidly charges and discharges the load capacitance.

40. 30. The high voltage, high frequency switching circuit of claim 29, wherein the output generates a negative bias voltage of greater than -2 kV in a plasma when the high voltage switching power supply is not providing high voltage pulses.

41. 30. The high voltage, high frequency switching circuit of claim 29, wherein the output is capable of generating high voltage pulses having voltages in excess of 1 kV and frequencies in excess of 10 kHz with pulse fall times of less than about 400 ns.

42. A high voltage, high frequency switching circuit, a high voltage switching power supply that generates pulses having a voltage greater than 1 kV and a frequency greater than 10 kHz; a transformer having a primary side and a secondary side; an output electrically coupled to the secondary side of the transformer; a primary sink electrically coupled to a primary side of the transformer and arranged in parallel with an output of the high voltage switching power supply, the primary sink comprising at least one resistor for discharging a load coupled to the output and at least one inductor arranged in series with the at least one resistor.

43. 13. The high voltage, high frequency switching circuit of claim 12, wherein the primary sink includes a switch connected in series with the at least one resistor and / or the at least one inductor.

44. 13. The high voltage, high frequency switching circuit of claim 12, wherein the output is capable of generating high voltage pulses having a voltage greater than 1 kV, a frequency greater than 10 kHz, and a pulse fall time less than about 400 ns.

45. 13. The high voltage, high frequency switching circuit of claim 12, wherein the primary sink is configured to dissipate greater than about 1 kilowatt of power.

46. 13. The high voltage, high frequency switching circuit of claim 12, wherein the high voltage switching power supply comprises a power supply, at least one switch, and a step-up transformer.

47. 13. The high voltage, high frequency switching circuit of claim 12, wherein the primary sink handles greater than 10 kW of peak power.

48. 13. The high voltage, high frequency switching circuit of claim 12, wherein the resistor in the primary sink has a resistance of less than about 400 ohms.

49. 13. The high-voltage, high-frequency switching circuit of claim 12, wherein the primary sink includes an inductor and a resistor, and an inductance L of the inductor and a resistance R of the resistor are set to satisfy L / R≈tp, where tp is a pulse width of a pulse.

50. The primary sink resistor comprises a resistor R, and the output is [Equation 2] where t ｆ 13. The high voltage, high frequency switching circuit of claim 12, wherein: is the pulse fall time.

51. 13. The high voltage, high frequency switching circuit of claim 12, wherein the output generates a negative bias voltage in the plasma that is used to accelerate ions to a surface.

52. 13. The high voltage, high frequency switching circuit of claim 12, wherein the output generates a negative potential difference of greater than −2 kV from the electrode or the substrate (or wafer and plasma) to ground when the high voltage switching power supply is not supplying high voltage pulses.

53. A high voltage, high frequency switching circuit, a high voltage switching power supply that generates pulses at voltages greater than 1 kV and frequencies greater than 10 kHz; a transformer having a primary side and a secondary side; an output electrically coupled to the secondary side of the transformer; a primary sink electrically coupled to a primary side of the transformer and arranged in parallel with an output of the high voltage switching power supply, the primary sink including at least one resistor, at least one inductor, and a switch arranged in series; 1. A high voltage, high frequency switching circuit, wherein the output is capable of generating high voltage pulses having a voltage greater than 1 kV, a frequency greater than 10 kHz, and a pulse fall time less than about 400 ns, the output being electrically connected to a plasma-type load.

54. 54. The high voltage, high frequency switching circuit of claim 53, wherein the plasma-type load can be modeled as having a capacitive element with a magnitude less than 20 nF.

55. 54. The high voltage, high frequency switching circuit of claim 53, wherein the plasma-type load is designed to accelerate ions to a surface.

56. 54. The high voltage, high frequency switching circuit of claim 53, wherein the potential for accelerating ions to the surface is established by operation of a high voltage, high frequency switching power supply.

57. 54. The high voltage, high frequency switching circuit of claim 53, wherein said plasma type is generally capacitive in nature.

58. 54. The high voltage, high frequency switching circuit of claim 53, wherein the plasma-type load comprises a dielectric barrier discharge.

59. 54. The high voltage, high frequency switching circuit of claim 53, wherein said high voltage, high frequency switching power supply provides a peak power in excess of 100 kW.

60. 54. The high voltage, high frequency switching circuit of claim 53, wherein the high voltage switching power supply comprises a power supply, at least one switch, and a step-up transformer.

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