Semiconductor device

Abstract

To delay the progress of deterioration of a solder.SOLUTION: A semiconductor device includes: a semiconductor chip 12 including a main electrode 12a2 on a top face 12a and another main electrode on a bottom face 12b respectively; and a lead frame 13a including a main electrode joint part 14a which comprises a joint surface 14a2 joined to the main electrode 12a2 via a solder 17b and in which the joint surface 14a2 is positioned within the top face 12a of the semiconductor chip 12 in a planar view, and a rising part 15a1 extending from an outer periphery of the main electrode joint part 14a. Further, a first height H1 from an outer edge region 14a22 of the joint surface 14a2 to the top face 12a of the semiconductor chip 12 is larger than a second height H2 from an intermediate region 14a21 excluding the outer edge region 14a22 from the joint surface 14a2 to the top face 12a of the semiconductor chip 12.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] The semiconductor device includes a conductive plate, a semiconductor chip soldered onto the conductive plate, and a lead frame soldered to electrodes on the top surface of the semiconductor chip (see, for example, Patent Documents 1 to 6). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-079228 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-128194 [Patent Document 3] International Publication No. 2020 / 003495 [Patent Document 4] International Publication No. 2019 / 167102 [Patent Document 5] Japanese Patent Application Laid-Open No. 2013-004943 [Patent Document 6] International Publication No. 2023 / 119837 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of delaying the progression of solder deterioration. [Means for solving the problem]

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor chip including a first electrode on its upper surface and a second electrode on its lower surface; and a wiring member having a bonding surface joined to the first electrode via solder, wherein the bonding surface includes a bonding portion located within the upper surface of the semiconductor chip in a planar view and a rising portion extending from the outer periphery of the bonding portion, wherein a first height from an outer edge region of the bonding surface to the upper surface of the semiconductor chip is greater than a second height from an intermediate region excluding the outer edge region from the bonding surface to the upper surface of the semiconductor chip.

[0006] Furthermore, a first thickness of an outer edge portion of the joint surface of the solder that contacts the outer edge region may be greater than a second thickness of a central portion of the joint surface of the solder that contacts the intermediate region. The first thickness may be 750 μm or less, and the second thickness may be 150 μm or more and 350 μm or less.

[0007] The solder may be arranged such that an angle from an outer peripheral side surface in contact with the semiconductor chip to an end of the joining surface of the joining portion relative to the first electrode of the semiconductor chip is 20° or more and 45° or less.

[0008] The joining surface may further include bosses provided at four corners of the intermediate region. In addition to the four corners, a plurality of bosses may be further provided along the outer periphery of the intermediate region of the joining surface. The solder may also be Sn-0.7Cu. The solder may have a Young's modulus of 50 GPa or more and a yield point of 30 MPa or less at 25°C.

[0009] The solder may also be Sn-5Sb. The outer edge regions of the joining surface of the joining portion may be provided at four corners of the joining surface.

[0010] The outer edge region of the bonding surface of the bonding portion may be inclined so as to move away from the top surface of the semiconductor chip as it extends outward. The outer edge region of the joining surface included in the joining portion may be inclined so that an end of the outer edge region extends beyond a main surface of the joining portion opposite the joining surface and is higher than the main surface.

[0011] The outer edge region of the joint surface included in the joint portion may be stepped relative to the intermediate region of the joint surface and positioned higher than the intermediate region. The package may further include a gel that seals the semiconductor chip, the solder, and the wiring member.

[0012] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Effects of the Invention]

[0013] According to the disclosed technology, the progression of solder deterioration can be slowed down. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment; [Figure 2] FIG. 1 is a side view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment. [Figure 4] 1 is a side cross-sectional view (part 1) of a semiconductor unit included in a semiconductor device according to a first embodiment; [Figure 5] 2 is an enlarged cross-sectional side view of a semiconductor unit included in the semiconductor device of the first embodiment. FIG. [Figure 6] 2 is a side cross-sectional view (part 2) of a semiconductor unit included in the semiconductor device of the first embodiment; FIG. [Figure 7] 1 is a side cross-sectional view of a semiconductor unit included in a semiconductor device of Reference Example 1. FIG. [Figure 8] 1 is a plan view of a semiconductor unit included in a semiconductor device of Reference Example 1. FIG. [Figure 9] FIG. 10 is a side cross-sectional view of a semiconductor unit included in a semiconductor device of Reference Example 2. [Figure 10] FIG. 2 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment (modification 1-1). [Figure 11] FIG. 10 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment (modification 1-2). [Figure 12] FIG. 10 is an enlarged side cross-sectional view of a semiconductor unit included in a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is a side cross-sectional view of a semiconductor unit included in a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is an enlarged cross-sectional side view of a semiconductor unit included in a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the XY plane facing upward (+Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "up" refers to the upward direction (+Z direction) in the semiconductor device 1 of FIG. 1. The terms "back surface" and "lower surface" refer to the XY plane facing downward (-Z direction) in the semiconductor device 1 of FIG. 1. Similarly, "lower" refers to the downward direction (-Z direction) in the semiconductor device 1 of FIG. 1. As necessary, the same directionality as above will be used in other drawings as well. The terms "higher" and "upper" refer to the upper position (+Z direction) in the semiconductor device 1 of FIG. 1. Similarly, the terms "lower" and "lower" refer to the lower position (-Z direction) in the semiconductor device 1 of FIG. 1. The terms "front surface," "upper surface," "upper," "back surface," "lower surface," "lower," and "side" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. In the following explanation, "main component" refers to a component containing 80 vol% or more. "Almost the same" means that the difference is within a range of ±10%. "Perpendicular," "orthogonal," and "parallel" mean that the difference is within a range of ±10°.

[0016] [First embodiment] A semiconductor device 1 according to a first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view of the semiconductor device according to the first embodiment, and Fig. 2 is a side view of the semiconductor device according to the first embodiment. Fig. 2 is a side view of the side of the semiconductor device 1 in Fig. 1 parallel to the XZ plane, as viewed in the +Y direction.

[0017] The semiconductor device 1 includes a semiconductor module 2 and a heat sink 3. The semiconductor module 2 also includes semiconductor units 10a, 10b, and 10c and a case 20 that houses the semiconductor units 10a, 10b, and 10c. The semiconductor units 10a, 10b, and 10c housed in the case 20 are each sealed with a sealing member (not shown). The semiconductor units 10a, 10b, and 10c all have the same configuration. When there is no need to distinguish between the semiconductor units 10a, 10b, and 10c, they will be described as a semiconductor unit 10. Details of the semiconductor unit 10 will be described later.

[0018] The case 20 included in the semiconductor module 2 includes an outer frame 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, a W-phase output terminal 24a, a V-phase output terminal 24b, a U-phase output terminal 24c, and control terminals 25a, 25b, 25c.

[0019] The outer frame 21 has a generally rectangular shape in a plan view and is surrounded on all four sides by outer walls 21a, 21b, 21c, and 21d. The outer walls 21a and 21c correspond to the long sides of the outer frame 21, and the outer walls 21b and 21d correspond to the short sides of the outer frame 21. The corners where the outer walls 21a, 21b, 21c, and 21d are connected do not necessarily have to be right angles and may be rounded as shown in FIG. 1 . Fastening holes 21i that penetrate the outer frame 21 are formed in the corners of the front surface of the outer frame 21. The fastening holes 21i formed in such corners of the outer frame 21 may be formed lower than the front surface of the outer frame 21.

[0020] The outer frame 21 has unit housing sections 21e1, 21e2, and 21e3 opening along the outer walls 21a and 21c on the front surface thereof. The unit housing sections 21e1, 21e2, and 21e3 are rectangular in plan view. The unit housing sections 21e1, 21e2, and 21e3 house semiconductor units 10a, 10b, and 10c, respectively. As will be described later, the semiconductor units 10a, 10b, and 10c are arranged along the X direction on the front surface of the heat sink 3. The outer frame 21 is attached to the front surface of the heat sink 3, and the semiconductor units 10a, 10b, and 10c are surrounded (housed) in the unit housing sections 21e1, 21e2, and 21e3 of the outer frame 21, respectively.

[0021] In a plan view, outer frame 21 has first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c on the outer wall 21a side of the front surface. First connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c correspond to unit housing sections 21e1, 21e2, 21e3, respectively. One end of first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c is exposed on the outer wall 21a side of the front surface. The other end is exposed inside unit housing sections 21e1, 21e2, 21e3 and is electrically connected to semiconductor units 10a, 10b, 10c.

[0022] For example, in the unit storage section 21e2, the other ends of the first and second connection terminals 22b and 23b are respectively joined to the semiconductor unit 10b (which are included in conductive circuit patterns 11b1 and 11b3, which will be described later). Similarly, the other ends of the first and second connection terminals 22a and 23a and the first and second connection terminals 22c and 23c are respectively joined to the semiconductor unit 10a and the semiconductor unit 10c (which are included in conductive circuit patterns 11b1 and 11b3, which will be described later).

[0023] Furthermore, W-phase output terminal 24a, V-phase output terminal 24b, and U-phase output terminal 24c are provided on the outer wall 21c side of the front surface. W-phase output terminal 24a, V-phase output terminal 24b, and U-phase output terminal 24c correspond to unit housing portions 21e1, 21e2, and 21e3, respectively. One ends of W-phase output terminal 24a, V-phase output terminal 24b, and U-phase output terminal 24c are exposed on the outer wall 21c side of the front surface. The other ends are exposed inside unit housing portions 21e1, 21e2, and 21e3 and are electrically connected to semiconductor units 10a, 10b, and 10c.

[0024] For example, in the unit storage section 21e2, the other end of the V-phase output terminal 24b is ultrasonically bonded to the semiconductor unit 10b (which is included in a conductive circuit pattern 11b2, described later). Similarly, the other ends of the W-phase output terminal 24a and the U-phase output terminal 24c are ultrasonically bonded to the semiconductor units 10a and 10c (which are included in a conductive circuit pattern 11b2, described later).

[0025] Nuts are housed on the outer wall 21a side of the front surface of the outer frame 21, facing openings at one end of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c. Similarly, nuts are housed on the outer wall 21c side of the front surface of the outer frame 21, facing openings at one end of the U-phase output terminal 24c, the V-phase output terminal 24b, and the W-phase output terminal 24a.

[0026] Furthermore, the front surface of outer frame 21 is provided with control terminals 25a, 25b, and 25c along the +Y direction side (outer wall 21c side) of unit storage sections 21e1, 21e2, and 21e3 in a plan view. Control terminals 25a, 25b, and 25c may each be provided in two pieces. One end of control terminals 25a, 25b, and 25c extends vertically upward (in the +Z direction) from the front surface of unit storage sections 21e1, 21e2, and 21e3 on the outer wall 21c side. The other end faces in the -Y direction from the outer wall 21c side of unit storage sections 21e1, 21e2, and 21e3 and is exposed inside unit storage sections 21e1, 21e2, and 21e3.

[0027] The outer frame 21 includes first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, W-phase output terminal 24a, V-phase output terminal 24b, U-phase output terminal 24c, and control terminals 25a, 25b, and 25c, and is integrally formed by injection molding using a thermoplastic resin, thereby forming the case 20. The thermoplastic resin may be, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0028] The first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the W-phase output terminal 24a, the V-phase output terminal 24b, the U-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal with excellent conductivity. Such a metal may be, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the W-phase output terminal 24a, the V-phase output terminal 24b, the U-phase output terminal 24c, and the control terminals 25a, 25b, 25c may be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0029] The sealing material is filled into each of unit housing portions 21e1, 21e2, and 21e3 of outer frame 21 to seal semiconductor units 10 in unit housing portions 21e1, 21e2, and 21e3. The sealing material seals the other ends of first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, W-phase output terminal 24a, V-phase output terminal 24b, U-phase output terminal 24c, and control terminals 25a, 25b, and 25c in unit housing portions 21e1, 21e2, and 21e3. The sealing material also seals wires 26, which will be described later. Such a sealing material may be a thermosetting resin. Examples of thermosetting resins include epoxy resin, phenol resin, maleimide resin, and polyester resin. The sealing material may be a gel. A filler may be added to the sealing material. The filler may be an insulating ceramic having high thermal conductivity.

[0030] The heat sink 3 has a rectangular, flat plate shape in a plan view. The heat sink 3 may correspond to the shape of the outer frame 21 in a plan view, and the corners may be rounded. Furthermore, the heat sink 3 has insertion holes formed therein corresponding to the fastening holes 21i in a plan view. The rear surfaces of the semiconductor units 10a, 10b, and 10c are disposed on the front surface of the heat sink 3 via a bonding member (described later). Furthermore, the rear surface of the case 20 (outer frame 21) is disposed on the front surface of the heat sink 3 via an adhesive (described later). Thus, the semiconductor units 10a, 10b, and 10c are housed in the case 20 on the front surface of the heat sink 3. Then, wiring is performed for the semiconductor units 10a, 10b, and 10c, and the unit housing portions 21e1, 21e2, and 21e3 are sealed with a sealing member. As a result, a semiconductor device 1 having a semiconductor module 2 configured on the heat sink 3 is obtained. A cooling device that circulates a refrigerant to cool the semiconductor module 2 may be provided on the rear surface of the heat sink 3 in an area corresponding to the arrangement area of ​​the semiconductor module 2. Alternatively, a plurality of heat dissipation fins may be formed on the rear surface of the heat sink 3.

[0031] Next, the semiconductor units 10a, 10b, and 10c (semiconductor unit 10) will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view of the semiconductor unit included in the semiconductor device of the first embodiment. FIG. 4 is a side cross-sectional view of the semiconductor unit included in the semiconductor device of the first embodiment. Note that FIG. 4 is a cross-sectional view taken along dashed line II in FIG. 3. In addition, in FIG. 3, the positions of the main electrode 12a2 and bosses 14a7 and 14b7 relative to main electrode bonding portions 14a and 14b, which will be described later, are indicated by dashed lines.

[0032] The semiconductor unit 10 may be a device that constitutes a single-phase inverter circuit. Such a semiconductor unit 10 includes an insulating circuit board 11, two semiconductor chips 12, and lead frames 13a and 13b. The semiconductor chips 12 are joined to the insulating circuit board 11 by solder 17a.

[0033] The insulating circuit board 11 includes an insulating plate 11a, conductive circuit patterns 11b1, 11b2, and 11b3, and a metal plate 11c. The insulating plate 11a and the metal plate 11c are rectangular in plan view. The corners of the insulating plate 11a and the metal plate 11c may be round-chamfered or C-chamfered. The size of the metal plate 11c is smaller than the size of the insulating plate 11a in plan view, and the metal plate 11c is formed inside the insulating plate 11a.

[0034] The insulating plate 11a is made of a material that has insulating properties and excellent thermal conductivity. Such insulating plate 11a is made of ceramics. Examples of ceramics include aluminum oxide, aluminum nitride, and silicon nitride.

[0035] The conductive circuit patterns 11b1, 11b2, and 11b3 are examples of conductive plates and are formed on the front surface of the insulating plate 11a. The conductive circuit patterns 11b1, 11b2, and 11b3 are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the conductive circuit patterns 11b1, 11b2, and 11b3 may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0036] The conductive circuit pattern 11b1 occupies half of the area on the +X-direction side of the front surface of the insulating plate 11a, and occupies the entire area from the -Y-direction side to the +Y-direction side. The areas of the conductive circuit pattern 11b1 surrounded by dashed lines are bonded to the other ends of the first connection terminals 22a, 22b, and 22c. This bonding may be performed by ultrasonic bonding, for example.

[0037] The conductive circuit pattern 11b2 occupies half of the front surface of the insulating plate 11a on the -X direction side. Furthermore, the conductive circuit pattern 11b2 occupies from the +Y direction edge of the front surface of the insulating plate 11a to just before the -Y direction edge. The areas surrounded by dashed lines in the conductive circuit pattern 11b2 are where the other ends of the W-phase output terminal 24a, the V-phase output terminal 24b, and the U-phase output terminal 24c are bonded. For example, ultrasonic bonding may be used for this bonding.

[0038] Conductive circuit pattern 11b3 occupies an area surrounded by conductive circuit patterns 11b1 and 11b2 on the front surface of insulating plate 11a. Ends of second connection terminals 23a, 23b, and 23c are bonded to the area surrounded by the dashed line in conductive circuit pattern 11b3. This bonding may be performed by ultrasonic bonding, for example.

[0039] The conductive circuit patterns 11b1, 11b2, and 11b3 are merely examples, and the number, shape, size, and position of the conductive circuit patterns 11b1, 11b2, and 11b3 may be selected appropriately as needed.

[0040] The metal plate 11c is formed on the back surface of the insulating plate 11a. The metal plate 11c is rectangular. The area of ​​the metal plate 11c in a plan view is smaller than that of the insulating plate 11a and larger than the area of ​​the region in which the conductive circuit patterns 11b1, 11b2, and 11b3 are formed. The corners of the metal plate 11c may be round-chamfered or C-chamfered. The metal plate 11c is formed on the entire surface of the insulating plate 11a except for the edges. The metal plate 11c is mainly composed of a metal with excellent thermal conductivity. This metal is, for example, copper, aluminum, or an alloy containing at least one of these.

[0041] Examples of insulating circuit board 11 having such a configuration include a DCB (Direct Copper Bonding) board and an AMB (Active Metal Brazed) board. Insulating circuit board 11 may be attached to the front surface of heat sink 3 via a bonding member (not shown). Heat generated in semiconductor chip 12 can be conducted to heat sink 3 via conductive circuit patterns 11b1 and 11b2, insulating plate 11a, and metal plate 11c, and dissipated.

[0042] Lead-free solder is used for the solders 17a and 17b. Lead-free solder is primarily composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth. The solder may also contain additives. The solders 17a and 17b may also contain unavoidable traces of impurities. In particular, the solder 17b connecting the lead frames 13a and 13b to the semiconductor chip 12 (described later) is preferably made of either Sn (tin)-0.7Cu (copper) or Sn-5Sb (antimony), with Sn-5Sb being particularly preferred. The additive may be, for example, nickel, germanium, cobalt, or silicon. The addition of the additive improves the wettability, gloss, and bonding strength of the solders 17a and 17b, thereby improving reliability.

[0043] The joining member (not shown) that joins the semiconductor unit 10 and the heat sink 3 may be a brazing material or a thermal interface material. The brazing material is primarily composed of, for example, at least one of a tin alloy, an aluminum alloy, a titanium alloy, a magnesium alloy, a zirconium alloy, and a silicon alloy. The thermal interface material is, for example, an elastomer sheet, an RTV (Room Temperature Vulcanization) rubber, a gel, an adhesive containing a phase change material, or a silicone mixed with ceramics. By attaching the semiconductor unit 10 to the heat sink 3 via such a brazing material or thermal interface material, the heat dissipation performance of the semiconductor unit 10 can be improved.

[0044] The semiconductor chip 12 includes an upper surface 12a and a lower surface 12b, and includes a power device element made of silicon. The power device element is a reverse-conducting (RC)-IGBT (insulated gate bipolar transistor). The RC-IGBT is a semiconductor element in which an IGBT, which is a switching element, and an FWD, which is a diode element, are arranged in anti-parallel within a single chip. The upper surface 12a of the semiconductor chip 12 includes a control electrode 12a1 (gate electrode) and a main electrode 12a2 (see FIG. 5), which are output electrodes (emitter electrodes). The lower surface 12b of the semiconductor chip 12 includes an input electrode (collector electrode), which is a main electrode (not shown). The control electrode 12a1 is provided on one side of the upper surface 12a of the semiconductor chip 12. The main electrode 12a2 is provided on the upper surface 12a of the semiconductor chip 12, excluding the control electrode 12a1.

[0045] Alternatively, the semiconductor chip 12 may be a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of silicon carbide. In the power MOSFET, the body diode may function as the FWD. Such a semiconductor chip 12 has, for example, an input electrode (drain electrode) as a main electrode on the back surface, and an output electrode (source electrode) as a main electrode 12a2 and a control electrode 12a1 (gate electrode) on the front surface.

[0046] Furthermore, the semiconductor chip 12 may use a pair of a switching element and a diode element, each made of silicon, instead of an RC-IGBT or a power MOSFET. The switching element is, for example, an IGBT or a power MOSFET. Such a semiconductor chip has, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the bottom surface, and a control electrode 12a1 (gate electrode) and an output electrode (source electrode or emitter electrode) as a main electrode 12a2 on the top surface. For example, an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode is used as the FWD for the diode element. Such a semiconductor chip has, for example, an output electrode (cathode electrode) as a main electrode on the bottom surface, and an input electrode (anode electrode) as a main electrode on the top surface.

[0047] The lead frames 13a and 13b are an example of wiring members, and electrically connect and wire the semiconductor chip 12 (on the conductive circuit patterns 11b2 and 11b1) and the conductive circuit patterns 11b1, 11b2, and 11b3.

[0048] The lead frame 13a directly connects the main electrode 12a2 of the semiconductor chip 12 (on the conductive circuit pattern 11b2) to the conductive circuit pattern 11b3. The lead frame 13b directly connects the main electrode 12a2 of the semiconductor chip 12 (on the conductive circuit pattern 11b1) to the conductive circuit pattern 11b2. Such lead frames 13a and 13b include main electrode joints 14a and 14b, conductive portions 15a and 15b, and circuit joints 16a and 16b.

[0049] The main electrode joints 14a and 14b are each joined to the main electrode 12a2 of the semiconductor chip 12 (on the conductive circuit patterns 11b2 and 11b1) via solder 17b. Although only the cross-sectional view of the main electrode joint 14a is shown, the main electrode joint 14b has a similar configuration to the main electrode joint 14a. Details of the main electrode joints 14a and 14b will be described later.

[0050] The conductive portions 15a, 15b electrically and mechanically connect the main electrode junctions 14a, 14b and the circuit junctions 16a, 16b. The conductive portions 15a, 15b may, for example, straddle the main electrode junctions 14a, 14b and the circuit junctions 16a, 16b. The circuit junctions 16a, 16b are flat and bonded to the conductive circuit patterns 11b3, 11b2, respectively, via solder 17a. In this case, ultrasonic bonding may be used instead of solder 17a. Here, the conductive portions 15a and the circuit junctions 16a may have the same width. The width of the conductive portion 15b may be narrower than the width of the circuit junctions 16b.

[0051] The lead frames 13a and 13b are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the lead frames 13a and 13b may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0052] Furthermore, control electrodes 12a1 of semiconductor chips 12 of semiconductor units 10a, 10b, and 10c housed in unit housing portions 21e1, 21e2, and 21e3 of case 20 are mechanically and electrically connected to the other ends of control terminals 25a, 25b, and 25c by wires 26. Wires 26 are primarily made of a material with excellent conductivity. Such materials include, for example, gold, copper, aluminum, or an alloy containing at least one of these. Preferably, wires 26 may be an aluminum alloy containing a trace amount of silicon.

[0053] Next, the main electrode joints 14a, 14b of the lead frames 13a, 13b of the semiconductor unit 10 will be further described with reference to FIGS. 5 and 6. FIG. 5 is an enlarged side cross-sectional view of a semiconductor unit included in the semiconductor device of the first embodiment. FIG. 6 is a side cross-sectional view of a semiconductor unit included in the semiconductor device of the first embodiment. FIG. 5 shows an enlarged side cross-sectional view of the main electrode joint 14a of the lead frame 13a and its surroundings in FIG. 4. FIG. 6 is a cross-sectional view taken along dashed dotted line II-II in FIG. 3. Note that while FIG. 5 shows the main electrode joint 14a of the lead frame 13a, the main electrode joint 14b of the lead frame 13b may also have a similar configuration to the main electrode joint 14a of the lead frame 13a.

[0054] As described above, the lead frame 13a includes the main electrode joint portion 14a, the conductive portion 15a, and the circuit joint portion 16a (not shown). The main electrode joint portion 14a has a rectangular, flat plate shape in a plan view.

[0055] Such main electrode bonding portion 14a includes an upper surface 14a1 and a lower bonding surface 14a2 that is bonded to main electrode 12a2 of semiconductor chip 12 via solder 17b. In addition, bosses 14a7 are provided on bonding surface 14a2. Upper surface 14a1 and bonding surface 14a2 are substantially parallel. Upper surface 14a1 is recessed to correspond to boss 14a7. Upper surface 14a1 may be substantially flat except for these recesses.

[0056] The area of ​​the bonding surface 14a2 of the main electrode bonding portion 14a is smaller than the area of ​​the top surface 12a of the semiconductor chip 12. Therefore, the bonding surface 14a2 of the main electrode bonding portion 14a is located within the top surface 12a of the semiconductor chip 12 in a plan view (included within the top surface 12a).

[0057] Furthermore, in the main electrode joint portion 14a, when viewed from the side, the first height H1 from the outer edge region 14a22 of the joint surface 14a2 to the upper surface 12a of the semiconductor chip 12 is greater than the second height H2 from the intermediate region 14a21 excluding the outer edge region 14a22 from the joint surface 14a2 to the upper surface 12a of the semiconductor chip 12.

[0058] The outer edge region 14a22 is a continuous, annular outer peripheral portion of the bonding surface 14a2 in a plan view, and may extend over a predetermined width from the outer edge of the bonding surface 14a2. This width may be uniform throughout. In the first embodiment, the outer edge region 14a22 is inclined outwardly so as to move away from the top surface 12a of the semiconductor chip 12. That is, the outer edge region 14a22 is inclined at an obtuse angle relative to the intermediate region 14a21. Therefore, the first height H1 is the shortest distance from the outer edge of the outer edge region 14a22 (the connection point between the outer edge region 14a22 and the top surface 14a1) to the top surface 12a of the semiconductor chip 12 directly below.

[0059] As described above, the intermediate region 14a21 is the portion of the bonding surface 14a2 excluding the outer edge region 14a22. The intermediate region 14a21 may be approximately parallel to the top surface 12a of the semiconductor chip 12. The second height H2 is the gap between the intermediate region 14a21 and the top surface 12a of the semiconductor chip 12, and may be uniform overall.

[0060] Bosses 14a7 may be formed in the intermediate region 14a21 of the bonding surface 14a2. The bosses 14a7 may be formed, for example, at each of the four corners of the intermediate region 14a21. By providing the bosses 14a7, the solder 17b between the bonding surface 14a2 and the top surface 12a of the semiconductor chip 12 can be maintained at a predetermined thickness.

[0061] The height of the bosses 14a7 may be, for example, 0.1 mm or more and 0.4 mm or less, or may be the same height. The bosses 14a7 may be cylindrical and have a diameter of, for example, 0.5 mm or more and 2.0 mm or less. The bosses 14a7 are not limited to cylindrical shapes, but may also be rectangular pillar shapes. The bosses 14a7 may be formed, for example, by pressing the flat main electrode joint portion 14a. Therefore, when the bosses 14a7 are formed on the joint surface 14a2 of the main electrode joint portion 14a, the upper surface 14a1 is recessed at a location corresponding to the boss 14a7. Alternatively, a columnar or spherical body may be joined (for example, by welding) to the joint surface 14a2 of the main electrode joint portion 14a, which is flat and has a flat upper surface 14a1 and joint surface 14a2.

[0062] The conductive portion 15a includes a rising portion 15a1. The rising portion 15a1 extends upward from the outer periphery of the upper surface 14a1 of the main electrode joint 14a relative to the upper surface 14a1. In the first embodiment, the rising portion 15a1 rises approximately perpendicular to the upper surface 14a1 of the main electrode joint 14a. The rising portion 15a1 does not have to be approximately perpendicular to the upper surface 14a1 of the main electrode joint 14a, but may rise at an obtuse angle relative to the upper surface 14a1 of the main electrode joint 14a. The rising portion 15a1 is formed along the X direction on the outer periphery of the main electrode joint 14a in the -Y direction in a plan view.

[0063] As described above, the lead frame 13b also includes a main electrode bonding portion 14b, a conductive portion 15b, and a circuit bonding portion 16b (not shown). Like the main electrode bonding portion 14a, the main electrode bonding portion 14b also includes an upper surface 14b1 and a bonding surface 14b2 on the lower surface that is bonded to the main electrode 12a2 of the semiconductor chip 12 via solder 17b. Also, like the bonding surface 14a2, a boss 14b7 is provided on the bonding surface 14b2.

[0064] Similar to the rising portion 15a1, the conductive portion 15b also includes a rising portion (not shown). The rising portion rises substantially perpendicular to the upper surface 14b1 of the main electrode joint 14b. The rising portion does not have to be substantially perpendicular to the upper surface 14b1 of the main electrode joint 14b, but may rise at an obtuse angle. The rising portion is formed along the Y direction on the outer periphery of the main electrode joint 14b in the -X direction in a plan view (see FIG. 3).

[0065] Furthermore, the outer circumferential ring-shaped continuous side of the solder 17b joining the main electrode joint 14a of the lead frame 13a and the upper surface 12a of the semiconductor chip 12 forms a shape (fillet-like) that widens outward. The fillet-shaped outer peripheral side surface 17b1 of the solder 17b connects the end of the upper surface 12a (main electrode 12a2) of the semiconductor chip 12 to the upper surface 14a1 of the main electrode joint 14a. The inclination angle of the outer peripheral side surface 17b1 with respect to the upper surface 12a (main electrode 12a2) of the semiconductor chip 12 may be 20° or more and 45° or less.

[0066] Furthermore, the intermediate region 14a21, the outer edge region 14a22, and the boss 14a7 of the main electrode joint portion 14a may be embedded in the solder 17b, with the upper surface 14a1 exposed from the solder 17b. A gap is provided between each boss 14a7 and the upper surface 12a of the semiconductor chip 12. Solder 17b is provided in this gap to join the bottom surface of the boss 14a7 to the upper surface 12a of the semiconductor chip 12.

[0067] The first thickness of the outer edge portion of the solder 17b that contacts the outer edge region 14a22 of the joint surface 14a2 is also the first height H1. The second thickness of the central portion of the solder 17b that contacts the intermediate region 14a21 of the joint surface 14a2 is also the second height H2. In this case, the first thickness (first height H1) is greater than the second thickness (second height H2). The first height H1 may be, for example, 750 μm or less. The second height H2 may be, for example, 150 μm or more and 350 μm or less.

[0068] Because the outer edge region 14a22 is inclined, the solder 17b comes into contact with the outer edge region 14a22. At this time, the shortest distance from the outer edge of the outer edge region 14a22 (top surface 14a1) of the solder 17b to the top surface 12a of the semiconductor chip 12 is the first thickness. The first thickness is the thickest part of the solder 17b. In other words, the thickest part of the solder 17b is included in the outer edge portion.

[0069] As with the solder 17b joining the main electrode joint 14b of the lead frame 13b to the upper surface 12a of the semiconductor chip 12, the outer edge portion also has the thickest portion, similar to the above.

[0070] Here, the semiconductor unit 100 of Reference Example 1 will be described with reference to FIGS. 7 and 8. FIG. 7 is a side cross-sectional view of the semiconductor unit included in the semiconductor device of Reference Example 1, and FIG. 8 is a plan view of the semiconductor unit included in the semiconductor device of Reference Example 1. Note that FIGS. 7 and 8 correspond to FIGS. 4 and 3 of the first embodiment, respectively. FIG. 7 is a cross-sectional view taken along dashed line II in FIG. 8. Also, in FIG. 8, the positions of the main electrode 12a2 and bosses 14a7 and 14b7 relative to main electrode bonding portions 140a and 140b, which will be described later, are indicated by dashed lines.

[0071] In Reference Example 1, the semiconductor device 1 includes a semiconductor unit 100 instead of the semiconductor unit 10. The semiconductor unit 100 has a similar configuration to the semiconductor unit 10 of the first embodiment, except for the lead frames 130a and 130b. The lead frames 130a and 130b of the Reference Example also include main electrode bonding portions 140a and 140b, conductive portions 15a and 15b, and circuit bonding portions 16a and 16b, similar to the lead frames 13a and 13b of the first embodiment. However, unlike the main electrode bonding portions 14a and 14b of the first embodiment, the main electrode bonding portions 140a and 140b of Reference Example 1 are flat and have a uniform thickness overall.

[0072] In addition, in Reference Example 1, the thickness of the solder 17b that joins the main electrode joint portions 140a, 140b of the lead frames 130a, 130b to the upper surface 12a of the semiconductor chip 12 is thicker than the second height H2 of the first embodiment.

[0073] In the semiconductor unit 100 of Reference Example 1, heat generated by the semiconductor chip 12 during power cycles causes deformation of the semiconductor chip 12 and the main electrode joints 140a, 140b of the lead frames 130a, 130b. This deformation causes the solder 17b to expand and contract, resulting in distortion. This may result in cracks occurring at the outer end of the solder 17b in a planar view. For example, a crack may occur at any location on the outer end of the solder 17b (particularly on the short side of the main electrode joints 140a, 140b) in a planar view. Repeated expansion and contraction of the solder 17b during power cycles may cause a crack C to propagate from the crack into the solder 17b, as shown in FIG. 7 . Furthermore, cracks may occur at each corner of the outer end of the solder 17b in a planar view. In this case, as shown in FIG. 8 , the crack propagates from the four corners of the solder 17b toward the interior in a planar view. If cracks C propagate in the solder 17b and the solder 17b deteriorates, the thermal conductivity of the solder 17b will decrease. This will reduce the cooling performance for the semiconductor chip 12, making the semiconductor chip 12 more susceptible to failure. Note that while the lead frame 130a has been described here, cracks will similarly occur in the solder 17b of the lead frame 130b, and cracks C will propagate therein.

[0074] Furthermore, the semiconductor unit 100 of Reference Example 2 is the semiconductor unit 100 of Reference Example 1 in which the thickness of the solder 17b is thinner than the second height H2 of the first embodiment. The semiconductor unit 100 of Reference Example 2 has the same configuration as the semiconductor unit 100 of Reference Example 1 except for the thickness of the solder 17b. The semiconductor unit 100 of Reference Example 2 will be described with reference to FIG. 9. FIG. 9 is a side cross-sectional view of a semiconductor unit included in the semiconductor device of Reference Example 2. FIG. 9 corresponds to FIG. 7. Furthermore, although FIG. 9 shows the lead frame 130a, the lead frame 130b is also similarly joined with solder 17b that is thinner than the second height H2.

[0075] In the semiconductor unit 100 of Reference Example 2, the solder 17b expands and contracts during power cycles, causing distortion, and cracks are likely to occur at the outer end of the solder 17b in a plan view. Cracks are particularly likely to occur when the solder 17b is thin, and cracks C are likely to develop from the cracks. In Reference Example 2, as in Reference Example 1, the solder 17b containing cracks C has reduced thermal conductivity, resulting in reduced cooling performance for the semiconductor chip 12.

[0076] Furthermore, if the solder 17b is thin, there is a high possibility that the crack C will propagate to the main electrode 12a2 of the semiconductor chip 12. In this case, as shown in Fig. 9, the main electrode 12a2 of the semiconductor chip 12 may be damaged. As a result, the semiconductor chip 12 becomes more susceptible to failure.

[0077] Furthermore, as the power density and capacity of the semiconductor module 2 (semiconductor unit 100) increases, such deterioration of the solder 17b becomes more pronounced. Therefore, for example, by using an epoxy resin as a sealing member for the semiconductor unit 100 of Reference Examples 1 and 2, it is possible to suppress compression and shrinkage of the solder 17b and delay the progression of deterioration due to cracks in the solder 17b and cracks C. However, epoxy resin is costly.

[0078] The semiconductor device 1 includes a semiconductor chip 12 having a main electrode 12a2 on its upper surface 12a and another main electrode on its lower surface 12b, and a lead frame 13a having a bonding surface 14a2 bonded to the main electrode 12a2 via solder 17b, the bonding surface 14a2 including a main electrode bonding portion 14a located within the upper surface 12a of the semiconductor chip 12 in a plan view, and a rising portion 15a1 extending from the outer periphery of the main electrode bonding portion 14a. Furthermore, a first height H1 from an outer edge region 14a22 of the bonding surface 14a2 to the upper surface 12a of the semiconductor chip 12 is greater than a second height H2 from an intermediate region 14a21, which is defined by excluding the outer edge region 14a22 from the bonding surface 14a2, to the upper surface 12a of the semiconductor chip 12. Therefore, the first thickness (first height H1) of the outer edge portion of the solder 17b that contacts the outer edge region 14a22 of the bonding surface 14a2 is also greater than the second thickness (second height H2) of the central portion of the solder 17b that contacts the intermediate region 14a21 of the bonding surface 14a2. In other words, when the thickness of the solder 17b is thicker on the outer edge side than in the center in a plan view, stress generated on the outer edge side of the solder 17b can be reduced. Furthermore, the bosses 14a7 allow the bonding surface 14a2 of the main electrode bonding portion 14a to maintain a certain thickness or more relative to the main electrode 12a2 (top surface 12a) of the semiconductor chip 12. Therefore, even if the semiconductor chip 12 and the main electrode bonding portions 14a, 14b of the lead frames 13a, 13b are thermally deformed during a power cycle of the semiconductor device 1, cracks are unlikely to occur on the outer edge of the solder 17b. Even if a crack does occur, the propagation of the crack C is suppressed, thereby delaying the progression of deterioration of the solder 17b. This results in an improvement in the power cycle resistance of the semiconductor device 1. Furthermore, since the progression of deterioration of the solder 17b is delayed, a relatively inexpensive gel can be used as the sealing member instead of epoxy resin, and the manufacturing cost of the semiconductor device 1 can also be reduced.

[0079] Furthermore, in order to reduce stress on the solder 17b due to the power cycle of the semiconductor device 1, it is desirable that the solder 17b be made of a high-strength material. The solder 17b preferably contains, for example, Sn-0.7Cu or Sn-5Sb. To obtain a higher power cycle resistance, it is desirable that the Young's modulus at 25°C be 50 GPa or more and the yield point be 30 MPa or less. An example of the solder 17b within this range is Sn-5Sb. The solder 17b containing Sn-5Sb achieves high strength and high heat resistance, and can further improve the power cycle resistance of the semiconductor device 1.

[0080] (Variation 1-1) Modification 1-1 of the first embodiment will be described with reference to FIG. 10. FIG. 10 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment (modification 1-1). Note that FIG. 10 corresponds to FIG. 3 of the first embodiment. In FIG. 10, the positions of the main electrode 12a2 and bosses 14a7 and 14b7 relative to the main electrode joints 14a and 14b are indicated by dashed lines.

[0081] In the semiconductor device 1 of the first embodiment, the outer edge regions 14a22, 14b22 of the lead frames 13a, 13b are inclined relative to the intermediate regions 14a21, 14b21 so that the outer edge of the solder 17b is thicker than the center (see FIGS. 5 and 6). This reduces stress generated on the outer edge of the solder 17b. Also, as described in Reference Examples 1 and 2, cracks tend to propagate from the four corners toward the inside of the outer end of the solder 17b in a plan view.

[0082] Therefore, in the semiconductor device 1, the outer edge regions 14a22, 14b22 of the lead frames 13a, 13b (see FIG. 6) may have at least four corners that are inclined in plan view, as shown in FIG. 10. Even in this case, even if the semiconductor chip 12 and the main electrode joints 14a, 14b of the lead frames 13a, 13b are deformed by heat during the power cycle of the semiconductor device 1, cracks are unlikely to occur at the corners of the solder 17b, and even if cracks do occur, the progression of the cracks C can be suppressed, thereby slowing the progression of deterioration of the solder 17b.

[0083] Furthermore, in the semiconductor device 1, the outer edge regions 14a22, 14b22 of the lead frames 13a, 13b may be inclined not only at the four corners but also at the outer end of the solder 17b where cracks are likely to occur and grow.

[0084] (Variation 1-2) Modification 1-2 of the first embodiment will be described with reference to FIG. 11. FIG. 11 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment (modification 1-2). Note that FIG. 11 corresponds to FIG. 3 of the first embodiment. In FIG. 11, the positions of the main electrode 12a2 and bosses 14a7 and 14b7 relative to the main electrode joint portions 14a and 14b are indicated by dashed lines. For the main electrode joint portions 13a and 13b in modification 1-2, reference can be made to FIGS. 4 to 6.

[0085] In the semiconductor device 1 of the first embodiment, bosses 14a7 are formed at the four corners of an intermediate region 14a21 of a bonding surface 14a2 of the lead frame 13a (see FIGS. 3 to 5). Bosses 14a7 are also formed at the four corners of an intermediate region 14b21 of a bonding surface 14b2 of the lead frame 13b (see FIGS. 3 to 6).

[0086] Such bosses 14a7 are not limited to the four corners of the intermediate region 14a21, and five or more may be provided along the periphery of the intermediate region 14a21. For example, as shown in FIG. 11, ten bosses 14a7 may be formed along the periphery of the intermediate region 14a21 of the bonding surface 14a2. The more bosses 14a7 there are, the more reliably the first height H1 and the second height H2 of the solder 17b can be maintained. As a result, even if the semiconductor chip 12 and the main electrode bonding portions 14a, 14b of the lead frames 13a, 13b are deformed by heat during a power cycle of the semiconductor device 1, cracks are less likely to occur at the corners of the solder 17b. Even if cracks do occur, the propagation of the cracks C is suppressed, further delaying the progression of deterioration of the solder 17b.

[0087] [Second embodiment] In the second embodiment, the outer edge regions 14a22, 14b22 of the main electrode bonding portions 14a, 14b of the lead frames 13a, 13b are different from those in the first embodiment. This semiconductor device will be described with reference to FIGS. 12 and 13. FIG. 12 is an enlarged side cross-sectional view of a semiconductor unit included in the semiconductor device of the second embodiment. FIG. 13 is a side cross-sectional view of a semiconductor unit included in the semiconductor device of the second embodiment. The semiconductor device of the second embodiment has the same configuration as the semiconductor device 1 of the first embodiment, except for the outer edge regions 14a22, 14b22 of the lead frames 13a, 13b. For a plan view of the semiconductor unit 10 of the second embodiment, see FIG. 3. FIG. 12 is an enlarged view of the cross section taken along dashed line II in FIG. 3. FIG. 13 is a cross section taken along dashed line II-II in FIG. 3. Note that the insulating circuit substrate 11 is not shown in FIGS. 12 and 13.

[0088] In the second embodiment, outer edge regions 14a22 and 14b22 of the bonding surfaces 14a2 and 14b2 of the main electrode bonding portions 14a and 14b included in the lead frames 13a and 13b are stepped relative to the intermediate regions 14a21 and 14b21 of the bonding surfaces 14a2 and 14b2, and are located above (in the +Z direction) the intermediate regions 14a21 and 14b21. The outer edge regions 14a22 and 14b22 are generally parallel to the upper surfaces 14a1 and 14b1 of the main electrode bonding portions 14a and 14b, and are flat. The width of the outer edge regions 14a22 and 14b22 (the distance from the outer edge of the main electrode bonding portions 14a and 14b to the inside in a plan view) may be, for example, 0.5 mm or more and 3 mm or less.

[0089] Therefore, in the lead frames 13a and 13b, the first height H1 from the outer edge regions 14a22 and 14b22 of the bonding surfaces 14a2 and 14b2 to the top surface 12a of the semiconductor chip 12 is greater than the second height H2 from the intermediate regions 14a21 and 14b21 of the bonding surfaces 14a2 and 14b2 to the top surface 12a of the semiconductor chip 12. Therefore, in the second embodiment, the first thickness (first height H1) of the outer edge portion of the solder 17b that contacts the outer edge regions 14a22 and 14b22 of the bonding surfaces 14a2 and 14b2 is also greater than the second thickness (second height H2) of the central portion of the solder 17b that contacts the intermediate regions 14a21 and 14b21 of the bonding surfaces 14a2 and 14b2. Note that while FIG. 12 shows the first and second heights H1 and H2 of the lead frame 13a, the same heights are true for the lead frame 13b. That is, the thickness of the solder 17b is thicker on the outer edge side than on the center side in plan view, which reduces the stress generated on the outer edge side of the solder 17b. As a result, similar to the first embodiment, the power cycle resistance of the semiconductor device 1 is improved.

[0090] In the second embodiment, as in the first modification of the first embodiment, at least four corners of the outer edge regions 14a22, 14b22 of the lead frames 13a, 13b may be stepped relative to the intermediate regions 14a21, 14b21 in a plan view, and may be located above (in the +Z direction) the intermediate regions 14a21, 14b21. Furthermore, as in the second modification of the first embodiment, the bosses 14a7 are not limited to the four corners of the intermediate regions 14a21, 14b21, and five or more bosses 14a7 may be provided along the outer periphery of the intermediate regions 14a21, 14b21.

[0091] [Third embodiment] In the third embodiment, the outer edge regions 14a22, 14b22 of the main electrode bonding portions 14a, 14b of the lead frames 13a, 13b are different from those of the first and second embodiments. Such a semiconductor device will be described with reference to FIG. 14 . FIG. 14 is an enlarged side cross-sectional view of a semiconductor unit included in the semiconductor device of the third embodiment. The semiconductor device of the third embodiment has the same configuration as the semiconductor device 1 of the first embodiment, except for the outer edge regions 14a22, 14b22 of the lead frames 13a, 13b. FIG. 14 is an enlarged view of the cross section taken along dashed line II in FIG. 3 . The cross section taken along dashed line II-II in FIG. 3 is omitted. Although the main electrode bonding portion 14a of the lead frame 13a will be described here, the main electrode bonding portion 14b of the lead frame 13b is also similar.

[0092] The outer edge region 14a22 of the bonding surface 14a2 of the main electrode bonding portion 14a is inclined outward, away from the top surface 12a of the semiconductor chip 12. Furthermore, the outer edge region 14a22 is inclined so that its outer end extends beyond the top surface 14a1 of the main electrode bonding portion 14a opposite the bonding surface 14a2 and is higher than the top surface 14a1. Therefore, in the lead frame 13a, the first height H1 from the outer edge region 14a22 of the bonding surface 14a2 to the top surface 12a of the semiconductor chip 12 is greater than the first height H1 in the first embodiment. The second height H2 may be the same as the second height H2 in the first embodiment.

[0093] As a result, the first thickness (first height H1) of the outer edge portion of the solder 17b that contacts the outer edge region 14a22 of the joining surface 14a2 is greater than the same thickness (first height) in the first embodiment. Therefore, the stress generated on the outer edge side of the solder 17b in the third embodiment can be reduced more than in the first embodiment. As a result, the power cycle resistance of the semiconductor device is improved more than in the first embodiment.

[0094] Furthermore, the configurations disclosed in the above embodiments can be combined as appropriate within the scope of not causing any contradiction. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0095] 1. Semiconductor device 2. Semiconductor Module 3 Heat sink 10, 10a, 10b, 10c semiconductor unit 11 Insulated circuit board 11a Insulating plate 11b1, 11b2, 11b3 Conductive circuit patterns 11c metal plate 12 Semiconductor chips 12a Top side 12a1 Control electrode 12a2 Main electrode 12b Bottom side 13a, 13b Lead frame 14a,14b Main electrode junction 14a1,14b1 Top surface 14a2,14b2 joint surface 14a21,14b21 intermediate area 14a22, 14b22 Outer region 14a7,14b7 Boss 15a,15b Continuity part 15a1 Rising section 16a,16b circuit junction 17a, 17b solder 17b1 Outer side 20 cases 21 Outer Frame 21a, 21b, 21c, 21d Exterior wall 21e1, 21e2, 21e3 Unit storage area 21i fastening hole 22a, 22b, 22c First connection terminal 23a, 23b, 23c Second connection terminal 24a W phase output terminal 24b V phase output terminal 24c U phase output terminal 25a, 25b, 25c control terminals 26 wires

Claims

1. a semiconductor chip including a first electrode on an upper surface and a second electrode on a lower surface; a wiring member including a bonding surface bonded to the first electrode via solder, the bonding surface being located within the upper surface of the semiconductor chip in a plan view, and a rising portion extending from an outer periphery of the bonding portion; Including, a first height from an outer edge region of the bonding surface to the top surface of the semiconductor chip is greater than a second height from an intermediate region of the bonding surface excluding the outer edge region to the top surface of the semiconductor chip; Semiconductor device.

2. a first thickness of an outer edge portion of the joint surface of the solder that is in contact with the outer edge region is greater than a second thickness of a central portion of the joint surface of the solder that is in contact with the intermediate region; The semiconductor device according to claim 1 .

3. The first thickness is 750 μm or less, and the second thickness is 150 μm or more and 350 μm or less. The semiconductor device according to claim 2 .

4. the solder has an angle of 20° or more and 45° or less from an outer peripheral side surface in contact with the semiconductor chip to an end of the joining surface of the joining portion with respect to the first electrode of the semiconductor chip; The semiconductor device according to claim 2 .

5. The joining surface further includes bosses provided at four corners of the intermediate region. The semiconductor device according to claim 1 .

6. In addition to the four corners of the intermediate region of the joining surface, a plurality of bosses are further provided along the outer periphery. The semiconductor device according to claim 5 .

7. The solder is Sn-0.7Cu. The semiconductor device according to claim 1 .

8. The solder has a Young's modulus of 50 GPa or more and a yield point of 30 MPa or less at 25°C. The semiconductor device according to claim 1 .

9. The solder is Sn-5Sb. The semiconductor device according to claim 8 .

10. The outer edge regions of the joining surface of the joining portion are provided at four corners of the joining surface. The semiconductor device according to claim 1 .

11. the outer edge region of the bonding surface of the bonding portion is inclined so as to move away from the top surface of the semiconductor chip as it goes outward; The semiconductor device according to claim 1 .

12. The outer edge region of the joining surface included in the joining portion is inclined so that an end of the outer edge region extends beyond a main surface of the joining portion opposite to the joining surface and is higher than the main surface. The semiconductor device according to claim 11.

13. the outer edge region of the bonding surface included in the bonding portion forms a step with respect to the intermediate region of the bonding surface and is located higher than the intermediate region; The semiconductor device according to claim 1 .

14. a gel that seals the semiconductor chip, the solder, and the wiring member; The semiconductor device according to claim 1 , further comprising:

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