Light emitting device

Abstract

To suppress fluctuations in an electric characteristic in a transistor having an oxide semiconductor film, and improve reliability.SOLUTION: A semiconductor device has a transistor, and the transistor has: a first gate electrode; a first insulation film on the first gate electrode; a first oxide semiconductor film on the first insulation film; a source electrode that is electrically connected to the first oxide semiconductor film; a drain electrode that is electrically connected to the first oxide semiconductor film; a second insulation film on the first oxide semiconductor film; a second oxide semiconductor film that functions as a second gate electrode on the second insulation film; and a third insulation film on the second oxide semiconductor film. The second insulation film has an excessive oxygen region, in which the excessive oxygen region has a density gradient.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor film. Regarding the law.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. Process, Machine, Manufacture, or Composition of Matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials, such as silicon, are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] For example, oxygen is released by heating into the insulating film underlying the oxide semiconductor film that forms the channel region. and a semiconductor device in which oxygen vacancies in the oxide semiconductor film are reduced by using an insulating film that emits oxygen. (For example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-9836 Summary of the Invention [Problem to be solved by the invention]

[0007] When a transistor is manufactured using an oxide semiconductor film for a channel region, The oxygen vacancies formed in the semiconductor layer are problematic because they affect transistor characteristics. When oxygen vacancies are formed in the oxide semiconductor film, hydrogen bonds to the oxygen vacancies to supply carriers. When a carrier supply source is generated in the oxide semiconductor film, The electrical characteristics of the transistor change, typically the threshold voltage shift. Therefore, the electrical characteristics of each transistor vary. In the channel region, the fewer oxygen vacancies the better.

[0008] In view of the above problems, one embodiment of the present invention provides a transistor including an oxide semiconductor film, One of the objectives is to suppress fluctuations in electrical characteristics and improve reliability. An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a novel display device.

[0009] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above can be solved by the specification. It is clear from the description of the specification, etc. that the problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: a first insulating film on the first gate electrode; and a first oxide film on the first insulating film. a semiconductor film; a source electrode electrically connected to the first oxide semiconductor film; a drain electrode electrically connected to the conductive film; and a second insulating film on the first oxide semiconductor film. a second oxide semiconductor film serving as a second gate electrode over the second insulating film; a third insulating film on the oxide semiconductor film, the second insulating film having an excess oxygen region and an excess The semiconductor device has an oxygen region with a concentration gradient.

[0011] In the above embodiment, the excess oxygen region has an oxygen concentration that increases toward the surface of the second insulating film. It is preferable to have a region.

[0012] In the above embodiment, the third insulating film contains either or both of nitrogen and hydrogen. It is preferable that the

[0013] In the above embodiment, the first oxide semiconductor film contains In and M (M is Al, Ga, Y In the above embodiment, the second oxide preferably contains Sn and Zn. The compound semiconductor film preferably contains In and M (M is Al, Ga, Y, or Sn). In the above embodiment, the first oxide semiconductor film preferably has a multilayer structure. In the above-described embodiment, the first oxide semiconductor film has a crystalline portion, and the crystalline portion has a c-axis orientation. It is preferable that the

[0014] In the above embodiment, the first gate electrode and the second gate electrode are electrically connected. It is preferable that this be done.

[0015] Another aspect of the present invention is a semiconductor device comprising: a display; Another embodiment of the present invention is a display device including the display device and a touch sensor. Another aspect of the present invention is a display module having any of the above aspects. The semiconductor device, the display device, or the display module according to any one of the preceding claims, and an operation key or and a battery. [Effects of the Invention]

[0016] According to one embodiment of the present invention, a transistor including an oxide semiconductor film can be manufactured by changing electrical characteristics. Furthermore, the present invention can suppress the vibration and improve the reliability. In this way, a semiconductor device with reduced power consumption can be provided. Furthermore, a novel semiconductor device can be provided. It is possible to provide a display device.

[0017] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other effects from the descriptions in the aspects and claims. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a diagram illustrating the results of SIMS measurements. [Figure 2] FIG. 1 is a diagram illustrating the results of SIMS measurements. [Figure 3] FIG. 1 is a diagram illustrating the results of SIMS measurements. [Figure 4] FIG. 1 is a cross-sectional view illustrating a sample for SIMS measurement. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 6] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating a sample for measuring sheet resistance. [Figure 8] FIG. 10 is a diagram illustrating the measurement results of sheet resistance. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 12] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 13] FIG. 1 is a diagram illustrating a band structure. [Figure 14] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 17]1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 19] FIG. 1 is a model diagram showing oxygen moving into an oxide semiconductor film. [Figure 20] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 21] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device and a semiconductor device. [Figure 22] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 23] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 24] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 25] Electron diffraction pattern of CAAC-OS. [Figure 26] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 27] 1A to 1C illustrate a method for forming a CAAC-OS film. [Figure 28] A diagram explaining the InMZnO4 crystal. [Figure 29] 1A to 1C illustrate a method for forming a CAAC-OS film. [Figure 30] FIG. 2 is a diagram illustrating the positions where particles adhere to a pellet. [Figure 31] FIG. 2 is a diagram illustrating the positions where particles adhere to a pellet. [Figure 32] 1A and 1B are a top view illustrating one embodiment of a display device and a circuit diagram illustrating one embodiment of a pixel. [Figure 33] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 34] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 35] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 36] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 37] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 38] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 39] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 40] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 41] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 42] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 43] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 44] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 45] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 46] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 47] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 48] FIG. 1 is a top view illustrating one embodiment of a pixel. [Figure 49] FIG. 1 is a cross-sectional view illustrating one embodiment of a pixel. [Figure 50] FIG. 1 is a circuit diagram illustrating one embodiment of a pixel. [Figure 51] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 52] 2A to 2C are diagrams illustrating a circuit configuration of a resistor element, as well as a top view and a cross section of the resistor element. [Figure 53] 3A and 3B are a circuit diagram and a cross-sectional schematic diagram illustrating a sensor circuit unit. [Figure 54] 1A and 1B are a top view and a cross-sectional view illustrating a display device. [Figure 55] FIG. 1 is a perspective view showing an example of a touch panel. [Figure 56] FIG. 2 is a schematic cross-sectional view illustrating an example of a peripheral portion and a terminal portion of a display device. [Figure 57] FIG. 2 is a schematic cross-sectional view illustrating an example of a terminal portion of a display device. [Figure 58] FIG. 1 is a cross-sectional view showing an example of a display device. [Figure 59] FIG. 1 is a cross-sectional view showing an example of a touch sensor. [Figure 60] FIG. 1 is a cross-sectional view showing an example of a touch panel. [Figure 61]1A and 1B are a block diagram and a timing chart of a touch sensor; [Figure 62] Circuit diagram of a touch sensor. [Figure 63] 1A to 1C are diagrams illustrating a manufacturing process of a display device using a lateral electric field mode liquid crystal element. [Figure 64] 1A to 1C are diagrams illustrating displays on a display device according to one embodiment of the present invention. [Figure 65] 1A to 1C are diagrams illustrating displays on a display device according to one embodiment of the present invention. [Figure 66] 1A to 1C are diagrams illustrating an example of a display method on a display device according to an embodiment. [Figure 67] 1A to 1C are diagrams illustrating an example of a display method on a display device according to an embodiment. [Figure 68] FIG. 2 is a diagram illustrating a display module. [Figure 69] 1A to 1C illustrate electronic devices. [Figure 70] FIG. [Figure 71] FIG. 2 is a diagram illustrating the configuration of a film formation apparatus. [Figure 72] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 73] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 74] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 75] FIG. 10 is a graph showing Id-Vg characteristics of a transistor. [Figure 76] 10A and 10B are diagrams illustrating GBT test results of transistors. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above description, and the embodiments and details thereof may be modified without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the embodiments described below. It is not to be construed as being limited to the content.

[0020] In addition, the position, size, range, etc. of each component shown in the drawings etc. are not necessarily shown in order to facilitate understanding. It may not represent the actual position, size, range, etc. Therefore, the disclosed invention The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0021] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. Therefore, for example, "first" may be changed to "second" " or "third" etc. as appropriate. The ordinal numbers used to identify an aspect of the present invention may not match. There is a match.

[0022] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in explaining the relationship with reference to the drawings. The values ​​change depending on the direction in which each component is depicted. It is not limited to words and phrases, and can be rephrased appropriately depending on the situation.

[0023] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, the same The reference numerals are used commonly even among different drawings.

[0024] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device.

[0025] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the dielectric constant is low enough, it may have the properties of an "insulator." The boundary between "insulator" and "insulator" is vague and it may not be possible to strictly distinguish them. The term "semiconductor" in the above may be replaced with "insulator." The term "insulator" in the specification etc. may be replaced with "semiconductor." In some cases, the term "insulator" used in this specification can be rephrased as "semi-insulator." .

[0026] In addition, even when the term "semiconductor" is used in this specification, for example, a material having electrical conductivity is also included. If the electrical conductivity is sufficiently high, it may have the properties of a "conductor." The boundary between "conductor" and "electroconductor" is vague and it may not be possible to strictly distinguish them. The term "semiconductor" in the above may be replaced with "conductor." The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0027] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The semiconductor device has a channel region therein, and a current flows through the drain, the channel region, and the source. In this specification and the like, the channel region is a region where a current mainly flows. The flow area.

[0028] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0029] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the specification, the channel length is any one value, maximum The value may be a minimum or average value.

[0030] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate electrode overlaps with the electrode (the area where current flows) forms a channel. The length of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. In the detailed description, the channel width is any one value, maximum The value may be a minimum or average value.

[0031] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0032] Also, a voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. be.

[0033] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. It refers to a film with a high content of oxygen, preferably 55 atomic % to 65 atomic % and 100 atomic % of nitrogen. % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 0.1 atomic % or more The silicon nitride oxide film is a film containing silicon dioxide in a range of 10 atomic % or more. The composition of the film is such that the nitrogen content is higher than the oxygen content, and preferably the nitrogen content is 55 atomic % or more. 5 atomic % or less, oxygen is 1 atomic % to 20 atomic % and silicon is 25 atomic % to 35 atomic % % or less, and hydrogen is contained in a concentration range of 0.1 atomic % to 10 atomic %.

[0034] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0035] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that two straight lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0036] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. The description will be made with reference to FIGS.

[0037] <1-1. Configuration example 1 of semiconductor device> FIG. 5A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 5(B) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 5(A). 5(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 5(A). In FIG. 5A, in order to avoid complication, the transistor 100 Some of the components (such as the insulating film that functions as the gate insulating film) are omitted in the illustration. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is the channel width direction. In the top view of the transistor, 5(A), some of the components may be omitted.

[0038] The transistor 100 includes a conductive film 104 over a substrate 102, which functions as a first gate electrode. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. The oxide semiconductor film 108 on the insulating film 107 and the insulating film 108 electrically connected to the oxide semiconductor film 108 The conductive film 112a serving as a source electrode and the oxide semiconductor film 108 The conductive film 112b functions as a drain electrode connected to the oxide semiconductor film 108, the conductive film 11 2a and 112b, and insulating films 114 and 116, and a conductive film provided on the insulating film 116. The oxide semiconductor film 120a electrically connected to the insulating film 112b and the oxide semiconductor film 120b on the insulating film 116 The conductive film 120b, the insulating film 116, and the insulating film 11 on the oxide semiconductor films 120a and 120b 8 and has.

[0039] In the transistor 100, the insulating films 106 and 107 are The insulating films 114 and 116 function as a first gate insulating film. The insulating film 118 functions as a second gate insulating film for protecting the transistor 100. It should be noted that in this specification and the like, the insulating films 106 and 107 are the insulating film 114 and 116 as a second insulating film, the insulating film 118 as a third insulating film, In the transistor 100, the oxide semiconductor film 12 The oxide semiconductor film 120a functions as a pixel electrode used in a display device, and the oxide semiconductor film 120b functions as a transistor. It functions as the second gate electrode of the transistor 100 .

[0040] In addition, the oxide semiconductor film 108 is formed on the oxide semiconductor film 104 side, which functions as the first gate electrode. and an oxide semiconductor film 108c on the oxide semiconductor film 108b. In addition, one or both of the oxide semiconductor film 108b and the oxide semiconductor film 108c Both of them contain In, M (wherein M is Al, Ga, Y, or Sn), and Zn.

[0041] For example, the oxide semiconductor film 108b may be made of a material in which the atomic ratio of In is larger than the atomic ratio of M. It is preferable to use a material other than the oxide semiconductor film 108c. It is preferable to use a material in which the atomic ratio of In is smaller than that of b.

[0042] The oxide semiconductor film 108b is made of a material in which the atomic ratio of In is larger than the atomic ratio of M. The field effect mobility (sometimes simply referred to as mobility, or μFE) of the transistor 100 is Specifically, the field effect mobility of the transistor 100 can be increased by 10c m 2 / Vs, and more preferably the field effect mobility of the transistor 100 is greater than 30 cm 2 / Vs can be exceeded.

[0043] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. By using this as a driver, a semiconductor device or display device with a narrow frame width (also called a narrow frame) can be provided. Furthermore, the transistor having high field-effect mobility can be effectively used in a display device. A source driver (especially a shift register of the source driver) that supplies a signal to the signal line By using it in a multi-channel digital multi-channel (a demultiplexer connected to the output terminal of a digital multi-channel digital multi-channel) Therefore, it is possible to provide a display device with a small number of wirings.

[0044] On the other hand, the oxide semiconductor film 108b is made of a material in which the atomic ratio of In is larger than the atomic ratio of M. However, if the transistor 100 has a high conductivity, the electrical characteristics of the transistor 100 are likely to fluctuate when irradiated with light. In the semiconductor device of one embodiment of the present invention, an oxide semiconductor film 108b is formed on the oxide semiconductor film 108c. In other words, the oxide semiconductor film 108 has a multilayer structure. The oxide semiconductor film 108c is made of a material having a lower atomic ratio of In than the oxide semiconductor film 108b. Since the oxide semiconductor film 108 is made of a material, it can have a larger Eg than the oxide semiconductor film 108b. Therefore, the oxide semiconductor film 108b and the oxide semiconductor film 108c are stacked in a stacked structure. The compound semiconductor film 108 can have improved resistance to a negative bias stress test using light.

[0045] In addition, the oxide semiconductor film 108, particularly the channel region of the oxide semiconductor film 108b, Impurities such as hydrogen and moisture are problematic because they affect transistor characteristics. Therefore, in the channel region of the oxide semiconductor film 108b, hydrogen, moisture, and the like are present. The fewer the impurities, the better. The oxygen vacancies that occur are problematic because they affect transistor characteristics. When oxygen vacancies are formed in the channel region of the membrane 108b, hydrogen bonds to the oxygen vacancies, A carrier supply source is generated in the channel region of the oxide semiconductor film 108b. When the oxide semiconductor film 108b is formed, the electric characteristics of the transistor 100 including the oxide semiconductor film 108b are changed. Generally, a shift in the threshold voltage occurs. In the hole region, the fewer oxygen deficiencies the better.

[0046] In view of this, in one embodiment of the present invention, an insulating film in contact with the oxide semiconductor film 108, specifically The insulating film 107 formed under the oxide semiconductor film 108 and the oxide semiconductor film 108 The insulating films 114 and 116 formed above the insulating film 10 contain excess oxygen. 7, and oxygen or excess oxygen is transferred from the insulating films 114 and 116 to the oxide semiconductor film 108. By increasing the temperature, oxygen vacancies in the oxide semiconductor film can be reduced. To suppress the fluctuation of the electrical characteristics of the transistor 100, particularly the fluctuation of the transistor 100 due to light irradiation. This becomes possible.

[0047] In one embodiment of the present invention, the insulating film 107 and the insulating films 114 and 116 are treated with an excess of oxygen. In order to incorporate the element, there is no increase in the manufacturing process or the increase in the manufacturing process is extremely small. Therefore, the yield of the transistor 100 can be increased.

[0048] Specifically, in the step of forming the oxide semiconductor film 108b, a sputtering method is used. In addition, by forming the oxide semiconductor film 108b in an atmosphere containing oxygen gas, the oxide semiconductor Oxygen or excess oxygen is added to the insulating film 107, which is the surface on which the film 108b is to be formed.

[0049] In addition, in the step of forming the oxide semiconductor films 120a and 120b, a sputtering method The oxide semiconductor films 120a and 120b are formed in an atmosphere containing oxygen gas using The insulating film 116, which is the surface on which the oxide semiconductor films 120a and 120b are to be formed, is exposed to oxygen or excess oxygen. When oxygen or excess oxygen is added to the insulating film 116, the insulating film 11 Oxygen or excess oxygen is also contained in the insulating film 114 and the oxide semiconductor film 108 located below the insulating film 6. May be added.

[0050] <1-2. Oxygen added to insulating films> Here, the following samples A1 to A3 were prepared and evaluated for the oxygen added to the insulating film. The oxygen added to the insulating film will be described with reference to FIGS.

[0051] [Structure of Samples A1 to A3] First, the structures of samples A1 to A3 will be described. FIG. 4A illustrates the structure of sample A1. 4(A) is a schematic cross-sectional view illustrating the structure of sample A1; FIG. 4(B) is a schematic cross-sectional view illustrating the structure of sample A2; 1C is a schematic cross-sectional view illustrating the structure of sample A3.

[0052] The sample A1 shown in FIG. 4A includes a substrate 102 and an oxide semiconductor film 108 over the substrate 102. 4B, the insulating films 114 and 116 are formed on the oxide semiconductor film 108. The sample A2 includes a substrate 102, an oxide semiconductor film 108 on the substrate 102, and an oxide semiconductor film 108, and an oxide semiconductor film 120b on the insulating film 116. 4C, a sample A3 is formed by stacking a substrate 102 and an oxide semiconductor layer on the substrate 102. The oxide semiconductor film 108, the insulating films 114 and 116 on the oxide semiconductor film 108, and the oxide semiconductor film on the insulating film 116. The insulating film 118 is formed on the oxide semiconductor film 120b.

[0053] In the cross-sectional schematic diagrams shown in Figs. 4(A), (B), and (C), The components having the same functions as the components of the transistor 100 shown in FIG. The same reference numerals and hatching are used.

[0054] [Method for preparing sample A1] Next, a method for fabricating Sample A1 will be described. First, an oxide semiconductor film 1 was formed on a substrate 102. The oxide semiconductor film 108 was formed by sputtering using a sputtering apparatus. Argon gas with a flow rate of 100 sccm and argon gas with a flow rate of 100 sccm were placed in the chamber of the ring device. and oxygen gas were introduced into the sputtering chamber. =1:1:1.2 [atomic %] metal oxide sputtering target, 2.5kW power The power supply applied to the metal oxide sputtering target was An AC power supply was used as the power source. The thickness of the oxide semiconductor film 108 was set to 35 nm.

[0055] Next, insulating films 114 and 116 were formed over the oxide semiconductor film 108. A silicon oxynitride film with a thickness of 50 nm was formed using a PECVD apparatus. The insulating film 116 is a silicon oxynitride film having a thickness of 400 nm, which is deposited by using a PECVD apparatus. The insulating film 114 and the insulating film 116 were formed by vacuum deposition using a PECVD apparatus. It formed continuously inside.

[0056] The conditions for forming the insulating film 114 were a substrate temperature of 220° C. and a silica flow rate of 50 sccm. Nitrogen gas and nitrous oxide gas at a flow rate of 2000 sccm were introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 116 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 kJ / cm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was introduced into the chamber between the parallel plate electrodes installed in the PECVD device. The film was formed by supplying RF power of 1500 W to the substrate.

[0057] Next, a heat treatment was carried out at 350°C for 1 hour in a nitrogen gas atmosphere. .

[0058] Sample A1 was fabricated through the above steps.

[0059] [Preparation method of sample A2] As the sample A2, an oxide semiconductor film 108 and insulating films 114 and 116 were formed on a substrate 102. The process up to the heat treatment was the same as that for sample A1.

[0060] Next, the oxide semiconductor film 120b was formed over the insulating film 116. As the substrate, a 100 nm thick In-Ga-Zn oxide film (hereinafter referred to as IGZO film) was used. The substrate temperature was set to 170°C, and oxygen gas ( 18 O) into the chamber The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn=4:2:4.1 (atomic ratio). .

[0061] Sample A2 was fabricated through the above steps.

[0062] [Preparation method of sample A3] As the sample A3, an oxide semiconductor film 108 and insulating films 114 and 116 were formed on a substrate 102. Then, heat treatment was performed to form an oxide semiconductor film 120b over the insulating film 116. The oxide semiconductor film 120b is formed by a method similar to that of Sample A2.

[0063] Next, the insulating film 118 was formed over the oxide semiconductor film 120b. A silicon nitride film having a thickness of 100 nm was formed using a PECVD apparatus. The film formation conditions were a substrate temperature of 350°C, silane gas at a flow rate of 50 sccm, and Nitrogen gas at a flow rate of 1000 sccm and ammonia gas at a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 100 Pa, and 2 The film was formed by supplying a high frequency power of 1000 W using a 7.12 MHz high frequency power supply.

[0064] Sample A3 was fabricated through the above steps.

[0065] <1-3. Secondary Ion Mass Spectrometry (SIMS) Oxygen concentration in insulating films measured by spectrometry Next, SIMS analysis was carried out on the samples A1 to A3 prepared above. The elements to be analyzed are: 18 In addition, the SIMS analysis was carried out on the silicon oxide film. Quantitative analysis was performed using SiO2 as a standard.

[0066] The SIMS analysis results are shown in Figure 1. In Figure 1, the vertical axis represents 18 The horizontal axis is the O concentration. The horizontal axis indicates the depth from the surface of the oxide semiconductor film 120b to the surface of the oxide semiconductor film 120b. In FIG. 1, the solid line represents the measurement result of sample A1, and the thin dashed line represents the measurement result of sample A2. The thick dashed line indicates the measurement result of sample A2, and the thick dashed line indicates the measurement result of sample A3. 16 (silicon oxide film) 18 The concentration of O contained in the silicon oxide film 18 Natural occurrence of O The concentration was obtained from the current ratio (0.2%). The method of analyzing from the substrate side, known as SSDP-SIMS (Substrate Side D epth Profile Secondary Ion Mass Spectrom etry).

[0067] As shown in FIG. 1, the samples A2 and A3 in which the oxide semiconductor film 120b was formed had an insulating film 11 4, 116, 18 O has a concentration gradient. More specifically, the concentration gradient is The insulating film 116 has a region where the oxygen concentration increases toward the surface. When the oxygen concentration profile is viewed from the film 120b side, the oxygen concentration near the surface of the insulating film 116 is The oxygen concentration is increased toward the insulating film 114 side. The oxide semiconductor film 108 has a region where the oxygen concentration is high in the vicinity of the oxide semiconductor film 108. In other words, it can be said that the oxygen concentration gradient is U-shaped.

[0068] By setting the oxygen concentration gradient as described above, oxygen can be suitably added to the oxide semiconductor film 108. In addition, oxygen vacancies in the oxide semiconductor film 108 can be filled with excess oxygen. As a result, a highly reliable semiconductor device can be realized.

[0069] <1-4. Hydrogen Concentration in Insulating Films and Oxide Semiconductor Films by SIMS> Next, the insulating films 114 and 116 and the oxide semiconductor film 10 included in the sample A2 fabricated as described above were removed. The hydrogen concentration in the films 8 and 120b was analyzed by SIMS. The element to be analyzed was H. In addition, the SIMS analysis was performed using the IGZO film as the standard. Quantitative analysis was carried out using a silicon oxide film (SiO2) as a standard.

[0070] The SIMS analysis results are shown in Figures 2(A)(B) and 3(A)(B). A)(B) are the SIMS analysis results of sample A2, and Fig. 3(A)(B) are the SIMS analysis results of sample A3. The results of MS analysis are shown in Figures 2(A) and 3(A). Figures 2(B) and 3(B) show quantitative results based on silicon oxide film (SiO2). This is the result.

[0071] In addition, in Figures 2(A)(B) and 3(A)(B), the vertical axis represents the H concentration and the horizontal axis represents the depth. 2A and 2B, the horizontal axis represents the thickness of the oxide semiconductor film 120b. 3(A) and 3(B), the thickness of the insulating film 118 near the surface is set to 0 nm. The vicinity of the surface was set to 0 nm. In addition, the SIMS analysis was performed using a method of analyzing from the substrate 102 side ( The method used was SSDP-SIMS.

[0072] From the results shown in FIGS. 2(A) and 2(B) and 3(A) and 3(B), it is clear that the insulating films 114 and 116 There is no significant difference in the hydrogen concentration between the sample A2 and the sample A3. This suggests that hydrogen contained in the insulating film 8 does not penetrate into the insulating films 114 and 116. On the other hand, the hydrogen concentration in the oxide semiconductor film 120b is higher in Sample A3 than in Sample A2. This is because the formation of the insulating film 118 allows hydrogen contained in the insulating film 118 to react with the oxide semiconductor. It is suggested that it has penetrated into the body membrane 120b.

[0073] Thus, it was confirmed that hydrogen was added from the insulating film 118 to the oxide semiconductor film 120b. Therefore, the carrier concentration in the oxide semiconductor film 120b can be increased. The semiconductor film 120b can be used as an oxide conductive film.

[0074] <1-5. Thermal Desorption Spectroscopy (TDS) Regarding the amount of oxygen released from insulating films during spectroscopy Next, the amount of oxygen released from the insulating film containing excess oxygen was evaluated. In order to measure the amount of oxygen released from the insulating film, the following samples B1 to B6 were prepared: The amount of oxygen released in TDS was evaluated.

[0075] [Structures of Samples B1 to B6] First, samples B1 to B6 will be described. Samples B1 to B6 were formed under the following conditions: This is a sample to confirm the amount of oxygen added to the insulating film by changing the temperature.

[0076] As samples B1 to B6, a silicon oxynitride film having a thickness of 400 nm was formed on a glass substrate. The silicon oxynitride film was formed using a PECVD device and then heat-treated. The substrate temperature was set to 350°C, and the flow rate of silane gas was 160 sccm and the flow rate of 4000 nitrous oxide gas (200 sccm) was introduced into the chamber, and the pressure was set to 200 Pa. The formation was performed by supplying 1500 W of RF power between parallel plate electrodes placed in a VD device. The heat treatment conditions were as follows: using an RTA device, treatment was performed at 650°C for 6 minutes in a nitrogen atmosphere. The heat treatment causes oxygen contained in the silicon oxynitride film during film formation to be released. After the heat treatment, a 50-nm-thick oxide semiconductor film was deposited on the silicon oxynitride film by sputtering. After that, the oxide semiconductor film was removed to expose the surface of the silicon oxynitride film. Note that the conditions for forming the oxide semiconductor films were different among Samples B1 to B6.

[0077] [Formation conditions for sample B1] The oxide semiconductor film of Sample B1 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 180 Argon gas at a flow rate of 20 sccm and oxygen gas at a flow rate of 20 sccm were introduced into the chamber. That is, the atmosphere was set to 10% oxygen gas, the pressure was set to 0.6 Pa, and the sputtering equipment was set The target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was heated to 2500W. It was formed by supplying AC power.

[0078] [Formation conditions for sample B2] The oxide semiconductor film of Sample B2 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 100 Argon gas at a flow rate of 100 sccm and oxygen gas at a flow rate of 100 sccm were introduced into the chamber. That is, the atmosphere was set to 50% oxygen gas and the pressure was set to 0.6 Pa. The target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was heated to 2500W. It was formed by supplying AC power.

[0079] [Formation conditions for sample B3] The oxide semiconductor film of Sample B3 was formed under the conditions of a substrate temperature of 170° C. and a flow rate of 200 Oxygen gas was introduced into the chamber at a rate of 100 sccm, i.e., the atmosphere was 100% oxygen gas. The pressure was set to 0.6 Pa, and the target (In:Ga:Z n=4:2:4.1 [atomic ratio]) was supplied with 2500 W of AC power.

[0080] [Formation conditions for sample B4] The oxide semiconductor film of Sample B4 was formed under the following conditions: the substrate temperature was room temperature, and the flow rate was 50 scc. Argon gas at a flow rate of 3 sccm and oxygen gas at a flow rate of 3 sccm were introduced into the chamber. The gas atmosphere was set to 6% and the pressure was set to 0.4 Pa. - target (In2O3:SnO2:SiO2 = 85:10:5 [weight ratio]) 1000W The DC power was supplied to form the

[0081] [Formation conditions for sample B5] The oxide semiconductor film of Sample B5 was formed under the following conditions: the substrate temperature was room temperature, and the flow rate was 25 scc. Argon gas at a flow rate of 25 sccm and oxygen gas at a flow rate of 25 sccm were introduced into the chamber. The atmosphere was set to 50% nitrogen gas and the pressure was set to 0.4 Pa. The target (In2O3:SnO2:SiO2 = 85:10:5 [weight ratio]) was The device was formed by supplying 0 W of DC power.

[0082] [Formation conditions for sample B6] The oxide semiconductor film of Sample B6 was formed under the following conditions: the substrate temperature was room temperature, and the flow rate was 50 scc. m of oxygen gas was introduced into the chamber, i.e., the atmosphere was 100% oxygen gas, and the pressure was The pressure was 0.4 Pa, and the target (In2O3:SnO2 The film was formed by supplying 1000 W of DC power to a silicon dioxide film (SiO2 = 85:10:5 [weight ratio]).

[0083] Next, mass released from the silicon oxynitride films of Samples B1 to B6 fabricated as described above was measured. The charge ratio (M / z) was 32, which corresponds to the amount of released gas equivalent to oxygen (O2). The amount of gas released was measured using a TDS device. The amount of gas released, equivalent to oxygen, was measured when the surface temperature of the film was in the range of 50°C to 600°C. .

[0084] The TDS measurement results of samples B1 to B6 are shown in FIG. 6. In FIG. 6, the vertical axis represents M / z= The horizontal axis shows the release amount of 32, and the horizontal axis shows the sample name.

[0085] From the results shown in Figure 6, the emission amount of M / z=32 for sample B1 was 1.19 × 10 14 [pcs / c m 3 In addition, the amount of emission of M / z=32 in sample B2 was 5.02 × 10 14 [pcs / c m 3 In addition, the amount of M / z=32 released from sample B3 was 1.14 × 10 15 [pcs / c m 3 In addition, the amount of emission of M / z=32 in sample B4 was 4.09 × 10 13 [pcs / c m 3 In addition, the amount of emission of M / z=32 in sample B5 was 3.11 × 10 14 [pcs / c m 3 In addition, the amount of emission of M / z=32 in sample B6 was 8.40 × 10 14 [pcs / c m 3 ] was.

[0086] In this way, the insulating film (here, the silicon oxynitride film) on the surface where the oxide semiconductor film is to be formed is By forming an oxide semiconductor film in an oxygen atmosphere by a sputtering method, In particular, it was suggested that oxygen can be added to the oxide semiconductor film under the conditions of oxygen gas. By increasing the gas flow rate, a large amount of oxygen can be added to the insulating film.

[0087] <1-6. Oxide conductors> Next, the oxide conductor will be described. In the step of forming the oxide semiconductor films 120a and 120b, A function of supplying excess oxygen into the insulating films 114 and 116, or a function of removing oxygen from the insulating films 114 and 116. It functions as a protective film that suppresses the release of elements.

[0088] The oxide semiconductor films 120a and 120b are formed before the step of forming the insulating film 118. After the step of forming the insulating film 118, the insulating film 118 functions as a semiconductor. The semiconductor films 120a and 120b function as conductors.

[0089] In order for the oxide semiconductor films 120a and 120b to function as conductors, the oxide semiconductor Oxygen vacancies are formed in the films 120a and 120b, and hydrogen is added to the oxygen vacancies from the insulating film 118. As a result, a donor level is formed near the conduction band. The oxide semiconductor films 120a and 120b have high conductivity and become conductive. 0b can be referred to as oxide conductors. 120b may be referred to as an oxide conductor (OC). Generally, oxide semiconductors have a large energy gap and are therefore transparent to visible light. On the other hand, an oxide conductor is an oxide semiconductor having a donor level near the conduction band. Therefore, the influence of absorption due to donor levels is small in oxide conductors, and they do not absorb visible light. It has the same level of transparency as nitride semiconductors.

[0090] Here, in a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film), The port resistance will be described with reference to FIGS.

[0091] [Structures of Samples C1 to C8] Here, samples C1 to C8 having an oxide conductor film were fabricated. The structure of sample 8 will be explained using Figures 7(A), (B), and (C). 7(B) and (C) are top views of the dashed lines Z1 to Z8 shown in FIG. 2 is a cross-sectional schematic diagram corresponding to the cross section of FIG.

[0092] The samples C1 and C2 are made of a substrate 302, conductive films 312a and 312b on the substrate 302, and , insulating films 314 and 316 on the substrate 302 and the conductive films 312a and 312b, and the insulating film 316 The insulating films 314 and 316 have a conductive film 31 Openings 352a, 352b, 352c, and 352d are provided that reach into 2a.

[0093] Samples C3 to C8 are made of a substrate 302, conductive films 312a and 312b on the substrate 302, and a substrate Insulating films 314 and 316 on the plate 302 and the conductive films 312a and 312b, and insulating film 316 The insulating film 318 includes an oxide semiconductor film 320 and an insulating film 318 over the oxide semiconductor film 320. The insulating films 314 and 316 have openings 352a, 352b, and 352c that reach the conductive film 312a. The insulating film 318 is provided with openings 352c and 352d that reach the conductive film 312a. 54a, 354b are provided.

[0094] As described above, the samples C1 and C2 have the insulating film 318 different from the samples C3 to C8. This is a structure that is not provided.

[0095] In Samples C1 to C8, the oxide semiconductor film 320 has openings 352a, 352b, and 352c. The conductive film 312a is electrically connected to the conductive films 312a and 312b via the conductive film 52c. It functions as a measurement pad for measuring the port resistance.

[0096] The length L of the oxide semiconductor film 320 is set to 10 cm, and the width W of the oxide semiconductor film 320 is set to It was set to 10 μm.

[0097] The substrate 302, conductive films 312a and 312b, and insulating film shown in FIGS. 7(A), 7(B), and 7(C) 314, the insulating film 316, the insulating film 318, and the oxide semiconductor film 320 are the same as those shown in FIG. The substrate 102, the conductive films 112a and 112b, the insulating film 114, the insulating film 116, and the insulating film 11 8 and the oxide semiconductor film 120a.

[0098] [Preparation method of sample C1] First, a method for manufacturing the sample C1 will be described. A conductive film is formed on a substrate 302. The conductive film was processed to form conductive films 312a and 312b. A glass substrate was used. The conductive films 312a and 312b were made of 50 nm thick tongue films. A stainless steel film, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm were formed by spat. The layers were successively formed in a vacuum using a pulverizing apparatus.

[0099] Next, insulating films 314 and 316 were formed on the substrate 302 and the conductive films 312a and 312b. The insulating film 314 is a silicon oxynitride film having a thickness of 50 nm, which is deposited using a PECVD apparatus. The insulating film 316 was formed by depositing a silicon oxynitride film having a thickness of 400 nm on a substrate. The insulating film 314 and the insulating film 316 were formed using an ECVD apparatus. The layers were formed continuously in a vacuum using a VD device.

[0100] The conditions for forming the insulating film 314 were a substrate temperature of 220° C. and a silica flow rate of 50 sccm. Nitrogen gas and nitrous oxide gas at a flow rate of 2000 sccm were introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 316 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 kJ / cm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was introduced into the chamber between the parallel plate electrodes installed in the PECVD device. The film was formed by supplying RF power of 1500 W to the substrate.

[0101] Next, a first heat treatment was carried out at 350° C. in a nitrogen gas atmosphere. It was set to one hour.

[0102] Next, openings 352a and 352b reaching the conductive film 312a and a conductive film 312b are formed. Openings 352a, 352b, 352c, 352d were formed. d was formed using a dry etching device.

[0103] Next, a film is formed on the insulating film 316 so as to cover the openings 352a, 352b, 352c, and 352d. The oxide semiconductor film 32 is formed on the substrate 10 and processed. The oxide semiconductor film 320 was formed by adding silicon oxide to a thickness of 100 nm. The indium tin oxide film (In-Sn-Si oxide: hereinafter referred to as ITSO) was then heated at a substrate temperature of 10000 K. The chamber was heated to room temperature and argon gas with a flow rate of 72 sccm and oxygen gas with a flow rate of 5 sccm. The atmosphere was set to 6.5% oxygen gas, the pressure was set to 0.4 Pa, and the spa The target (In2O3:SnO2:SiO2 = 85:1) placed in the quartz crystallization device The mixture was formed by supplying 1000 W of DC power to a mixture of 1000 W and 1000 W of SiO2 (0:5 [weight ratio]).

[0104] Next, a second heat treatment was carried out at 250° C. in a nitrogen gas atmosphere. The time was set to 1 hour. Sample C1 was prepared through the above steps.

[0105] [Preparation method of sample C2] Sample C2 differs from Sample C1 described above only in the formation conditions of the oxide semiconductor film 320. Other than that, the fabrication method was the same as that of sample C1.

[0106] The oxide semiconductor film 320 of the sample C2 was an ITSO film having a thickness of 100 nm, which was grown at a substrate temperature of The temperature was set to room temperature, and oxygen gas was introduced into the chamber at a flow rate of 50 sccm. The atmosphere was 0.00% and the pressure was 0.4 Pa. The target placed in the sputtering device (In2O3:SnO2:SiO2=85:10:5 [weight ratio]) C power was supplied to form the

[0107] [Preparation method of sample C3] Next, a manufacturing method of Sample C3 will be described. The above samples were formed using the same materials and by the same manufacturing method as sample C2.

[0108] Next, an insulating film 318 was formed over the insulating film 316 and the oxide semiconductor film 320. As the substrate 318, a silicon nitride film having a thickness of 100 nm was formed using a PECVD apparatus. The conditions for forming the insulating film 318 were a substrate temperature of 350° C. and a silicate gas flow rate of 50 sccm. Ammonia gas with a flow rate of 100 sccm, nitrogen gas with a flow rate of 5000 sccm, and , was introduced into the chamber, the pressure was set to 100 Pa, and a parallel A 27.12MHz high-frequency power supply was used to supply 1000W of high-frequency power between the flat electrodes. The film was formed.

[0109] Next, openings 354a and 354b were formed in desired regions of the insulating film 318. 4a and 354b were formed using a dry etching device.

[0110] [Method for preparing samples C4 to C8] Samples C4 to C8 were prepared by forming the oxide semiconductor film 320 under the same conditions as Sample C3. The only difference was the thickness of the sample C1, and the other manufacturing methods were the same as those for sample C3.

[0111] [Sample C4] The oxide semiconductor film 320 of sample C4 was an IGZO film having a thickness of 100 nm, and was grown at a substrate temperature of The temperature was set to 170°C, oxygen gas was introduced into the chamber at a flow rate of 200 sccm, and the pressure was set to 0.6 The sputtering target was a polycrystalline metal oxide (In:Ga:Zn=1:1: The film was formed by applying 2500 W of AC power to a sample with an atomic ratio of 1.2.

[0112] [Sample C5] The oxide semiconductor film 320 of sample C5 was an IGZO film with a thickness of 35 nm, and the substrate temperature was The temperature was set to 170°C, and oxygen gas was introduced into the chamber at a flow rate of 200 sccm. The atmosphere was 100% and the pressure was 0.6 Pa. The target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was subjected to 2500W of AC power. The mixture was added and a film was formed.

[0113] [Sample C6] The oxide semiconductor film 320 of sample C6 was an IGZO film with a thickness of 50 nm, and the substrate temperature was The temperature was set to 170°C, and oxygen gas was introduced into the chamber at a flow rate of 200 sccm. The atmosphere was 100% and the pressure was 0.6 Pa. The target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was subjected to 2500W of AC power. The mixture was added and a film was formed.

[0114] [Sample C7] The oxide semiconductor film 320 of sample C7 was an IGZO film having a thickness of 100 nm, and was grown at a substrate temperature of The temperature was set to 170°C, and oxygen gas was introduced into the chamber at a flow rate of 200 sccm. The atmosphere was 100% gas, the pressure was 0.6 Pa, and polycrystalline metal oxide sputtering was performed. The target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was supplied with 2500W of AC power. was added to form a film.

[0115] [Sample C8] The oxide semiconductor film 320 of sample C8 was a first IGZO film having a thickness of 50 nm, The temperature was set to 170°C, and oxygen gas was introduced into the chamber at a flow rate of 300 sccm. The atmosphere was 100% nitrogen gas, and the pressure was 0.8 Pa. Polycrystalline metal oxide sputtering was performed. The target (In:Ga:Zn=1:3:6 [atomic ratio]) was subjected to an AC power of 2500 W. Then, a second IGZO film with a thickness of 50 nm was formed at a substrate temperature of 170°C. Argon gas at a flow rate of 180 sccm and oxygen gas at a flow rate of 20 sccm were introduced into the chamber. In other words, the atmosphere was made of 10% oxygen gas, the pressure was set to 0.6 Pa, and the polycrystalline metal Oxide sputtering target (In:Ga:Zn=4:2:4.1 [atomic ratio]) The film was formed by applying 2500 W of AC power.

[0116] [Sheet resistance] Next, the sheet resistance of the samples C1 to C8 was measured. , the conductive film 312a exposed from the openings 352b and 352d shown in FIGS. A probe was brought into contact with the oxide semiconductor film 312b, and the sheet resistance of the oxide semiconductor film 320 was measured. One of the conductive films 312a and 312b is set to ground potential, and the other is set to 0.01V. was applied.

[0117] The results of measuring the sheet resistance of samples C1 to C8 are shown in FIG. 8. In FIG. The horizontal axis indicates the sample name.

[0118] From the results shown in FIG. 8, it can be seen that the samples C1, C3, and C5 to C8 Port resistance is 1.0 x 10 2 Ω / cm 2 Over 1.0 x 10 4 Ω / cm 2 It turns out that That is, the oxide semiconductor films used in Samples C1, C3, and C5 to C8 320 is a degenerate semiconductor, and the bottom of the conduction band and the Fermi level are the same or almost the same. On the other hand, in samples C2 and C4, the sheet resistance is estimated to be 1.0 × 10 4 Ω / cm 2 The value exceeded this.

[0119] As described above, the oxide semiconductor film 320 is formed from the material used and the oxide semiconductor film 320 It is suggested that the resistance can be arbitrarily controlled by the presence or absence of the insulating film 318 formed thereon. Therefore, the oxide semiconductor film 320 functions not only as an electrode but also as a resistor. It was confirmed that it also has the function of a child.

[0120] <1-7. Components of semiconductor device> The components included in the semiconductor device of this embodiment will be described in detail below.

[0121] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and A fire substrate or the like may be used as the substrate 102. Also, silicon or silicon carbide may be used as the material. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductors such as silicon germanium, etc. It is also possible to apply a substrate, an SOI substrate, etc., and a semiconductor element is provided on these substrates. The substrate 102 may be a glass substrate. If you are using 6th generation (1500mm x 1850mm), 7th generation (1870mm x 220 0mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 280 By using large area substrates such as 10th generation (2950mm x 3400mm), Larger display devices can be fabricated.

[0122] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0123] [Conductive Films Functioning as First Gate Electrode, Source Electrode, and Drain Electrode] A conductive film 104 that functions as a gate electrode and a conductive film 112 that functions as a source electrode The conductive film 112b functioning as a drain electrode is made of chromium (Cr), copper (C u), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (M o), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), a metal element selected from nickel (Ni), iron (Fe), cobalt (Co), or the above Alloys containing metal elements or alloys combining the above metal elements are used, respectively. It can be formed.

[0124] The conductive films 104, 112a, and 112b may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride film Two-layer structure with tungsten film laminated on top, tantalum nitride film or tungsten nitride film Two-layer structure with tungsten film stacked, titanium film, and aluminum film stacked on the titanium film. There are also three-layer structures, such as a titanium film on top of an aluminum film. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of these may be used.

[0125] The conductive films 104, 112a, and 112b are made of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light-transmitting properties, such as indium tin oxide doped with silicon oxide, is used. It is also possible.

[0126] The conductive films 104, 112a, and 112b are made of a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. This allows for processing using a wet etching process, which reduces manufacturing costs. It becomes possible.

[0127] [Insulating film functioning as first gate insulating film] The insulating films 106 and 107 functioning as gate insulating films of the transistor 100 are Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon oxide is deposited by vapor deposition, sputtering, etc. silicon oxide film, silicon nitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film , hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, oxide Tantalum film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film The insulating films 106 and 107 may each be an insulating layer containing one or more films. Instead of the laminated structure, a single layer insulating film selected from the above materials or an insulating film with three or more layers may also be used.

[0128] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain excess acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0129] Note that the oxide semiconductor film 108, which functions as a channel region of the transistor 100, is in contact with the oxide semiconductor film 108. The insulating film 107 is preferably an oxide insulating film, and the oxide content is in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen-excess region). The insulating film 107 is an insulating film capable of releasing oxygen. To provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Oxygen may be added to the insulating film 107 after it has been formed. More on this later.

[0130] Furthermore, when hafnium oxide is used as the insulating film 107, the following effects are achieved. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared to the case where silicon oxide is used, the thickness of the insulating film 107 can be made larger, so that the tunnel This reduces the leakage current due to the current flowing through the transistor. Furthermore, hafnium oxide, which has a crystalline structure, can be used to form amorphous structures. Therefore, the off-state current is small. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic crystals. The types are not limited to these.

[0131] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so The gate insulating film of the transistor 150 is made physically thick by including a silicon nitride film. Therefore, the decrease in the dielectric strength voltage of the transistor 100 can be suppressed, and further, the dielectric strength can be improved. The edge breakdown voltage can be improved, and electrostatic breakdown of the transistor 100 can be suppressed.

[0132] [Oxide semiconductor film] The oxide semiconductor film 108 can be formed using the above-described materials.

[0133] When the oxide semiconductor film 108b is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose satisfies In>M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is I n:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4 .1, In:M:Zn=5:1:7, etc.

[0134] In addition, when the oxide semiconductor film 108c is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form the film is In≦M. It is preferable that the atomic ratio of the metal elements in such a sputtering target is In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn= 1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, etc. .

[0135] The oxide semiconductor film 108b and the oxide semiconductor film 108c are made of In-M-Zn oxide. In this case, the sputtering target is a target containing polycrystalline In-M-Zn oxide. It is preferable to use a target containing polycrystalline In-M-Zn oxide. Therefore, the oxide semiconductor films 108b and 108c having crystallinity can be easily formed. Note that the atomic ratio between the oxide semiconductor film 108b and the oxide semiconductor film 108c to be formed is are the atomic ratios of the metal elements contained in the sputtering target as errors. For example, the sputtering of the oxide semiconductor film 108b When the atomic ratio of In:Ga:Zn=4:2:4.1 is used as the target, the film formation The atomic ratio of the oxide semiconductor film 108b is approximately In:Ga:Zn=4:2:3. Alternatively, the oxide semiconductor film 108b may be formed by sputtering an atomic When the numerical ratio of In:Ga:Zn=5:1:7 is used, the oxide semiconductor film 108b is formed. The atomic ratio of In:Ga:Zn may be approximately In:Ga:Zn=5:1:6.

[0136] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. eV or more, more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In particular, the oxide semiconductor film 108b has an energy gap of 2 eV or more, preferably 2 e The oxide semiconductor film 108c has an energy It is preferable to use an oxide semiconductor film having a gap of 2.5 eV or more and 3.5 eV or less. In addition, the energy gap of the oxide semiconductor film 108c is larger than that of the oxide semiconductor film 108b. The larger one is preferable.

[0137] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a thickness of 3n m or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 200 nm or less. The thickness is set to 50 nm or more.

[0138] The oxide semiconductor film 108c is an oxide semiconductor film with low carrier density. For example, the oxide semiconductor film 108c has a carrier density of 1×10 17 pieces / cm 3 Below is good Preferably 1 x 10 15 pieces / cm 3 or less, more preferably 1 × 1013 pieces / cm 3 below, More preferably 1 × 10 11 pieces / cm 3 The following applies.

[0139] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, the oxide semiconductor film 108b and the oxide semiconductor The carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic ratio, It is preferable to set the distance, density, etc. appropriately.

[0140] Note that the oxide semiconductor films 108b and 108c each contain impurities. By using an oxide semiconductor film with a low concentration of impurities and a low density of defect states, it is possible to obtain even better electrical properties. In this case, the impurity concentration is low, and A low density of defect levels (low oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a carrier generation source. Therefore, the carrier density can be reduced. The transistor in which the hole region is formed has electrical characteristics in which the threshold voltage is negative (normal It is also called "on." It is rare for it to become a high-purity intrinsic or substantially high-purity intrinsic In some oxide semiconductor films, the density of defect states is low, and therefore the density of trap states may also be low. Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. Very small, with a channel width of 1×10 6 Even if the element has a channel length L of 10 μm, When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 After A The following characteristics can be obtained.

[0141] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are lost. It takes a long time for the charge to dissipate, and it can behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0142] The hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. The oxygen vacancies are formed in the lattice from which oxygen is desorbed (or in the portions from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can bond with oxygen, which bonds with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor film 108 obtained by SIMS analysis is degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than or equal to 5x1, more preferably 0 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 below Let's say.

[0143] The oxide semiconductor film 108b has a region with a lower hydrogen concentration than the oxide semiconductor film 108c. The oxide semiconductor film 108b preferably has a region where the oxide semiconductor film 108c has a larger thickness than the oxide semiconductor film 108b. By having a region with a low hydrogen concentration, a highly reliable semiconductor device can be obtained.

[0144] In addition, silicon and carbon, which are Group 14 elements, are contained in the oxide semiconductor film 108b. If the oxide semiconductor film 108b contains oxygen, oxygen vacancies increase in the oxide semiconductor film 108b, causing the oxide semiconductor film 108b to become n-type. Therefore, the concentrations of silicon and carbon in the oxide semiconductor film 108b and the oxide semiconductor film 10 The concentration of silicon and carbon near the interface with 8b (concentration obtained by SIMS analysis) is 2× 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following do.

[0145] In addition, in the oxide semiconductor film 108b, the alkali metal or or alkaline earth metal concentration is 1×10 18 atoms / cm 3 Below, preferably 2x 1016 atoms / cm 3 The alkali metals and alkaline earth metals are oxides. When bonded to a semiconductor, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkaline earth metal in the oxide semiconductor film 108b is It is preferable to reduce the concentration of metalloids.

[0146] When nitrogen is contained in the oxide semiconductor film 108b, electrons serving as carriers are generated. The carrier density increases and the oxide semiconductor film containing nitrogen is easily converted to n-type. A transistor using the oxide semiconductor film tends to be normally on. In the present invention, it is preferable that the nitrogen content is reduced as much as possible. For example, it is possible to determine by SIMS analysis that the nitrogen content is reduced as much as possible. The resulting nitrogen concentration is 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0147] The oxide semiconductor film 108b and the oxide semiconductor film 108c each have a non-single-crystal structure. The non-single crystal structure may be, for example, a CAAC-OS (C Axis Aliphatic Crystal) structure, which will be described later. gned Crystalline Oxide Semiconductor), polyconductor The non-single crystalline structure includes a crystalline structure, a microcrystalline structure, or an amorphous structure. The defect density of CAAC-OS is the lowest.

[0148] [Insulating film functioning as second gate insulating film] The insulating films 114 and 116 function as a second gate insulating film of the transistor 100 . The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108 . That is, the insulating films 114 and 116 contain oxygen. The insulating film 114 is an insulating film that can form an insulating film 116 to be formed later. The oxide semiconductor film 108 also functions as a film for reducing damage to the oxide semiconductor film 108 during the formation of the oxide semiconductor film 108.

[0149] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0150] Furthermore, it is preferable that the insulating film 114 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 3 x 10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects contained is high, oxygen will be bonded to the defects, and the oxygen in the insulating film 114 will The amount of transmission of light decreases.

[0151] In the insulating film 114, all the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, Oxygen may move in the film 114. When the oxide insulating film capable of forming the insulating film 114 is formed, the insulating film 116 and the insulating film 116 are formed on the insulating film 114. The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0152] The insulating film 114 is formed using an oxide insulating film with a low density of states due to nitrogen oxides. Note that the density of states due to the nitrogen oxide can be determined by the valence Energy of the top of the electronic band (Ev_os) and energy of the bottom of the conduction band of the oxide semiconductor film The oxide insulating film may be formed between the gate electrode and the gate electrode of the nitride semiconductor layer. Silicon oxynitride film with low emission or aluminum oxynitride film with low nitrogen oxide emission For example, a silicon film or the like can be used.

[0153] In addition, a silicon oxynitride film that emits a small amount of nitrogen oxides can be analyzed by thermal desorption spectroscopy. This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of release is 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 55°C or lower. The amount released by heating at 0°C or below.

[0154] Nitrogen oxides (NO x , x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO or NO forms a level in the insulating film 114. The oxides of nitrogen are located within the energy gap of the insulating film 114 and the film 108. When the oxide semiconductor film 108 diffuses to the interface between the insulating film 114 and the oxide semiconductor film 108, the level As a result, the trapped electrons may be trapped in the insulating film 114 and the oxide semiconductor. Since it remains near the interface of the conductor film 108, the threshold voltage of the transistor is shifted in the positive direction. It makes them do it.

[0155] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with the ammonia contained in the insulating film 116 during the heat treatment. Therefore, the nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0156] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor can be reduced. It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0157] Note that the heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less. The first signal has a g value of 2.037 or more and 2.039 or less, and the second signal has a g value of 2.001 or more. A second signal less than .003 and a third signal with a g value between 1.964 and 1.966. The split width of the first signal and the second signal, and the The split width of the second signal and the third signal is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 or more and 2.039 or less, and the g value is 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The total spin density of the third signal is 1×10 18 spins / cm 3 Less than Typically, it is 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Not yet It is full.

[0158] In addition, the g value is between 2.037 and 2.039 in the ESR spectrum below 100K. The first signal has a g value of 2.001 or more and 2.003 or less, and the second signal has a g value of 1 The third signal, between 0.964 and 1.966, is nitrogen oxide (NO x , x is greater than 0 These correspond to signals caused by nitrogen oxides (<2 or less, preferably 1 to 2). Examples include nitrogen monoxide and nitrogen dioxide. That is, the g value is between 2.037 and 2.039. a first signal having a g value of 2.001 or more and 2.003 or less, and a second signal having a g value of The smaller the sum of the spin densities of the third signals, which are between 1.964 and 1.966, the This means that the amount of nitrogen oxide contained in the oxide insulating film is small.

[0159] The oxide insulating film has a nitrogen concentration of 6×10 as measured by SIMS. 20 atoms / cm 3 The following is the result.

[0160] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film using a VD method, a dense and hard film can be obtained. It can be formed.

[0161] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric value. The oxide insulating film had a desorption of 1.0 x 10 oxygen atoms in TDS analysis. 1 9 atoms / cm 3 or more, preferably 3.0 × 1020 atoms / cm 3 That's all The surface temperature of the film in the above TDS is 100°C or higher and 70°C or lower. A temperature of 0°C or lower, or a temperature in the range of 100°C to 500°C is preferred.

[0162] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., of 400 nm or less can be used.

[0163] Furthermore, it is preferable that the insulating film 116 has a small number of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is 1.5 x 10 18 spins / cm 3 Less than, or even 1×10 18 spins / cm 3 It is preferable that the insulating film 116 has a higher oxide semiconductor content than the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0164] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating film In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a broken line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single-layer structure.

[0165] [An oxide semiconductor film functioning as a pixel electrode and an oxide semiconductor film functioning as a second gate electrode] Semiconductor film] The oxide semiconductor film 120a functions as a pixel electrode, and the oxide semiconductor film 120b functions as a second gate electrode. The oxide semiconductor film 120b may be made of the same material as the oxide semiconductor film 108 described above. and similar manufacturing methods.

[0166] Alternatively, the oxide semiconductor film 120a serving as a pixel electrode and the oxide semiconductor film 120b serving as a second gate electrode may be formed of a metal oxide. The oxide semiconductor film 120b that functions as the oxide semiconductor film 108 described above is For example, the oxide semiconductor films 120a and 120b include In oxide, In-Sn oxide, In-Zn oxide, In-Ga oxide, Zn oxide , Al-Zn oxide, or In-Ga-Zn oxide, etc. can be used. It is preferable to use In-Sn oxide or In-Ga-Zn oxide.

[0167] Specifically, the oxide semiconductor films 120a and 120b are made of indium gallium zinc oxide. oxide (IGZO), indium tin oxide (ITO), indium zinc oxide, indium Tin silicon oxide (ITSO) or the like can be used.

[0168] That is, the oxide semiconductor film 120a functioning as a pixel electrode and the second gate electrode The oxide semiconductor film 120b that functions as the oxide semiconductor film 108 (the oxide semiconductor film 108 b and the oxide semiconductor film 108c). The oxide semiconductor film 120b serving as a second gate electrode and the oxide semiconductor film 108 (oxide the oxide semiconductor film 108b and the oxide semiconductor film 108c contain the same metal element. This makes it possible to reduce manufacturing costs.

[0169] For example, the oxide semiconductor film 120a serving as a pixel electrode and the oxide semiconductor film 120b serving as a second gate electrode In the case of In-M-Zn oxide, the oxide semiconductor film 120b that functions as a The atomic ratio of the metal elements in the sputtering target used to form a Zn oxide film is: It is preferable that In≧M is satisfied. The molecular ratios were In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M: Examples include Zn=4:2:4.1 and In:M:Zn=5:1:7.

[0170] In addition, the oxide semiconductor film 120a functions as a pixel electrode, and the oxide semiconductor film 120b functions as a second gate electrode. The structure of the functional oxide semiconductor film 120b may be a single layer structure or a stacked structure of two or more layers. In the case where the oxide semiconductor films 120a and 120b have a stacked-layer structure, The composition of the oxide semiconductor film 120a is not limited to the above-mentioned sputtering target. The case where 120b has a laminated structure will be described later.

[0171] [Insulating film that functions as a protective insulating film for transistors] The insulating film 118 functions as a protective insulating film for the transistor 100.

[0172] The insulating film 118 contains either hydrogen or nitrogen, or both. The insulating film 118 contains nitrogen and silicon. The insulating film 118 contains oxygen, hydrogen, water, and alkali. The insulating film 118 has a function of blocking metals, alkaline earth metals, etc. As a result, oxygen diffuses from the oxide semiconductor film 108 to the outside, and oxygen contained in the insulating films 114 and 116 is The diffusion of oxygen from the oxide semiconductor film 108 to the outside and the penetration of hydrogen, water, and the like from the outside into the oxide semiconductor film 108 are prevented. It can be prevented.

[0173] The insulating film 118 is formed between the oxide semiconductor film 120a functioning as a pixel electrode and the second The oxide semiconductor film 120b serving as a gate electrode contains hydrogen and / or nitrogen. In particular, the insulating film 118 contains hydrogen and converts the hydrogen into an oxide. It is preferable that the insulating film 118 has a function of supplying the insulating film 118 to the oxide semiconductor films 120a and 120b. When hydrogen is supplied to the oxide semiconductor films 120a and 120b, the oxide semiconductor films 120a , 120b function as a conductor.

[0174] The insulating film 118 may be, for example, a nitride insulating film. Examples include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. etc.

[0175] Note that the various films described above, such as the conductive film, insulating film, and oxide semiconductor film, are formed by sputtering. It can be formed by a coating method or a PECVD method, but other methods, such as thermal CVD (Ch It may be formed by thermal vapor deposition (CVD). As an example of the method, MOCVD (Metal Organic Chemical Vapor Deposition) Deposition (Atomic Layer Deposition) and ALD (Atomic Layer Deposition) n) method may also be used.

[0176] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0177] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0178] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence. For example, by switching between two or more types of switching valves (also called high-speed valves), The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the fuel gas. In case of simultaneously introducing an inert gas, the inert gas is The second source gas may be introduced as a carrier gas, and an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction order until a desired thickness is achieved. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin FETs.

[0179] Thermal CVD methods such as MOCVD and ALD can be used to form conductive films, insulating films, and oxides in the above-described embodiments. It can form various films such as semiconductor films and metal oxide films. For example, In-Ga-Zn When forming an O film, trimethylindium, trimethylgallium, and dimethylzinc are used. Lead is used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is The compound is Zn(CH3)2. The compound is not limited to these combinations, and may be trimethylgalactose. Triethylgallium (chemical formula Ga(C2H5)3) can be used instead of diethylgallium. Diethylzinc (chemical formula Zn(C2H5)2) can also be used instead of methylzinc.

[0180] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is vaporized hafnium amide (such as TDMAH) and acid Two types of gases are used: tetrakisdimethylamide (TDMA) and ozone (O3) as a chlorine gas. The chemical formula for Hf is Hf[N(CH3)2]4. Other materials include tetrahydrofuran, Examples include rakis(ethylmethylamido) hafnium.

[0181] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0182] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, removing the chlorine contained in the adsorbed material, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0183] For example, when forming a tungsten film using an ALD deposition system, WF6 An initial tungsten film is formed using WF6 gas and B2H6 gas, and then WF6 gas and H2 The tungsten film is formed using SiH4 gas instead of B2H6 gas. It may be used.

[0184] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed using a film formation device that uses ALD. When forming a film, an In-O layer is formed using In(CH3)3 gas and O3 gas. Then, a GaO layer is formed using Ga(CH3)3 gas and O3 gas, and then Z The ZnO layer is formed using n(CH3)2 gas and O3 gas. The order of these layers is The example is not limited to this. In addition, by mixing these gases, an In-Ga-O layer or an In-Zn-O layer can be formed. Alternatively, a mixed compound layer such as a Ga-Zn-O layer may be formed. HO gas obtained by bubbling with an inert gas such as HCl may be used. However, O gas containing no H may be used. It is preferable to use In(C2H5) instead of In(CH3)3 gas. 3 gas may be used. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Alternatively, Zn(CH3)2 gas may be used.

[0185] <1-8. Configuration example 2 of semiconductor device> Next, examples of structures different from the transistor 100 shown in FIGS. 5A, 5B, and 5C will be described. Explain using 9(A)(B)(C).

[0186] FIG. 9A is a top view of a transistor 150 which is a semiconductor device of one embodiment of the present invention. 9(B) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 9(A). 9(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 9(A). Correct.

[0187] The transistor 150 has an opening 152 in the channel width direction of the transistor 100 shown above. The difference is that the transistors 152b and 152c are provided. 00 and has the same effect. We will explain about this.

[0188] As shown in FIG. 9C, the oxide semiconductor film 120b functioning as the second gate electrode , the insulating films 106, 107, and the openings 152b, 152c provided in the insulating films 114, 116. 2c, it is connected to the conductive film 104 that functions as the first gate electrode. The same potential is applied to the oxide semiconductor film 104 and the oxide semiconductor film 120b.

[0189] In this embodiment, openings 152b and 152c are provided to separate the conductive film 104 and the acid However, the present invention is not limited to this. For example, only one of the openings 152b and 152c is formed, and the conductive film 5. The oxide semiconductor film 104 may be connected to the oxide semiconductor film 120b. Unlike the transistor 100, the conductive film 104 and the oxide semiconductor film 120b are not connected to each other. In this case, different potentials are applied to the conductive film 104 and the oxide semiconductor film 120b. This can be done.

[0190] As shown in FIG. 9B, the oxide semiconductor film 108 functions as a first gate electrode. and the oxide semiconductor film 120b functioning as a second gate electrode. The second electrode is sandwiched between two films that function as gate electrodes. The length in the channel length direction of the oxide semiconductor film 120b functioning as the gate electrode of The length in the channel width direction is the length of the oxide semiconductor film 108 in the channel length direction and the The length of the oxide semiconductor film 108 is longer than the length of the insulating films 114 and 116. The oxide semiconductor film 120b is covered with the oxide semiconductor film 120b. The compound semiconductor film 120b and the conductive film 104 functioning as the first gate electrode are connected to an insulating film 106 , 107, and the insulating films 114, 116 are connected in openings 152b, 152c. Therefore, the side surfaces of the oxide semiconductor film 108 in the channel width direction are covered with the insulating films 114 and 116. The gate electrode 120b faces the oxide semiconductor film 120b functioning as the second gate electrode with a gate electrode interposed therebetween.

[0191] In other words, in the channel width direction of the transistor 150, The conductive film 104 and the oxide semiconductor film 120b functioning as the second gate electrode are Insulating films 106 and 107 function as first gate insulating films and The insulating films 114 and 116 are connected to each other through openings, and the first gate The insulating films 106 and 107 function as the first gate insulating film and the insulating film 108 function as the second gate insulating film. The oxide semiconductor film 108 is surrounded by insulating films 114 and 116 interposed therebetween.

[0192] With such a structure, the oxide semiconductor film 108 included in the transistor 150 The conductive film 104 functions as a first gate electrode and the conductive film 105 functions as a second gate electrode. The transistor 150 can be electrically surrounded by the electric field of the oxide semiconductor film 120b. As shown above, a channel region is formed by the electric field of the first gate electrode and the second gate electrode. The device structure of the transistor that electrically surrounds the oxide semiconductor film is called the Surround This can be called an ed channel (S-channel) structure.

[0193] Since the transistor 150 has an S-channel structure, The conductive film 104 functions as a gate electrode, and the electric field for inducing the channel is effectively applied to the oxide semiconductor. This allows the voltage to be applied to the body film 108, improving the current driving capability of the transistor 150. It is possible to obtain high on-current characteristics. It is also possible to increase the on-current. Therefore, it is possible to miniaturize the transistor 150. The conductive film 104 functions as a first gate electrode and the oxide film 105 functions as a second gate electrode. Since the transistor 150 has a structure surrounded by the oxide semiconductor film 120b, Strength can be increased.

[0194] <1-9. Configuration example 3 of semiconductor device> Next, examples of structures different from the transistor 100 shown in FIGS. 5A, 5B, and 5C will be described. Explain using 10(A)(B)(C).

[0195] FIG. 10A is a top view of a transistor 160 which is a semiconductor device of one embodiment of the present invention. 10(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 10(A). 10(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 10(A). This corresponds to a cross-sectional view.

[0196] The transistor 160 is a combination of the transistor 100 shown above and an oxide film that functions as a pixel electrode. The gate electrode is made of an oxide semiconductor film 120a and an oxide semiconductor film 120b that functions as a second gate electrode. The other configurations are the same as those of the transistor 100, and the same effects are achieved. The following describes the configurations that are different from the transistor 100.

[0197] The oxide semiconductor film 120a of the transistor 160, which functions as a pixel electrode, is The semiconductor layer 120a has a stacked structure of a nitride semiconductor film 120a_1 and an oxide semiconductor film 120a_2. The oxide semiconductor film 120b serving as a second gate electrode of the transistor 160 120b_1 and an oxide semiconductor film 120b_2 are stacked on top of each other.

[0198] The oxide semiconductor film 120a and the oxide semiconductor film 120b are stacked to form a layer structure. Oxygen can be suitably introduced into the insulating film 116. , the oxide semiconductor film 120b, and the insulating film 118 are stacked together, whereby hydrogen contained in the insulating film 118 is This can prevent the intrusion into the insulating film 116.

[0199] The oxide semiconductor film 120a_1 and the oxide semiconductor film 120b_1 are formed using a The atomic ratio of the metal elements in the sputtering target preferably satisfies In≦M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn= 1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M :Zn=1:3:4, In:M:Zn=1:3:6, etc.

[0200] The oxide semiconductor film 120a_2 and the oxide semiconductor film 120b_2 are formed using a The atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn= 1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M :Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:7 etc. Examples include:

[0201] In addition, when the oxide semiconductor films 120a and 120b have a two-layer stack structure, the oxide semiconductor film The flow rate of the oxygen gas used to form the first oxide semiconductor film is lower than the flow rate of the oxygen gas used to form the oxide semiconductor film. The flow rate of the oxygen gas used to form the first oxide semiconductor film is preferably high. By increasing the amount of oxygen, oxygen can be suitably added to the insulating film 116, particularly to the surface of the insulating film 116. In addition, the flow rate of oxygen gas can be reduced when forming the second oxide semiconductor film. This makes it possible to reduce the resistance of the oxide semiconductor film.

[0202] By configuring the oxide semiconductor film 120a and the oxide semiconductor film 120b as described above, Furthermore, a semiconductor device with excellent reliability can be provided.

[0203] <1-10. Configuration example 4 of semiconductor device> Next, examples of a configuration different from that of the transistor 150 shown in FIGS. Explain using 11(A)(B)(C).

[0204] FIG. 11A is a top view of a transistor 170 which is a semiconductor device of one embodiment of the present invention. 11(B) is a cross-sectional view taken along the dashed line X1-X2 in FIG. 11(A). 11(C) corresponds to the cross section taken along the dashed line Y1-Y2 in FIG. 11(A). This corresponds to a cross-sectional view.

[0205] The transistor 170 is a combination of the transistor 150 shown above and an oxide film that functions as a pixel electrode. The gate electrode is made of an oxide semiconductor film 120a and an oxide semiconductor film 120b that functions as a second gate electrode. The other configurations are the same as those of the transistor 150, and the same effects are achieved. In addition, regarding the structures of the oxide semiconductor films 120a and 120b, may be the same as the transistor 160 described above.

[0206] <1-11. Configuration example 5 of semiconductor device> Next, modifications of the transistor 150 shown in FIGS. 9A, 9B, and 9C and FIG. 11A will be described. Modifications of the transistor 170 shown in (B) and (C) will be explained with reference to FIGS. 12 to 14. Reveal.

[0207] 12A and 12B are cross-sectional views of modified examples of the transistor 150 shown in FIGS. 9B and 9C. 12C and 12D show the transistor 170 shown in FIGS. FIG.

[0208] The transistor 150A shown in FIGS. 12A and 12B is the same as the transistor shown in FIGS. 9B and 9C. The oxide semiconductor film 108 included in the gate electrode 150 has a three-layer structure. The oxide semiconductor film 108 included in the transistor 150A includes an oxide semiconductor film 108a and The oxide semiconductor film 108b and the oxide semiconductor film 108c are included.

[0209] The transistor 170A shown in FIGS. 12(C) and 12(D) is the same as the transistor shown in FIGS. 11(B) and 11(C). The oxide semiconductor film 108 included in the transistor 170 has a three-layer structure. The oxide semiconductor film 108 included in the transistor 170A is an oxide semiconductor film 108a. , an oxide semiconductor film 108b, and an oxide semiconductor film 108c.

[0210] Here, the band structure of the insulating film in contact with the oxide semiconductor films 108a, 108b, and 108c is 13. The band structures of the insulating films in contact with the oxide semiconductor films 108b and 108c are shown in FIG. This will be used to explain.

[0211] FIG. 13A illustrates the insulating film 107, the oxide semiconductor films 108a, 108b, and 108c, and This is an example of a band structure in the film thickness direction of a laminated structure including an insulating film 114. ) is a multilayer structure including the insulating film 107, the oxide semiconductor films 108b and 108c, and the insulating film 114. This is an example of a band structure in the film thickness direction of a layer structure. Therefore, the insulating film 107, the oxide semiconductor films 108a, 108b, and 108c, and the insulating film 114 are electrically conductive. The energy level (Ec) at the bottom of the conductive band is shown.

[0212] In addition, in FIG. 13(A), silicon oxide films are used as the insulating films 107 and 114, and oxide semiconductor films are used. The conductor film 108a is made of a metal oxide film having an atomic ratio of In:Ga:Zn=1:1:1.2. The oxide semiconductor film 108b was formed using an oxide semiconductor film formed using an oxide target. A metal oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 was used. The oxide semiconductor film 108c is formed by using an oxide semiconductor film having a metal element number of 100 or less. The oxide formed using a metal oxide target with a ratio of In:Ga:Zn=1:1:1.2 FIG. 1 is a band diagram of a structure using a compound semiconductor film.

[0213] In addition, in FIG. 13(B), silicon oxide films are used as the insulating films 107 and 114, and oxide semiconductor films are used. The conductor film 108b is a metal oxide film having an atomic ratio of In:Ga:Zn=4:2:4.1. The oxide semiconductor film 108c was formed using an oxide semiconductor film formed using an oxide target. A metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1.2 was used. FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed by

[0214] As shown in FIGS. 13A and 13B, in the oxide semiconductor films 108a, 108b, and 108c, In other words, the energy level at the bottom of the conduction band changes smoothly. In order to have such a band structure, the oxide The interface between the oxide semiconductor film 108a and the oxide semiconductor film 108b, or the oxide semiconductor film 108b At the interface between the oxide semiconductor film 108c and the oxide semiconductor film 108b, defect quasi-crystallization such as trap centers and recombination centers occurs. Assume that there are no impurities that would form positions.

[0215] In order to form a continuous junction in the oxide semiconductor films 108a, 108b, and 108c, Each film is deposited using a multi-chamber deposition system (sputtering system) equipped with a lock chamber. It is necessary to continuously stack the layers without exposing them to the air.

[0216] 13A and 13B, the oxide semiconductor film 108b forms a well. In the transistor using the above stacked structure, the channel region is formed of the oxide semiconductor film 1 It can be seen that it is formed in 08b.

[0217] Note that the boundary between the oxide semiconductor film 108b and the insulating film (the insulating film 107 or the insulating film 114) The trap levels that may be formed near the surface are reduced by providing the oxide semiconductor films 108a and 108c. Therefore, the distance from the oxide semiconductor film 108b is increased.

[0218] In addition, the trap states are below the conduction band of the oxide semiconductor film 108b which functions as a channel region. The energy level (Ec) at the edge of the electron trap may be farther from the vacuum level, and electrons may be trapped in the trap level. When electrons accumulate in the trap level, negative fixed This results in a charge, and the threshold voltage of the transistor shifts in the positive direction. The trap level is lower than the energy level (Ec) of the conduction band minimum of the oxide semiconductor film 108b. It is preferable to configure the trap level so that it is close to the empty level. This makes it difficult for electrons to accumulate, which increases the on-state current of the transistor. , the field effect mobility can be increased.

[0219] The oxide semiconductor films 108a and 108c have a conduction band lower than that of the oxide semiconductor film 108b. The energy level of the edge is close to the vacuum level, and typically, and the energy levels of the conduction band minimums of the oxide semiconductor films 108a and 108c. The difference between the two is 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV That is, the electron affinity of the oxide semiconductor films 108a and 108c and the The difference between the electron affinity of the organic film 108b and the electron affinity of the organic film 108c is 0.15 eV or more, or 0.5 eV or more, and eV or less, or 1 eV or less.

[0220] With such a structure, the oxide semiconductor film 108b serves as a main current path. That is, the oxide semiconductor film 108b functions as a channel region, and the oxide semiconductor film 1 The oxide semiconductor film 108a and 108c function as oxide insulating films. a and 108c are metal elements constituting the oxide semiconductor film 108b in which the channel region is formed. Since the oxide semiconductor film 108a is made of one or more of the oxide semiconductor films 108a and 108b, The interface with the oxide semiconductor film 108b or the interface between the oxide semiconductor film 108b and the oxide semiconductor film 108c Therefore, the movement of carriers at the interface is Since the electrons are not blocked, the field effect mobility of the transistor is increased.

[0221] In addition, the oxide semiconductor films 108a and 108c function as part of a channel region. To prevent this, a material with sufficiently low conductivity is used. The films 108a and 108c are also called oxide insulating films based on their physical properties and / or functions. Alternatively, the oxide semiconductor films 108a and 108c may have a high electron affinity (vacuum level and conduction band the energy level of the oxide semiconductor film 108b is smaller than that of the oxide semiconductor film 108b, and the energy level of the oxide semiconductor film 108b is smaller than that of the oxide semiconductor film 108b. The difference between the energy level of the oxide semiconductor film 108b and the energy level of the bottom of the conduction band of the oxide semiconductor film 108b (band-off In addition, a material having a threshold value that depends on the magnitude of the drain voltage is used. In order to suppress the occurrence of a difference in the voltage between the oxide semiconductor films 108a and 108c, The energy level of the conduction band minimum of the oxide semiconductor film 108b is higher than the energy level of the conduction band minimum of the oxide semiconductor film 108b. For example, a material having a conductivity closer to a vacuum level than that of the oxide semiconductor film 108b is preferably used. The energy level of the conduction band minimum and the energy level of the oxide semiconductor films 108a and 108c The difference from the negative level is preferably 0.2 eV or more, more preferably 0.5 eV or more.

[0222] In addition, the oxide semiconductor films 108a and 108c do not contain a spinel crystal structure. It is preferable that the oxide semiconductor films 108a and 108c have a spinel crystal structure. When the spinel type crystal structure is contained, the conductive film 112a, 11 The constituent elements of 2b may diffuse into the oxide semiconductor film 108b. When the conductive films 108a and 108c are made of CAAC-OS, the structure of the conductive films 112a and 112b is This is preferable because it increases the blocking property of the component element, for example, copper element.

[0223] The thicknesses of the oxide semiconductor films 108a and 108c are determined by the amount of the constituent elements of the conductive films 112a and 112b. The insulating film has a thickness that is greater than or equal to a thickness that can prevent the insulating film from diffusing into the oxide semiconductor film 108b. The thickness of the oxide semiconductor film 108b is set to be less than the thickness that prevents oxygen from being supplied from the film 114 to the oxide semiconductor film 108b. When the thickness of the oxide semiconductor films 108a and 108c is 10 nm or more, the conductive films 112a and This can prevent the constituent elements of the oxide semiconductor film 112b from diffusing into the oxide semiconductor film 108b. In addition, when the thickness of the oxide semiconductor films 108a and 108c is 100 nm or less, the insulating film 114 Oxygen can be effectively supplied from the oxide semiconductor film 108b to the oxide semiconductor film 108b.

[0224] In this embodiment, the oxide semiconductor films 108a and 108c are formed by adding a metal element. The atomic ratio of In:Ga:Zn was 1:1:1.2. However, the present invention is not limited to this. The compound semiconductor films 108a and 108c have an atomic ratio of In:Ga:Zn=1:1:1. In:Ga:Zn=1:3:2 [atomic ratio], In:Ga:Zn=1:3:4 [atomic ratio] ], or a metal oxide target with In:Ga:Zn=1:3:6 [atomic ratio] A formed oxide semiconductor film may be used.

[0225] The oxide semiconductor films 108a and 108c were formed using a compound of In:Ga:Zn=1:1:1 [primary When a metal oxide target having a molecular weight ratio of 100 to 1000 is used, the oxide semiconductor films 108a and 108c have a In:Ga:Zn=1:β1(0<β1≦2):β2(0<β2≦2) The oxide semiconductor films 108a and 108c are formed of In:Ga:Zn=1:3:4 [atomic When a metal oxide target having a molecular weight ratio of 100 to 1000 is used, the oxide semiconductor films 108a and 108c have a In:Ga:Zn=1:β3(1≦β3≦5):β4(2≦β4≦6) The oxide semiconductor films 108a and 108c are formed of In:Ga:Zn=1:3:6 [atomic When a metal oxide target having a molecular weight ratio of 100 to 1000 is used, the oxide semiconductor films 108a and 108c have a In:Ga:Zn=1:β5(1≦β5≦5):β6(4≦β6≦8) .

[0226] In addition, the oxide semiconductor film 108c included in the transistor 150 and the transistor 150A In the drawing, the oxide semiconductor film 108c is exposed from the conductive films 112a and 112b. In other words, a part of the oxide semiconductor film has a depression. However, one embodiment of the present invention is not limited to this, and the conductive film 11 The oxide semiconductor film in the region exposed from 2a and 112b does not necessarily have to have a recess. An example is shown in Figure 14(A)(B)(C)(D). Figure 14(A)(B)(C)(D) shows 14A and 14B are cross-sectional views showing an example of a semiconductor device. The oxide semiconductor film 108c of the sintered body 150 has a structure without a recess, and the oxide semiconductor film 108c of the sintered body 150 has a structure without a recess, as shown in FIGS. 14(C) and 14(D). The oxide semiconductor film 108c of the transistor 150A shown above does not have a recess. do.

[0227] In addition, the transistor according to this embodiment can be freely combined with each of the above structures. It is possible to do this.

[0228] <1-12. Manufacturing method of semiconductor device> Next, a method for manufacturing the transistor 100, which is a semiconductor device of one embodiment of the present invention, will be described with reference to FIGS. 15 to 18.

[0229] 15(A) to 15(F), 16(A) to 16(F), and 17(A) 17(F) to 18(F) illustrate a method for manufacturing a semiconductor device. 15(A), (C), (E), 16(A), (C), (E), and 1 7(A), (C), and (E) and 18(A), (C), and (E) are cross-sectional views in the channel length direction. 15(B)(D)(F), 16(B)(D)(F), 17(B)(D)(F) 18(B), (D) and (F) are cross-sectional views in the channel width direction.

[0230] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, a conductive film 104 is formed, which functions as a first gate electrode. On the conductive film 104, insulating films 106 and 107 are formed to function as a first gate insulating film (see FIG. 15(A)(B)).

[0231] In this embodiment, a glass substrate is used as the substrate 102, and a gate electrode is formed on the substrate 102. As the conductive film 104, a tungsten film having a thickness of 100 nm is formed by sputtering. In addition, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 by the PECVD method. Then, a silicon oxynitride film having a thickness of 50 nm is formed as the insulating film 107 by the PECVD method. Form.

[0232] The insulating film 106 may have a stacked structure of silicon nitride films. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminated structure with a silicon film can be formed. An example of the three-layer laminated structure is as follows: It can be formed as follows.

[0233] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PE-CV was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency was generated. If a power of 2000 W is supplied using a frequency power supply and the thickness is formed to be 50 nm, good.

[0234] For the second silicon nitride film, silane at a flow rate of 200 sccm and 2000 sccm The PECVD equipment was operated using nitrogen at a flow rate of 2000 sccm and ammonia gas at a flow rate of 2000 sccm as raw material gases. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high frequency power supply A power of 2000 W may be supplied using a heater to form the film to a thickness of 300 nm.

[0235] The third silicon nitride film was formed using silane at a flow rate of 200 sccm and silane at a flow rate of 5000 sccm. The pressure in the reaction chamber was adjusted to 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power supply. It is sufficient to form it so that the thickness is 50 nm.

[0236] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during the formation can be 350° C. or less.

[0237] By forming the insulating film 106 as a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper (Cu) is used for 4, the following effects are achieved.

[0238] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has the function of releasing hydrogen and functions as a gate insulating film. The third silicon nitride film can improve the breakdown voltage of the insulating film. The hydrogen released from the silicon nitride film is small, and the hydrogen released from the second silicon nitride film is diffused. can be suppressed.

[0239] The insulating film 107 is formed by a method using an oxide semiconductor film 108 (more specifically, an oxide In order to improve the interface characteristics with the oxide semiconductor film 108b), the insulating film is formed of an oxygen-containing insulating film. preferable.

[0240] Next, an oxide semiconductor film 108b_0 and an oxide semiconductor film 108c_0 are formed over the insulating film 107. (See Figures 15(C)(D)(E)(F)).

[0241] 15C and 15D show a case where an oxide semiconductor film 108b_0 is formed on the insulating film 107. 15(C) and 15(D) are schematic cross-sectional views of the inside of a film forming apparatus when a spatula is used as a film forming apparatus. A sputtering device is used, and a target 191 is installed inside the sputtering device. A plasma 192 formed below the target 191 is shown schematically.

[0242] First, when the oxide semiconductor film 108b_0 is formed, a first oxygen gas is added to the oxide semiconductor film 108b_0. The plasma is discharged. At this time, the insulating film on which the oxide semiconductor film 108b_0 is to be formed is Oxygen is added to the oxide semiconductor film 107. In addition to the oxygen gas in 1, inert gases (e.g., helium gas, argon gas, xenon gas) etc.) may be mixed.

[0243] The first oxygen gas is at least the oxygen gas contained in the oxide semiconductor film 108b_0. The first gas in the entire deposition gas when the oxide semiconductor film 108b_0 is formed may be the first gas. The proportion of oxygen gas is more than 0% and not more than 100%, preferably 10% to 100%. It is more preferably 30% or more and 100% or less.

[0244] In addition, in FIGS. 15C and 15D, oxygen or excess oxygen added to the insulating film 107 is This is shown schematically by dashed arrows.

[0245] Note that the substrate temperature during the formation of the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 was However, the thickness of the oxide semiconductor film 108b_0 and the thickness of the oxide semiconductor film 108b_1 may be the same or different. By making the substrate temperature the same as that of the conductive film 108c_0, the manufacturing cost can be reduced. This is preferable because it can be

[0246] For example, the substrate temperature when the oxide semiconductor film 108 is formed is set to a temperature higher than room temperature and lower than 340° C. Preferably, the temperature is from room temperature to 300°C, more preferably from 100°C to 250°C. The temperature is preferably 100° C. or higher and 200° C. or lower. By doing so, the crystallinity of the oxide semiconductor film 108 can be improved. Therefore, when using a large glass substrate (for example, 6th to 10th generations), oxide semiconductor When the substrate temperature during the deposition of the solid film 108 is set to 150° C. or higher and lower than 340° C., the substrate 102 Therefore, when using a large glass substrate, In this case, the substrate temperature during the formation of the oxide semiconductor film 108 is set to 100° C. or higher and lower than 150° C. By doing so, deformation of the glass substrate can be suppressed.

[0247] In addition, the sputtering gas must be highly purified. The oxygen gas and argon gas used in this process have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using the oxide semiconductor film, it is possible to prevent moisture and the like from being taken into the oxide semiconductor film as much as possible. .

[0248] In addition, when the oxide semiconductor film is formed by sputtering, The chamber is cladded to remove as much water as possible, which is an impurity for the oxide semiconductor film. A high vacuum (5×10) was used by using an adsorption type vacuum pump such as an ion pump. -7 Pa to 1× 10 -4 It is preferable to evacuate the gas to a temperature of about 100 Pa. Alternatively, a turbomolecular pump and a cold A trap is used to extract gases, especially gases containing carbon or hydrogen, from the exhaust system into the chamber. It is preferable to prevent backflow.

[0249] After the oxide semiconductor film 108b_0 is formed, the oxide semiconductor film 108c The oxide semiconductor film 108c_0 is formed on the oxide semiconductor film 108b_0. When forming O, plasma may be discharged in an atmosphere containing the second oxygen gas.

[0250] Note that the ratio of the first oxygen gas and the ratio of the oxide semiconductor The ratio of the second oxygen gas may be the same as or different from that used when forming the conductive film 108c_0. For example, when the oxide semiconductor film 108c_0 is formed, the second acid is contained in the entire deposition gas. The ratio of the elemental gas is more than 0% and not more than 100%, preferably 10% or more and not more than 100%. , and more preferably 30% or more and 100% or less.

[0251] Note that when the oxide semiconductor film 108c_0 is formed, the second oxygen gas and the argon gas are When using the above, it is preferable to make the flow rate of the argon gas greater than the flow rate of the second oxygen gas. By increasing the flow rate of argon gas, the oxide semiconductor film 108c_0 becomes a dense film. In addition, in order to form the oxide semiconductor film 108c_0 into a dense film, The substrate temperature when the oxide semiconductor film 108c_0 is formed is The oxidation temperature is typically 250°C or less, and preferably 150°C to 190°C. When the compound semiconductor film 108c_0 is a dense film, the gold contained in the conductive films 112a and 112b This can prevent metal elements from entering the oxide semiconductor film 108b_0.

[0252] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by sputtering, 0 was formed, and then successively in vacuum, an In-Ga-Zn metal oxide target (In: The oxide semiconductor was deposited by sputtering using Ga:Zn=1:1:1.2 (atomic ratio). The conductive film 108c_0 is formed. In addition, the substrate temperature during the formation of the oxide semiconductor film 108b_0 is The substrate temperature during the formation of the oxide semiconductor film 108c_0 is set to 170° C. The oxide semiconductor film 108b_0 was formed using an oxygen gas at a flow rate of 60 sccm. The oxide semiconductor film 108 was formed by the argon gas at a flow rate of 140 sccm. The deposition gas for forming c_0 was oxygen gas at a flow rate of 100 sccm and cm of argon gas is used.

[0253] Next, the oxide semiconductor film 108b_0 and the oxide semiconductor film 108c_0 are formed into a desired shape. By this process, island-shaped oxide semiconductor films 108b and 108c are formed. (See Figures 16(A) and 16(B)).

[0254] Next, a source electrode and a drain electrode are formed over the insulating film 107 and the oxide semiconductor film 108. Then, a conductive film 112 is formed by sputtering (see FIGS. 16C and 16D).

[0255] In this embodiment, the conductive film 112 is a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 40 A laminated film in which a 0 nm thick aluminum film and a 10 nm thick aluminum film are laminated in this order is formed by sputtering. In this embodiment, the conductive film 112 has a two-layer stacked structure, but the present invention is not limited to this. For example, the conductive film 112 may be a tungsten film having a thickness of 50 nm and a 400 nm thick tungsten film having a thickness of 400 nm. A three-layer laminate structure consisting of a 100 nm thick aluminum film and a 100 nm thick titanium film stacked in sequence. You may do so.

[0256] Next, the conductive film 112 is processed into a desired shape, thereby forming conductive films separated from each other. 112a and 112b are formed (see FIGS. 16(E) and 16(F)).

[0257] In this embodiment, the conductive film 112 is processed using a dry etching apparatus. However, the method for processing the conductive film 112 is not limited to this. For example, a wet etching method may be used. Note that the conductive film 112 may be formed by using a wet etching apparatus. The conductive film 112 can be processed by using a dry etching apparatus rather than by etching. On the other hand, a dry etching apparatus can be used to form a conductive film 1 It is preferable to process the conductive film 112 using a wet etching apparatus rather than processing the conductive film 12. The manufacturing cost can be reduced.

[0258] After the conductive films 112a and 112b are formed, the oxide semiconductor film 108 (more specifically, The surface (back channel side) of the oxide semiconductor film 108c may be cleaned. For example, cleaning using a chemical solution such as phosphoric acid can be used. By performing the cleaning, impurities (for example, impurities adhering to the surface of the conductive film 108c) are removed. The cleaning process can remove elements contained in 112a and 112b. In some cases, cleaning may not be necessary.

[0259] In addition, either one of the steps of forming the conductive films 112a and 112b and the cleaning step may be performed. In either case, the region of the oxide semiconductor film 108 exposed from the conductive films 112a and 112b is However, it may become thinner.

[0260] Next, the insulating film 114 and the conductive films 112a and 112b are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. An insulating film 116 is formed (see FIGS. 17(A) and (B)).

[0261] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposure to the air. After the insulating film 114 is formed, it is preferable to control the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the atmosphere. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. At the same time, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced. .

[0262] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. It is preferable to use the following gases. Typical examples of deposition gases containing silicon include silane, disilane, and the like. Examples of oxidizing gases include nitrous oxide, nitrous dioxide, etc. In addition, the flow rate of the oxidizing gas is set to be 20 times or more greater than the flow rate of the deposition gas. The pressure in the processing chamber is set to less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is set to less than 100 Pa. By using the PECVD method at a pressure of 50 Pa or less, preferably 50 Pa or less, the insulating film 114 is The insulating film contains the above and has a small amount of defects.

[0263] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220°C. Silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm were used as source gases. The pressure in the processing chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6 x 10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using the silicon oxynitride film.

[0264] The insulating film 116 is formed by depositing a substrate placed in a vacuum-evacuated processing chamber of a PECVD device. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the processing chamber. is set to 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less. , 0.17 W / cm to the electrode installed in the processing chamber 2 More than 0.5W / cm 2 Below are some more good ones: Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0265] The conditions for forming the insulating film 116 are as follows: a high frequency voltage of the above power density in a reaction chamber of the above pressure; By supplying power, the decomposition efficiency of the source gas in the plasma increases, and oxygen radicals increase. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes higher than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is As a result, the stoichiometric amount of oxygen in the film is reduced by the heat treatment in the subsequent process. Oxides that contain more oxygen than the stoichiometric composition and lose some of the oxygen when heated An insulating film can be formed.

[0266] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0267] In the film formation conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the number of defects in the insulating film 116. In the ESR measurement, the g value of 2.001, which is due to the dangling bond of silicon, The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5 × 10 17 spins / cm 3 The following is a missing An oxide insulating film with few defects can be formed. As a result, the signal quality of the transistor 100 can be improved. It can increase reliability.

[0268] After the insulating films 114 and 116 are formed, heat treatment (hereinafter referred to as first heat treatment) is performed. The first heat treatment is preferably performed to remove nitrogen oxides contained in the insulating films 114 and 116. Alternatively, the first heat treatment can reduce the amount of oxides in the insulating films 114 and 116. Part of the oxygen contained in the oxide semiconductor film 108 is transferred to the oxide semiconductor film 108. This can reduce the amount of oxygen vacancies.

[0269] The temperature of the first heat treatment is typically less than 400°C, preferably less than 375°C, and The first heat treatment is preferably performed at a temperature of 150° C. or higher and 350° C. or lower. Dry air (water content is 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb The reaction may be carried out under an atmosphere of air (see below) or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or rare gas does not contain hydrogen, water, etc. Heat treatment is performed using an electric furnace, RTA (Rapid Thermal Anneal), etc. It is possible.

[0270] Next, a mask is formed on the insulating film 116 by a lithography process, and the insulating films 114 and 11 An opening 152a is formed in a desired region of the conductive film 112b. (See Figures 17(C) and (D)).

[0271] Next, the oxide semiconductor film 120 is formed over the insulating film 116 so as to cover the opening 152a. (See Figures 17(E) and 17(F) and Figures 18(A) and 18(B)).

[0272] 17(E) and 17(F) show the state when the oxide semiconductor film 120 is formed on the insulating film 116. 17(E) and 17(F) are cross-sectional views of the inside of a film forming apparatus. A ring device is used, and a target 193 is installed inside the sputtering device. A plasma 194 formed below the get 193 is shown schematically.

[0273] First, when the oxide semiconductor film 120 is formed, a plasma is generated in an atmosphere containing a third oxygen gas. At this time, the insulating film 116 on which the oxide semiconductor film 120 is to be formed contains When the oxide semiconductor film 120 is formed, oxygen is added to the oxide semiconductor film 120. , by mixing inert gas (e.g., helium gas, argon gas, xenon gas, etc.) For example, argon gas and third oxygen gas may be used, and the flow rate of the argon gas may be set higher than that of the oxygen gas. It is preferable to increase the flow rate of the third oxygen gas. In this case, oxygen can be suitably added to the insulating film 116. For example, an oxide semiconductor film The formation condition of 120 is that the ratio of the third oxygen gas in the entire film formation gas is 50% or more. It is 100% or less, preferably 80% or more and 100% or less.

[0274] In addition, in FIGS. 17(E) and 17(F), the oxygen or excess oxygen added to the insulating film 116 is This is shown schematically by dashed arrows.

[0275] The substrate temperature during the formation of the oxide semiconductor film 120 is set to be equal to or higher than room temperature and lower than 340° C. , preferably from room temperature to 300°C, more preferably from 100°C to 250°C, The temperature is preferably 100° C. or higher and 200° C. or lower. This can improve the crystallinity of the oxide semiconductor film 120. Therefore, when a large glass substrate (for example, 6th to 10th generations) is used, the oxide semiconductor When the substrate temperature during the deposition of the film 120 is set to 150° C. or higher and lower than 340° C., the substrate 102 Therefore, when using a large glass substrate, In this case, the substrate temperature during the formation of the oxide semiconductor film 120 is set to 100° C. or higher and lower than 150° C. This makes it possible to suppress deformation of the glass substrate.

[0276] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=4: 2:4.1 [atomic ratio]) by sputtering to form the oxide semiconductor film 120. The substrate temperature during the formation of the oxide semiconductor film 120 is set to 170° C. The film-forming gas used in forming the compound semiconductor film 120 is oxygen gas at a flow rate of 100 sccm. .

[0277] The oxide semiconductor film 120 is not limited to the above composition. For example, the oxide semiconductor film 120 may be formed of the above-described oxide Semiconductor film (e.g., In:Ga:Zn=1:1:1 [atomic ratio], In:Ga:Zn=1 :3:2 [atomic ratio], In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn = 1:3:6 [atomic ratio], In:Ga:Zn = 3:1:2 [atomic ratio], In:Ga: Zn=4:2:3 [atomic ratio], etc.) may also be used.

[0278] The oxide semiconductor film 120 is formed in an atmosphere containing a third oxygen gas, thereby providing an insulating The film 116 may contain oxygen or excess oxygen near the surface.

[0279] Next, the oxide semiconductor film 120 is processed into a desired shape to form an island-shaped oxide semiconductor film 1 Then, an oxide semiconductor film 20a and an island-shaped oxide semiconductor film 120b are formed (see FIGS. 18C and 18D).

[0280] Next, the insulating film 118 is formed over the insulating film 116 and the oxide semiconductor films 120a and 120b. (See Figures 18(E) and 18(F)).

[0281] The insulating film 118 contains either hydrogen or nitrogen, or both. For example, a silicon nitride film is preferably used as the insulating film 118. For example, it can be formed by using a sputtering method or a PECVD method. When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to be less than 400° C., preferably 375° C. The temperature is preferably less than 180° C., and more preferably 180° C. or more and 350° C. or less. In this case, it is preferable to set the substrate temperature within the above range, since a dense film can be formed. By setting the substrate temperature in the above range when forming the insulating film 118, the insulating films 114 and 1 Oxygen or excess oxygen in the oxide semiconductor film 106 can be transferred to the oxide semiconductor film 108.

[0282] After the insulating film 118 is formed, a heat treatment similar to the first heat treatment described above (hereinafter referred to as the first heat treatment) is performed. In this manner, when the oxide semiconductor film 120 is formed, After adding oxygen to the insulating film 116, the insulating film 116 is heated to a temperature lower than 400° C., preferably lower than 375° C., Preferably, the insulating film 116 is subjected to heat treatment at a temperature of 180° C. or higher and 350° C. or lower. The oxygen or excess oxygen is transferred into the oxide semiconductor film 108 (particularly the oxide semiconductor film 108b). As a result, oxygen vacancies in the oxide semiconductor film 108 can be filled. A region with a high oxygen concentration can be formed near the surface of the conductive film 108.

[0283] Here, oxygen moving into the oxide semiconductor film 108 will be described with reference to FIGS. FIG. 19 shows the relationship between the substrate temperature (typically less than 375° C.) during the formation of the insulating film 118 and the temperature of the insulating film 118. The oxide semiconductor film 118 is formed by a second heat treatment (typically at a temperature lower than 375° C.). 19 is a model diagram showing oxygen moving into the oxide semiconductor 108. The oxygen (oxygen radical, oxygen atom, or oxygen molecule) shown in the film 108 is represented by a dashed arrow. are.

[0284] The oxide semiconductor film 108 shown in FIG. 19 is a film in contact with the oxide semiconductor film 108 (here, Oxygen vacancies are filled by the movement of oxygen from the insulating films 107 and 114. In particular, in the semiconductor device of one embodiment of the present invention, the oxide semiconductor film 108b is formed by sputtering. During film formation, oxygen gas is used to add oxygen to the insulating film 107. In addition, oxygen gas is used during the sputtering deposition of the oxide semiconductor film 120. Since oxygen is added to the insulating film 116, the insulating film 116 has an excess oxygen region. Therefore, the oxide semiconductor film 108 sandwiched between the insulating films having the excess oxygen region has a preferable oxygen vacancy. will be appropriately compensated.

[0285] Further, the insulating film 106 is provided below the insulating film 107, and the insulating films 114 and 11 An insulating film 118 is provided above the insulating films 106 and 118. By forming the insulating films 107, 114, and 116 from a thin material such as silicon nitride, Since the oxygen contained therein can be trapped in the oxide semiconductor film 108, the oxide semiconductor film 108 can be suitably oxidized. This allows oxygen to migrate to oxygen vacancies that may be formed in the compound semiconductor film 108.

[0286] The side edge of the oxide semiconductor film 108 is connected to the conductive film 10 4 and an oxide semiconductor film 120b functioning as a second gate electrode. Therefore, the oxide semiconductor film 108 with reduced oxygen vacancies is further By electrically covering the electrodes, a highly reliable semiconductor device can be realized.

[0287] The insulating film 118 contains either hydrogen or nitrogen, or both. By forming the insulating film 118, the oxide semiconductor films 120a and 120b in contact with the insulating film 118 are 0b has a high carrier density due to the addition of either hydrogen or nitrogen or both. The oxide conductive film can function as an oxide conductive film.

[0288] In addition, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, silicon It is preferable to use a deposition gas containing ammonium, nitrogen, and ammonia as source gases. By using a small amount of ammonia compared to the amount of oxygen, the ammonia dissociates in the plasma and becomes active. The activated species are formed by bonding silicon and hydrogen contained in the silicon-containing deposition gas. This breaks the triple bond between silicon and nitrogen, promoting the bonding of silicon and nitrogen. It is possible to form a dense silicon nitride film with few silicon and hydrogen bonds and few defects. On the other hand, if the amount of ammonia relative to nitrogen is high, the deposition gas containing silicon and nitrogen The decomposition of the silicon does not proceed, and silicon and hydrogen bonds remain, resulting in increased defects and roughness. For these reasons, the source gas is not suitable for ammonia. It is preferable that the flow rate ratio of nitrogen to oxygen is 5 times or more and 50 times or less, or 10 times or more and 50 times or less.

[0289] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, and the like using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed using nitrogen and ammonia as source gases. The flow rates were 50 sccm for silane, 5000 sccm for nitrogen, and 1000 sccm for ammonia. The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and the flow rate was 27.12 Mpa. A high-frequency power supply of 1000 W was used to supply high-frequency power to the parallel plate electrodes. The device has an electrode area of ​​6000 cm 2 It is a parallel plate type PECVD device, and the supplied voltage The force can be converted to power per unit area (power density) as 1.7 x 10 -1 W / cm 2 is .

[0290] In this embodiment, the insulating film 118 and the oxide semiconductor films 120a and 120b Hydrogen or nitrogen is added to the oxide semiconductor films 120a and 120b to increase the carrier density of the oxide semiconductor films 120a and 120b. However, the present invention is not limited to this. By performing treatment to add an impurity element to the oxide semiconductor films 120a and 120b, The carrier density of 0b may be increased.

[0291] The impurity elements are typically hydrogen, boron, carbon, nitrogen, fluorine, aluminum, and the like. Examples of rare gas elements include uranium, silicon, phosphorus, chlorine, and rare gas elements. The impurity elements are uranium, neon, argon, krypton, and xenon. When added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is broken, and oxygen vacancies are formed. Alternatively, when an impurity element is added to the oxide semiconductor film, the metal in the oxide semiconductor film is The oxygen that was bonded to the metal element bonds with the impurity element, and oxygen is released from the metal element, resulting in an oxygen deficiency. As a result, the carrier density in the oxide semiconductor film increases, and the conductivity becomes higher.

[0292] Through the above steps, the transistor 100 illustrated in FIGS.

[0293] Note that the transistor 100 has a bottom-gate structure. For example, By repurposing an amorphous silicon production line, there is no or very little capital investment required. It can be manufactured with little capital investment.

[0294] In addition, in all the manufacturing steps of the transistor 100, the substrate temperature is preferably less than 400° C. or less than 375°C, and more preferably between 180°C and 350°C. This is preferable because it is possible to minimize deformation (distortion or warpage) of the substrate even when using such a substrate. In the manufacturing process of the transistor 100, the substrate temperature is increased. Typically, the substrate temperature during the formation of the insulating films 106 and 107 is less than 400° C., preferably the substrate temperature during deposition of the oxide semiconductor film 108 (room temperature or higher, 3 Less than 40°C, preferably 100°C or more and 200°C or less, more preferably 100°C or more and 15 0°C), the substrate temperature during the formation of the insulating films 116 and 118 (less than 400°C, preferably 37 5°C or less, more preferably 180°C or more and 350°C or less), the first heat treatment or the second heat treatment Heat treatment (less than 400°C, preferably less than 375°C, more preferably 180°C or more to 35°C) (below 0°C)

[0295] In the above manufacturing method, the oxide semiconductor film 120 is formed over the insulating film 116. 1, a structure in which oxygen is added to the insulating film 116 when the oxide semiconductor film 120 is formed is illustrated. However, it is not limited to this.

[0296] For example, the manufacturing method shown in FIGS. 20 and 21 may be used. 21A to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device. 20(A), (C), (E) and 21(A) and (C) are diagrams showing the channel length direction. 20(B), (D), (F) and 21(B) and (D) are cross-sectional views of the channel width direction. FIG.

[0297] First, the steps up to FIGS. 16(E) and 16(F) are performed, and then the oxide semiconductor film 108 and the conductive film 108 are formed. Insulating films 114 and 116 are formed on the films 112a and 112b (see FIGS. 20(A) and (B)). .

[0298] After the insulating films 114 and 116 are formed, first heat treatment is preferably performed. The heat treatment in step 1 can reduce nitrogen oxides contained in the insulating films 114 and 116. Furthermore, part of the oxygen contained in the insulating films 114 and 116 is converted into oxide by the first heat treatment. The oxygen vacancies in the oxide semiconductor film 108 are reduced by transferring the oxygen vacancies to the oxide semiconductor film 108. can be done.

[0299] Next, the oxide semiconductor film 120 is formed over the insulating film 116. Then, oxygen 140 is added to the insulating films 116 and 114 or the oxide semiconductor film 108 (FIG. 2). 0(C)(D)).

[0300] 20(C) and 20(D), the insulating film 114 or the insulating film 116 is doped with Oxygen is schematically indicated by dashed arrows. By adding oxygen 140 to the insulating film 116, a large amount of oxygen is added near the surface of the insulating film 116. can be done.

[0301] In addition, oxygen 140 can be added to the insulating film 116 through the oxide semiconductor film 120 by The methods include ion doping, ion implantation, and plasma treatment. Depending on the device or conditions for adding, the insulating film 11 located below the insulating film 116 may be damaged. 4, or the oxide semiconductor film 108 may also be doped with oxygen 140. Examples of 40 include excess oxygen or oxygen radicals. When the insulating film 116 is formed, a bias is applied to the substrate side to effectively add oxygen 140 to the insulating film 116. The bias can be, for example, ashing equipment. The bias power density applied to the device was set to 1 W / cm 2 More than 5W / cm 2 The following should do: The oxide semiconductor film 120 is provided over the insulating film 116 and oxygen 140 is added thereto, whereby the oxide semiconductor film 120 is formed as an oxide semiconductor film. The semiconductor film 120 functions as a protective film that suppresses oxygen from being released from the insulating film 116. Therefore, more oxygen can be added to the insulating film 116.

[0302] In addition, oxygen 140 is added to the insulating film 116 through the oxide semiconductor film 120, and then the insulating film 116 is heated. The second heat treatment may be carried out in the same manner as the first heat treatment described above. This can be the same as heat treatment.

[0303] Next, the oxide semiconductor film 120 is removed to expose the surface of the insulating film 116. An insulating film 118 is formed on the film 116 (see FIGS. 20(E) and (F)).

[0304] When the oxide semiconductor film 120 is removed, part of the insulating film 116 may also be removed. The oxide semiconductor film 120 can be removed by dry etching, wet etching, or the like. Etching method, or a combination of dry etching and wet etching methods, etc. In this embodiment, a wet etching method is used to form an oxide semiconductor The oxide semiconductor film 120 is removed by wet etching. It is preferable to use such a material since it is possible to reduce manufacturing costs.

[0305] The insulating film 118 is formed by using, for example, a sputtering method or a PECVD method. For example, when the insulating film 118 is formed by the PECVD method, the substrate temperature is set to 40 It is less than 0°C, preferably less than 375°C, and more preferably 180°C or higher and 350°C or lower. By setting the substrate temperature in the above range when forming the insulating film 118, a dense film can be formed. In addition, it is preferable that the substrate temperature when forming the insulating film 118 is set within the above range. By this, oxygen or excess oxygen in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. It becomes possible to move it.

[0306] After the insulating film 118 is formed, a heat treatment (third heat treatment) equivalent to the second heat treatment described above is performed. After adding oxygen 140 to the insulating film 116, a heat treatment may be performed at a temperature of less than 400° C. Heat treatment is preferably carried out at a temperature of less than 375°C, more preferably at a temperature of 180°C or higher and 350°C or lower. By performing this process, oxygen or excess oxygen in the insulating film 116 is oxidized to the oxide semiconductor film 108 (particularly, the oxide and oxygen vacancies in the oxide semiconductor film 108 are filled by transferring the oxygen atoms into the oxide semiconductor film 108b). can be done.

[0307] Next, a mask is formed on the insulating film 118 by a lithography process, and the insulating films 114 and 11 An opening 152a is formed in a desired region of the insulating film 118. A mask is formed by a film process, and the desired insulating films 106, 107, 114, 116, and 118 are formed. The openings 152b and 152c are formed in the conductive film 112. The openings 152b and 152c are formed so as to reach the conductive film 10 4 (see Figures 21(A) and (B)).

[0308] The opening 152a and the openings 152b and 152c may be formed in the same process. The opening 152a and the openings 152b and 152c may be formed in different steps. When forming the same layer in the same process, for example, a gray-tone mask or a half-tone mask is used. The openings 152b and 152c may be formed in multiple steps. For example, openings are first formed in the insulating films 106 and 107, and then the openings are The upper insulating films 114, 116, and 118 may be opened.

[0309] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 152a, 152b, and 152c. The conductive film is processed into a desired shape, thereby forming the oxide semiconductor films 120a and 120b. (See Figure 21(C)(D).)

[0310] A transistor can be manufactured through the above steps. The cross-sectional view is of transistor 150B, which is a variation of transistor 150 shown above. It also serves as a

[0311] Note that the structures and methods described in this embodiment mode may be combined as appropriate with structures and methods described in other embodiment modes. They can be used in combination.

[0312] (Embodiment 2) In this embodiment, the structure of an oxide semiconductor will be described with reference to FIGS. I will explain.

[0313] <2-1. Structure of oxide semiconductors> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0314] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxides. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0315] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. This can also be described as a structure that has a high degree of order but no long-range order.

[0316] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor (isotropic amorphous). The oxide semiconductor is then oxidized to form a completely amorphous structure. However, a-like OS is a semiconductor that can be used in a microscopic area. Although it has a periodic structure, it has voids and is an unstable structure. It can be said that the physical properties are similar to those of an amorphous oxide semiconductor.

[0317] In the oxide semiconductor film of one embodiment of the present invention, among the above-described oxide semiconductors, C AAC-OS is preferable. When the oxide semiconductor film is made of CAAC-OS, Improving the crystallinity of the film and reducing impurities, oxygen vacancies, or defect state density in the oxide semiconductor film It is possible.

[0318] <2-2.CAAC-OS> First, let me explain about CAAC-OS.

[0319] CAAC-OS is an oxide having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0320] A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by TEM. When observing the TEM image, multiple pellets can be seen. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries (also called grain boundaries), are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS due to the grain boundary. This means that the decrease in electron mobility due to the SiO2 layer is unlikely to occur.

[0321] Below, we will explain the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration correction function was used to obtain high-resolution TEM images. , specifically referred to as a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images can be obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0322] An enlarged Cs-corrected high-resolution TEM image of area (1) in Figure 22(A) is shown in Figure 22(B). From Figure 22(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0323] As shown in Figure 22(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The pellets can also be called nanocrystals (nc). AAC-OS, CANC(C-Axis Aligned nanocrystals) ) can also be referred to as an oxide semiconductor.

[0324] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 22(D)). The tilt between the pellets observed in FIG. 22(C) The location where the crack occurs corresponds to the area 5161 shown in FIG. 22(D).

[0325] FIG. 23(A) shows the C of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. 23(A) shows the s-corrected high-resolution TEM image. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 23(B), Fig. 23(C), and Fig. 23(D), respectively. As shown in Figure 23(D), Figure 23(B), Figure 23(C) and Figure 23(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0326] Next, we will explain the CAAC-OS analyzed by XRD. The structure of CAAC-OS with nO4 crystals was solved by the out-of-plane method. When the analysis was performed, a peak appeared at a diffraction angle (2θ) of approximately 31°, as shown in FIG. 24(A). This peak is attributed to the (009) plane of the InGaZnO4 crystal. The CAAC-OS crystal has a c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface on which the CAAC-OS is formed or the upper surface. It can be seen that it is facing in the direction.

[0327] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31 In addition to the peak around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS crystals do not have a c-axis orientation. The more preferable CAAC-OS is a structure produced by the out-of-plane method. The analysis shows a peak at 2θ around 31°, but no peak at 2θ around 36°.

[0328] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction almost perpendicular to the c-axis. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 5 The sample is fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a (φ scan) is performed, no clear peak appears as shown in Figure 24(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane as shown in Figure 24(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and b-axis is irregular.

[0329] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, the probe diameter is 300 nm parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the presence of InGaZnO4 This includes spots due to the (009) plane of the crystal. The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied to the same sample perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in Figure 25(B). 5(B), a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. The first ring in FIG. 25(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface.

[0330] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the incorporation of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0331] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon are more oxidative than metal elements that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0332] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0333] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 Such an oxide semiconductor can be a highly pure intrinsic or substantially highly pure oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect states. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0334] <2-3.nc-OS> Next, we will explain nc-OS.

[0335] In the high-resolution TEM image, nc-OS has two distinct regions: one where crystals can be confirmed and the other where clear crystals can be confirmed. The crystalline part contained in nc-OS is The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0336] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, in contrast to nc-OS, there are cases where it is difficult to distinguish the particles from the pellets. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, a probe diameter larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction is performed on nc-OS, high brightness regions are observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. This may be the case.

[0337] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) The semiconductor may also be referred to as an oxide semiconductor having a structure (s).

[0338] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0339] <2-4.a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a semiconductor.

[0340] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystalline parts can be clearly seen, and areas where crystalline parts can be seen. and areas where it is not possible to

[0341] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0342] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as Sample B) and CAAC-OS (hereinafter referred to as Sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0343] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all the materials have crystalline parts.

[0344] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing is 0.28 nm or more and 0.30 nm or less are considered to be InGaZnO4 crystal parts. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0345] Figure 26 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystalline part of ke OS grows in size according to the cumulative amount of electron irradiation. Specifically, as shown in Figure 26 (1), the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2 × 10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron irradiation dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystal part within the range of As shown in (2) and (3) in Figure 26, regardless of the cumulative electron dose, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that...

[0346] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, the growth of the crystals by electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC- It is clear that it has an unstable structure compared to the OS.

[0347] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal of the same composition. The density of the nc-OS is 78.6% or more and less than 92.3% of that of the normal crystal. The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0348] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It will be less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0349] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions may be used in any proportion. By combining single crystals with the desired composition, the density equivalent to that of a single crystal can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0350] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the above-mentioned compounds.

[0351] <2-5. CAAC-OS film formation method> An example of a method for forming a CAAC-OS film will be described below.

[0352] Figure 27 is a schematic diagram of the inside of the film formation chamber. CAAC-OS is formed by sputtering. It is possible.

[0353] As shown in FIG. 27, the substrate 5220 and the target 5230 are arranged facing each other. There is a plasma 5240 between the substrate 5220 and the target 5230. A heating mechanism 5260 is provided below the substrate 5220. Although not shown, the target 5230 is bonded to the backing plate. A number of magnets are placed facing the magnet 5230. The sputtering method that uses magnetron sputtering to increase the deposition rate is called magnetron sputtering. can be.

[0354] The distance d between the substrate 5220 and the target 5230 (target-substrate distance (TS distance) The distance is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The deposition chamber is mostly filled with deposition gas (e.g., oxygen, argon, or oxygen in a volume of 5). % or more), and the pressure is 0.01 Pa or more and 100 Pa or less, preferably is controlled to be 0.1 Pa or more and 10 Pa or less. By applying a voltage, a discharge starts and plasma 5240 is observed. A high density plasma region is formed near the nozzle 5230 by the magnetic field. In the region, the deposition gas is ionized to generate ions 5201. , for example, oxygen cations (O + ) and argon cations (Ar + ) etc.

[0355] The target 5230 has a polycrystalline structure having a plurality of crystal grains, and As an example, FIG. 28 shows a target 5230 containing InMZn 28( ) shows the crystal structure of O4 (element M is, for example, Al, Ga, Y, or Sn). A) The crystal structure of InMZnO4 when observed parallel to the b axis. In ZnO4 crystals, the oxygen atoms have a negative charge, so two adjacent M-Zn Therefore, the InMZnO4 crystal has two adjacent M -Zn-O layer has a cleavage plane between them.

[0356] Ions 5201 generated in the high-density plasma region are attracted to the target 5230 by the electric field. The particles are accelerated and eventually collide with the target 5230. At this time, flat or planar particles are formed from the cleavage plane. Pellets 5200, which are pellet-shaped sputtered particles, are peeled off (see FIG. 27). 200 is the portion sandwiched between the two cleavage planes shown in FIG. 28(A). When only 200 is extracted, the cross section looks like Figure 28(B) and the top surface looks like Figure 28(C). It can be seen that the pellet 5200 is formed by the impact of the collision of the ion 5201. This may cause distortion of the structure.

[0357] The pellet 5200 is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. Alternatively, the pellet 5200 may have a hexagonal, for example, regular hexagonal, plane. The sputtered particles are in the form of plates or pellets. However, the shape of the pellets 5200 is not limited to triangles or hexagons, for example, when it is a shape made up of multiple triangles For example, a quadrilateral (e.g., a rhombus) is formed by joining two triangles (e.g., an equilateral triangle). ) may also be used.

[0358] The thickness of the pellet 5200 is determined depending on the type of deposition gas. 5200 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5200 has a width of 1 nm or more and 100 nm or less, preferably Preferably, the thickness is 2 nm or more and 50 nm or less, and more preferably, 3 nm or more and 30 nm or less. The target 5230 having In-M-Zn oxide is bombarded with ions 5201. As a result, a pellet 5 having three layers, an M-Zn-O layer, an In-O layer and an M-Zn-O layer, was obtained. As the pellet 5200 peels off, particles are released from the target 5230. Particle 5203 is also ejected. Particle 5203 has a collection of one atom or several atoms. Therefore, particles 5203 are called atomic particles. It is also possible.

[0359] As the pellet 5200 passes through the plasma 5240, its surface becomes negatively or positively charged. For example, when the pellet 5200 is in the plasma 5240, 2- negative charge from As a result, the oxygen atoms on the surface of the pellet 5200 may become negatively charged. In addition, when the pellet 5200 passes through the plasma 5240, It may grow by combining with indium, element M, zinc, or oxygen in 40. .

[0360] The pellets 5200 and particles 5203 that have passed through the plasma 5240 are Some of the particles 5203 are small in mass and can be removed by a vacuum pump or other device. It may be discharged to the outside.

[0361] Next, the deposition of pellets 5200 and particles 5203 on the surface of the substrate 5220 is described. This will be explained with reference to FIG.

[0362] First, the first pellet 5200 is deposited on the substrate 5220. The pellet 5200 is a flat plate. Since the pellet 52 has a shape like a flat surface, it is deposited with the flat surface facing the surface of the substrate 5220. The charge on the surface of 00 on the substrate 5220 side is released through the substrate 5220.

[0363] Next, the second pellet 5200 reaches the substrate 5220. At this time, the already deposited The surface of the first pellet 5200 and the surface of the second pellet 5200 are charged. As a result, the second pellet 5200 is pushed into the pile already. Avoiding the pellets 5200 on which the substrate 5220 is stacked, place the flat side a little away from the surface of the substrate 5220. By repeating this process, countless pellets 52 are deposited on the surface of the substrate 5220. 5200 is deposited to a thickness of one layer. There will be areas where no deposition occurs (see Figure 29(A)).

[0364] Next, the particles 5203 that have received energy from the plasma reach the surface of the substrate 5220. The particles 5203 can be deposited in active areas such as the surface of the pellet 5200. Therefore, the particles 5203 move to the area where the pellet 5200 is not deposited, and the pellet The particle 5203 adheres to the side of the nozzle 5200. The bond becomes more active, and the pellet 5200 is chemically bonded to the lateral growth portion 52 02 (see Figure 29(B)).

[0365] Furthermore, the laterally growing portion 5202 grows in the lateral direction (also called lateral growth), The pellets 5200 are connected to each other (see FIG. 29(C)). Lateral growth 5202 is formed until the undeposited area is filled. Deposition mechanism of atomic layer deposition (ALD) method Similar to a rhythm.

[0366] Therefore, even if the pellets 5200 are piled up in different directions, Particles 5203 grow laterally and fill the gaps between particles 5200, forming clear grain boundaries. In addition, the particles 5203 smoothly connect the pellets 5200. Therefore, a crystal structure different from either single crystal or polycrystal is formed. A crystalline structure having distortion between the crystalline regions (pellets 5200) is formed. The regions filling the gaps are distorted crystalline regions, so it is not appropriate to refer to these regions as amorphous structures. It is considered not to be a good idea.

[0367] Next, a new pellet 5200 is deposited with its flat side facing the surface (see FIG. 29(D)). ) Then, particles 5203 accumulate to fill the undeposited areas of the pellet 5200. By this, the lateral growth portion 5202 is formed (see FIG. 29(E)). 3 adheres to the side of the pellet 5200, and the lateral growth portion 5202 grows laterally. The pellets 5200 in the mth layer are connected (see FIG. 29(F)). The deposition continues until several layers are formed, resulting in a thin film structure having a stack.

[0368] The deposition pattern of the pellets 5200 also changes depending on the surface temperature of the substrate 5220. For example, if the surface temperature of the substrate 5220 is high, the pellet 5200 may be heated to the surface of the substrate 5220. As a result, the pellets 5200 are interdigitated with the particles 5203. The proportion of bonds without any bonds increases, resulting in a CAAC-OS with higher orientation. The surface temperature of the substrate 5220 during the formation of the OS film is set to be equal to or higher than room temperature and lower than 340° C., preferably room temperature. and 300°C or less, more preferably 100°C or more and 250°C or less, and even more preferably 100°C or more and 250°C or less. ℃ or more and 200 ℃ or less. Therefore, the substrate 5220 is a large-area substrate of the 8th generation or more. Even when using a CAAC-OS film, warping and other problems caused by the film formation hardly occur. I understand.

[0369] On the other hand, when the surface temperature of the substrate 5220 is low, the pellet 5200 moves to the surface of the substrate 5220. As a result, pellets 5200 do not pile up. In the case of nc-OS, the pellet 5200 is negatively charged. As a result, the pellets 5200 may be deposited at regular intervals. Although the orientation is low, the film has a slight regularity, which makes it more uniform than an amorphous oxide semiconductor. The entire structure is dense.

[0370] In addition, in CAAC-OS, the gaps between pellets are extremely small, Large pellets of different sizes may be formed. The inside of one large pellet has a single crystal structure. For example, the size of the pellet is 10 nm or more and 200 nm or less when viewed from the top. It may be between 100 nm and 100 nm, or between 20 nm and 50 nm.

[0371] According to the above film formation model, it is believed that pellets are deposited on the surface of the substrate. CAAC-OS can be deposited even on surfaces that do not have a crystalline structure. Therefore, the above-mentioned film formation model, which is a growth mechanism different from epitaxial growth, is highly valid. In addition, because this is the deposition model described above, the CAAC-OS and nc-OS It can be seen that uniform film formation is possible even on large glass substrates. For example, Even if the structure of the substrate surface (surface to be formed) is amorphous (for example, amorphous silicon oxide), It is possible to form a CAAC-OS film.

[0372] In addition, even if the surface of the substrate on which the film is to be formed is uneven, the pellets will adhere to the shape of the uneven surface. It is clear that the arrangement is

[0373] In addition, from the above-mentioned film formation model, the following conditions are required to form a CAAC-OS film with high crystallinity: First, in order to lengthen the mean free path, we need to create a higher vacuum. Next, to reduce damage near the substrate, the plasma energy is Next, heat energy is applied to the surface to be formed, and the damage caused by the plasma is weakened each time a film is formed. It will heal.

[0374] In addition, the above-mentioned film formation model is based on the In-M-Zn oxide target with multiple crystal grains. When a complex oxide has a polycrystalline structure such as a crystalline material, and one of the crystal grains contains a cleavage plane, For example, a mixture of indium oxide, an oxide of element M, and zinc oxide may be used. The present invention can also be applied to the case where an object target is used.

[0375] The target of the mixture does not have a cleavage plane, so when sputtered, atoms are released from the target. During film formation, a strong electric field region of plasma is formed near the target. Therefore, atomic particles detached from the target are connected by the action of the strong electric field region of the plasma. For example, first, atomic particles of indium bond together and grow laterally. Next, M-Zn-O layers are formed above and below it to complement it. Thus, even when a mixed target is used, pellets may be formed. Therefore, even when a target made of a mixture is used, the above-mentioned film formation model can be applied. It is possible.

[0376] However, if a strong electric field region of the plasma is not formed near the target, Only atomic particles peeled off from the substrate are deposited on the substrate surface. In this case, atomic particles may grow laterally. However, because the orientation of atomic particles is not uniform, However, the crystal orientation in the resulting thin film is not uniform. .

[0377] <2-6. Lateral Growth> In the following, particles 5203 are attached (also called bonded or adsorbed) in the lateral direction of the pellet 5200. .) and explain lateral growth.

[0378] Figure 30 (A) (B) (C) (D) (E) shows the structure of Pellet 5200 and the metal ions attached to it. The pellet 5200 is a pellet having a crystal structure of InMZnO4. From the structure, we assumed a cluster model that extracts 84 atoms while maintaining the stoichiometric composition. In the following, the case where the element M is Ga will be described. ) shows the structure of the pellet 5200 as seen from a direction parallel to the c-axis. The structure of the PET 5200 is shown as seen from a direction parallel to the a-axis.

[0379] The positions where the metal ions are attached are indicated as position A, position B, position a, position b, and position c. Position A is a grid surrounded by one gallium particle and two zinc particles on the top surface of the pellet 5200. Position B is located above the interatomic site. Position a is above the interstitial site surrounded by one. Position b shows the In-O layer and the Ga-Zn layer on the side of the pellet 5200. The position c is the gallium site on the side of the pellet 5200. is.

[0380] Next, metal ions were placed at the assumed positions A, B, a, b, and c. The relative energies for the two cases were evaluated by first-principles calculations. Vienna Ab initio Simulation Package) In addition, the exchange-correlation potential is PBE (Perdew-Burke-Ernzerh Generalized Gradient Approximation (GGA) of type The ion potential is PAW (Project AAW). The cutoff energy was 40 0 eV, and k-point sampling was limited to the Γ point. Indium ions (In 3+ ), gallium ions (Ga 3+ ) and and zinc ions (Zn 2+ ) is placed. The relative energy In the calculated models, the energy of the lowest model is set to 0 eV. This is the relative value when

[0381] [Table 1]

[0382] As a result, it was found that metal ions tended to adhere to the side of pellet 5200 rather than to the top. In particular, at the indium site at position a, not only indium ions but also The results also showed that zinc ions were most likely to adhere.

[0383] Similarly, oxygen ions (O 2- The ease of adhesion of the ) was evaluated. 1(A)(B)(C)(D)(E) show the structure of pellet 5200 and the oxygen ions attached to it. 31(F) shows the position of the pellet 5200 when viewed from a direction parallel to the c-axis. FIG. 31(G) shows the structure of the pellet 5200 as seen from a direction parallel to the b-axis. show.

[0384] The positions where oxygen ions are attached are shown as positions C, D, d, e, and f. Position C is the position where the gallium is bonded to the upper surface of the pellet 5200. The position d is the position where the zinc on the top surface of the pellet 5200 is bonded. Position e is the position where the gallium bonded to the side of pellet 5200. Position f is the position where the zinc on the side of the pellet 5200 is bonded.

[0385] Next, oxygen ions were placed at the assumed positions C, D, d, e, and f. The relative energies for positions C, D, and E are evaluated by first-principles calculations. d, oxygen ions (O 2- ) is placed in the vinegar.

[0386] [Table 2]

[0387] As a result, it was found that oxygen ions also tend to adhere to the side of the pellet 5200 rather than the top surface. It was.

[0388] Therefore, the particle 5203 approaching the pellet 5200 is attracted to the side of the pellet 5200. It can be seen that the particles 52 adhere preferentially to the side of the pellet 5200. The above-mentioned film formation model in which lateral growth of pellet 5200 occurs due to the 03 is highly valid. It can be said that

[0389] Note that the configuration shown in this embodiment may be appropriately combined with configurations shown in other embodiments or examples. , can be used in combination.

[0390] (Embodiment 3) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 50. In this embodiment, the display element of the display device is A configuration (liquid crystal display device) having a liquid crystal element will be specifically described.

[0391] <3-1.Liquid crystal display device> A liquid crystal display device 880 shown in FIG. 32(A) includes a pixel portion 871, a gate driver 874, and , a source driver 876, and a gate driver 8 74, the potential of which is controlled by m scanning lines 877, and each of which is arranged parallel or approximately parallel. and n signal lines 879 whose potentials are controlled by a source driver 876. Furthermore, the pixel section 871 has a plurality of pixels 870 arranged in a matrix. , along the signal line 879, each of which has a common line 875 arranged parallel or approximately parallel to each other. The gate driver 874 and the source driver 876 may be collectively referred to as a drive circuit unit. There is a match.

[0392] Each scanning line 877 corresponds to one of the pixels 870 arranged in m rows and n columns in the pixel section 871. , are electrically connected to n pixels 870 arranged in any row. The line 879 is formed by dividing m pixels 870 arranged in m rows and n columns into m pixels arranged in any one of the columns. The pixel 870 is electrically connected to the m and n. Both m and n are integers of 1 or more. The pixel line 875 is connected to m pixels 870 arranged in m rows and n columns in any one of the rows. The pixel 870 is electrically connected to the pixel 870.

[0393] FIG. 32B shows a pixel 870 that can be used in the liquid crystal display device 880 shown in FIG. 1 shows an example of a circuit configuration that can be implemented.

[0394] A pixel 870 shown in FIG. 32B includes a liquid crystal element 851, a transistor 852, and a capacitor. It has a child 855.

[0395] The transistor described in the above embodiment 1 can be used as the transistor 852. Cut.

[0396] One of the pair of electrodes of the liquid crystal element 851 is connected to the transistor 852, and the potential is The other of the pair of electrodes of the liquid crystal element 851 is connected to the common line 875, and a common potential is applied to the liquid crystal element 851. The alignment state of the liquid crystal is controlled by data written to the transistor 852 .

[0397] The liquid crystal element 851 controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of the liquid crystal is achieved by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field). The liquid crystal element 851 is controlled by an electric field in a diagonal direction or an electric field in a diagonal direction. The liquid crystals used are thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, and polymer dispersed liquid crystals. These liquid crystal materials can be used under certain conditions. Cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. Indicates directions, etc.

[0398] In addition, when the in-plane switching method is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used in the liquid crystal layer. The blue phase is a characteristic of the liquid crystal composition containing a liquid crystal and a chiral agent. The composition does not require alignment treatment and has little viewing angle dependency. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This can prevent defects and damage to the liquid crystal display device during the manufacturing process.

[0399] As a driving method of the liquid crystal display device 880 having the liquid crystal element 851, TN (Twiste d Nematic mode, IPS (In-Plane-Switching) mode , FFS (Fringe Field Switching) mode, ASM (Axia (Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, F LC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. It can be used.

[0400] In addition, the liquid crystal display device 880 is a normally black type liquid crystal display device, for example, a vertical alignment ( The liquid crystal display device may be a transmission type liquid crystal display device that employs a vertical alignment (VA) mode. MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV Modes, etc. can be used.

[0401] <3-2. In-plane switching mode LCDs> First, horizontal electric field mode liquid crystal display devices, typically FFS mode and IPS mode liquid crystal displays, The display device will now be described.

[0402] In the configuration of the pixel 870 shown in FIG. 32B, the source electrode of the transistor 852 and One of the drain electrodes is electrically connected to the signal line 879, and the other is connected to one of the pair of liquid crystal elements 851. The gate electrode of the transistor 852 is electrically connected to one of the electrodes of the scan line The transistor 852 is electrically connected to the data signal writing terminal 877. It has the function of controlling.

[0403] In the configuration of the pixel 870 shown in FIG. 32B, one of a pair of electrodes of the capacitor 855 is , connected to the other of the source electrode and the drain electrode of the transistor 852. The other of the pair of electrodes 5 is electrically connected to the common line 875. The value of is set appropriately according to the specifications of the pixel 870. The capacitance element 855 stores the written data. It functions as a storage capacitor to hold the data. In the liquid crystal display device 880, one of a pair of electrodes of the capacitor element 855 is connected to the liquid crystal element 851. The other electrode of the capacitor 855 is a part or the whole of one of the pair of electrodes. It is a part or the whole of the other of the pair of electrodes of the element 851 .

[0404] <3-3. Configuration example 1 of a transverse electric field mode element substrate> Next, a specific configuration of the element substrate included in the liquid crystal display device 880 will be described. A liquid crystal display device 880 driven in the FFS mode has a plurality of pixels 870a, 87 The top view of 870b and 870c is shown in FIG.

[0405] In FIG. 33, the conductive film 813 functioning as the scanning line is oriented in a direction substantially perpendicular to the signal line ( The conductive film 821a that functions as a signal line is provided so as to extend in the center (left and right direction). The scanning lines are provided so as to extend in a direction substantially perpendicular to the scanning lines (vertical direction in the drawing). The conductive film 813 is electrically connected to a gate driver 874 and serves as a signal line. The functioning conductive film 821a is electrically connected to the source driver 876 (FIG. 32( See A).

[0406] The transistor 852 is provided near the intersection of the scan line and the signal line. The gate electrode 852 includes a conductive film 813 that functions as a gate electrode, a gate insulating film (not shown in FIG. 33), and a gate insulating film 814. ), an oxide semiconductor film 808 in which a channel region is formed on the gate insulating film, The conductive films 821a and 821b function as a source electrode and a drain electrode. The conductive film 813 also functions as a scan line, and a region overlapping with the oxide semiconductor film 808 The conductive film 821a functions as a gate electrode of the transistor 852. The region overlapping with the oxide semiconductor film 808 serves as the source electrode or In FIG. 33, the scanning line has an edge in the top view. The portion is located outside the edge of the oxide semiconductor film 808. As a result, the oxide contained in the transistor The oxide semiconductor film 808 is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed. can.

[0407] The conductive film 821b is electrically connected to the oxide semiconductor film 819a which functions as a pixel electrode. An insulating film (not shown in FIG. 33) is formed over the oxide semiconductor film 819a. A common electrode 829 is provided therebetween.

[0408] The common electrode 829 has striped regions extending in a direction intersecting the signal lines. The striped regions are connected to regions extending in a direction parallel or approximately parallel to the signal lines. In a plurality of pixels of the liquid crystal display device 880, a common electrode 82 having a striped region 9, each region is at the same potential.

[0409] The capacitor 855 is formed in a region where the oxide semiconductor film 819a and the common electrode 829 overlap with each other. The oxide semiconductor film 819a and the common electrode 829 have a light-transmitting property. The element 855 is light-transmitting.

[0410] In addition, since the capacitor 855 has a light-transmitting property, the capacitor 855 is large and is disposed in the pixel 870. Therefore, the aperture ratio can be increased, typically to 50% or more. Preferably, the charge amount can be increased to 60% or more. For example, in a high-resolution display device, such as a liquid crystal display device, The area of ​​the element is reduced, and the area of ​​the capacitance element is also reduced. However, in the present embodiment, the amount of charge stored in the capacitor element is small. Since the capacitor 855 has a light-transmitting property, by providing the capacitor in the pixel, This allows the aperture ratio to be increased while obtaining a sufficient amount of charge. High resolution of 100ppi or more, 300ppi or more, or even 500ppi or more It can be suitably used in a display device.

[0411] In addition, in a liquid crystal display device, the larger the capacitance value of the capacitance element, the more the capacitance value of the capacitance element increases. In this case, the period during which the alignment of the liquid crystal molecules in the liquid crystal element can be kept constant can be extended. When displaying a still image, the period can be extended, reducing the number of times the image data is rewritten. It is possible to reduce the number of circuits, and power consumption can be reduced. The structure shown in FIG. 1 allows the aperture ratio to be increased even in high-resolution display devices. Light from light sources such as backlights can be used efficiently, reducing the power consumption of display devices It is possible.

[0412] Next, cross-sectional views taken along dashed lines Q1-R1 and S1-T1 in FIG. 33 are shown in FIG. 4. The transistor 852 shown in FIG. 34 is a channel-etched transistor. The dashed line Q1-R1 indicates the channel length direction of the transistor 852 and the capacitance element 8 55, and the cross section taken along S1-T1 shows the channel width of transistor 852. 33 is a cross-sectional view of the oxide semiconductor layer that functions as the second gate electrode. The membrane 819b is omitted for clarity of illustration.

[0413] The transistor 852 shown in FIG. 34 has a first gate electrode provided on a substrate 811. a conductive film 813 functioning as a gate electrode; a substrate 811 and a conductive film 812 functioning as a first gate electrode; 3, an insulating film 815 formed on the insulating film 815, and an insulating film The oxide film 815 and the insulating film 817 overlap with the conductive film 813 functioning as a gate electrode. a source electrode and a drain electrode in contact with the oxide semiconductor film 808; The conductive films 821a and 821b functioning as a source electrode and a drain electrode are Insulating films 823 and 825 are provided over the conductive films 821a and 821b which function as conductive electrodes. an oxide semiconductor film 819b which functions as a second gate electrode over an insulating film 825; 825 and an insulating film 827 over the oxide semiconductor film 819b.

[0414] In addition, an oxide semiconductor film 819a is formed over the insulating film 825. 9a is one of the conductive films 821a and 821b which function as a source electrode and a drain electrode, Here, the conductive film 821b and the insulating film 823 are formed through openings formed in the insulating film 825. An insulating film 827 is formed over the insulating film 825 and the oxide semiconductor film 819a. In addition, a common electrode 829 is formed on the insulating film 827.

[0415] In addition, in a region where the oxide semiconductor film 819a, the insulating film 827, and the common electrode 829 overlap with each other, functions as a capacitor element 855 .

[0416] The cross-sectional structure of one aspect of the embodiment of the present invention is not limited to this. The oxide semiconductor film 819a may have a slit or a comb-like shape. The shape may also be used.

[0417] As shown in FIG. 35, the common electrode 829 is formed on the insulating film 827. The insulating film 828 may be provided on the insulating film 828. The insulating film 828 functions as a planarization film.

[0418] <3-4. Configuration example 2 of transverse electric field mode element substrate> Next, a liquid crystal display device 880 includes a plurality of pixels 8 having a different configuration from the pixels shown in FIG. 36 shows top views of 70d, 870e, and 870f. is driven in IPS mode.

[0419] In FIG. 36, the conductive film 813 functioning as a scanning line is provided extending in the left-right direction in the drawing. The conductive film 821a functioning as a signal line has a bent V-shaped portion. The scanning line is extended in a direction (vertical direction in the drawing) substantially perpendicular to the scanning line. The conductive film 813 functioning as a scan line is electrically connected to a gate driver 874. The conductive film 821a functioning as a signal line is electrically connected to the source driver 876. (See FIG. 32(A)).

[0420] The transistor 852 is provided near the intersection of the scan line and the signal line. The gate electrode 852 includes a conductive film 813 that functions as a gate electrode, a gate insulating film (not shown in FIG. 36), and a gate insulating film 814. ), an oxide semiconductor film 808 in which a channel region is formed on the gate insulating film, The conductive films 821a and 821b function as a source electrode and a drain electrode. The conductive film 813 also functions as a scan line, and a region overlapping with the oxide semiconductor film 808 The conductive film 821a functions as a gate electrode of the transistor 852. The region overlapping with the oxide semiconductor film 808 serves as the source electrode or In FIG. 36, the scanning line has an end portion in the top view. The portion is located outside the edge of the oxide semiconductor film 808. As a result, the oxide contained in the transistor The oxide semiconductor film 808 is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed. can.

[0421] The conductive film 821b is electrically connected to the oxide semiconductor film 819a which functions as a pixel electrode. The oxide semiconductor film 819a is formed in a comb-like shape. An insulating film (not shown in FIG. 36) is provided on 819a, and a common electrode 829 is provided on the insulating film. The common electrode 829 is provided on the upper surface of the oxide semiconductor film 819a so as to partially overlap with the oxide semiconductor film 819a. In the plan view, the interdigital grooves 814 are formed in a comb shape so as to be interdigitated with the oxide semiconductor film 819a. The scan electrodes 829 are connected to areas extending in a direction parallel or approximately parallel to the scan lines. Therefore, in a plurality of pixels of the liquid crystal display device 880, the common electrodes 829 are at the same potential. Note that the oxide semiconductor film 819a and the common electrode 829 are connected to the signal line (the conductive film 821a). It has a V-shaped curve that follows the curve.

[0422] The capacitor 855 is formed in a region where the oxide semiconductor film 819a and the common electrode 829 overlap with each other. The oxide semiconductor film 819a and the common electrode 829 have a light-transmitting property. The element 855 is light-transmitting.

[0423] Next, cross-sectional views taken along dashed lines Q2-R2 and S2-T2 in FIG. 36 are shown in FIG. 7. The transistor 852 shown in FIG. 37 is a channel-etched transistor. The dashed line Q2-R2 indicates the channel length direction of the transistor 852 and the capacitance element 8 55, and the cross section taken along S2-T2 shows the channel width of transistor 852. 36 is a cross-sectional view of the oxide semiconductor layer that functions as the second gate electrode. The membrane 819b is omitted for clarity of illustration.

[0424] The transistor 852 shown in FIG. 37 functions as a gate electrode provided over the substrate 811. a conductive film 813 serving as a gate electrode; and a conductive film 814 formed over the substrate 811 and the conductive film 813 serving as a gate electrode. an insulating film 815 formed on the insulating film 815; an insulating film 817 formed on the insulating film 815; The oxide semiconductor film 8 overlaps with the conductive film 813 functioning as a gate electrode with the insulating film 817 interposed therebetween. and a conductive film serving as a source electrode and a drain electrode in contact with the oxide semiconductor film 808. the oxide semiconductor film 808, and the oxide semiconductor film 808 as a source electrode and a drain electrode. Insulating films 823 and 825 are provided on the functional conductive films 821a and 821b, and insulating film 82 The oxide semiconductor film 819b serving as a second gate electrode, the insulating film 825, and the oxide semiconductor film 819b function as a second gate electrode over the insulating film 825. and an insulating film 827 on the nitride semiconductor film 819b.

[0425] In addition, an oxide semiconductor film 819a is formed over the insulating film 825. 9a is one of the conductive films 821a and 821b which function as a source electrode and a drain electrode, Here, the conductive film 821b and the insulating film 823 are formed through openings formed in the insulating film 825. An insulating film 827 is formed over the insulating film 825 and the oxide semiconductor film 819a. In addition, a common electrode 829 is formed on the insulating film 827.

[0426] In addition, in a region where the oxide semiconductor film 819a, the insulating film 827, and the common electrode 829 overlap with each other, functions as a capacitor element 855 .

[0427] The liquid crystal display devices shown in FIGS. 36 and 37 include an oxide semiconductor film 819a and a common electrode 82. The capacitor element of the pixel is formed by the structure in which the vicinity of each end of each of the electrodes 9 overlaps. With this configuration, in a large liquid crystal display device, the capacitance element can be made not too large but of an appropriate size. It can be formed to any size.

[0428] As shown in FIG. 38, the common electrode 829 is formed on the insulating film 827. It may be provided on 828.

[0429] 39 and 40, the oxide semiconductor film 819a and the common electrode 829 The size of the capacitor element may be determined depending on the resolution and driving method of the display device. Therefore, the positional relationship between the oxide semiconductor film 819a and the common electrode 829 can be appropriately determined. It should be noted that the common electrode 829 of the display device shown in FIG. 40 functions as a flattening film. Alternatively, the insulating film 828 may be provided on the insulating film 828 (see FIG. 41).

[0430] 36 and 37, the signal line (conductor) of the oxide semiconductor film 819a The width (d1 in FIG. 37) of the region extending in a direction parallel or approximately parallel to the conductive film 821a) is The width of the region of the signal line of the signal electrode 829 extending in a direction parallel or approximately parallel to the signal line (d2 in FIG. 37) is As shown in Figures 42 and 43, the width The width d1 may be larger than the width d2. Also, the width d1 and the width d2 may be equal. In a pixel (for example, pixel 870d), the oxide semiconductor film 819a and / or the common electrode The electrode 829 has a plurality of regions extending in a direction parallel or substantially parallel to the signal line, each of which has a different width. It may be possible.

[0431] 44, an insulating film 828 provided on the insulating film 827 is 8, the common electrode 829 and the area overlapping the common electrode 829 may be removed. In this case, the insulating film 828 can be etched using the common electrode 829 as a mask. The unevenness of the common electrode 829 on the insulating film 828, which functions as a planarizing film, can be suppressed. The side of the insulating film 828 is gently sloped from the end of the common electrode 829 to the insulating film 827. As shown in FIG. 45, the surface of the insulating film 828 is parallel to the substrate 811. A configuration in which part of the area is not covered by the common electrode 829 is also possible.

[0432] 46 and 47, the common electrode is formed on the same layer as the oxide semiconductor film 819a. 46 and 47. The electrode 819c is formed using the same material as the oxide semiconductor film 819a and by applying the same oxide semiconductor film. It can be formed by processing.

[0433] <3-5. Vertical Alignment Mode Liquid Crystal Display Device> Next, we developed a liquid crystal display (LCD) operating in vertical alignment (VA) mode. The structure of a pixel having a liquid crystal element will be described with reference to Figs. 48 and 49. 49 is a top view of a pixel included in a liquid crystal display device, taken along the line A1-B1 in FIG. 50 is an equivalent circuit diagram of a pixel included in a liquid crystal display device. do.

[0434] VA type is a type of method for controlling the arrangement of liquid crystal molecules in an LCD panel. In a liquid crystal display device, when no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. It is a method that faces.

[0435] In the following, we will divide a pixel into several regions (subpixels) and This is called multi-domain or multi-domain. In the following explanation, we will focus on LCD devices that take multi-domain design into consideration. I will explain.

[0436] Z1 in FIG. 48 is a top view of the substrate 600 on which the pixel electrode 624 is formed, and Z3 is a common 6 is a top view of the substrate 601 on which the electrode 640 is formed, and Z2 is a top view of the substrate 601 on which the pixel electrode 624 is formed. 6 is a top view of a state in which a substrate 600 and a substrate 601 on which a common electrode 640 is formed are superimposed. be.

[0437] On the substrate 600, a transistor 628, a pixel electrode 624 connected thereto, and a capacitor The drain electrode 618 of the transistor 628 is formed by insulating film 623 and The insulating film 625 is electrically connected to the pixel electrode 624 through an opening 633 formed in the insulating film 625. An insulating film 627 is provided on the element electrode 624 .

[0438] The transistor described in the first embodiment can be used as the transistor 628. Cut.

[0439] The capacitor element 630 is formed by a wiring 613 on the capacitor wiring 604, which is the first capacitor wiring, and an insulating film 6 23, an insulating film 625, and a pixel electrode 624. The gate wiring 615 of the gate electrode 628 can be formed of the same material at the same time. 13 can be formed simultaneously with the drain electrode 618 and the wiring 616 using the same material. do.

[0440] The pixel electrode 624 is formed using the oxide semiconductor film having low sheet resistance described in Embodiment 1. can be applied.

[0441] The pixel electrode 624 is provided with a slit 646. The slit 646 controls the alignment of the liquid crystal. This is for the purpose.

[0442] The transistor 629, the pixel electrode 626 connected thereto, and the capacitor 631 are The transistor 628, the pixel electrode 624, and the capacitor 630 can be formed in the same manner. The transistor 628 and the transistor 629 are both connected to the wiring 616. 6 functions as a source electrode in the transistor 628 and the transistor 629. The pixel of the liquid crystal display panel shown in this embodiment mode has a pixel electrode 624 and a pixel electrode 626. The pixel electrode 624 and the pixel electrode 626 are sub-pixels.

[0443] A colored film 636 and a common electrode 640 are formed on the substrate 601. A structure 644 is formed. A slit 647 is provided in the common electrode 640. An alignment film 648 is formed on the pixel electrode 624, and a common electrode 640 and a structure An alignment film 645 is formed on the structure 644. A liquid crystal layer is formed between the substrate 600 and the substrate 601. 650 is formed.

[0444] The slits 647 formed in the common electrode 640 and the structure 644 control the alignment of the liquid crystal. It has the function of controlling

[0445] When a voltage is applied to the pixel electrode 624 in which the slit 646 is provided, The slit 646 and the structure 6 on the substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the slits 44 and slits 647 so that they interdigitate with each other, the oblique electric field is effectively By generating a liquid crystal and controlling its orientation, the direction of the liquid crystal orientation can be varied depending on the location. In other words, the viewing angle of the liquid crystal display panel is widened by making it multi-domain. Either the structure 644 or the slit 647 is provided on the plate 601 side. That's fine.

[0446] FIG. 49 shows a state in which the substrate 600 and the substrate 601 are superimposed and liquid crystal is injected. The pixel electrode 624, the liquid crystal layer 650, and the common electrode 640 are overlapped with each other, so that the liquid crystal A child is formed.

[0447] The equivalent circuit of this pixel structure is shown in Figure 50. Transistors 628 and 629 are , both connected to the gate wiring 602 and wiring 616. In this case, the capacitance wiring 604 and the capacitance By making the potential of the wiring 605 different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 can be controlled individually. This allows for precise control of the liquid crystal orientation, widening the viewing angle.

[0448] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0449] (Fourth embodiment) In this embodiment, a semiconductor device of one embodiment of the present invention and a display device including the semiconductor device will be described. The device will be described with reference to Figures 51 to 54. The display device has a light-emitting element (particularly an electroluminescence (EL) element) as a display element. The configuration will be specifically described below.

[0450] <4-1. Explanation of display devices> The display device shown in FIG. 51(A) has a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a driving circuit section 504) and a transistor or a light emitting element for correcting the temperature a circuit section (hereinafter referred to as a temperature sensor circuit section 508) and a circuit section (hereinafter referred to as a The sensor circuit section 50 has a protection circuit section 506 and a terminal section 507. 8 and the protection circuit unit 506 may not be provided.

[0451] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or all of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Bearing). It can be implemented by

[0452] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter referred to as a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a), for supplying signals (data signals) for driving the display elements of the pixels. The source driver 504b includes a driving circuit such as the circuit (hereinafter referred to as a source driver 504b).

[0453] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is inputted through the terminal section 507, and a signal for outputting the shift register is outputted. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a receives a scanning signal and outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the plurality of gate drivers 504a drive the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it into the initialization signal However, the gate driver 50 has a function of supplying 4a can also supply other signals. For example, as shown in Figure 51(A), The gate driver 504a is connected to wiring (hereinafter referred to as ANODE_1 to ANODE_2) that controls the potential of the light-emitting element. It is electrically connected to the

[0454] The source driver 504b includes a shift register and the like. Through the terminal section 507, signals for driving the shift register as well as the source of the data signal are transmitted. The source driver 504b receives a signal (image signal) that is to be output from the pixel circuit The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0455] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches, The image signal can be time-divided and output as a data signal. The source driver 504b may be configured using the same.

[0456] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is input via the data line DL, and a data signal is given via one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or less than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via the input terminal 504a (n is a natural number equal to or less than Y).

[0457] The protection circuit unit 506 shown in FIG. 51(A) includes, for example, a gate driver 504a and a pixel circuit 501. Alternatively, the protection circuit unit 506 is connected to the scanning line GL, which is the wiring between the source It is connected to the data line DL, which is the wiring between the driver 504b and the pixel circuit 501. The protection circuit unit 506 is connected to the wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit unit 506 may be a circuit including the source driver 504b and the terminal unit 507. The terminal portion 507 can be connected to a wiring between the external circuit and the display device. This refers to the part where terminals for inputting power, control signals, and image signals are provided.

[0458] When a potential outside a certain range is applied to the wiring to which the protection circuit unit 506 is connected, This is a circuit that brings the wiring into a conductive state with another wiring.

[0459] For example, the protection circuit portion 506 can have the structure shown in FIG.

[0460] FIG. 52A shows an example of a circuit configuration that can be used as the protection circuit unit 506. In FIG. The protection circuit unit 506 includes a transistor 510 and a resistor element 512. One of the source electrode and the drain electrode of the transistor 510 is electrically connected to the data line DL. The other of the source electrode and the drain electrode of the transistor 510 is connected to one electrode of the resistor element 512. The gate electrode of the transistor 510 is electrically connected to the The other of the source electrode and the drain electrode of the resistor element 512 is electrically connected to the other of the source electrode and the drain electrode of the resistor element 512. The other electrode is electrically connected to the scanning line GL. A ground electrode may be provided.

[0461] The transistor 510 may be the transistor 100 of the first embodiment. The resistor element 512 may have the configuration shown in FIGS. can.

[0462] FIG. 52(B) is an example of a top view of the resistance element 512, and FIG. 52(C) is an example of a top view of the resistance element 512. ) corresponds to the cross-sectional view of the cross section taken along the dashed dotted line A3-A4 shown in FIG.

[0463] The resistor element 512 includes electrodes 542a and 542b on a substrate 532, and a resistor element 512 is formed by connecting the substrate 532 and the electrodes 542a and 542b. Insulating films 544 and 546 on the electrodes 542a and 542b, and the insulating films The oxide semiconductor film 550 on the insulating film 546 and the insulating film on the oxide semiconductor film 550 and a membrane 548.

[0464] Substrate 532, insulating films 544 and 546, electrodes 542a and 542b, and an oxide semiconductor film 550 , and the insulating film 548 are the same as the substrate 102 and the insulating films 114 and 116 described above, respectively. The conductive films 112a and 112b, the oxide semiconductor film 120, and the insulating film 118 are formed using the same materials. It can be used.

[0465] The electrode 542a and the electrode 542b are electrically connected to each other through an oxide semiconductor film 550. The oxide semiconductor film 550 functions as a resistor.

[0466] As shown in FIGS. 52(B) and 52(C), the oxide semiconductor film 550 has a shape (specifically, length, Alternatively, as shown in FIG. 8, the material of the oxide semiconductor film may be changed. Any resistance value can be obtained.

[0467] As shown in FIG. 51(A), a pixel section 502 and a drive circuit section 504 are provided with a protection circuit section 506. By providing 06, ESD (Electro Static Discharge) This can improve the display device's resistance to overcurrents caused by electrostatic discharge (ESD) and other factors. However, the configuration of the protection circuit unit 506 is not limited to this. For example, the gate driver 504 a) and a protection circuit unit 506 connected to the source driver 504b. Alternatively, the protection circuit section 506 may be connected to the terminal section 507. A continuous configuration is also possible.

[0468] The sensor circuit portion 508 has a function of correcting the temperature of the transistor or light-emitting element.

[0469] For example, the sensor circuit section 508 can have the configuration shown in FIG.

[0470] FIG. 53A is an example of a circuit configuration that can be used as the sensor circuit section 508. The sensor circuit unit 508 includes a transistor 556, a resistor element 558, and a monitor light emitting element. The gate electrode of the transistor 556 is connected to the gate line for monitoring. and a source electrode and a drain electrode of the transistor 556 electrically connected to MONI_G. One end is electrically connected to one electrode of the light emitting element 572m, and the other end is connected to the source of the transistor 556. The other of the source electrode and drain electrode is electrically connected to the monitor drain line MONI_D. One electrode of the resistor element 558 is connected to the source electrode and drain electrode of the transistor 556. The other electrode of the resistor element 558 is electrically connected to the other of the drain electrodes. The node line MONI_ANO is electrically connected to one electrode of the light emitting element 572m. is electrically connected to the monitor source line MONI_S, and the other The electrodes are electrically connected to the cathode wires.

[0471] The transistor 556 is a driving transistor in the pixel section 502, for example, For example, the sensor circuit unit 508 supplies electricity to the light emitting element 572m. When a current is applied, the gate electrode, source electrode, and drain electrode of the transistor 556, It also has the function of monitoring the voltage and current of the anode line. ,monitor gate line MONI_G, monitor drain line MONI_D, monitor the anode line MONI_ANO for the monitor and the source line MONI_S for the monitor, respectively. Since they are provided independently, it is possible to measure each signal individually.

[0472] For example, by measuring the potential of the monitor source line, the monitor light emitting element 572 m characteristics can be measured. The potential of the drain line MONI_D for the monitor and the source line MONI_S for the monitor are measured. By doing so, the characteristics of the transistor 556 can be measured. Measure the potential of the node line MONI_ANO and the monitor drain line MONI_D. By doing so, the characteristics of the resistance element 558 can be measured.

[0473] Alternatively, the anode line MONI_ANO for the monitor and the gate line MO for the monitor Apply voltage to NI_G to monitor drain line MONI_D and monitor source line MONI_D. By measuring the potential of the drain wire, the temperature can be measured from the potential of the monitor drain wire MONI_D. Alternatively, the anode line MONI_ANO for the monitor and the monitor Apply a voltage to the gate line MONI_G for the monitor, and By measuring the potential of the monitor source line, the potential of the monitor source line MONI_S can be calculated. The Vgs of the transistor 556 and the voltage applied to the light emitting element 572m are measured from the It can be determined.

[0474] Using the above measured values, the other electrode of the light emitting element 572m is electrically connected to Correction can be made by changing the potential of the cathode line or the video data potential. As shown in FIG. 51(A), a sensor circuit portion 508 is provided at each of the four corners of the pixel portion 502. In this configuration, the correction method may be changed depending on the position of each pixel.

[0475] The sensor circuit section 508 may have the configuration shown in FIG. 53(B), for example. 53(B) is a cross-sectional view illustrating the sensor circuit section 508.

[0476] The sensor circuit portion 508 shown in FIG. 53B includes a transistor 556 and a resistor element 558. The transistor 556 includes a conductive film 104 over a substrate 102, and a conductive film 104 and a conductive film 106 over the substrate 102. The insulating films 106 and 107 on the conductive film 104, the oxide semiconductor film 108 on the insulating film 107, and the oxide semiconductor film 108 are a conductive film 112a electrically connected to the oxide semiconductor film 108; The conductive film 112b, the oxide semiconductor film 108, and the conductive films 112a and 112b are electrically connected to each other. 2b, and an oxide semiconductor film 120b on the insulating film 116. do.

[0477] The resistor element 558 is formed by insulating films 106 and 107 on the substrate 102 and a The conductive films 112b and 112c, the insulating film 107, and the insulating film on the conductive films 112b and 112c 114, 116, the oxide semiconductor film 120c on the insulating film 116, and the oxide semiconductor film 120 The oxide semiconductor film 120c has the insulating films 114 and 118 over it. 16 is electrically connected to the conductive film 112b through an opening 152a provided in the conductive film 112b. The oxide semiconductor film 120c is exposed through an opening 152d formed in the insulating films 114 and 116. The conductive film 112b is electrically connected to the conductive film 112c in the transistor 556. serves as the other of the source and drain electrodes, and in the resistor element 558, The conductive film 112c functions as one of the pair of electrodes of the resistor element 558. The conductive film 112c functions as the other anode line MONI_AN for monitoring. It functions as O.

[0478] Note that the transistor 556 has a function similar to that of the transistor 150 described in Embodiment 1. Therefore, in each component of the transistor 556, The same reference numerals and hatching as those in 50 are used. The elements are materials that can be used for the transistor 150 described in Embodiment 1. Please take this into consideration.

[0479] The other of the pair of electrodes of the resistor element 558 is connected to the source electrode and drain electrode of the transistor 556. The conductive film that functions as the rain electrode is formed by processing the same conductive film. The oxide semiconductor film 120c is formed by processing the same oxide semiconductor film as the oxide semiconductor film 120b. As described in Embodiment 1, the oxide semiconductor film 120b is formed of an oxide Since it can be used as a solid conductor (OC), it is possible to use the same oxide as the oxide semiconductor film 120b. The oxide semiconductor film 120c formed by processing the semiconductor film is also an oxide conductor (OC). Therefore, in the circuit diagram shown in FIG. 8 is marked with the symbol OC.

[0480] The oxide semiconductor film 120c included in the resistor 558 has the same structure as the oxide semiconductor film 120b. For example, the oxide semiconductor film 120c is formed using an indium tin oxide (ITO) film. Indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium Zinc oxide, indium tin silicon oxide (ITSO), etc. can be used.

[0481] Referring again to FIG. 51(A), the gate driver 504a and a source driver 504b form the driving circuit unit 504. The present invention is not limited to this configuration. For example, only the gate driver 504a may be formed, and a separately prepared A substrate (for example, a substrate made of a single crystal semiconductor film or a polycrystalline semiconductor film) on which a source driver circuit is formed A drive circuit board (formed on the substrate) may be mounted.

[0482] <4-2. Example of pixel circuit configuration> Furthermore, the plurality of pixel circuits 501 shown in FIG. 51(A) may be, for example, a configuration shown in FIG. 51(B). It can be said that:

[0483] The pixel circuit 501 shown in FIG. 51B includes transistors 552 and 554 and a capacitor 56. 2 and a light-emitting element 572. The transistor described in the above embodiment can be applied to either or both of them.

[0484] One of the source and drain electrodes of the transistor 552 is supplied with a data signal. The transistor 55 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n). The gate electrode 2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are connected to the network.

[0485] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0486] One of a pair of electrodes of the capacitor 562 is connected to the source electrode and drain electrode of the transistor 552. The other of the pair of electrodes of the capacitor 562 is electrically connected to the transistor. The gate electrode (also referred to as a back gate electrode) of the transistor 554 is electrically connected to the second gate electrode (also referred to as a back gate electrode). The capacitor 562 functions as a storage capacitor for holding written data.

[0487] One of the source and drain electrodes of the transistor 554 is connected to the anode line (ANODE _m).

[0488] One of the anode and cathode of the light emitting element 572 is connected to the source electrode of the transistor 554 and The other end is electrically connected to the cathode line (CATHODE). One of the anode and cathode of the light emitting element 572 is electrically connected to a capacitor element. The other of the pair of electrodes 562 is electrically connected.

[0489] For example, an organic EL element can be used as the light emitting element 572. The element 572 is not limited to this, and an inorganic EL element made of an inorganic material may also be used.

[0490] In a display device having the pixel circuit 501 of FIG. 51(B), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0491] The pixel circuit 501 to which the data has been written is turned off by turning off the transistor 552. Furthermore, the transistor 554 is held in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted at a brightness that corresponds to the flow rate. By repeating this process row by row, an image can be displayed.

[0492] In this embodiment, the display device has a light-emitting element 572 as a display element. Although the configuration is exemplified, the display device is not limited to this and may have various elements. .

[0493] The display device may be, for example, an LED (white LED, red LED, green LED, blue LED, etc. ), transistors (transistors that emit light according to current), electron-emitting devices, electronic ink, Electrophoretic element, Grating Light Valve (GLV), Plasma Display (PDP) ), display elements using MEMS (microelectromechanical systems), digital Digital Micromirror Device (DMD), Digital Micro Shutter (DMS), MIRASOL®, an IMOD (Interference Modulation) element shutter-type MEMS display element, optical interference-type MEMS display element, electro Wetting elements, piezoelectric ceramic displays, display elements using carbon nanotubes In addition to these, there are also other types of sensors that can be used to detect electrical or magnetic effects. The display medium may have a variable contrast, brightness, reflectance, transmittance, etc. An example of a display device using electron emission elements is a field emission display (F ED) or SED type flat panel display (SED: Surface-conductive LCD (Electron-emitter Display) and other LCDs. Examples of display devices include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, etc.). LCD, reflective LCD, direct-view LCD, projection LCD An example of a display device using electronic ink or electrophoretic elements is the Semi-transmissive LCD displays and reflective LCD displays are also available. In this case, a part or all of the pixel electrode is designed to function as a reflective electrode. For example, a part or all of the pixel electrodes may be made of aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM should be placed under the reflective electrode. This can further reduce power consumption.

[0494] The display device uses a progressive method, an interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB ( The three colors are not limited to R, G, and B (R stands for red, G for green, and B for blue). For example, It may be composed of four pixels, a B pixel and a W (white) pixel. As shown in the figure, two colors of RGB compose one color element, and two different colors are selected depending on the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but may be applied to monochrome display devices. It can also be applied to display devices.

[0495] Also, backlights for display devices (organic EL elements, inorganic EL elements, LEDs, fluorescent lights, etc.) A white light (W) may be provided in the display device. Also, a colored layer (also called a color filter) may be provided in the display device. As the colored layer, for example, red (R), green (G), blue (B) ), yellow (Y), etc. can be used in combination as appropriate. In this case, the color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. By placing the color layer in the display, the decrease in brightness caused by the color layer can be reduced during bright display, and power consumption can be reduced by 2. However, it may be possible to reduce the emission by approximately 100% to 30%. When using optical elements to display full color, R, G, B, Y, and white (W) are By using a self-luminous element, the color layer can be In some cases, power consumption can be further reduced compared to when using a conventional method.

[0496] <4-3. Example of pixel configuration of display device> Here, regarding an example of a display device having the pixel circuit shown in FIG. 51(B), 54(A) is a top view of a pixel portion of a display device, and FIG. 54(A) is a cross-sectional view taken along the dashed line X1-X2 in FIG. In order to avoid complexity of the drawings, some of the components are omitted.

[0497] The display device shown in FIGS. 54(A) and 54(B) has a first gate electrode on a substrate 702. a conductive film 704 formed on the conductive film 704, insulating films 706 and 707 formed on the conductive film 704, and an oxide film on the insulating film 707. The semiconductor film 708, the insulating film 707, and the source electrode and the drain electrode over the oxide semiconductor film 708 Conductive films 712a and 712b functioning as gate electrodes, and a conductive film 712c over the insulating film 707 , the oxide semiconductor film 708, and the insulating films 714, 712a, 712b, and 712c. 16, an oxide semiconductor film 720 serving as a second gate electrode over the insulating film 716, and An insulating film 718 on the insulating film 716 and the oxide semiconductor film 720, and a planarizing insulating film on the insulating film 718 an insulating film 722 functioning as a film; and a conductive film 722 functioning as a pixel electrode on the insulating film 722. 4a and 724b, and the function of suppressing electrical connection between the conductive film 724a and the conductive film 724b. a structure 726 having conductive films 724a and 724b and an EL layer 728 on the structure 726; , and a conductive film 730 on the EL layer 728 .

[0498] The conductive film 712c is formed through an opening 752c formed in the insulating films 706 and 707. The gate electrode 702 is electrically connected to the conductive film 704. The conductive film 720 is connected to the conductive film 712 through the openings 752 a provided in the insulating films 714 and 716 . The conductive film 724a is electrically connected to the insulating films 714, 716, 718, and 719. 22 is electrically connected to the conductive film 712b through an opening 752b provided in the conductive film 752b.

[0499] In addition, a conductive film 724a functioning as a pixel electrode, an EL layer 728, a conductive film 730, The light emitting element 572 is formed by the above method. Vapor deposition methods (including vacuum deposition methods), printing methods (e.g., letterpress printing, intaglio printing, gravure printing) It can be formed by methods such as printing, lithography, stencil printing, ink jet printing, coating, etc. can.

[0500] As shown in FIG. 54(B) and FIG. 54(A)(B), the pixel configuration of the display device is as follows: By using a structure including two transistors and one capacitor, the number of wirings can be reduced. For example, as shown in Figure 54(B) and Figure 54(A), the pixel may have a gate. The three lines can be a ground line, a data line, and an anode line. This makes it possible to increase the aperture ratio of the pixels of the display device. This makes it difficult for short circuits to occur between adjacent wiring, providing display devices with high yields. It becomes possible to do this.

[0501] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0502] (Embodiment 5) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention and a display device including the semiconductor device will be described. An electronic device having an input device attached thereto will be described with reference to FIGS.

[0503] <5-1. Explanation of the touch panel> In the present embodiment, an example of an electronic device is a device that combines a display device and an input device. The touch panel 2000 will be described. The case where the .sigma. is used will be explained.

[0504] 55(A) and (B) are perspective views of the touch panel 2000. In B), representative components of touch panel 2000 are shown for clarity.

[0505] The touch panel 2000 includes a display device 2501 and a touch sensor 2595 (see FIG. 5 5(B)). The touch panel 2000 also includes a substrate 2510, a substrate 2570, and a substrate The substrate 2510, the substrate 2570, and the substrate 2590 are all However, any one of the substrates 2510, 2570, and 2590 is flexible. Alternatively, one or all of the components may be configured to be non-flexible.

[0506] The display device 2501 has a plurality of pixels on a substrate 2510 and a display device that can supply signals to the pixels. The plurality of wirings 2511 are arranged around the periphery of the substrate 2510. The wire is routed through a cable, part of which forms the terminal 2519. The terminal 2519 is an FPC2509 (1) and electrically connect.

[0507] Here, an example of the configuration of the outer periphery and terminal portion of the substrate 2510 of the display device 2501 will be described. 56 and 57. FIG. 56(A) illustrates an example of the outer periphery of the substrate. 56(A) is a cross-sectional view illustrating an example of a terminal portion, and FIG. 56(B) is a cross-sectional view illustrating an example of a terminal portion. 10A, 10B, and 10C are cross-sectional views illustrating an example of a terminal portion.

[0508] The structure shown in FIG. 56(A) is an insulating film 906 on a substrate 2510 and an insulating film A film 907, insulating films 914 and 916 on the insulating film 907, and the insulating film 906 and the insulating film 916 an insulating film 918 on the insulating film 918; an insulating film 940 on the insulating film 918; and and an upper seal material 942.

[0509] The insulating films 906, 907, 914, 916, and 918 are the insulating films shown in Embodiment 1. The membranes 106, 107, 114, 116, and 118 are formed using the same material and method. can be done.

[0510] The insulating film 940 may be made of an organic insulating material such as an acrylic resin. By forming the insulating film 940, unevenness caused by transistors and the like can be smoothed. The sealing material 942 can be made of, for example, epoxy resin or glass. It is preferable to use a frit as the sealing material. It is preferable to use an opaque material.

[0511] By using the structure of the outer periphery of the substrate shown in FIG. 56(A), the insulating film 906 and the insulating film 918 However, since they are in contact with each other, it is possible to prevent impurities such as moisture from entering from the outside. can.

[0512] The structure shown in FIG. 56(B) is a conductive film 904 on a substrate 2510, and a conductive film 905 on the substrate 2510. An insulating film 906 on the film 904, an insulating film 907 on the insulating film 906, and a conductive film on the insulating film 907. a conductive film 912; insulating films 914 and 916 on the conductive film 912; and a conductive film 912. the insulating films 906 and 916 and the insulating film 916 on the oxide semiconductor film 920; The insulating films 914 and 916 have a thickness that reaches the oxide semiconductor film 920. The insulating film 918 has an opening 930a that reaches the oxide semiconductor film 920. The oxide semiconductor film 920 has an opening 930b formed therethrough. It is electrically connected to FPC2509(1) via a

[0513] The conductive films 904 and 912 and the oxide semiconductor film 920 are the same as those in the conductive film 904 described in Embodiment 1. The conductive film 104, the conductive film 112, and the oxide semiconductor film 120 are formed using the same material and method. It is possible.

[0514] In FIG. 56(B), the conductive film 904 is provided on the substrate 2510. However, the present invention is not limited to this example. For example, as shown in FIG. 57(A), A structure without the conductive film 904 may be used. 2. However, the present invention is not limited to this. For example, For example, as shown in FIG. 57B, the oxide semiconductor film 920 may not be provided. Alternatively, as shown in FIG. 57C, the conductive film 904 and the oxide semiconductor film 920 are not provided. This may also be configured as follows.

[0515] However, as shown in FIG. 56(B) and FIG. 57(A), the anisotropic conductive film 944 is connected to In the region where the oxide semiconductor film 920 is provided, the oxide semiconductor film 920 is preferably provided. By adopting such a structure, the adhesion to the anisotropic conductive film 944 can be improved.

[0516] Referring again to FIG. 55(B), the substrate 2590 includes a touch sensor 2595 and a touch The sensor 2595 is electrically connected to a plurality of wires 2598. is routed around the outer periphery of the substrate 2590, and a part of it constitutes a terminal. It is electrically connected to FPC2509(2). For clarity, in Figure 55(B), A touch sensor 2595 is provided on the back side of the plate 2590 (the surface facing the substrate 2510). Electrodes, wiring, etc. are shown by solid lines.

[0517] As the touch sensor 2595, for example, a capacitance type touch sensor can be applied. The capacitive type includes a surface type electrostatic capacitance type and a projected type electrostatic capacitance type.

[0518] The projected capacitive type is mainly divided into self-capacitance type and mutual capacitance type, which differ mainly in the driving method. The mutual capacitance method is preferable because it allows simultaneous multi-point detection.

[0519] The touch sensor 2595 shown in FIG. 55(B) is a projected capacitive touch sensor. This is a configuration in which the .

[0520] The touch sensor 2595 can detect the proximity or contact of a detection object such as a finger. Various sensors can be applied.

[0521] The projected capacitive touch sensor 2595 has an electrode 2591 and an electrode 2592. The electrode 2591 is electrically connected to one of the plurality of wirings 2598, and the electrode 2592 is It is electrically connected to any other of the plurality of wirings 2598.

[0522] As shown in FIG. 55(B), the electrodes 2592 are formed by a plurality of four-sided electrodes repeatedly arranged in one direction. The shapes have corner-connected shapes.

[0523] The electrode 2591 is quadrilateral and is repeated in a direction intersecting the direction in which the electrode 2592 extends. are placed.

[0524] The wiring 2594 is electrically connected to the two electrodes 2591 that sandwich the electrode 2592. In this case, it is preferable that the area of ​​the intersection between the electrode 2592 and the wiring 2594 is as small as possible. This reduces the area where no electrodes are provided, reducing variations in transmittance. As a result, the variation in brightness of light passing through the touch sensor 2595 can be reduced. can be done.

[0525] The shapes of the electrodes 2591 and 2592 are not limited to this, and may take various shapes. For example, multiple electrodes 2591 are arranged with as few gaps as possible, and A plurality of electrodes 2592 are provided at intervals so that there is an area where they do not overlap with the electrodes 2591. In this case, a contact between two adjacent electrodes 2592 may be provided. Providing an insulated dummy electrode is preferable because it can reduce the area of ​​the region with different transmittance. .

[0526] The conductive films such as the electrodes 2591, 2592, and wiring 2598, that is, the touch panel Materials that can be used for the wiring and electrodes that make up the filter include indium oxide, tin oxide, and oxide. Examples of the transparent conductive film include a transparent conductive film containing zinc oxide (e.g., ITO). As a material that can be used for the wiring and electrodes that constitute the device, for example, a material with a low resistance value is preferred. Examples include silver, copper, aluminum, carbon nanotubes, graphene, and halogens. Metal halide (such as silver halide) may also be used. Even if metal nanowires (several nanometers in diameter) are used, which are composed of multiple conductors, Alternatively, a metal mesh made of a conductor may be used. Nanowires, Cu nanowires, Al nanowires, Ag mesh, Cu mesh, Al plated For example, Ag nanowires may be used for the wiring and electrodes that make up the touch panel. When using a material with a visible light transmittance of 89% or more and a sheet resistance of 40Ω / □ or more, 0Ω / □ or less. Examples of materials that can be used include metal nanowires, metal meshes, and carbon nanotubes. Tubes, graphene, etc. have high transmittance in visible light, so they are suitable for electrodes ( For example, it may be used as a pixel electrode or a common electrode.

[0527] <5-2. Explanation of display devices> Next, the display device 2501 will be described in detail with reference to Figures 58(A) and 58(B). 8(A) and 8(B) correspond to cross-sectional views taken along the dashed line X1-X2 shown in FIG. 55(B).

[0528] The display device 2501 has a plurality of pixels arranged in a matrix. and a pixel circuit for driving the display element.

[0529] [Configuration using EL elements as display elements] First, a configuration using an EL element as a display element will be described below with reference to FIG. 58(A). In the following description, the case where an EL element that emits white light is applied will be described. However, the EL element is not limited to this. For example, EL elements having different emission colors may be applied so that the colors of the light emitted from the EL elements are different.

[0530] The substrate 2510 and the substrate 2570 are, for example, made of a material having a water vapor permeability of 10 -5 g / (m 2 ·day) or less, preferably 10 -6 g / (m 2 · Flexibility of less than 1 day Alternatively, the thermal expansion coefficient of the substrate 2510 and the thermal expansion coefficient of the substrate 2570 can be adjusted. It is preferable to use a material with a thermal expansion coefficient that is approximately equal to the coefficient of linear expansion of the material. For example, a material with a linear expansion coefficient of 1×10 - 3 / K or less, preferably 5×10 -5 / K or less, more preferably 1×10 -5 / K or less Certain materials may be used advantageously.

[0531] The substrate 2510 is made of an insulating layer 2510a that prevents impurities from diffusing into the EL element, and a flexible The substrate 2510b and the adhesive layer 2 that bonds the insulating layer 2510a and the flexible substrate 2510b together. The substrate 2570 is a laminate having a layer 510c and a layer 510d. and a flexible substrate 2570b. 2570b and an adhesive layer 2570c that bonds them together.

[0532] The adhesive layer 2510c and the adhesive layer 2570c may be made of, for example, polyester or polyolefin. Polyimide, polycarbonate or acrylic The material used is a resin containing styrene, polyurethane, epoxy resin, or a resin having a siloxane bond. You can be there.

[0533] In addition, a sealing layer 2560 is provided between the substrate 2510 and the substrate 2570. It is preferable that the refractive index of the sealing material is larger than that of air. When light is extracted to the layer 2560 side, the sealing layer 2560 can also serve as an optical element.

[0534] A sealant may be formed on the outer periphery of the sealing layer 2560. As a result, the area surrounded by the substrate 2510, the substrate 2570, the sealing layer 2560, and the sealant The sealing layer 2560 may have an EL element 2550. It may be filled with an inert gas (nitrogen, argon, etc.). Also, a desiccant may be placed in the inert gas. It may be configured to adsorb moisture and the like.

[0535] The display device 2501 shown in FIG. 58(A) includes a pixel 2505. 505 is a light emitting module 2580, an EL element 2550, and a and a transistor 2502t that can supply a 2t functions as a part of the pixel circuit.

[0536] The light emitting module 2580 also includes an EL element 2550 and a colored layer 2567 . The EL element 2550 has a lower electrode, an upper electrode, and an EL element between the lower electrode and the upper electrode. The layer.

[0537] Furthermore, when the sealing layer 2560 is provided on the side from which light is extracted, the sealing layer 2560 has a property of E The L element 2550 and the colored layer 2567 are in contact with each other.

[0538] The colored layer 2567 is located so as to overlap the EL element 2550. A part of the light emitted by 50 passes through the colored layer 2567 and travels to the light emitting module in the direction of the arrow shown in the figure. It is ejected outside of Rule 2580.

[0539] The display device 2501 is also provided with a light-shielding layer 2568 in the light-emitting direction. Layer 2568 is provided to surround colored layer 2567 .

[0540] The colored layer 2567 may have a function of transmitting light in a specific wavelength band. For example, For example, a color filter that transmits light in the red wavelength band, a color filter that transmits light in the green wavelength band, a color filter that transmits light in the blue wavelength band, a color filter that transmits light in the yellow wavelength band, Each color filter can be made of various materials. In this regard, printing methods, inkjet methods, etching methods using photolithography technology, etc. It can be formed by

[0541] The display device 2501 is also provided with an insulating layer 2521. The insulating layer 2521 covers the resistor 2502t and other components. In addition, the insulating layer 2521 has a function of suppressing impurity diffusion. This prevents the reliability of the transistor 2502t and the like from being reduced due to the diffusion of impurities. can be suppressed.

[0542] The EL element 2550 is formed above the insulating layer 2521. The lower electrode of 50 is provided with a partition wall 2528 that overlaps the edge of the lower electrode. A spacer for controlling the distance between the substrate 2510 and the substrate 2570 is formed on the partition wall 2528. You may do so.

[0543] The scan line driver circuit 2504 includes a transistor 2503t, a capacitor 2503c, and The driver circuit and the pixel circuit can be formed on the same substrate in the same process. .

[0544] Moreover, wiring 2511 capable of supplying signals is provided on the substrate 2510 . A terminal 2519 is provided on the wiring 2511. The terminal 2519 is also provided with an FP C2509(1) is electrically connected. FPC2509(1) also transmits video signals, It has the function of supplying clock signals, start signals, reset signals, etc. 509(1) may have a printed wiring board (PWB) attached.

[0545] Note that either one or both of the transistor 2502t and the transistor 2503t The transistor described in the above embodiment may be applied to the transistor. The transistor has a highly purified oxide semiconductor film with high crystallinity. Therefore, the current value (off-state current value) at the time of the image signal or the like can be reduced. The data retention time can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, which has the effect of reducing power consumption. The refresh operation will be described in detail later.

[0546] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving can be used in a display device. By using it in the device 2501, the switching transistor of the pixel circuit and the In other words, a separate driver circuit can be formed on the same substrate. Since it is not necessary to use a semiconductor device formed from a silicon wafer or the like, The number of parts in the device can be reduced. Also, the pixel circuit can be driven at high speed. By using a transistor, a high-quality image can be provided.

[0547] [Configuration using liquid crystal elements as display elements] Next, a configuration using a liquid crystal element as a display element will be explained below with reference to FIG. 58(B). In the following description, a reflective liquid crystal display device that displays by reflecting external light will be described. However, the liquid crystal display device is not limited to this. For example, a light source (backlight , side light, etc.) to make a transmissive liquid crystal display device, or a combination of reflective and transmissive functions. The liquid crystal display device may also have such a function.

[0548] The display device 2501 shown in FIG. 58(B) has the following features in common with the display device 2501 shown in FIG. 58(A). The other configurations are the same as the display device 2501 shown in FIG. is.

[0549] A pixel 2505 of a display device 2501 shown in FIG. 58(B) includes a liquid crystal element 2551 and a liquid crystal element and a transistor 2502t capable of supplying power to the transistor 2551.

[0550] The liquid crystal element 2551 has a lower electrode (also called a pixel electrode), an upper electrode, and a and an upper electrode, and a liquid crystal layer 2529 between the lower electrode and the upper electrode. The orientation state of the liquid crystal layer 2529 can be changed by applying a voltage between the electrodes. In addition, a spacer 2530a and a spacer 2530b are provided in the liquid crystal layer 2529. Although not shown in FIG. 58(B), the liquid crystal layer 25 of the upper electrode and the lower electrode An alignment film may be provided on each side in contact with 29.

[0551] The liquid crystal layer 2529 may be a thermotropic liquid crystal, a low molecular weight liquid crystal, a high molecular weight liquid crystal, a high molecular weight liquid crystal, or a high molecular weight liquid crystal. The liquid crystal material can be a dispersion liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. Depending on the conditions, cholesteric phase, smectic phase, cubic phase, chiral nematic phase, etc. In addition, when a liquid crystal display device employs a horizontal electric field method, an alignment film When a liquid crystal exhibiting a blue phase is used, the alignment Since there is no need to provide a film, rubbing treatment is not required. It is possible to prevent electrostatic breakdown caused during the rubbing process, and the liquid crystal display during the manufacturing process This can reduce malfunctions and damage to display devices.

[0552] The spacers 2530a and 2530b are obtained by selectively etching the insulating film. The spacers 2530a and 2530b are spaced apart by a distance between the substrate 2510 and the substrate 2570. The spacers 2530a and 2530b are provided to control the cell gap. The sizes of the particles may be different from each other, and it is preferable that the particles are provided in a columnar or spherical shape. In 58(B), the spacers 2530a and 2530b are provided on the substrate 2570 side. However, the present invention is not limited to this configuration, and the substrate 2510 may be provided thereon.

[0553] The upper electrode of the liquid crystal element 2551 is provided on the substrate 2570 side. An insulating layer 2531 is provided between the electrode and the colored layer 2567 and the light-shielding layer 2568. The edge layer 2531 has the function of flattening the unevenness caused by the colored layer 2567 and the light-shielding layer 2568. The insulating layer 2531 may be, for example, an organic resin film. The lower electrode 2551 functions as a reflective electrode. 501 is a reflection type display that uses external light and reflects it at the lower electrode to display it through the colored layer 2567. In the case of a transmission type liquid crystal display device, a transparent electrode is used as the lower electrode. All that is needed is to give it a function as a pole.

[0554] The display device 2501 shown in FIG. 58(B) also includes an insulating layer 2522. The insulating layer 2522 covers the transistor 2502t and the like. and forming unevenness on the lower electrode of the liquid crystal element. This makes it possible to form irregularities on the surface of the lower electrode. When light is incident on the lower electrode, it becomes possible for the light to be diffusely reflected on the surface of the lower electrode. In the case of a transmission type liquid crystal display device, the above-mentioned unevenness can be provided. It may also be configured so that this is not the case.

[0555] <5-3. Explanation of touch sensors> Next, the touch sensor 2595 will be described in detail with reference to FIG. 55(B) along the dashed line X3-X4.

[0556] The touch sensor 2595 is made up of electrodes 2591 and electrodes 2592 arranged in a staggered pattern on a substrate 2590. 2592, an insulating layer 2593 covering the electrodes 2591 and 2592, and the adjacent electrodes 25 91 and a wiring 2594 that electrically connects them.

[0557] The electrode 2591 and the electrode 2592 are formed using a light-transmitting conductive material. Examples of conductive materials having the formula include indium oxide, indium tin oxide, and indium zinc oxide. Conductive oxides such as zinc oxide, zinc oxide, and zinc oxide doped with gallium can be used. A film containing graphene may also be used. The film containing graphene may be, for example, a film-like The graphene oxide film can be formed by reducing the graphene oxide film formed on the substrate. For example, a method of applying heat can be mentioned.

[0558] For example, a film of a light-transmitting conductive material is formed on the substrate 2590 by sputtering. After that, various patterning techniques such as photolithography are used to remove unnecessary parts. , an electrode 2591 and an electrode 2592 can be formed.

[0559] The insulating layer 2593 may be made of a resin such as acrylic or epoxy. In addition to resins with siloxane bonds, silicon oxide, silicon oxynitride, aluminum oxide, Inorganic insulating materials such as rubber can also be used.

[0560] An opening reaching the electrode 2591 is provided in the insulating layer 2593, and a wiring 2594 is adjacent to the opening. The transparent conductive material is used to increase the aperture ratio of the touch panel. Therefore, it can be suitably used for the wiring 2594. A material having higher conductivity than the electrode 2592 is preferable for the wiring 2594 because it can reduce electrical resistance. It can be used appropriately.

[0561] The electrodes 2592 extend in one direction, and a plurality of electrodes 2592 are provided in a stripe pattern. Moreover, the wiring 2594 is provided so as to intersect with the electrode 2592.

[0562] A pair of electrodes 2591 is provided with one electrode 2592 sandwiched therebetween. A pair of electrodes 2591 are electrically connected.

[0563] The plurality of electrodes 2591 are arranged in a direction that is not necessarily perpendicular to one electrode 2592. The angle does not have to be 0 degrees, and may be greater than 0 degrees but less than 90 degrees.

[0564] The wiring 2598 is electrically connected to the electrode 2591 or the electrode 2592. A part of the wiring 2598 functions as a terminal. The wiring 2598 is made of, for example, aluminum. Aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum, iron, Use of metal materials such as ballast, copper, or palladium, or alloy materials containing such metal materials. can be done.

[0565] An insulating layer covering the insulating layer 2593 and the wiring 2594 is provided, and the touch sensor 2595 may be protected.

[0566] The connection layer 2599 electrically connects the wiring 2598 and the FPC 2509(2). .

[0567] The connection layer 2599 is made of an anisotropic conductive film (ACF). conductive film) and anisotropic conductive paste (ACP) Conductive Paste) can be used.

[0568] <5-4. Explanation of the touch panel> Next, details of the touch panel 2000 will be described with reference to FIG. (A) corresponds to a cross-sectional view taken along the dashed dotted line X5-X6 shown in FIG. 55(A).

[0569] The touch panel 2000 shown in FIG. 60(A) is the same as the display device 250 described in FIG. 55(A). 1 and the touch sensor 2595 described in FIG. 59 are bonded together.

[0570] The touch panel 2000 shown in FIG. 60(A) has the same configuration as that described in FIG. 58(A). , an adhesive layer 2597 and an anti-reflective layer 2569 .

[0571] The adhesive layer 2597 is provided in contact with the wiring 2594. The substrate 2590 is attached to the substrate 2570 so that the sensor 2595 overlaps the display device 2501. The adhesive layer 2597 is preferably transparent. The material 597 can be a thermosetting resin or an ultraviolet curing resin. For example, Acrylic resin, urethane resin, epoxy resin, or siloxane resin may be used. This can be done.

[0572] The anti-reflection layer 2569 is provided at a position overlapping the pixel. For example, a circular polarizer can be used.

[0573] Next, for a touch panel with a different configuration from that shown in Figure 60(A), Figure 60(B) This will be used to explain.

[0574] FIG. 60(B) is a cross-sectional view of the touch panel 2001. The panel 2001 is a touch panel 2000 shown in FIG. 60(A) and a display device 2501. The location of the touch sensor 2595 is different. Here, the different configurations are explained in detail. The description of the touch panel 2000 is cited for the parts where a similar configuration can be used.

[0575] The colored layer 2567 is located below the EL element 2550. The L element 2550 emits light to the side where the transistor 2502t is provided. As a result, a part of the light emitted by the EL element 2550 passes through the colored layer 2567 and is reflected by the light emitting element 2550 in the direction of the arrows shown in the figure. The light is emitted to the outside of the light emitting module 2580 in the direction of the mark.

[0576] The touch sensor 2595 is provided on the substrate 2510 side of the display device 2501. .

[0577] The adhesive layer 2597 is between the substrate 2510 and the substrate 2590 and is in contact with the display device 2501. Stick the Chisensor 2595 together.

[0578] As shown in FIGS. 60(A) and 60(B), the light emitted from the light emitting element is guided by the substrate 2510 and the substrate 2511. It may be injected through either or both of the plates 2570 .

[0579] <5-5. Explanation of touch panel driving method> Next, an example of a method for driving a touch panel will be described with reference to FIG.

[0580] FIG. 61(A) is a block diagram showing the configuration of a mutual capacitance type touch sensor. In (A), a pulse voltage output circuit 2601 and a current detection circuit 2602 are shown. In FIG. 61(A), the electrodes 2621 to which the pulse voltage is applied are designated as X1-X6, and the change in current The electrodes 2622 for detecting the change are shown as Y1-Y6, each with six wires. In addition, FIG. 61(A) shows a capacitance formed by overlapping an electrode 2621 and an electrode 2622. 2603. The electrodes 2621 and 2622 are interchangeable in function. It may be possible.

[0581] The pulse voltage output circuit 2601 is a circuit for applying pulses to the X1-X6 wirings in sequence. When a pulse voltage is applied to the wiring of X1-X6, the voltage that forms the capacitance 2603 An electric field is generated between the electrodes 2621 and 2622. The electric field generated between the electrodes is By using the change in the mutual capacitance of the capacitance 2603, the proximity of the object to be detected or A contact can be detected.

[0582] The current detection circuit 2602 detects the change in the mutual capacitance of the capacitor 2603 between the wires Y1 and Y6. This is a circuit for detecting changes in current. The wiring of Y1-Y6 detects the proximity of the object to be detected, Or, if there is no contact, the detected current value will not change, but the proximity of the object to be detected, or When the mutual capacitance decreases due to contact, a decrease in the current value is detected. The detection may be performed using an integrating circuit or the like.

[0583] Next, FIG. 61(B) shows the input of the mutual capacitance type touch sensor shown in FIG. 61(A). The timing chart of the output waveform is shown in Figure 61(B). In addition, in FIG. 61(B), when the object to be detected is not detected ( Two cases are shown: when the object is detected (touched) and when the object is not detected (touched). For the wiring of Y1-Y6, the waveform is shown as a voltage value corresponding to the detected current value. There are.

[0584] A pulse voltage is applied to the wires X1-X6 in order, and the The waveform in the Y6 wiring changes. When there is no proximity or contact of the object to be detected, X1-X6 The waveforms of Y1-Y6 change uniformly according to the change in the voltage of the wiring. Or, at the contact point, the current value decreases, and the corresponding voltage waveform also changes. do.

[0585] In this way, by detecting the change in mutual capacitance, the proximity or contact of the object to be detected can be detected. It is possible.

[0586] <5-6. Explanation of sensor circuit> In addition, in FIG. 61(A), only a capacitor 2603 is provided at the intersection of the wiring as a touch sensor. Although the configuration of a passive touch sensor has been shown, an active touch sensor having a transistor and a capacitor may also be used. One of the sensor circuits included in the active type touch sensor may be An example is shown in Figure 62.

[0587] The sensor circuit shown in FIG. 62 includes a capacitor 2603, a transistor 2611, and a transistor 2612 and a transistor 2613.

[0588] A signal G2 is applied to the gate of the transistor 2613, and a signal G3 is applied to either the source or the drain of the transistor 2613. A voltage VRES is applied, and the other is connected to one electrode of the capacitor 2603 and the transistor 2611 The transistor 2611 has a source and a drain electrically connected to the gate of the transistor 2611. The source or drain of the transistor 2612 is electrically connected to the voltage VS The transistor 2612 receives a signal G1 at its gate and a signal S at its source or The other electrode of the drain is electrically connected to the wiring ML. The other electrode of the capacitor 2603 is connected to a voltage VS S is given.

[0589] Next, the operation of the sensor circuit shown in Figure 60 will be described. First, the signal G2 is When a potential is applied to turn on the transistor 2613, the gate of the transistor 2611 is turned on. A potential corresponding to the voltage VRES is applied to the node n to which the signal G2 is connected. When a potential that turns off the transistor 2613 is applied, the potential of the node n Retained.

[0590] Next, the mutual capacitance of the capacitor 2603 changes when a detection object such as a finger approaches or touches the sensor. As a result, the potential of the node n changes from VRES.

[0591] The read operation applies a potential to the signal G1 that turns on the transistor 2612. The current flowing through the transistor 2611 in accordance with the potential of the node n, that is, the current flowing through the wiring ML By detecting this current, the proximity or contact of the object to be detected can be detected. This can be done.

[0592] The transistor 2611, the transistor 2612, and the transistor 2613 are In particular, the transistor 2613 can be applied to the transistor shown in the above embodiment. By using the transistor described in this embodiment, the potential of the node n can be maintained for a long period of time. This allows the node n to be supplied with VRES again (refresh operation). ) can be reduced in frequency.

[0593] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0594] (Sixth embodiment) In this embodiment, a display element of a lateral electric field mode (also called a horizontal electric field mode) is used. A display device using a liquid crystal element will be described with reference to FIG.

[0595] FIG. 63 is a flow chart for explaining the manufacturing process of a display device using a lateral electric field mode liquid crystal element. In FIG. 63, oxide semiconductors (especially CAAC-OS), low-temperature polysilicon Low Temperature Poly-Silicon (LTPS), and When hydrogenated amorphous silicon (a-Si:H) is used as the active layer of a transistor, Each represents an example of a manufacturing process.

[0596] <6-1.CAAC-OS> The use of CAAC-OS in a transistor will be described. A gate electrode (GE) is formed in the device (SP). When processing the gate electrode, one mask is used.

[0597] Next, a gate insulating film (GI) is formed on the gate electrode using a PECVD device. Then, a sputtering device is used to form a silicon carbide (SiC) on the gate insulating film. An oxide semiconductor (OS) film is formed as an active layer. The oxide semiconductor film is processed into an island shape. Use one mask when

[0598] Next, a part of the gate insulating film is processed to form an opening that reaches the gate electrode. When forming the opening, one mask is used.

[0599] Next, a conductive film is formed over the gate insulating film and the oxide semiconductor film using a sputtering apparatus. The conductive film is then processed to form source and drain electrodes (S / D electrodes). It should be noted that one mask is used when forming the source electrode and the drain electrode.

[0600] Next, a PECVD apparatus is used to form a pattern on the oxide semiconductor film, the source electrode, and the drain electrode. An oxidation film is formed.

[0601] Next, a part of the passivation film is processed to form an opening that reaches the source electrode or the drain electrode. A mouth is formed. When forming the opening, one mask is used.

[0602] Next, a film is placed on the passivation film to cover the opening formed in the passivation film. A conductive film is formed using a sputtering device, and the common electrode is formed by processing the conductive film. When forming the common electrode, one mask is used.

[0603] Next, an insulating film is formed on the passivation film and the common electrode using a PECVD device. After that, a part of the insulating film is opened to form an opening that reaches the source electrode or the drain electrode. When forming the insulating film (when forming an opening in a part of the insulating film), Use one card.

[0604] Next, a conductive film is formed on the insulating film using a sputtering device, and the conductive film is processed. The pixel electrodes are formed by this process. Note that one mask is used when forming the pixel electrodes.

[0605] Through the above steps, a liquid crystal display device of the lateral electric field mode can be manufactured. When the -OS is used, the number of masks required for a lateral electric field mode liquid crystal display device is eight.

[0606] <6-2.LTPS> The case where LTPS is used for a transistor will be explained. First, the sputtering equipment A light-shielding film is formed using a mask. When processing the light-shielding film, one mask is used.

[0607] Next, a base insulating film is formed on the light-shielding film using a PECVD device. Using a PECVD device, Si is formed on the film to become the active layer. To anneal the film, excimer laser annealing (ELA) is used. After the ELA process, the active layer Si is annealed by crystallizing silicon ( In order to perform ELA on a large area, Large-scale equipment is required, and linear irregularities specific to ELA may occur.

[0608] Next, the p-Si is processed to form islands. When processing the p-Si into islands, a mask is used. Use one.

[0609] Next, a gate insulating film (GI) is formed on the p-Si using a PECVD device. After that, a gate electrode (GE) is formed on the gate insulating film using a sputtering device. When forming the gate electrode, one mask is used. Additionally, a portion of the gate insulating film is also removed.

[0610] Next, ion doping (ID: Ion D) is performed to form an n+ region in the p-Si. The impurity is implanted using a masking device. Next, to form an n-region in the p-Si, an ion doping device is used. When forming the n-region, the impurity is implanted on the entire surface without using a mask. Next, an ion doping device is used to form a p+ region in the p-Si. The impurity is implanted using a mask. do.

[0611] Next, thermal activation is performed. For the thermal activation, an annealing furnace, an RTA device, etc. may be used. stomach.

[0612] Next, an interlayer insulating film is formed on the p-Si and gate electrode using a PECVD device. Then, the interlayer insulating film and part of the gate insulating film are processed to form n+ and p+ regions. An opening is formed that reaches the substrate. When forming the opening, one mask is used.

[0613] Next, a conductive film is formed on the interlayer insulating film in which the opening is formed, using a sputtering device. The conductive film is then processed to form source and drain electrodes (S / D electrodes). It should be noted that one mask is used when forming the source electrode and the drain electrode.

[0614] Next, a planarizing insulating film is formed on the source electrode and the drain electrode using a coater device. As the planarizing insulating film, for example, an organic resin film or the like may be used. When forming, one mask is used.

[0615] Next, a conductive film is formed on the planarization insulating film using a sputtering apparatus. A common electrode is formed on the substrate. When forming the common electrode, one mask is used.

[0616] Next, an insulating film is formed on the common electrode using a PECVD device. An opening is formed in a part of the insulating layer, reaching the source electrode or the drain electrode. When forming the film (when forming an opening in a part of the insulating film), one mask is used.

[0617] Next, a conductive film is formed on the insulating film using a sputtering device, and the conductive film is processed. The pixel electrodes are formed by this process. Note that one mask is used when forming the pixel electrodes.

[0618] Through the above steps, a lateral electric field mode liquid crystal display device can be manufactured. When using this, the number of masks required for a lateral electric field mode liquid crystal display device is 11.

[0619] <6-3. a-Si:H> The case of using a-Si:H for a transistor will be explained. First, the sputtering equipment The gate electrode (GE) is formed using a mask. Use one of the following.

[0620] Next, a gate insulating film (GI) is formed on the gate electrode using a PECVD device. After that, a silicon film that will become the active layer is formed on the gate insulating film using a PECVD device. When processing the silicon film into islands, one mask is used.

[0621] Next, a part of the gate insulating film is processed to form an opening that reaches the gate electrode. When forming the opening, one mask is used.

[0622] Next, a conductive film is formed on the gate insulating film using a sputtering apparatus. The capacitor electrodes are formed by processing the mask. Use 10 pieces.

[0623] Next, a conductive film is formed on the gate insulating film and the silicon film using a sputtering device. The conductive film is processed to form source and drain electrodes (S / D electrodes). It should be noted that one mask is used when forming the source electrode and the drain electrode.

[0624] Next, a conductive film is formed on the source electrode and the drain electrode using a sputtering device. The conductive film is processed to form a common electrode. , use one mask.

[0625] Next, an insulating film is formed on the common electrode using a PECVD device. An opening is formed in a part of the insulating film, reaching the source electrode or the drain electrode. When forming the insulating film (when forming an opening in a part of the insulating film), one mask is used.

[0626] Next, a conductive film is formed on the insulating film using a sputtering device, and the conductive film is processed. The pixel electrodes are formed by this process. Note that one mask is used when forming the pixel electrodes.

[0627] By the above process, a liquid crystal display device of the horizontal electric field mode can be manufactured. When :H is used, the number of masks required for a lateral electric field mode liquid crystal display device is eight.

[0628] In each flow shown for CAAC-OS, LTPS, and a-Si:H, Electrode formation, insulating film formation on the common electrode, and pixel electrode formation are performed using a horizontal electric field mode liquid crystal. Due to the process involved in the display device, the liquid crystal element is in a vertical electric field mode (e.g., VA mode, etc.) ) liquid crystal display device, or when an organic EL element is used as a display element. may be different processes.

[0629] As shown in Figure 63, a CAAC transistor is used in a liquid crystal element of the horizontal electric field mode. By using -OS, the manufacturing process can be simplified compared to LTPS. A transistor using CAAC-OS has the same performance as a transistor using a-Si:H. The mobility is high with the number of masks. Therefore, the transistor using CAAC-OS has The device may include a part or all of the driver circuit (gate driver or source driver). This makes it possible to

[0630] The characteristics of each process are summarized in Table 3.

[0631] [Table 3]

[0632] As shown in Table 3, by using CAAC-OS, the number of masks required is equivalent to that of a-Si:H. It can be fabricated and has better electrical properties (field effect mobility (simply called mobility), or on / off ratio, etc.) is high. Therefore, by using CAAC-OS, As shown in Table 3, it is possible to produce a display device with high display quality. Compared to LTPS, S has a lower maximum process temperature and is also Therefore, it is possible to realize a display device with reduced manufacturing costs. become.

[0633] Note that transistors using oxide semiconductors, such as CAAC-OS...

Claims

1. a light-emitting element having a first pixel electrode; a first transistor, one of a source electrode or a drain electrode of which is electrically connected to the first pixel electrode, and the other of which is electrically connected to an anode line, and which has a function of controlling the supply of current to the light-emitting element in accordance with an image signal; a second transistor, one of a source electrode and a drain electrode of which is electrically connected to the first gate electrode of the first transistor; A light-emitting device having a pixel comprising: a first conductive film that overlaps with the first pixel electrode and with a second pixel electrode of an adjacent pixel, and that functions as the first gate electrode; a semiconductor film having a region disposed above the first conductive film and having a channel formation region of the first transistor; a second conductive film having a region disposed above the semiconductor film and functioning as a second gate electrode of the first transistor; a third conductive film having a region disposed above the semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region disposed above the semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; the first pixel electrode has a region disposed above the third conductive film via an insulating film; each of the first pixel electrode and the second pixel electrode has a region in contact with an upper surface of the insulating film; a region of the first conductive film that overlaps with the third conductive film is larger than a region of the first conductive film that overlaps with the fourth conductive film; Light-emitting device.

2. a light-emitting element having a first pixel electrode; a first transistor, one of a source electrode or a drain electrode of which is electrically connected to the first pixel electrode, and the other of which is electrically connected to an anode line, and which has a function of controlling the supply of current to the light-emitting element in accordance with an image signal; a second transistor, one of a source electrode and a drain electrode of which is electrically connected to the first gate electrode of the first transistor; A light-emitting device having a pixel comprising: a first conductive film that overlaps with the first pixel electrode and with a second pixel electrode of an adjacent pixel, and that functions as the first gate electrode; a semiconductor film having a region disposed above the first conductive film and having a channel formation region of the first transistor; a second conductive film having a region disposed above the semiconductor film and functioning as a second gate electrode of the first transistor; a third conductive film having a region disposed above the semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region disposed above the semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; the first pixel electrode has a region disposed above the third conductive film via an insulating film; each of the first pixel electrode and the second pixel electrode has a region in contact with an upper surface of the insulating film; a region of the first conductive film that overlaps with the third conductive film is larger than a region of the first conductive film that overlaps with the fourth conductive film; a region of the first conductive film that overlaps with the third conductive film has an overlap with the second conductive film; Light-emitting device.

3. a light-emitting element having a first pixel electrode; a first transistor, one of a source electrode or a drain electrode of which is electrically connected to the first pixel electrode, and the other of which is electrically connected to an anode line, and which has a function of controlling the supply of current to the light-emitting element in accordance with an image signal; a second transistor, one of a source electrode and a drain electrode of which is electrically connected to the first gate electrode of the first transistor; A light-emitting device having a pixel comprising: a first conductive film that overlaps with the first pixel electrode and with a second pixel electrode of an adjacent pixel, and that functions as the first gate electrode; a semiconductor film having a region disposed above the first conductive film and having a channel formation region of the first transistor; a second conductive film having a region disposed above the semiconductor film and functioning as a second gate electrode of the first transistor; a third conductive film having a region disposed above the semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region disposed above the semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; the first pixel electrode has a region disposed above the third conductive film via an insulating film and a region in contact with the third conductive film; each of the first pixel electrode and the second pixel electrode has a region in contact with an upper surface of the insulating film; a region of the first conductive film that overlaps with the third conductive film is larger than a region of the first conductive film that overlaps with the fourth conductive film; Light-emitting device.

4. a light-emitting element having a first pixel electrode; a first transistor, one of a source electrode or a drain electrode of which is electrically connected to the first pixel electrode, and the other of which is electrically connected to an anode line, and which has a function of controlling the supply of current to the light-emitting element in accordance with an image signal; a second transistor, one of a source electrode and a drain electrode of which is electrically connected to the first gate electrode of the first transistor; A light-emitting device having a pixel comprising: a first conductive film that overlaps with the first pixel electrode and with a second pixel electrode of an adjacent pixel, and that functions as the first gate electrode; a semiconductor film having a region disposed above the first conductive film and having a channel formation region of the first transistor; a second conductive film having a region disposed above the semiconductor film and functioning as a second gate electrode of the first transistor; a third conductive film having a region disposed above the semiconductor film and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region disposed above the semiconductor film and functioning as the other of the source electrode and the drain electrode of the first transistor; the first pixel electrode has a region disposed above the third conductive film via an insulating film and a region in contact with the third conductive film; each of the first pixel electrode and the second pixel electrode has a region in contact with an upper surface of the insulating film; a region of the first conductive film that overlaps with the third conductive film is larger than a region of the first conductive film that overlaps with the fourth conductive film; a region of the first conductive film that overlaps with the third conductive film has an overlap with the second conductive film; Light-emitting device.

Images