Semiconductor device

Abstract

To provide a semiconductor device which suppresses wire flow and can suppress increase in physical size.SOLUTION: A sealing body 30 is a resin molding, and seals a semiconductor element 40L, at least a part of a substrate 50, a part of a signal terminal 93L, a bonding wire 110, and a relay substrate 150L. The bonding wire 110 electrically connects a pad 40P of the semiconductor element 40L, and a land 152a of the relay substrate 150L. Out of a surface metal body 52 of the substrate 50, the semiconductor element 40L is arranged in relay wiring 55 as a wiring part, and the relay substrate 150L is arranged in an island 58L electrically separated from the wiring part.SELECTED DRAWING: Figure 125

Description

[Technical Field]

[0001] TECHNICAL FIELD The disclosure herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device. This semiconductor device includes an insulating substrate (wiring member), a semiconductor element having main electrodes on both sides, a control terminal (signal terminal), and a sealing resin (sealing body). The semiconductor element is disposed on the insulating substrate, and one of the main electrodes is electrically connected to a metal foil (metal body) on the insulating substrate. The control electrode (pad) of the semiconductor element is connected to the signal terminal via a metal wire (bonding wire). The sealing body seals a part of the insulating substrate, the semiconductor element, a part of the control terminal, and the metal wire. The contents of the prior art documents are incorporated by reference as explanations of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-60410 Summary of the Invention [Problem to be solved by the invention]

[0004] One semiconductor device disclosed in Patent Document 1 electrically connects a control electrode and a control terminal using a metal wire. This configuration requires a long metal wire, which may result in wire sweep during molding of the encapsulating resin. Another disclosed semiconductor device separates the metal foil on the semiconductor element side of the insulating substrate into a metal foil connected to a main electrode and a metal foil connected to a control terminal. The control terminal and the control electrode are then electrically connected via the metal wire and metal foil. When providing metal foil, or so-called lands, to which the metal wire and control terminal are connected as part of the conductor of the insulating substrate, the conductor is thick, resulting in a large land size. The need for multiple large lands increases the physical size of the semiconductor device. Further improvements in semiconductor devices are desired in the above and other aspects not mentioned.

[0005] One disclosed object is to provide a semiconductor device that can suppress wire sweep and prevent an increase in size. [Means for solving the problem]

[0006] The semiconductor device disclosed herein comprises: a wiring member (50) having an insulating substrate (51), a front metal body (52) disposed on the front surface of the insulating substrate, and a back metal body (53) disposed on the surface of the insulating substrate opposite to the front surface; a semiconductor element (40) disposed on a wiring member, the semiconductor element having a first main electrode (40D) provided on one surface and electrically connected to the front surface metal body, a second main electrode (40S) provided on a back surface opposite to the one surface in the plate thickness direction, and a plurality of signal pads (40P) provided on the back surface at positions different from the second main electrode; A plurality of signal terminals (93); an interconnection substrate (150) disposed on the wiring member, having a plurality of surface lands (152a) provided on a surface opposite to a surface facing the wiring member, and positioned midway along a current path between the semiconductor element and the signal terminal; a bonding wire (110) electrically connecting the pad and the corresponding surface land; a resin molded body and a sealing body (30) that seals the semiconductor element, at least a part of the wiring member, a part of the signal terminal, the relay board, and the bonding wires; The surface metal body has a wiring portion (54, 55) on which the semiconductor element is disposed and to which the first main electrode is electrically connected, and an island portion (58) on which the relay substrate is disposed and which is electrically isolated from the wiring portion, the relay board has a plurality of front surface lands, a back surface land (152e) provided on a surface facing the island portion and electrically connected to the island portion, and connection portions (152c, 152d, 152f) that electrically connect some of the plurality of front surface lands to the back surface lands; The island portion is fixed to a predetermined potential via the rear surface land, the connection portion, and a part of the front surface land.

[0007] According to the disclosed semiconductor device, the pads of the semiconductor element and the signal terminals are electrically connected via an intermediate substrate. Bonding wires electrically connect the pads to the surface lands of the intermediate substrate. This shortens the length of the bonding wires, thereby suppressing wire sweep during molding of the encapsulation body. Furthermore, the surface lands of the intermediate substrate are formed using so-called printed circuit board micro-wiring technology. Therefore, compared to a configuration in which multiple intermediate lands are provided as part of a surface metal body instead of an intermediate substrate, an increase in physical size can be suppressed. As a result, wire sweep and an increase in physical size can be suppressed.

[0008] Furthermore, the relay substrate is disposed in an island portion that is electrically isolated from the wiring portion, thereby improving insulation reliability.

[0009] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims and in this section are intended to exemplify correspondences with the following embodiments and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied; [Figure 2] FIG. 1 is a perspective view showing a semiconductor device. [Figure 3] FIG. 1 is a perspective view showing a semiconductor device. [Figure 4] FIG. 1 is a plan view showing a semiconductor device. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is an enlarged view of region IX shown in FIG. 8. [Figure 10] FIG. 1 is an exploded perspective view illustrating a semiconductor device. [Figure 11] FIG. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. [Figure 12] FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. [Figure 13] FIG. 2 is a plan view showing a circuit pattern on the substrate on the source electrode side. [Figure 14] FIG. 2 is a diagram showing the arrangement of a circuit pattern, a semiconductor element, and terminals on the drain electrode side. [Figure 15] 1A and 1B are diagrams showing the arrangement of a circuit pattern, a semiconductor element, and terminals on the source electrode side. [Figure 16] FIG. 10 is a plan view showing a current loop of a reference example. [Figure 17] FIG. 2 is a plan view showing a current loop. [Figure 18] FIG. 1 is a side view showing a current loop. [Figure 19] FIG. 10 is a diagram showing current density in a reference example. [Figure 20] FIG. 10 is a diagram showing current density for this embodiment. [Figure 21] FIG. [Figure 22] FIG. [Figure 23] FIG. 10 is a plan view showing a circuit pattern on a substrate on the drain electrode side in a modified example. [Figure 24] FIG. 10 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. [Figure 25] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 26] FIG. 10 is a diagram for explaining the effect of inductance Ls. [Figure 27] FIG. 10 is a diagram for explaining the effect of inductance Ls. [Figure 28] FIG. 2 is a plan view showing a circuit pattern on the substrate on the source electrode side. [Figure 29] FIG. [Figure 30] FIG. 4 is a cross-sectional view showing an arm connection portion. [Figure 31] FIG. 10 is a plan view showing a modified example of the substrate on the source electrode side. [Figure 32] FIG. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. [Figure 33] FIG. [Figure 34] FIG. 10 is a plan view showing a modified example of the substrate on the drain electrode side; [Figure 35] FIG. [Figure 36] FIG. 10 is a cross-sectional view showing a modified example of the arm connection portion. [Figure 37] FIG. 10 is a cross-sectional view showing a modified example of the arm connection portion. [Figure 38] FIG. 10 is a plan view showing a circuit pattern on a substrate on the source electrode side in a modified example. [Figure 39] FIG. 10 is a cross-sectional view showing warpage at high temperatures. [Figure 40] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 41] FIG. 1 is a cross-sectional view showing a semiconductor device at room temperature. [Figure 42] FIG. 1 is a cross-sectional view showing a semiconductor device at a high temperature. [Figure 43] FIG. 10 is a diagram showing the relationship between the ratio of thicknesses T1 and T2 and the amount of warpage. [Figure 44] FIG. 10 is a cross-sectional view showing a modified example. [Figure 45] FIG. 10 is a cross-sectional view showing a modified example. [Figure 46] FIG. 10 is an enlarged plan view of the periphery of a signal terminal in the semiconductor device according to the fourth embodiment. [Figure 47] FIG. 47 is a cross-sectional view taken along line XLVII-XLVII in FIG. 46. [Figure 48] FIG. 1 is a diagram illustrating wire bonding. [Figure 49] FIG. 10 is a cross-sectional view showing a modified example. [Figure 50] FIG. 10 is a cross-sectional view showing a modified example. [Figure 51] FIG. 10 is a cross-sectional view showing a modified example. [Figure 52] FIG. 10 is a cross-sectional view showing a modified example. [Figure 53] FIG. [Figure 54] FIG. [Figure 55] FIG. 54 is a cross-sectional view taken along the line LV-LV in FIG. 53. [Figure 56] FIG. 10 is a cross-sectional view showing a modified example. [Figure 57] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 58] FIG. 58 is a plan view seen from the LVIII direction shown in FIG. 57. [Figure 59] FIG. 58 is an enlarged view of the area LVIX shown in FIG. 57. [Figure 60] This is a diagram in which the bonding material is omitted from Figure 59. [Figure 61] FIG. [Figure 62] FIG. 62 is a plan view seen from the direction LXII shown in FIG. 61. [Figure 63] FIG. [Figure 64] FIG. 10 is a cross-sectional view showing a modified example. [Figure 65] FIG. 65 is an enlarged view of area LXV shown in FIG. 64. [Figure 66] FIG. 10 is a cross-sectional view showing a modified example. [Figure 67] FIG. 67 is an enlarged view of area LXVII shown in FIG. 66. [Figure 68] FIG. 10 is a cross-sectional view showing a modified example. [Figure 69] FIG. 10 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. [Figure 70] FIG. 1 is a diagram showing the relationship between the glass transition point and the linear expansion coefficient for a sealing body and an insulating base material. [Figure 71] FIG. 10 is a diagram showing warpage in a reference example. [Figure 72] FIG. 10 is a diagram showing warpage at high temperatures. [Figure 73] FIG. 13 is a cross-sectional view showing a semiconductor device according to a seventh embodiment. [Figure 74] FIG. 74 is an enlarged view of region LXXIV of FIG. 73. [Figure 75] 1A to 1C are diagrams illustrating a method for forming a roughened portion. [Figure 76] FIG. 10 is a cross-sectional view showing a modified example. [Figure 77] FIG. 10 is a cross-sectional view showing a modified example. [Figure 78] FIG. 10 is a cross-sectional view showing a modified example. [Figure 79] FIG. 13 is a cross-sectional view showing a semiconductor device according to an eighth embodiment. [Figure 80] FIG. 79 is an enlarged view of area LXXX in FIG. 79. [Figure 81] FIG. 10 is a diagram showing the relationship between the spacing, thickness, and inductance. [Figure 82] FIG. 10 is a diagram showing a simulation result when the distance is smaller than the thickness. [Figure 83] FIG. 10 is a diagram showing the simulation results when the spacing is greater than the thickness. [Figure 84] FIG. 13 is a cross-sectional view showing a semiconductor device according to a ninth embodiment. [Figure 85] FIG. [Figure 86] FIG. 85 is an enlarged view of area LXXXVI in FIG. 84. [Figure 87] FIG. 10 shows dimensions and angles. [Figure 88] FIG. [Figure 89] FIG. 22 is a cross-sectional view showing a semiconductor device according to a tenth embodiment. [Figure 90] FIG. 1 is a plan view showing a semiconductor element. [Figure 91] FIG. 89 is an enlarged view of region XCI in FIG. 89. [Figure 92] FIG. 3 is a cross-sectional view showing the arrangement of sintered members. [Figure 93] 10A to 10C are cross-sectional views showing a joining method. [Figure 94] 10 is a diagram showing the relationship between the distance between the inner circumferential surface of the protective film and the sintered member and the strain amplitude of the base electrode. FIG. [Figure 95] FIG. 2 is a cross-sectional view showing the arrangement of solder as a bonding material. [Figure 96] FIG. 22 is a cross-sectional view showing a semiconductor device according to an eleventh embodiment. [Figure 97] This is an enlarged view of area XCVII in Figure 96. [Figure 98] FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and an uneven oxide film. [Figure 99] This is an enlarged view of area XCIX in Figure 97. [Figure 100] FIG. 10 is a cross-sectional view showing a modified example. [Figure 101] FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and an uneven oxide film. [Figure 102] FIG. 10 is a cross-sectional view showing a modified example. [Figure 103] FIG. 2 is a plan view showing the arrangement of a semiconductor element, a sintered member, and an uneven oxide film. [Figure 104] FIG. 10 is a cross-sectional view showing a modified example. [Figure 105] FIG. 22 is a cross-sectional view showing a semiconductor device according to a twelfth embodiment. [Figure 106]FIG. 106 is an enlarged view of area CVI in FIG. 105. [Figure 107] FIG. 10 is a diagram showing the relationship between the Young's modulus and the yield stress of the base electrode, the sintered layer, and the brittle layer. [Figure 108] FIG. 10 is a cross-sectional view showing a modified example. [Figure 109] FIG. 10 is a cross-sectional view showing a modified example. [Figure 110] FIG. 10 is a cross-sectional view showing a modified example. [Figure 111] FIG. 23 is a diagram showing a circuit configuration of a power conversion device to which the semiconductor device according to the thirteenth embodiment is applied. [Figure 112] FIG. 1 is a perspective view showing a semiconductor device. [Figure 113] FIG. 1 is a plan view showing a semiconductor device. [Figure 114] FIG. 2 is a plan view showing a state in which a semiconductor element is mounted on a substrate on the drain electrode side. [Figure 115] FIG. 2 is a plan view showing a circuit pattern on the substrate on the drain electrode side. [Figure 116] FIG. 2 is a plan view showing a circuit pattern on the substrate on the source electrode side. [Figure 117] FIG. 114 is a cross-sectional view taken along line CXVII-CXVII in FIG. [Figure 118] FIG. 114 is a cross-sectional view taken along line CXVIII-CXVIII in FIG. [Figure 119] FIG. 114 is a cross-sectional view taken along line CXIX-CXIX in FIG. [Figure 120] FIG. 114 is a cross-sectional view taken along line CXX-CXX in FIG. 113. [Figure 121] FIG. 121 is an enlarged view of area CXXI ​​in FIG. 120. [Figure 122] FIG. 23 is a plan view showing the substrate on the drain electrode side and connected elements in the semiconductor device according to the fourteenth embodiment. [Figure 123] FIG. 2 is a plan view showing a connection structure between a semiconductor element and an intermediate substrate. [Figure 124] FIG. 124 is a cross-sectional view taken along line CXXIV-CXXIV in FIG. 123. [Figure 125]123 is a cross-sectional view of the semiconductor device corresponding to the line CXXV-CXXV in FIG. 122. [Figure 126] FIG. [Figure 127] FIG. 10 is a cross-sectional view showing a modified example. [Figure 128] FIG. 10 is a cross-sectional view showing a modified example. [Figure 129] FIG. 10 is a cross-sectional view showing a modified example. [Figure 130] FIG. [Figure 131] FIG. [Figure 132] FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0012] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile object using a rotating electric machine as a drive source. The mobile object may be, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), or a plug-in hybrid electric vehicle (PHEV), an aircraft such as an electric vertical take-off and landing aircraft or a drone, a ship, a construction machine, or an agricultural machine. An example of application to a vehicle will be described below.

[0013] (First embodiment) First, the schematic configuration of a vehicle drive system 1 will be described with reference to FIG.

[0014] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0015] The DC power supply 2 is a DC voltage source made up of a rechargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, i.e., an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 converts power between the DC power supply 2 and the motor generator 3.

[0016] <Power conversion device> Next, the circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0017] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0019] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a portion of each of the P line 7, the N line 8, and the output line 10 is configured with a conductive member such as a bus bar.

[0020] In this embodiment, an n-channel MOSFET 11 is used as the switching element constituting each arm. The number of switching elements constituting each arm is not particularly limited. It may be one or more. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0021] As an example, in this embodiment, each arm has two MOSFETs 11. The two MOSFETs 11 constituting one arm are connected in parallel. In the upper arm 9H, the drains of the two parallel-connected MOSFETs 11 are connected to a P line 7. In the lower arm 9L, the sources of the two parallel-connected MOSFETs 11 are connected to an N line 8. The sources of the two parallel-connected MOSFETs 11 in the upper arm 9H are connected to the drains of the two parallel-connected MOSFETs 11 in the lower arm 9L. The two parallel-connected MOSFETs 11 are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0022] A freewheeling diode 12 is connected in anti-parallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20. Details of the semiconductor device 20 will be described later.

[0023] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured with, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage increase and decrease. The power conversion device 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0024] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0025] The power conversion device 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0026] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0027] <Semiconductor device> Next, the semiconductor device will be described with reference to FIGS. 2 to 13. FIG. 2 is a perspective view of the semiconductor device 20. FIG. 3 is a perspective view of the semiconductor device 20 similar to FIG. 2. FIG. 3 is a see-through view showing the internal structure. FIG. 4 is a plan view of the semiconductor device 20. FIG. 4 is a see-through view showing the internal structure. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9 is an enlarged view of region IX indicated by a dashed line in FIG. 8.

[0028] Fig. 10 is an exploded perspective view for explaining the semiconductor device 20. For convenience, a lead frame 94 is shown in Fig. 10. Fig. 11 is a plan view showing a state in which a semiconductor element 40 is mounted on a substrate 50. Fig. 12 is a plan view showing the circuit pattern of the surface metal body 52 on the substrate 50. Fig. 13 is a plan view showing the circuit pattern of the surface metal body 62 on the substrate 60.

[0029] In the following, the thickness direction of the semiconductor element (semiconductor substrate) is referred to as the Z direction. The Y direction is perpendicular to the Z direction and is the direction in which the semiconductor elements constituting the upper arm 9H and the semiconductor elements constituting the lower arm 9L are arranged. The X direction is the direction perpendicular to both the Z direction and the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction is sometimes simply referred to as the planar view. Furthermore, the term "arrangement" is not limited to the mounting surface, and may be referred to as an arrangement when there is an overlapping positional relationship in a planar view.

[0030] 2 to 13, the semiconductor device 20 constitutes one of the upper and lower arm circuits 9, i.e., one phase of the upper and lower arm circuit 9. The semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection portion 80, and an external connection terminal 90.

[0031] The encapsulant 30 encapsulates some of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of a resin is an epoxy-based resin. The encapsulant 30 is molded using, for example, a transfer molding method using a resin. Such a encapsulant 30 may be referred to as an encapsulating resin body, a molded resin, or a resin molded body. The encapsulant 30 may be formed using, for example, a gel. The gel is filled (placed) in the opposing regions of the pair of substrates 50, 60, for example.

[0032] As shown in FIGS. 2 to 4, the sealing body 30 has a generally rectangular planar shape. The sealing body 30 has one surface 30a as its outer surface and a back surface 30b opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. The sealing body 30 also has side surfaces that connect the one surface 30a and the back surface 30b. The side surfaces include two side surfaces 30c and 30d from which the external connection terminals 90 protrude. The side surface 30d is opposite to the side surface 30c in the X direction.

[0033] The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon. Wide bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

[0034] The semiconductor element 40 of this embodiment has the above-described n-channel MOSFET 11 formed on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure such that a main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes of a switching element on both sides in its thickness direction, i.e., in the Z direction. Specifically, the main electrodes include a drain electrode 40D on one side and a source electrode 40S on the back side, which is the surface opposite to the first side in the Z direction.

[0035] When the diode 12 is a parasitic diode, the source electrode 40S also serves as an anode electrode, and the drain electrode 40D also serves as a cathode electrode. The diode 12 may be configured on a chip separate from the MOSFET 11. The drain electrode 40D is a main electrode (first main electrode) on the high potential side, and the source electrode 40S is a main electrode (second main electrode) on the low potential side. Hereinafter, the drain electrode 40D and the source electrode 40S may be referred to as main electrodes 40D and 40S.

[0036] The semiconductor element 40 has a generally rectangular shape in plan view. As shown in FIG. 11, the semiconductor element 40 has a pad 40P formed on the back surface at a position different from that of the source electrode 40S. The source electrode 40S and the pad 40P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 40D is formed on almost the entire surface. The source electrode 40S is formed on a portion of the back surface of the semiconductor element 40. In a plan view, the drain electrode 40D has a larger area than the source electrode 40S.

[0037] The pad 40P is an electrode for signals. The pad 40P is electrically isolated from the source electrode 40S. The pad 40P is formed at the end opposite to the formation region of the source electrode 40S in the Y direction. The pad 40P includes a pad for a gate electrode.

[0038] The semiconductor device 20 includes a plurality of semiconductor elements 40 having the above-described configuration. The semiconductor elements 40 share a common configuration. The plurality of semiconductor elements 40 include a semiconductor element 40H that constitutes an upper arm 9H and a semiconductor element 40L that constitutes a lower arm 9L. The semiconductor element 40H is sometimes referred to as an upper arm element, and the semiconductor element 40L is sometimes referred to as a lower arm element. Each of the semiconductor elements 40H and 40L is an arm element that constitutes one arm. The semiconductor device 20 of this embodiment includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are aligned in the X direction. Similarly, the two semiconductor elements 40L are aligned in the X direction. The semiconductor elements 40H and 40L are aligned in the Y direction. The Y direction is a first direction perpendicular to the Z direction, which is the thickness direction of the semiconductor elements 40. The X direction is a second direction perpendicular to the Z direction and the first direction (Y direction). The semiconductor device 20 has two rows of semiconductor elements 40H and semiconductor elements 40L arranged along the Y direction.

[0039] The semiconductor elements 40 are arranged at approximately the same positions as each other in the Z direction. The drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

[0040] The substrates 50 and 60 are arranged in the Z direction so as to sandwich the plurality of semiconductor elements 40. The substrates 50 and 60 are arranged so as to face at least a portion of each other in the Z direction. The substrates 50 and 60 contain all of the plurality of semiconductor elements 40 (40H, 40L) in a plan view.

[0041] The substrate 50 is disposed on the drain electrode 40D side of the semiconductor element 40. The substrate 60 is disposed on the source electrode 40S side of the semiconductor element 40. The substrate 50 is electrically connected to the drain electrode 40D as described below, and provides a wiring function. Similarly, the substrate 60 is electrically connected to the source electrode 40S, and provides a wiring function. For this reason, the substrates 50 and 60 are sometimes referred to as wiring substrates. The substrate 50 is sometimes referred to as a drain substrate, and the substrate 60 is sometimes referred to as a source substrate. The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. For this reason, the substrates 50 and 60 are sometimes referred to as heat dissipation members. Of the pair of substrates 50 and 60 that sandwich the semiconductor element 40 in the Z direction, the substrate 50 is a first substrate, and the substrate 60 is a second substrate.

[0042] The substrate 50 has a facing surface 50a facing the semiconductor element 40 and a back surface 50b opposite the facing surface 50a. The substrate 50 includes an insulating base material 51, a front surface metal body 52, and a back surface metal body 53. The substrate 50 is a substrate in which the insulating base material 51 and the metal bodies 52 and 53 are laminated. The substrate 60 has a facing surface 60a facing the semiconductor element 40 and a back surface 60b opposite the facing surface 60a. The substrate 60 includes an insulating base material 61, a front surface metal body 62, and a back surface metal body 63. The substrate 60 is a substrate in which the insulating base material 61 and the metal bodies 62 and 63 are laminated. In the substrate 50, which is a first substrate, the insulating base material 51 is a first insulating base material, the front surface metal body 52 is a first front surface metal body, and the back surface metal body 53 is a first back surface metal body. In the substrate 60, which is the second substrate, the insulating base material 61 is a second insulating base material, the front surface metal body 62 is a second front surface metal body, and the back surface metal body 63 is a second back surface metal body. Hereinafter, the front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, 63.

[0043] The insulating substrate 51 electrically separates the front metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 from the back metal body 63. The insulating substrates 51, 61 are sometimes referred to as insulating layers. The insulating substrates 51, 61 are made of resin or inorganic ceramic material. Examples of resin that can be used include epoxy resin and polyimide resin. Examples of ceramic that can be used include Al2O3 (alumina) and Si3N4 (silicon nitride). When the insulating substrates 51, 61 are made of resin, the substrates 50, 60 are sometimes referred to as metal-resin substrates. When the insulating substrates 51, 61 are made of ceramic, the substrates 50, 60 are sometimes referred to as metal-ceramic substrates.

[0044] In the case of insulating substrates 51 and 61 made of a resin material, inorganic fillers (inorganic filling materials) may be contained in the resin to improve heat dissipation, insulation, and the like. The linear expansion coefficient may be adjusted by adding fillers. Examples of fillers that can be used include Al2O3, SiO2 (silicon dioxide), AlN (aluminum nitride), and BN (boron nitride). Insulating substrates 51 and 61 may contain only one type of filler or multiple types of fillers.

[0045] Considering heat dissipation and insulation, in the case of a resin-based insulating substrate, the thickness of each of the insulating substrates 51 and 61, i.e., the length in the Z direction, is preferably approximately 50 μm to 300 μm. In the case of a ceramic-based insulating substrate, the thickness of each of the insulating substrates 51 and 61 is preferably approximately 200 μm to 500 μm. In the Z direction, the front surfaces of the insulating substrates 51 and 61 are the inner surfaces, i.e., the surfaces facing the semiconductor element 40, and the back surfaces opposite the front surfaces in the Z direction are the outer surfaces. The insulating substrates 51 and 61 may be made of the same material or may be made of different materials. In this embodiment, the resin-based insulating substrates 51 and 61 are used, and the material composition is the same. The linear expansion coefficient of the insulating substrates 51 and 61 is adjusted to be approximately the same as that of the sealing body 30 by adding a filler to the resin. By adding a filler to the resin, the linear expansion coefficient of the insulating substrates 51 and 61 and the sealing body 30 is close to that of the metal (Cu) constituting the metal bodies 52, 53, 62, and 63.

[0046] The metal bodies 52, 53, 62, and 63 are provided as, for example, metal plates or metal foils. The metal bodies 52, 53, 62, and 63 are formed from metals with good electrical and thermal conductivity, such as Cu or Al. The thickness of each of the metal bodies 52, 53, 62, and 63 is, for example, approximately 0.1 mm to 3 mm. The front surface metal body 52 is disposed on the front surface of the insulating substrate 51 in the Z direction. The back surface metal body 53 is disposed on the back surface of the insulating substrate 51. Similarly, the front surface metal body 62 is disposed on the front surface of the insulating substrate 61 in the Z direction. The back surface metal body 63 is disposed on the back surface of the insulating substrate 61. The insulating substrates 51 and 61 are surfaces facing the semiconductor element 40 in the Z direction. As shown in FIGS. 5 to 9 and other figures, in this embodiment, the front surface metal body 52 is thicker than the back surface metal body 53. The front surface metal body 62 is thicker than the back surface metal body 63. The front surface metal body 52 on the drain electrode 40D side is thicker than the front surface metal body 62 on the source electrode 40S side. Alternatively, the back surface metal bodies 53, 63 may be made thicker than the corresponding front surface metal bodies 52, 62. The front surface metal body 52 and the back surface metal body 53 may be made approximately equal in thickness, or the front surface metal body 62 and the back surface metal body 63 may be made approximately equal in thickness.

[0047] The surface metal bodies 52, 62 are patterned. The surface metal bodies 52, 62 provide wiring, i.e., circuits. For this reason, the surface metal bodies 52, 62 are sometimes referred to as circuit patterns, wiring layers, or circuit conductors. The surface metal bodies 52, 62 may have a plating film of Ni, Au, or the like on the metal surface. Hereinafter, the pattern of the surface metal bodies 52, 62 may be referred to as a circuit pattern. The surface metal body 52 and the area on the surface of the insulating base material 51 where the surface metal body 52 is not disposed form the opposing surface 50a of the substrate 50. Similarly, the surface metal body 62 and the area on the surface of the insulating base material 61 where the surface metal body 62 is not disposed form the opposing surface 60a of the substrate 60.

[0048] For example, the front surface metal bodies 52, 62 may be prepared by patterning them into a predetermined shape by pressing or etching, and then attached to a two-layer laminate of an insulating base material 51, 61 and a back surface metal body 53, 63 to form the substrates 50, 60. After forming a three-layer laminate of the front surface metal bodies 52, 62, insulating base material 51, 61, and back surface metal bodies 53, 63, the front surface metal bodies 52, 62 may be patterned by cutting or etching.

[0049] 11 and other figures, the surface metal body 52 has a P wiring 54 and a relay wiring 55. The P wiring 54 and the relay wiring 55 are electrically separated by a predetermined gap. The gap is filled with the sealing body 30.

[0050] The P wiring 54 is connected to a P terminal 91P (described later) and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 is sometimes referred to as a positive wiring or a high-potential power supply wiring. The relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection part 80, and the output terminal 92. The relay wiring 55 electrically connects the arm connection part 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode of the semiconductor element 40L to the output terminal 92. In the front surface metal body 52 (first front surface metal body), the P wiring 54 is the first power supply wiring, and the relay wiring 55 is the first relay wiring.

[0051] The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. In the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the output terminal 92 side. In other words, the P wiring 54 is arranged in a position close to the side surface 30c of the sealing body 30, and the relay wiring 55 is arranged in a position close to the side surface 30d.

[0052] The P wiring 54 has a notch 540. The notch 540 opens on one of the four sides of a generally rectangular shape in plan view whose longitudinal direction is the X direction. The notch 540 is provided on the side facing the side surface 30c, at approximately the center in the X direction. The P wiring 54 has a base 541 and a pair of extensions 542. The base 541 and the pair of extensions 542 define the notch 540. The P wiring 54 has a generally U-shape (concave shape) in plan view.

[0053] The base 541 is a portion closer to the relay wiring 55 than the cutout 540 and the extension 542, and has a generally rectangular shape in plan view. The base 541 overlaps the semiconductor element 40H in plan view. That is, the semiconductor element 40H is disposed on the base 541. The drain electrode 40D of the semiconductor element 40H is connected to the base 541.

[0054] The two extension portions 542 extend from the base 541 in the same direction, specifically the Y direction, toward the side surface 30c of the sealing body 30. One of the extension portions 542 is connected to the vicinity of one end of the base 541 in the X direction, and the other is connected to the vicinity of the other end of the base 541. The ends of the U-shape of the P wiring 54, that is, the ends of the two extension portions 542 opposite the base 541, are at approximately the same position in the Y direction. The pair of extension portions 542 sandwich the notch 540 in the X direction. The length of the base 541 in the Y direction is longer than the depth of the notch 540 and the extension portions 542.

[0055] The relay wiring 55 also has a notch 550. The notch 550 is open on one of the four sides of the approximately rectangular planar shape. The notch 550 is provided on the side opposite the side surface 30d, approximately in the center in the X direction. That is, the front surface metal body 52 has a notch 540 on one of its ends in the Y direction and a notch 550 on the other end.

[0056] The relay wiring 55 has a base 551 and a pair of extension portions 552. The base 551 and the pair of extension portions 552 define a notch 550. The relay wiring 55 has a generally U-shape (concave shape) in plan view. The base 551 is a portion closer to the P wiring 54 than the notch 550 and the extension portions 552, and has a generally rectangular shape in plan view. The base 551 overlaps the semiconductor element 40L in plan view. That is, the semiconductor element 40L is disposed on the base 551. The drain electrode 40D of the semiconductor element 40L is connected to the base 551.

[0057] The two extension portions 552 extend from the base 551 in the same direction, specifically the Y direction, toward the side surface 30d of the sealing body 30. One of the extension portions 552 is connected to the vicinity of one end of the base 551 in the X direction, and the other is connected to the vicinity of the other end of the base 551. The ends of the U-shape of the relay wiring 55, that is, the ends of the two extension portions 552 opposite the base 551, are at approximately the same position in the Y direction. The pair of extension portions 552 sandwich the notch 550 in the X direction. The length of the base 551 in the Y direction is longer than the depth of the notch 550 and the extension portions 552.

[0058] 10 and 13, the surface metal body 62 has an N wiring 64 and a relay wiring 65. The N wiring 64 and the relay wiring 65 are electrically separated by a predetermined gap. The gap is filled with the sealing body 30.

[0059] The N wiring 64 is connected to an N terminal 91N, which will be described later, and the source electrode 40S of the semiconductor element 40L. The N wiring 64 electrically connects the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The N wiring 64 is sometimes referred to as an N wiring. The relay wiring 65 is connected to the source electrode 40S of the semiconductor element 40H and the arm connecting portion 80. The relay wiring 65 electrically connects the source electrode 40S of the semiconductor element 40H and the arm connecting portion 80. In the front surface metal body 62 (second front surface metal body), the N wiring 64 is a second power supply wiring, and the relay wiring 65 is a second relay wiring.

[0060] The N wiring 64 has a base 640 and a pair of extension portions 641. The N wiring 64 has a generally U-shape in plan view. The base 640 is arranged alongside the relay wiring 65 in the Y direction. The base 640 is arranged on the side surface 30d in the Y direction. The base 640 has a generally rectangular shape in plan view with the X direction as its longitudinal direction. As shown in FIG. 15 , the base 640 overlaps the semiconductor element 40L in plan view. That is, the semiconductor element 40L is arranged on the base 640. The source electrode 40S of the semiconductor element 40L is connected to the base 640.

[0061] The two extension portions 641 extend from the base 640 in the same direction, specifically the Y direction, toward the side surface 30c of the sealing body 30. One of the extension portions 641 is connected to the vicinity of one end of the base 640 in the X direction, and the other is connected to the vicinity of the other end of the base 640. The ends of the U-shape of the N wiring 64, that is, the ends of the two extension portions 641 opposite the base 640, are at approximately the same position in the Y direction.

[0062] The pair of extension portions 641 form both ends of the surface metal body 62 in the X direction. The pair of extension portions 641 are arranged near the end of the substrate 60. In a plan view, a portion of each of the pair of extension portions 641 overlaps the P wiring 54. The length of the extension portion 641 in the Y direction is longer than that of the base portion 640. The N wiring 64 also has a notch 642. The notch 642 opens on one of the four sides of the approximately rectangular shape in plan view whose longitudinal direction is the Y direction. The notch 642 is provided on the side opposite the side surface 30c, approximately in the center in the X direction. The base portion 640 and the pair of extension portions 641 define the notch 642.

[0063] As described above, the relay wiring 65 is arranged alongside the N wiring 64, specifically the base 640, in the Y direction. In the Y direction, the relay wiring 65 is arranged close to the side surface 30c of the sealing body 30, and the base 640 is arranged close to the side surface 30d. The relay wiring 65 is arranged between the pair of extension portions 641 in the X direction. The relay wiring 65 is sandwiched between the pair of extension portions 641. The relay wiring 65 is arranged within the cutout 642. The relay wiring 65 is arranged with a predetermined interval (gap) between it and the N wiring 64. In a plan view, a portion of the relay wiring 65 overlaps with the P wiring 54, and another portion overlaps with the relay wiring 55.

[0064] 15, the relay wiring 65 overlaps the semiconductor element 40H in a plan view. That is, the semiconductor element 40H is disposed on the relay wiring 65. The source electrode 40S of the semiconductor element 40H is connected to the relay wiring 65. A more detailed example of the circuit pattern of the front surface metal body 62 will be described later.

[0065] The back metal bodies 53, 63 are electrically isolated from the circuit including the semiconductor element 40 by the insulating substrates 51, 61. The back metal bodies 53, 63 are sometimes referred to as metal base substrates. Heat generated by the semiconductor element 40 is transferred to the back metal bodies 53, 63 via the front metal bodies 52, 62 and the insulating substrates 51, 61. The back metal bodies 53, 63 provide a heat dissipation function. In this embodiment, the back metal bodies 53, 63 have a generally rectangular planar shape, and their outer contours nearly match those of the front metal bodies 52, 62. The back metal bodies 53, 63 are so-called solid conductors disposed over almost the entire back surface of the insulating substrates 51, 61. As described above, the linear expansion coefficient of the insulating substrates 51, 61 is adjusted by adding a filler, thereby suppressing warping even when the patterns on the front and back surfaces are different. Of course, the rear surface metal bodies 53, 63 may be patterned so as to coincide with the front surface metal bodies 52, 62 in a plan view.

[0066] The back surface metal bodies 53, 63 in this embodiment are disposed over almost the entire area of ​​the back surface of the corresponding insulating base material 51, 61. To further enhance the heat dissipation effect, at least one of the back surface metal bodies 53, 63 may be exposed from the sealing body 30. In this embodiment, the back surface metal body 53 is exposed from one surface 30a of the sealing body 30, and the back surface metal body 63 is exposed from the back surface 30b. The exposed surface of the back surface metal body 53 is approximately flush with the one surface 30a. The exposed surface of the back surface metal body 63 is approximately flush with the back surface 30b. The back surface metal bodies 53, 63 form the back surfaces 50b, 60b of the substrates 50, 60.

[0067] The conductive spacer 70 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the substrate 60. For example, the conductive spacer 70 ensures a height sufficient for electrically connecting the corresponding signal terminal 93 to the pad 40P of the semiconductor element 40. The conductive spacer 70 is located midway along the electrical and thermal conduction path between the source electrode 40S of the semiconductor element 40 and the substrate 60, providing wiring and heat dissipation functions. The conductive spacer 70 contains a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a generally rectangular columnar body having approximately the same size as the source electrode 40S in a planar view.

[0068] The conductive spacers 70 may also be referred to as terminals, terminal blocks, or metal blocks. The semiconductor device 20 includes the same number of conductive spacers 70 as the number of semiconductor elements 40. Specifically, the semiconductor device 20 includes four conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40.

[0069] The arm connection portion 80 electrically connects the relay wirings 55 and 65. That is, the arm connection portion 80 electrically connects the upper arm 9H and the lower arm 9L. The arm connection portion 80 is provided between the semiconductor elements 40H and 40L in the Y direction. The arm connection portion 80 is provided in the overlapping region of the relay wirings 55 and 65 in a plan view. The arm connection portion 80 of this embodiment is configured with a joint portion 81 and a bonding material 103, which will be described later.

[0070] The joint portion 81 is a metal columnar body provided separately from the surface metal bodies 52, 62. Such a joint portion 81 is sometimes called a joint terminal. In the Z direction, a bonding material 103 is interposed between one end of the joint portion 81 and the relay wiring 55, and a bonding material 103 is interposed between the other end and the relay wiring 65.

[0071] Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52, 62. In other words, the joint portion 81 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. The arm connection portion 80 may not be provided with the joint portion 81. In other words, the arm connection portion 80 may be provided with only the bonding material 103.

[0072] The external connection terminals 90 are terminals for electrically connecting the semiconductor device 20 to external devices. The external connection terminals 90 are formed using a metal material with good conductivity, such as copper. The external connection terminals 90 are, for example, plate material. The external connection terminals 90 are sometimes referred to as leads. The external connection terminals 90 include a power supply terminal 91, an output terminal 92, and a signal terminal 93. The power supply terminal 91 includes a P terminal 91P and an N terminal 91N. The P terminal 91P, the N terminal 91N, and the output terminal 92 are main terminals electrically connected to main electrodes of the semiconductor element 40. The signal terminal 93 includes a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

[0073] The power supply terminal 91 is an external connection terminal 90 electrically connected to the above-described power supply lines 7 and 8. The P terminal 91P is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 91P may also be referred to as a positive terminal or a high-potential power supply terminal. The P terminal 91P is connected to the P wiring 54 of the surface metal body 52. ​​In other words, the P terminal 91P is connected to the drain electrode 40D of the semiconductor element 40H that constitutes the upper arm 9H.

[0074] The P terminal 91P is connected to the P wiring 54 near one end in the Y direction. The P terminal 91P extends in the Y direction from the connection (joint) with the P wiring 54 and protrudes from the side surface 30c near the center in the Z direction to the outside of the sealing body 30. The semiconductor device 20 of this embodiment includes two P terminals 91P. As shown in FIG. 11 , one of the P terminals 91P is connected to one of the pair of extension portions 542, and the other is connected to the other of the pair of extension portions 542. The P terminal 91P is arranged in a position close to the notch 540, i.e., closer to the inside, in each of the extension portions 542 so as to be adjacent to the N terminal 91N in plan view. The two P terminals 91P are arranged side by side in the X direction. The two P terminals 91P are arranged at approximately the same position in the Z direction.

[0075] The N terminal 91N is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 91N may also be referred to as a negative terminal or a low-potential power supply terminal. The N terminal 91N is connected to the N wiring 64 of the surface metal body 62. In other words, the N terminal 91N is connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L.

[0076] The N terminal 91N is connected to the N wiring 64 near one end in the Y direction. The N terminal 91N extends in the Y direction from the joint with the N wiring 64 and protrudes from the sealing body 30 near the center in the Z direction on the side surface 30c. The semiconductor device 20 is equipped with two N terminals 91N. As shown in FIG. 15 and other figures, one of the N terminals 91N is connected to one of a pair of extension portions 641, and the other is connected to the other of the pair of extension portions 641. The two N terminals 91N are arranged side by side in the Y direction. The two N terminals 91N are arranged at approximately the same position in the Z direction.

[0077] The two N terminals 91N are arranged outside the two P terminals 91P in the X direction. In a plan view, one of the N terminals 91N is arranged near one of the P terminals 91P, and the other N terminal 91N is arranged near the other P terminal 91P. The N terminal 91N and P terminal 91P that are adjacent in the X direction have their side surfaces facing each other at parts that include parts that protrude from the sealing body 30.

[0078] The output terminal 92 is electrically connected to the winding 3a (stator coil) of the corresponding phase of the motor generator 3. The output terminal 92 may also be referred to as an O terminal, an AC terminal, or the like. As shown in FIGS. 3 and 7, the output terminal 92 is connected to the relay wiring 55 of the surface metal body 52 on the substrate 50. In other words, the output terminal 92 is connected to the connection point between the upper arm 9H and the lower arm 9L.

[0079] The output terminal 92 is connected to the relay wiring 55 near one end in the Y direction. The output terminal 92 extends in the Y direction from the joint with the relay wiring 55 and protrudes outside the sealing body 30 from near the center in the Z direction on the side surface 30d. The semiconductor device 20 has two output terminals 92. One of the output terminals 92 is connected to one of the pair of extension portions 552, and the other is connected to the other of the pair of extension portions 552. The two output terminals 92 are arranged side by side in the X direction. The two output terminals 92 are arranged at approximately the same position in the Z direction.

[0080] The signal terminal 93 is electrically connected to a drive circuit (driver) (not shown). The signal terminal 93H is electrically connected to the pad 40P of the semiconductor element 40H via a connecting member such as a bonding wire 110. The number of signal terminals 93H is not particularly limited. The signal terminals 93H may include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40H. The semiconductor device 20 of this embodiment includes two signal terminals 93H. One of the signal terminals 93H is a terminal for a gate electrode. The gate electrode pads 40P of the two semiconductor elements 40H are electrically connected to the signal terminal 93H for the gate electrode. The signal terminal 93H is arranged at a position overlapping the notch 540 of the P wiring 54 in a plan view. The joint portion of the signal terminal 93H with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. ​​The two signal terminals 93H are arranged side by side in the X direction.

[0081] The signal terminal 93H extends in the Y direction from the joint with the bonding wire 110 and protrudes from the side surface 30c near the center in the Z direction to the outside of the sealing body 30. At least a part of the protruding portion of the signal terminal 93H extends in the same direction as the power terminal 91. The signal terminal 93H is arranged between the two P terminals 91P in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30c are arranged in the following order in the X direction: the N terminal 91N, the P terminal 91P, the two signal terminals 93H, the P terminal 91P, and the N terminal 91N.

[0082] The signal terminal 93L is electrically connected to the pad 40P of the semiconductor element 40L via a connecting member such as a bonding wire 110. The number of signal terminals 93L is not particularly limited. The signal terminals 93L may include at least a terminal for applying a drive voltage to the gate electrode of the semiconductor element 40L. The semiconductor device 20 of this embodiment includes four signal terminals 93L. One of the signal terminals 93L is a terminal for a gate electrode. The gate electrode pads 40P of two semiconductor elements 40L are electrically connected to the signal terminal 93L for the gate electrode. The signal terminal 93L is arranged at a position overlapping the notch 550 of the relay wiring 55 in a plan view. The joint portion of the signal terminal 93L with the bonding wire 110 faces the insulating substrate 51, not the surface metal body 52. ​​The four signal terminals 93L are arranged horizontally in the X direction.

[0083] The signal terminal 93L extends in the Y direction from the joint with the bonding wire 110 and protrudes from near the center of the side surface 30d in the Z direction to the outside of the sealing body 30. At least a part of the protruding portion of the signal terminal 93L extends in the same direction as the output terminal 92. The signal terminal 93L is disposed between the two output terminals 92 in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30d are disposed in the following order in the X direction: the output terminal 92, the four signal terminals 93L, and the output terminal 92.

[0084] The drain electrode 40D of the semiconductor element 40 is bonded to the surface metal body 52 via a bonding material 100. The source electrode 40S of the semiconductor element 40 is bonded to the conductive spacer 70 via a bonding material 101. The conductive spacer 70 is bonded to the surface metal body 62 via a bonding material 102. The joint portion 81 is bonded to the metal bodies 52, 62 via a bonding material 103. Of the external connection terminals 90, the P terminal 91P, the N terminal 91N, and the output terminal 92, which are main terminals, are bonded to the corresponding surface metal bodies 52, 62 via a bonding material 104.

[0085] The bonding materials 100-104 are conductive bonding materials. For example, solder can be used as the bonding materials 100-104. One example of solder is a multi-element lead-free solder containing Cu, Ni, and the like in addition to Sn. A sintered bonding material such as sintered silver may be used instead of solder. The P terminal 91P, the N terminal 91N, and the output terminal 92 may be directly bonded to the corresponding surface metal bodies 52, 62 without using the bonding material 104. The P terminal 91P, the N terminal 91N, and the output terminal 92 may be directly bonded to the surface metal bodies 52, 62 by, for example, ultrasonic welding, friction stir welding, or laser welding. When the joint portion 81 is provided separately from the substrates 50, 60, the joint portion 81 may be directly bonded to the surface metal bodies 52, 62.

[0086] As described above, in the semiconductor device 20, the multiple semiconductor elements 40 that constitute the upper and lower arm circuits 9 for one phase are sealed by the sealing body 30. The sealing body 30 integrally seals the multiple semiconductor elements 40, part of the substrate 50, part of the substrate 60, the multiple conductive spacers 70, the arm connection portion 80, and part of the external connection terminals 90. The sealing body 30 seals the insulating base materials 51, 61 and the surface metal bodies 52, 62 of the substrates 50, 60.

[0087] The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the substrate 50 is substantially flush with one surface 30a of the sealing body 30. The back surface 60b of the substrate 60 is substantially flush with the back surface 30b of the sealing body 30. Because the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

[0088] <Manufacturing method> Next, an example of a method for manufacturing the semiconductor device 20 will be described with reference to Fig. 10. In Fig. 10, the substrate 50 and the substrate 60 are shown facing each other to make the subsequent assembly easier to understand.

[0089] First, the semiconductor element 40, substrates 50 and 60, conductive spacer 70, joint portion 81, and lead frame 94 are prepared. As shown in FIG. 10, the lead frame 94 includes external connection terminals 90. The lead frame 94 is formed by subjecting a metal plate to processing such as pressing. The external connection terminals 90 are supported by an outer peripheral frame 94b via tie bars 94a.

[0090] Next, the semiconductor element 40, the joint portion 81, and the external connection terminal 90 are joined (connected) to the substrate 50. In addition, the conductive spacer 70 is joined to the semiconductor element 40.

[0091] At this time, the lead frame 94 and the semiconductor element 40 are placed on the substrate 50. In addition, a conductive spacer 70 is placed on the source electrode 40S of the semiconductor element 40. The lead frame 94 is placed so that a portion of each of the external connection terminals 90 overlaps the substrate 50 in a plan view. Specifically, the P terminal 91P and the N terminal 91N are placed so that they overlap the P wiring 54 of the surface metal body 52, and the output terminal 92 overlaps the relay wiring 55. In addition, the signal terminal 93H is placed so that it overlaps the insulating base material 51 exposed from the cutout 540, and the signal terminal 93L is placed so that it overlaps the insulating base material 51 exposed from the cutout 550.

[0092] Then, the drain electrode 40D of the semiconductor element 40 is bonded to the surface metal body 52 using a bonding material 100. The source electrode 40S is bonded to the conductive spacer 70 using a bonding material 101. The joint portion 81 is bonded to the surface metal body 52 using a bonding material 103. The P terminal 91P and the output terminal 92 are bonded to the surface metal body 52 using a bonding material 104. For example, in the case of solder, the bonding can be performed all at once by reflow. Figure 10 shows this bonded state.

[0093] Next, the pads 40P of the semiconductor element 40H and the signal terminals 93H are electrically connected by bonding wires 110. Similarly, the pads 40P of the semiconductor element 40L and the signal terminals 93L are electrically connected by bonding wires 110.

[0094] Next, the substrate 60 is bonded (connected). The source electrode 40S of the semiconductor element 40 and the surface metal body 62 are bonded via a bonding material 102. The joint portion 81 and the surface metal body 62 are bonded via a bonding material 103. The N terminal 91N and the surface metal body 62 are bonded via a bonding material 104. For example, in the case of solder, the bonding can be performed all at once by reflow.

[0095] Next, the sealing body 30 is molded by a transfer molding method. Although not shown in the drawings, in this embodiment, the sealing body 30 is molded so as to completely cover the substrates 50 and 60, and is then cut after molding. The sealing body 30 is cut along with a portion of the back surface metal bodies 53 and 63 of the substrates 50 and 60. This exposes the back surfaces 50b and 60b. The back surface 50b is approximately flush with one surface 30a of the sealing body 30, and the back surface 60b is approximately flush with the back surface 30b. Note that the sealing body 30 may be molded with the back surfaces 50b and 60b pressed against the cavity wall of a molding die and in close contact. In this case, the back surfaces 50b and 60b are exposed from the sealing body 30 when the sealing body 30 is molded. This eliminates the need for cutting after molding.

[0096] Next, unnecessary portions such as the tie bars 94a and the outer peripheral frame 94b are removed from the lead frame 94. In this manner, the semiconductor device 20 can be obtained.

[0097] <Location> Next, the positional relationship between the semiconductor element 40, the circuit patterns of the surface metal bodies 52 and 62, the arm connection portion 80, and the external connection terminal 90 connected to the circuit pattern will be described with reference to FIGS. 14 and 15. FIG. 14 is a diagram showing the arrangement of the circuit pattern of the surface metal body 52, the semiconductor element 40, and the terminals. FIG. 15 is a diagram showing the arrangement of the circuit pattern of the surface metal body 62, the semiconductor element 40, and the terminals. For convenience, FIGS. 14 and 15 only show the external connection terminal 90 connected to the circuit pattern. In FIG. 14, the placement area of ​​the semiconductor element 40 is indicated by "D" to clearly show the main electrode (drain electrode 40D) connected to the surface metal body 52. ​​Similarly, in FIG. 15, the placement area of ​​the semiconductor element 40 is indicated by "S" to clearly show the main electrode (source electrode 40S) connected to the surface metal body 62.

[0098] 14 is an imaginary line that passes through the midpoints of the two semiconductor elements 40 that make up one arm. The imaginary line CL1 passes through the midpoint (center) of the two semiconductor elements 40 in the arrangement direction, and extends in the Y direction. The imaginary line CL1 is, for example, a line that passes through the midpoint of two semiconductor elements 40H. Instead of semiconductor element 40H, the imaginary line CL1 may be a line that passes through the midpoint of semiconductor element 40L.

[0099] As shown in Figure 14, the arrangement of the two semiconductor elements 40H is approximately line-symmetric with respect to the imaginary line CL1. Similarly, the arrangement of the two semiconductor elements 40L is also approximately line-symmetric with respect to the imaginary line CL1. Here, approximately line-symmetric allows for errors of the order of manufacturing variations. The circuit pattern of the front surface metal body 52 is also approximately line-symmetric with respect to the imaginary line CL1. In other words, each of the P wiring 54 and the relay wiring 55 is approximately line-symmetric with respect to the imaginary line CL1.

[0100] The arrangement of the arm connection parts 80 connected to the relay wiring 55 is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the external connection terminals 90 connected to the surface metal body 52 is also approximately line-symmetrical with respect to the imaginary line CL1. That is, the arrangement of the two P terminals 91P is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the two output terminals 92 is also approximately line-symmetrical with respect to the imaginary line CL1.

[0101] As in FIG. 14, an imaginary line CL1 is shown in FIG. 15. The arrangement of the semiconductor elements 40H, 40L is the same as in FIG. 14. As shown in FIG. 15, the circuit pattern of the front surface metal body 62 is also approximately line-symmetrical with respect to the imaginary line CL1. That is, the N wiring 64 and the relay wiring 65 are each approximately line-symmetrical with respect to the imaginary line CL1. As in FIG. 14, the arrangement of the arm connection portion 80 connected to the relay wiring 65 is also approximately line-symmetrical with respect to the imaginary line CL1. The arrangement of the two N terminals 91N, which are external connection terminals 90 connected to the front surface metal body 62, is also approximately line-symmetrical with respect to the imaginary line CL1.

[0102] <Circuit pattern> Next, the circuit pattern of the surface metal body 62 will be described in more detail with reference to Fig. 15. The dashed dotted lines shown in Fig. 15 indicate the boundaries of the respective regions.

[0103] As described above, the front surface metal body 62 of the substrate 60 has the N wiring 64 and the relay wiring 65. The N wiring 64 has a base 640 and a pair of extension portions 641. The pair of extension portions 641 extend from the base 640 in the Y direction toward the side surface 30c of the sealing body 30. The N wiring 64 defines the outer contour of the front surface metal body 62. The relay wiring 65 is sandwiched between the pair of extension portions 641. The relay wiring 65 is arranged in the notch 642 of the N wiring 64.

[0104] As shown in FIG. 15, the relay wiring 65 has an end 650 as one end in the Y direction. The end 650 is an end on the base portion 640 side in the Y direction. On the other hand, the base portion 640 of the N wiring 64 has a side 640a facing the end 650. The facing side 640a is a portion of the base portion 640 between a pair of extension portions 641. The base portion 640 also has an arrangement region 640b for the semiconductor element 40L. The arrangement region 640b is defined by the outline of the semiconductor element 40L, as indicated by the two-dot chain line in FIG. 15. The arrangement region 640b includes an area overlapping the semiconductor element 40L in a plan view, and also includes an area between the elements when multiple semiconductor elements 40L are included. The area between the elements is an area where the semiconductor elements 40L face each other in the arrangement direction of the semiconductor elements 40L.

[0105] Here, the lengths L1, L2, and L3 in the X direction are defined as follows. The length L1 is the length of the end portion 650 of the relay wiring 65 as shown in FIG. 15. The length L2 is the length of the opposing side 640a of the base portion 640. The length L3 is the length of the arrangement region 640b in the base portion 640. In the present embodiment, the relationship L1 < L2 < L3 is satisfied.

[0106] The relay wiring 65 of the present embodiment has a width-reducing portion 651a. The width-reducing portion 651a includes the end portion 650. The width-reducing portion 651a is a portion within a predetermined range in the Y direction from the end portion 650. The length in the X direction of the width-reducing portion 651a, that is, the width, is minimum at the end portion 650. In the width-reducing portion 651a, the width W1 at an arbitrary first position is less than or equal to the width W2 at a second position farther from the end portion 650 than the first position.

[0107] The width of the width-reducing portion 651a may be reduced stepwise, for example, for each predetermined length in the Y direction. That is, the end portion in the X direction of the width-reducing portion 651a may change in a stepped manner. In the present embodiment, the length in the X direction of the width-reducing portion 651a becomes shorter as it approaches the base portion 640. That is, the width of the width-reducing portion 651a continuously decreases toward the base portion 640. The arm connection portion 80 is disposed in the width-reducing portion 651a.

[0108] The relay wiring 65 may have only the width-reducing portion 651a including the end portion 650. In this case, the semiconductor element 40H is also disposed in the width-reducing portion 651a. The relay wiring 65 of the present embodiment has a constant-width portion 651b. The constant-width portion 651b is continuous with the width-reducing portion 651a and is a portion having a constant width over a predetermined range in the Y direction. And the semiconductor element 40H is disposed in the constant-width portion 651b.

[0109] The relay wiring 65 of this embodiment further includes a reduced-width portion 651c. The reduced-width portion 651c includes an end portion 652 opposite the end portion 650. The reduced-width portion 651c is opposite the reduced-width portion 651a and continues to the constant-width portion 651b. The width of the reduced-width portion 651c is smallest at the end portion 652. In the reduced-width portion 651c, the width at an arbitrary first position is equal to or smaller than the width at a second position that is farther from the end portion 652 than the first position. In this embodiment, the width of the reduced-width portion 651c continuously decreases toward the end portion 652. In the relay wiring 65, the reduced-width portions 651a and 651c become narrower the further away they are from the constant-width portion 651b.

[0110] In this embodiment, the distance between the N wiring 64 and the relay wiring 65 is approximately constant throughout the opposing region. The extension portions 641 of the N wiring 64 are patterned so that the distance between them and the relay wiring 65 is approximately constant. Each of the extension portions 641 has a widened portion 641a, a fixed-width portion 641b, and a widened portion 641c.

[0111] The widened portion 641a is connected to the base 640 and is a portion that extends over a predetermined range in the Y direction from the boundary with the base 640. The length in the X direction of the widened portion 641a, i.e., the width, is greatest at the boundary with the base 640. In the widened portion 641a, the width at an arbitrary first position is equal to or greater than the width at a second position that is farther from the base 640 than the first position. In this embodiment, the width of the widened portion 641a continuously increases toward the base 640. The constant-width portion 641b is connected to the widened portion 641a and is a portion that has a constant width over a predetermined range in the Y direction. The constant-width portion 641b faces the constant-width portion 651b of the relay wiring 65.

[0112] The widened portion 641c is opposite to the widened portion 641a and continues to the constant width portion 641b. The widened portion 641a extends to a position closer to the side surface 30c than the narrowed width portion 651c. The widened portion 641c includes the tip end 641d of the extension portion 641. The width of the widened portion 641c is greatest at the tip end 641d. In the widened portion 641c, the width at an arbitrary first position is equal to or greater than the width at a second position that is farther from the tip end 641d than the first position. In this embodiment, the width of the widened portion 641c continuously increases toward the tip end 641d in the portion facing the narrowed width portion 651c. In the widened portion 641c, the portion closer to the tip end 641d than the facing portion has a constant width. In the N wiring 64, the width of a portion of the widened portion 641c and the widened portion 641a increases the further away from the constant width portion 641b.

[0113] <Current path> Next, the current path will be described with reference to FIGS. 16 to 20. FIG. 16 is a diagram showing a PN current loop of a reference example. In the reference example, the reference symbols of each element are those of the related elements of the semiconductor device 20 with r added to the end. The configuration of the reference example is almost the same as that of the semiconductor device 20, except for the number of signal terminals 93Lr and the patterns of the N wirings 64r and relay wirings 65r. FIG. 17 is a diagram showing a PN current loop in the semiconductor device 20 of this embodiment. FIG. 18 is a diagram showing a PN current loop in a side view of the semiconductor device 20 as seen from the X direction. The PN current loop refers to the loop shape of the current path from the P terminal 91P to the N terminal 91N.

[0114] When examining inductance, the PN current loop of P terminal 91P → P wiring 54 → semiconductor element 40H → relay wiring 65 → arm connection portion 80 → relay wiring 55 → semiconductor element 40L → N wiring 64 → N terminal 91N is taken into consideration. For this reason, to make the PN current loop easier to understand, a continuous solid line is shown from the P terminal 91P to the N terminal 91N. In reality, semiconductor elements 40H and 40L are controlled so that they are not turned on at the same time. For convenience, only the current path for one semiconductor element 40H and one semiconductor element 40L is shown, but the same applies to the other semiconductor element 40H and the other semiconductor element 40L.

[0115] 19 and 20 show the results of electromagnetic field simulations. Fig. 19 shows the current density of the reference example shown in Fig. 18. Fig. 20 shows the current density for the configuration of this embodiment shown in Fig. 16. The conditions for the electromagnetic field simulations were the same for both examples, except that the circuit patterns of the surface metal body 62 were different. In Figs. 19 and 20, the lower the current density, the coarser (lighter color), and the higher the current density, the denser (darker color).

[0116] As shown in FIG. 16 , in the semiconductor device 20r of the reference example, the relay wiring 65r has a generally rectangular planar shape. The length of the end 650r of the relay wiring 65r is approximately equal to the length of the placement region 640br of the semiconductor element 40Lr at the base 640r. The length of the opposing side 640ar at the base 640r is longer than the placement region 640br. Therefore, as indicated by the solid arrows in FIG. 16 , current enters the generally rectangular planar semiconductor element 40Lr through one side 400r and exits through another side 401r. The side 400r is the side opposite the side where the two semiconductor elements 40Lr face each other. As such, the current flows outward from the semiconductor element 40Lr in the X direction, resulting in a large PN current loop. The simulation results shown in FIG. 19 also clearly show that current flows outward from the semiconductor element 40Lr through the base 640r in the X direction.

[0117] On the other hand, in the semiconductor device 20 of this embodiment, as described above, the N wiring 64 and the relay wiring 65 are patterned and satisfy a predetermined positional relationship with the semiconductor element 40L. Due to this positional relationship, as shown in FIG. 17 , the N wiring 64 (extension portion 641) is also present above one side 400 of the semiconductor element 40L in a planar view. The side 400 is the side opposite the relay wiring 65. Therefore, current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. The Y-direction component of the current flowing from the semiconductor element 40L toward the N-terminal 91N increases, particularly near the semiconductor element 40L. The simulation results shown in FIG. 20 also clearly show that the current flowing from the semiconductor element 40L has a Y-direction component.

[0118] In this way, the current flowing through the N wiring 64 approaches the relay wiring 65, and the current path through the N wiring 64, i.e., the current path between the semiconductor element 40L and the N terminal 91N, is shortened. Therefore, the PN current loop is smaller than in the reference example. As shown in FIG. 18, the PN current loop is also small in the Z direction. The P wiring 54 and the N wiring 64 face each other in the Z direction. Furthermore, the relay wiring 55 and the N wiring 64 face each other in the Z direction.

[0119] <Summary of the First Embodiment> If the inductance of the main circuit wiring is high, the surge voltage will be large. If the semiconductor element is made thicker to ensure the withstand voltage, steady-state loss will increase. To reduce steady-state loss, the element area must be increased. Surge voltage can also be reduced by reducing the switching speed. In this case, the output to the motor generator will be reduced. In this way, if the inductance is high, the size of the semiconductor element will be large or the output will be small.

[0120] When components through which currents flow in opposite directions are arranged opposite to each other, the magnetic flux generated by the currents cancels out, reducing inductance. When the PN current loop in the main circuit wiring is smaller, components through which currents flow in opposite directions are closer to each other, increasing the magnetic flux cancellation effect and reducing inductance.

[0121] In this embodiment, the semiconductor elements 40H and 40L are arranged side by side in the Y direction, and the arm connection portion 80 is arranged between the semiconductor elements 40H and 40L. Of the main terminals, the power supply terminals 91 (91P, 91N) are drawn out in the same direction. In addition, in the Y direction, the P wiring 54 is arranged on the power supply terminal 91 side, and the relay wiring 55 is arranged on the opposite side. In the Y direction, the relay wiring 65 is arranged on the power supply terminal 91 side, and the base portion 640 of the N wiring 64 is arranged on the opposite side. The extension portion 641 of the N wiring 64 extends toward the power supply terminal 91 so as to sandwich the relay wiring 65 therebetween.

[0122] With such a configuration, the PN current loop becomes smaller. As a result, the inductance of the main circuit wiring can be reduced. For example, by arranging the P terminal 91P and the N terminal 91N in parallel, the inductance can be reduced. The relay wiring 65 and the N wiring 64 are also arranged (in parallel) with a predetermined interval therebetween. As a result, the inductance can be reduced. Further, the extended portion 641 of the N wiring 64 faces the P wiring 54. As a result, the inductance can be reduced.

[0123] In the present embodiment, the surface metal body 52 of the substrate 50 and the surface metal body 62 of the substrate 60 provide a wiring function for the semiconductor element 40. The surface metal bodies 52 and 62 are sealed by the sealing body 30. Since it is not necessary to secure the creepage distance as in the prior art, the N wiring 64 and the relay wiring 65 can be arranged closer to each other. As a result, the effect of magnetic flux cancellation is enhanced, and the inductance can be further reduced.

[0124] Further, as shown in FIG. 15, the length L1 of the end portion 650 of the relay wiring 65, the length L2 of the opposing side 640a of the base portion 640, and the length L3 of the arrangement region 640b of the semiconductor element 40L in the base portion 640 satisfy the relationship L1 < L2 < L3. By satisfying this dimensional relationship, as described above, current enters from one side 400 of the semiconductor element 40L and exits from the same side 400. Among the currents flowing from the semiconductor element 40L toward the N terminal 91N, particularly in the vicinity of the semiconductor element 40L, the Y-direction component increases. As a result, the current path through the N wiring 64, that is, the current path between the semiconductor element 40L and the N terminal 91N becomes shorter, and the PN current loop becomes smaller. Therefore, the inductance of the main circuit wiring can be further reduced.

[0125] Further, as the frequency of the current is higher, due to the skin effect, current concentrates on the opposing side between the extended portion 641 of the N wiring 64 and the relay wiring 65. As a result, the PN current loop can be further reduced, and thus the inductance can be further reduced.

[0126] 15, the relay wiring 65 has a reduced width portion 651a. This allows the width of the portion of the extension portion 641 facing the reduced width portion 651a to be increased. This makes it possible to suppress heat generation due to current flow without changing the size of the surface metal body 62 and, ultimately, the substrate 60. In other words, it is possible to suppress heat generation while reducing inductance.

[0127] In particular, in this embodiment, the length of the reduced width portion 651a in the X direction becomes shorter as it approaches the base 640. In other words, the width of the reduced width portion 651a continuously decreases toward the base 640. The reduced width portion 651a of the relay wiring 65 has a tapered shape. This makes it easier to maintain a constant distance between the relay wiring 65 and the extension portion 641. In other words, the extension portion 641 can be brought closer to the relay wiring 65, thereby reducing the size of the PN current loop. Furthermore, the width of the extension portion 641 can be increased, thereby suppressing heat generation.

[0128] In this embodiment, the relay wiring 65 has a constant-width portion 651b. The semiconductor element 40H is disposed in the constant-width portion 651b. The relay wiring 65, which has the reduced-width portion 651a and the constant-width portion 651b, has a shape identical to or similar to a baseball home base in a plan view. This allows the width of the extension portion 641 to be wider than in a configuration in which the semiconductor element 40H is disposed in the reduced-width portion 651a. Therefore, heat generation due to current flow can be suppressed without changing the size of the surface metal body 62, and therefore the substrate 60. In other words, heat generation can be suppressed while reducing inductance.

[0129] In this embodiment, the semiconductor device 20 includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged side by side in the X direction. Similarly, the two semiconductor elements 40L are arranged side by side in the X direction. In this manner, the semiconductor elements 40 constituting one arm are arranged side by side in a direction (X direction) perpendicular to the arrangement direction (Y direction) of the semiconductor elements 40H and 40L. In the X direction, a pair of extension portions 641 sandwich the relay wiring 65. This makes it possible to suppress current imbalance.

[0130] The semiconductor device 20 may include one N terminal 91N whose tip is branched into two so as to be individually connected to the pair of extension portions 641. In this embodiment, the semiconductor device 20 includes two N terminals 91N, which are individually connected to the pair of extension portions 641. This makes it easy to arrange another external connection terminal 90 between the two N terminals 91N. Since there is no need to avoid the external connection terminal 90 arranged between them, the size can be made smaller.

[0131] The semiconductor device 20 may include only one P terminal 91P. In this embodiment, the semiconductor device 20 includes two P terminals 91P. The N terminal 91N, P terminal 91P, signal terminal 93H, P terminal 91P, and N terminal 91N are arranged in this order in the X direction. The P terminal 91P and N terminal 91N are arranged side by side at both ends in the X direction. This makes it easy to reduce the size of the PN current loop. Furthermore, because the external connection terminals 90 are arranged with regularity in the X direction, it is easy to ensure line symmetry for the circuit patterns of the semiconductor element 40, the surface metal bodies 52 and 62, and the external connection terminals 90, as described above. This makes it possible to suppress current bias.

[0132] In this embodiment, the P terminal 91P and the N terminal 91N protrude from the side surface 30c of the sealing body 30, and the output terminal 92 protrudes from the side surface 30d. In this manner, the P terminal 91P and the N terminal 91N connected to the smoothing capacitor 5 are drawn in the same direction, and the output terminal 92 is drawn in the opposite direction. This improves the connectivity with the smoothing capacitor 5 and the connectivity with the motor generator 3. Furthermore, arranging the P terminal 91P and the N terminal 91N in parallel reduces inductance. This terminal arrangement makes it easier to reduce the size of the PN current loop.

[0133] <Modification> As an example of providing a plurality of each of the semiconductor elements 40H and 40L, an example of providing two of each has been shown, but it is not limited thereto. Three or more may be provided. For example, a configuration in which three semiconductor elements 40H are arranged side by side in the X direction and three semiconductor elements 40L are arranged side by side in the X direction may be adopted. The circuit pattern of the surface metal body 62 and the arrangement of the semiconductor elements 40 are not limited to the above examples. For example, it may be as shown in FIGS. 21 and 22. In FIGS. 21 and 22, for the sake of convenience, the sealing body 30 on the back surface 30b side with respect to the insulating base material 51 is omitted from the illustration. Also, among the substrates 60, the insulating base material 61 and the back surface metal body 63 are omitted from the illustration. Similar to FIG. 17, the PN current loop is indicated by a solid arrow. In FIGS. 21 and 22, the semiconductor device 20 includes two signal terminals 93L.

[0134] In FIG. 21, the semiconductor device 20 includes two arm connection portions 80. The relay wiring 65 has a substantially rectangular planar shape. The two arm connection portions 80 are arranged side by side in the X direction in the vicinity of the end portion 650. The interval between the two semiconductor elements 40L is larger than that in the above example (see FIG. 17). The length of the arrangement region 640b of the semiconductor element 40L is longer than that in the above example. As a result, the relationship of L1 < L2 < L3 is satisfied. Therefore, current enters from the side 400 of the semiconductor element 40L and exits from the same side 400. Even with such a configuration, the current path by the N wiring 64 becomes shorter, and the PN current loop can be made smaller. However, in the configuration shown in FIG. 17, the width of the N wiring 64, particularly the width of the extended portion 641, can be made wider. Also, in the case of the configuration shown in FIG. 17, only one arm connection portion 80 may be provided.

[0135] In FIG. 22, the semiconductor device 20 includes only one semiconductor element 40H and one semiconductor element 40L respectively. In this example, the arrangement region 640b coincides with the outer contour of the semiconductor element 40L. The length of one semiconductor element 40H or 40L in the X direction is longer than that in the above example (see FIG. 17). Thus, the relationship of L1 < L2 < L3 is satisfied. Therefore, current enters from side 400 of the semiconductor element 40L and exits from the same side 400. Even with such a configuration, the current path by the N wiring 64 is shortened, and the PN current loop can be reduced.

[0136] The arrangement of the external connection terminals 90 is not limited to the above example. For example, the P terminal 91P may be arranged on the outer side in the X direction and the N terminal 91N may be arranged on the inner side. In this case, as shown in FIGS. 23 and 24, the semiconductor element 40 and the circuit pattern are also reversed. FIG. 23 shows the substrate 50. FIG. 24 shows the substrate 60.

[0137] As shown in FIG. 23, the circuit pattern of the surface metal body 52 of the substrate 50 is the same as the circuit pattern of the surface metal body 62 of the substrate 60 shown in FIG. 15. The P wiring 54 has the same pattern as the N wiring 64 shown in FIG. 15. The semiconductor element 40H is arranged on the N wiring 64. The relay wiring 55 has the same pattern as the relay wiring 65 shown in FIG. 15. The semiconductor element 40L and the arm connection portion 80 are arranged on the relay wiring 55.

[0138] As shown in FIG. 24, the circuit pattern of the surface metal body 62 of the substrate 60 is the same as the circuit pattern of the surface metal body 52 of the substrate 50 shown in FIG. 14. The N wiring 64 has the same pattern as the P wiring 54 shown in FIG. 14. The semiconductor element 40L is arranged on the N wiring 64. The relay wiring 65 has the same pattern as the relay wiring 55 shown in FIG. 14. The semiconductor element 40H and the arm connection portion 80 are arranged on the relay wiring 65.

[0139] 23 and 24, the above-described first and second relationships are reversed. The semiconductor element 40L is the first element, and the semiconductor element 40H is the second element. The source electrode 40S is the first main electrode, and the drain electrode 40D is the second main electrode. The substrate 60 is the first substrate, and the substrate 50 is the second substrate. The insulating base material 61 is the first insulating base material, the front surface metal body 62 is the first front surface metal body, and the back surface metal body 63 is the first back surface metal body. The insulating base material 51 is the second insulating base material, the front surface metal body 52 is the second front surface metal body, and the back surface metal body 53 is the second back surface metal body.

[0140] (Second embodiment) This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to suppress transient current imbalance during switching, as described in this embodiment, the surface metal body to which multiple semiconductor elements are connected in parallel may have a predetermined structure.

[0141] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view showing the semiconductor device 20 of this embodiment. Fig. 25 corresponds to Fig. 8.

[0142] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 15). The semiconductor device 20 constitutes upper and lower arm circuits 9 for one phase. As shown in FIG. 25, the semiconductor device 20 includes a plurality of semiconductor elements 40, including two semiconductor elements 40H that serve as upper arm elements, substrates 50 and 60 that are arranged to sandwich the semiconductor elements 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is a first main electrode on the high potential side of the semiconductor elements 40. The surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is a second main electrode on the low potential side of the semiconductor elements 40. Although not shown, the semiconductor device 20 also includes two semiconductor elements 40L that serve as lower arm elements.

[0143] As in the previous embodiment, the front surface metal body 62 is substantially symmetrical with respect to the imaginary line CL1. As shown in Fig. 25, in this embodiment, the relay wiring 65 of the front surface metal body 62 has a slit 653. As will be described later, the N wiring 64 has a slit 643.

[0144] <Suppression effect of transient current imbalance> Next, the effect of suppressing transient current imbalance during switching will be described with reference to Fig. 26 and Fig. 27. Fig. 26 is an equivalent circuit diagram of two semiconductor elements 40 (MOSFETs 11) that form one arm. Fig. 27 is an image diagram (potential diagram) that clearly shows the potentials.

[0145] 26 and 27, one of the parallel-connected MOSFETs 11 is shown as MOSFET1, and the other is shown as MOSFET2. The inductance of the wiring on the drain electrode side (hereinafter referred to as drain wiring) is shown as Ld, and the inductance of the wiring on the source electrode side (hereinafter referred to as source wiring) is shown as Ls. The gate potential is shown as Vg, the potential of the source electrode of MOSFET1 as Vks1, the potential of the source electrode of MOSFET2 as Vks1, and the common source potential as Vs. The midpoint potential between potentials Vks1 and Vks2 is shown as Vm. The midpoint potential Vm is constant. Vm=(Vks1+Vks2) / 2.

[0146] The gate voltage of MOSFET1 is shown as Vgs1, and the gate voltage of MOSFET2 is shown as Vgs2. The current that flows through MOSFET1 when it is turned on is shown as I1, and the voltage that occurs across inductance Ls when current I1 flows is shown as ΔVs1. Similarly, the current that flows through MOSFET2 when it is turned on is shown as I2, and the voltage that occurs across inductance Ls when current I2 flows is shown as ΔVs2. ΔVs1=Ls×dI1 / dt. ΔVs2=Ls×dI2 / dt.

[0147] Suppose that a current I2 (I2>I1) greater than the current I1 flows due to variations in the characteristics of the MOSFET 11, as shown in FIG. 26. At this time, the voltage ΔVs generated across the inductance Ls is ΔVs1<ΔVs2. That is, as shown in FIG. 27, the potential Vks2 of the source electrode rises relative to the midpoint potential Vm, and the potential Vks1 falls. Therefore, the gate voltage Vgs1 is greater than the gate voltage Vgs2. The gate voltage Vgs2 is reduced, so the current I2 decreases. In this way, the inductance Ls of the source wiring has the function of suppressing transient current imbalance during switching due to variations in the characteristics of the semiconductor element 40 (MOSFET 11) connected in parallel.

[0148] However, if the inductance Ls of the source wiring is small, the function of suppressing the transient current imbalance described above is impaired, which causes bias in the switching loss and requires a margin in the thermal design.

[0149] <Circuit pattern on board> Next, the circuit pattern of the surface metal body 62 in the semiconductor device 20 of this embodiment will be described with reference to Fig. 28. Fig. 28 corresponds to Fig. 15. In Fig. 28, as in Fig. 15, the source electrode 40S is indicated as S in order to clarify the main electrode to which it is connected.

[0150] The N wiring 64 and the relay wiring 65 are source wirings to which the source electrode 40S of the semiconductor element 40 is connected. The N wiring 64 differs from the pattern of the preceding embodiment in that it has a slit 643. Similarly, the relay wiring 65 differs from the pattern of the preceding embodiment in that it has a slit 653. Except for the slits 643 and 653, the configuration is the same as that described in the preceding embodiment.

[0151] The slit 643 penetrates the N wiring 64 in its thickness direction (Z direction). The slit 643 is provided in a position in the base 640 overlapping with an opposing region of two semiconductor elements 40L. The opposing region is a region in which the semiconductor elements 40L face each other in the arrangement direction of the semiconductor elements 40L. That is, the slit 643 is provided between the semiconductor elements 40L that are lower arm elements in a plan view in the Z direction. The slit 643 is provided in the base 640 between electrical connection portions with the semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction, which is the arrangement direction of the semiconductor elements 40H, 40L. The slit 643 opens to the opposing side 640a of the base 640. The slit 643 is provided in an approximately central position of the N wiring 64 in the X direction.

[0152] In this way, the slit 643 extends in the Y direction from the source electrode 40S of the semiconductor element 40L toward the side where the N terminal 91N, which is the main terminal, is located, i.e., toward the side where current flows. The slit 643 does not open to the end 640c of the base 640. The slit 643 is provided up to near the lower end of the facing region of the semiconductor element 40L. The slit 643 divides the N wiring 64 into a region to which one of the semiconductor elements 40L is connected and a region to which another of the semiconductor elements 40L is connected. The slit 643 separates the current path of the source electrode 40S of the semiconductor element 40L, i.e., the source current path.

[0153] The slit 653 penetrates the relay wiring 65 in its thickness direction (Z direction). The slit 653 is provided in the relay wiring 65 at a position overlapping the opposing regions of the two semiconductor elements 40H. That is, the slit 653 is provided between the semiconductor elements 40H in plan view. The slit 653 is provided in the relay wiring 65 between the electrical connection portions with the semiconductor elements 40H. The slit 653 extends in the Y direction from between the semiconductor elements 40H. The slit 653 opens at the end 652. The slit 653 extends from the end 652 across the space between the semiconductor elements 40H (the opposing region) and to the vicinity of the arm connection portion 80. The slit 653 is provided in approximately the center of the relay wiring 65 in the X direction.

[0154] In this way, the slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the arm connection portion 80 in the Y direction. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the side where current flows. The slit 653 does not open to the end portion 650. The slit 643 is provided up to just before the arm connection portion 80. The slit 653 divides the relay wiring 65 into an area to which one of the semiconductor elements 40H is connected and an area to which another one is connected. The slit 653 separates the current path of the source electrode 40S of the semiconductor element 40H, i.e., the source current path.

[0155] <Summary of the second embodiment> 29 shows the source current paths. The solid arrows indicate the source current paths on the semiconductor element 40H side, and the dashed arrows indicate the source current paths on the semiconductor element 40L side. As described above, in this embodiment, slits 643 and 653 are provided in the surface metal body 62 to which the source electrode 40S, which is the main electrode on the low potential side, is connected.

[0156] The slits 643 are provided between adjacent semiconductor elements 40L in the N wiring 64 to which the semiconductor elements 40L are connected in parallel. The slits 643 divide the N wiring 64 and separate the source current paths of each semiconductor element 40L. This prevents currents (source currents) from flowing from the source electrodes 40S of the semiconductor elements 40L from joining together near the source electrodes 40S. In other words, the joining point of the source currents is moved away from the source electrodes 40S in a plan view. Therefore, in a parallel circuit of two semiconductor elements 40L (MOSFETs 11), the inductance Ls of the source wiring can be increased compared to a configuration without the slits 643. Because the inductance Ls is large, transient current imbalance during switching can be suppressed even if there is variation (deviation) in the characteristics of the two semiconductor elements 40L. The provision of the slits 643 allows transient current imbalance to be suppressed while maintaining high integration of the semiconductor elements 40L.

[0157] Similarly, the relay wiring 65 has a slit 653. The slit 653 is provided between the two semiconductor elements 40H. The slit 653 divides the relay wiring 65 and separates the source current paths of each semiconductor element 40H. This prevents currents (source currents) from flowing from the source electrodes 40S of the semiconductor elements 40H from joining together near the source electrodes 40S. In other words, the joining point of the source currents is moved away from the source electrodes 40S in a planar view. Therefore, in a parallel circuit of two semiconductor elements 40H, the inductance Ls of the source wiring can be increased compared to a configuration without the slit 653. Because the inductance Ls is large, transient current imbalance during switching can be suppressed even if there is variation (deviation) in the characteristics of the two semiconductor elements 40H. By providing the slit 653, transient current imbalance can be suppressed while maintaining high integration of the semiconductor elements 40H.

[0158] In this embodiment, the slit 643 extends from between adjacent semiconductor elements 40L in the Y direction toward the N terminal 91N. The slit 643 extends from the source electrode 40S of the semiconductor element 40L toward the current flowing side. This allows the source current paths of the semiconductor elements 40L to be separated by a longer distance. Therefore, in a parallel circuit of the semiconductor elements 40L, the inductance Ls of the source wiring can be increased. In other words, the effect of suppressing transient current imbalance can be improved.

[0159] Similarly, a slit 653 extends from between adjacent semiconductor elements 40H in the Y direction toward the arm connection portion 80. The slit 653 extends from the source electrode 40S of the semiconductor element 40H toward the current flowing side. This allows the source current paths of the semiconductor elements 40L to be separated by a longer distance. Therefore, in a parallel circuit of the semiconductor elements 40H, the inductance Ls of the source wiring can be increased. In other words, the effect of suppressing transient current imbalance can be improved.

[0160] Fig. 30 is a cross-sectional view taken along line XXX-XXX in Fig. 29. In this embodiment, the joint portion 81, the bonding material 103 connecting the joint portion 81 and the relay wiring 55, and the bonding material 103 connecting the joint portion 81 and the relay wiring 65 constitute the arm connection portion 80 that electrically connects the relay wirings 55, 65. The joint portion 81 is a separate member from the substrates 50, 60. The arm connection portion 80 electrically connects the relay wiring 65 connected to the source electrode 40S of the semiconductor element 40H and the relay wiring 55 connected to the drain electrode 40D of the semiconductor element 40L.

[0161] <Modification> In the above example, the multiple semiconductor elements 40 include two each of the semiconductor elements 40H and 40L, but this is not limiting. A configuration including two of the semiconductor elements 40H and 40L and one of the other may also be used. In this case, a slit may be provided in one of the two wirings (64, 65) of the front surface metal body 62, which forms one arm by connecting the multiple semiconductor elements 40 in parallel. For example, in a configuration including two semiconductor elements 40H and one semiconductor element 40L, the slit 643 may not be provided in the N wiring 64, but the slit 653 may be provided in the relay wiring 65 to which the semiconductor element 40H is connected. In this way, the multiple semiconductor elements 40 may include two arm elements of at least one of the semiconductor elements 40H and 40L.

[0162] The number of semiconductor elements 40 connected in parallel is not limited to two. Three or more semiconductor elements 40 may be connected in parallel to form one arm. For example, in a configuration including three semiconductor elements 40H, slits 653 may be provided between the three semiconductor elements 40H arranged side by side in the X direction and adjacent semiconductor elements 40H in a plan view. The multiple semiconductor elements 40 may include multiple arm elements of at least one of the semiconductor elements 40H and 40L. The multiple arm elements may also be included, that is, multiple semiconductor elements 40H and multiple semiconductor elements 40L.

[0163] The arrangement of the N terminal 91N is not limited to the above example. For example, the P terminal 91P may protrude from the side surface 30c of the sealing body 30, and the N terminal 91N may protrude from the side surface 30d. In this case, the pattern of the N wiring 64 may have a shape similar to that of the P wiring 54 or the relay wiring 55. That is, the extension portion 641 extends from the base portion 640 toward the side surface 30d of the sealing body 30. Even in this configuration, the slit 643 only needs to be provided at least between the semiconductor elements 40L. Furthermore, by configuring the slit 643 to extend from the opposing region of the semiconductor elements 40L to the outside of the opposing region toward the N terminal 91N, the inductance Ls can be further increased.

[0164] Although one slit 643, 653 is provided between the semiconductor elements 40, the present invention is not limited to this. At least one of the slits 643, 653 may be provided in plurality.

[0165] Although an example in which the slits 643 and 653 open at one of the ends of the front surface metal body 62 has been shown, this is not limiting. For example, in the example shown in FIGS. 31 and 32 , the slit 643 extends in the Y direction from the opposing side 640a of the base 640 to the end 640c. The slit 643 divides the base 640, and therefore the N wiring 64, into two. The slit 643 crosses the opposing region of the semiconductor elements 40L. One of the semiconductor elements 40L is disposed in one of the divided N wirings 64, and the other one of the semiconductor elements 40L is disposed in the other N wiring 64. Similarly, the slit 653 extends in the Y direction from the end 652 to the end 650 of the relay wiring 65. The slit 653 divides the relay wiring 65 into two. One of the semiconductor elements 40H is disposed in one of the divided relay wirings 65, and the other one of the semiconductor elements 40H is disposed in the other relay wiring 65.

[0166] The slits 643 and 653 are connected to each other to form a single slit extending in the Y direction. The surface metal body 62 is substantially symmetrical with respect to the imaginary line CL1. FIG. 33 shows the source current path. The solid arrow indicates the source current path of the semiconductor element 40H, and the dashed arrow indicates the source current path of the semiconductor element 40L. As described above, the slit 643 divides the N wiring 64 into two. This prevents one source current of the semiconductor element 40L and another source current from joining together on the substrate 60. Since the joining point of the source currents is further away, the inductance Ls of the source wiring can be further increased.

[0167] Similarly, slit 653 divides relay wiring 65 into two. This prevents the source current of semiconductor element 40H and another source current from merging on substrate 60. Since the merging point of the source currents is further away, the inductance Ls of the source wiring can be further increased. As a result, the effect of suppressing transient current imbalance can be improved. Figures 31, 32, and 33 are diagrams showing modified examples. Figure 31 corresponds to Figure 28. Figure 32 corresponds to Figure 11. Figure 33 corresponds to Figure 29.

[0168] 31 to 33, the arm connecting portions 80 are divided into the same number as the relay wirings 65 in accordance with the division of the relay wirings 65. The arm connecting portions 80 are individually connected to the relay wirings 65. This prevents the source currents from joining together at the arm connecting portions 80 as well, making it possible to further increase the inductance Ls.

[0169] In the configuration of the above-described modified example, a slit may be further provided in the surface metal body 52 of the substrate 50. As shown in FIGS. 34 and 35 , the relay wiring 55 of the surface metal body 52 has a slit 553. The slit 553 opens at an end 551a of the relay wiring 55. The end 551a faces the P wiring 54 in the Y direction. The slit 553 extends in the Y direction, crosses the arm connection portion 80 that is divided into two, and reaches the opposing region (between) the semiconductor element 40L. The slit 553 is provided up to near the lower end of the opposing region of the semiconductor element 40L.

[0170] When such a configuration is adopted, as shown in FIG. 35, a first current path through one pair of semiconductor elements 40H, 40L and a second current path through another pair of semiconductor elements 40H, 40L are almost completely separated within the semiconductor device 20. The current confluence point is provided outside the N terminal 91N. This allows the inductance Ls of the source wiring to be further increased. FIGS. 34 and 35 are diagrams showing modified examples. FIG. 34 corresponds to FIG. 32. FIG. 35 corresponds to FIG. 33. The semiconductor device 20 may also include an N bus bar connecting multiple N terminals 91N. In this case, the currents converge at the N bus bar. The N bus bar connecting the N terminals 91N may also be provided on the smoothing capacitor 5 side, for example.

[0171] Although an example has been shown in which the arm connection part 80 is configured by the joint part 81 and the bonding material 103 arranged on both ends of the joint part 81, the present invention is not limited to this. In the example shown in Fig. 36, the joint part 81 is provided integrally with the substrate 60. The joint part 81 is provided as a protrusion extending in the Z direction from the relay wiring 65. Like the joint part 81, the conductive spacer 70 is also provided integrally with the surface metal body 62 as a protrusion.

[0172] The surface metal body 62 having the protrusions may be formed, for example, by patterning a multi-gauge metal plate by press working and attaching it to the insulating base material 61. The surface metal body 62 having the protrusions may also be formed by etching thick Cu. It may also be formed by directly bonding a metal body that is a separate member from the substrate 60 to the surface metal body 62. In the configuration shown in FIG. 36, the arm connection part 80 is made up of a joint part 81 that is a protrusion of the relay wiring 65 and a bonding material 103 interposed between the tip of the joint part 81 and the relay wiring 55. FIG. 36 is a view corresponding to FIG. 30.

[0173] In the example shown in FIG. 37 , the joint portion 81 is eliminated. A bonding material 103 electrically connects the relay wirings 55 and 65. The bonding material 103 constitutes the arm connection portion 80. In FIG. 37 , the conductive spacer 70 is also eliminated, and the source electrode 40S of the semiconductor element 40 is connected to the surface metal body 62 via the bonding material 101. Although not shown, the arm connection portion 80 may be configured to include only the joint portion 81 without the bonding material 103. In this case, the joint portion 81 is directly bonded to the relay wirings 55 and 65.

[0174] The circuit patterns of the substrates 50 and 60 are not limited to the above examples. The substrate 60 shown in FIG. 38 shows an example in which slits 643 and 653 are applied to the circuit pattern shown in FIG. 24. In the example shown in FIG. 38, the slit 643 is provided between adjacent semiconductor elements 40L. The slit 643 extends from between the semiconductor elements 40L in the Y direction toward the N-terminal 91N, i.e., the side through which the source current flows. The slit 653 is provided between adjacent semiconductor elements 40H. The slit 653 extends from between the semiconductor elements 40H in the Y direction toward the arm connection portion 80.

[0175] In this embodiment, the arrangement of the external connection terminals 90 is not limited to the example shown in the figure. The P terminal 91P may be connected to the P wiring 54 at both ends in the X direction, for example. The N terminal 91N may be connected to the N wiring 64 at both ends in the X direction, for example. In this case, the N terminal 91N may be connected to the extension portion 641. The extension portion 641 may be removed from the N wiring 64 and connected to the base portion 640. The output terminal 92 may be connected to the relay wiring 55 at both ends in the X direction, for example.

[0176] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment and its modified examples.

[0177] (Third embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to effectively dissipate heat from the semiconductor element, the thickness above and below the semiconductor element may satisfy a predetermined relationship, as described in this embodiment.

[0178] <Warping at high temperatures> After careful investigation, it became clear that even when insulating base materials 51, 61 made of resin are used and the linear expansion coefficient is made closer to that of metal bodies 52, 53, 62, 63 by adding filler, warping can occur in semiconductor device 20, as shown in Fig. 39. Fig. 39 shows the state of semiconductor device 20 when semiconductor element 40 is in operation, that is, at high temperatures. The dashed dotted line in the figure is a reference line indicating the direction of warping.

[0179] The configuration shown in FIG. 39 is similar to that described in the preceding embodiment (see FIG. 5). For convenience, the external connection terminals 90 are omitted from FIG. 39. In FIG. 39, the semiconductor device 20 and the heat exchanger 121 of the cooler 120 are arranged side by side in the Z direction, which is a predetermined direction. The heat exchanger 121 is arranged on both sides of the semiconductor device 20 in the Z direction, sandwiching the semiconductor device. A thermally conductive member 130, such as silicone gel, is arranged between each of the heat exchanger 121 and the semiconductor device 20. The cooler 120 cools the semiconductor device 20 by circulating a refrigerant through the flow path of the heat exchanger 121. The refrigerant flowing through the flow path can be a phase-change refrigerant such as water or ammonia, or a phase-invariant refrigerant such as an ethylene glycol-based refrigerant. The thermally conductive member 130 is sometimes referred to as a thermal interface material (TIM). The thermally conductive member 130 conforms to the opposing surfaces of the heat exchanger 121 and the semiconductor device 20, filling the gap between the opposing surfaces.

[0180] As described above, in the semiconductor element 40, the drain electrode 40D, which is the main electrode on the high potential side, has a larger electrode area than the source electrode 40S, which is the main electrode on the low potential side. Furthermore, a conductive spacer 70 is interposed between the source electrode 40S and the substrate 60, whereas no conductive spacer 70 is interposed between the drain electrode 40D and the substrate 50. In other words, the thermal resistance of the heat transfer path from the semiconductor element 40 to the substrate 50 is smaller than that of the heat transfer path from the semiconductor element 40 to the substrate 60. In the semiconductor device 20 configured as described above, it is required to effectively dissipate heat to the substrate 50 side.

[0181] As shown in FIG. 39 , when warpage occurs, with the substrate 50 side concave and the substrate 60 side convex, the distance between the back surface 50b of the substrate 50 (the exposed surface) and the heat exchanger 121 increases, and the intervening heat conduction member 130 becomes thicker. This increases the thermal resistance between the substrate 50 and the heat exchanger 121, making it difficult to transfer heat (heat exchange) between the semiconductor device 20 and the cooler 120 (heat exchanger 121). The warpage shown in FIG. 39 is not desirable for effectively dissipating heat from the semiconductor element 40, i.e., for efficiently cooling the semiconductor device 20. FIG. 39 shows an example of a double-sided cooling structure in which the cooler 120 (heat exchanger 121) is arranged on both sides of the semiconductor device 20. However, a single-sided cooling structure in which the cooler 120 is arranged only on the substrate 50 side in the Z direction also has the same problem.

[0182] <Structure of semiconductor device> Through careful investigation, it has become clear that warpage of the semiconductor device 20 can be controlled by controlling the relative thickness of the portion of the semiconductor device 20 closer to the substrate 50 than the semiconductor element 40 and the portion closer to the substrate 60. The semiconductor device 20 of this embodiment has a configuration based on this finding. FIG. 40 is a cross-sectional view showing the semiconductor device 20 of this embodiment. FIG. 40 shows an ideal state in which the semiconductor device 20 is free of warpage.

[0183] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). Like FIG. 39, FIG. 40 shows the semiconductor device 20 together with the heat exchanger 121 of the cooler 120 and the heat conduction member 130. That is, FIG. 40 shows a semiconductor module 140 including the semiconductor device 20, the cooler 120, and the heat conduction member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchangers 121. The semiconductor device 20 is arranged alongside the cooler 120 (heat exchanger 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

[0184] The back surface metal bodies 53, 63 are exposed from the sealing body 30 as back surfaces 50b, 60b of the substrates 50, 60. One of the heat exchanger sections 121 of the cooler 120 is disposed facing one surface 30a and the back surface 50b of the sealing body 30, and the other of the heat exchanger sections 121 is disposed facing the back surfaces 30b and 60b of the sealing body 30. Heat conduction members 130 are disposed between the opposing surfaces of the semiconductor device 20 and the heat exchanger sections 121. The heat conduction members 130 are in close contact with the semiconductor device 20 and the heat exchanger sections 121.

[0185] The semiconductor device 20 is configured such that a thickness T1 on the substrate 50 side of the semiconductor element 40 and a thickness T2 on the substrate 60 side of the semiconductor element 40 satisfy the relationship T1≧T2. The other configurations are the same as those described in the preceding embodiment (see FIG. 5 ). The thickness T1 is the total thickness of the bonding material 101, the conductive spacer 70, the bonding material 102, and the substrate 60. The thickness T2 is the total thickness of the bonding material 100 and the substrate 50. Since the relationship T1≧T2 is satisfied, the substrate 50 is thicker than the substrate 60. The substrate 50 is thicker than the conductive spacer 70. In the substrate 50, the metal bodies 52 and 53 are thicker than the insulating base material 51. In the substrate 60, the metal bodies 62 and 63 are thicker than the insulating base material 61. The configurations of the parts other than the thickness relationships are the same as those described in the first embodiment.

[0186] <Simulation results> 41 to 43 show the results of a thermal stress simulation. FIG. 41 shows the state of the semiconductor device 20 shown in FIG. 40 at room temperature (RT). FIG. 42 shows the state of the semiconductor device 20 shown in FIG. 40 at a high temperature. At a high temperature, the semiconductor element 40 generates heat due to electrical current, i.e., the semiconductor element 40 is operating. As shown in FIGS. 41 and 42, warping occurs in the semiconductor device 20 at a high temperature. In this embodiment, since the relationship T1≧T2 is satisfied as described above, the expansion amount on the substrate 50 side is greater than the expansion amount on the substrate 60 side, as indicated by the dashed arrow in FIG. 42. This is because Cu, which constitutes the metal bodies 52, 53, 62, and 63, has the largest linear expansion coefficient and the substrate 50 is thick. As a result, a convex warp occurs on the side of the substrate 50 (the first substrate) and a concave warp occurs on the side of the substrate 60 (the second substrate). The dashed line in FIG. 42 is a reference line indicating the direction of warping.

[0187] FIG. 43 shows the relationship between the ratio of thicknesses T1 and T2 and the amount of warpage at high temperatures. In this simulation, the semiconductor element 40, conductive spacer 70, and bonding materials 100, 101, and 102 were all the same (common), and the thicknesses of the substrates 50 and 60 were adjusted so that the thickness ratio T1:T2 was a predetermined value. The material configurations were all the same (common). The vertical axis in FIG. 43 indicates the amount of warpage, expressed in arbitrary units (au). A warpage above 0 (zero) indicates a convex warpage toward the substrate 50 and a concave warpage toward the substrate 60, while a warpage below 0 (zero) indicates a concave warpage toward the substrate 50 and a convex warpage toward the substrate 60. T1:T2 was set to four levels: 1:2, 1:1.3, 1:1, and 1.5:1.

[0188] As shown in FIG. 43, when T1:T2 = 1:2, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and the amount of convex warp on the substrate 60 side was the largest among the four levels. When T1:T2 = 1:1.3, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and the amount of convex warp on the substrate 60 side became smaller than that when T1:T2 = 1:2. When T1:T2 = 1:1, it changed to a warp with a convex on the substrate 50 side and a concave on the substrate 60 side. When T1:T2 = 1.5:1, a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurred, and the amount of convex warp on the substrate 50 side was the largest among the four levels.

[0189] Thus, it became clear that when T1 < T2, a warp with a concave on the substrate 50 side and a convex on the substrate 60 side occurred, and when T1 ≧ T2, a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurred. That is, it became clear that by satisfying the relationship of T1 ≧ T2, the warp generated at high temperature can be controlled to be a warp with a convex on the substrate 50 side and a concave on the substrate 60 side. Also, it became clear that the larger T2 is with respect to T1, the larger the amount of convex warp on the substrate 60 side becomes, and the larger T1 is with respect to T2, the larger the amount of convex warp on the substrate 50 side becomes.

[0190] <Summary of the Third Embodiment> In this embodiment, the semiconductor device 20 satisfies the relationship of the above-described thickness T1 ≧ thickness T2. The thickness T1 on the side where the conductive spacer 70 is not provided between the semiconductor element 40 and the substrate 50 is equal to or greater than the thickness T2 on the side where the conductive spacer 70 is provided between the semiconductor element 40 and the substrate 60. Thereby, when the semiconductor element 40 operates (at high temperature), a warp with a convex on the substrate 50 side and a concave on the substrate 60 side occurs in the semiconductor device 20. Therefore, the facing distance between the semiconductor device 20 and the cooler 120 (heat exchange portion 121) on the substrate 50 side, which has a high contribution rate to heat dissipation, can be made narrower compared to a configuration that satisfies the relationship of thickness T1 < thickness T2. Since the facing distance becomes narrower, the thermal resistance between the semiconductor device 20 and the cooler 120 becomes smaller. Thereby, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20. In other words, the cooling efficiency of the semiconductor device 20 can be increased.

[0191] Specifically, the thickness of the heat conduction member 130 interposed between the semiconductor device 20 and the cooler 120 is thinner than in a configuration where the relationship of thickness T1 < thickness T2 is satisfied. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120, facilitating heat exchange between the semiconductor device 20 and the cooler 120. Therefore, the heat generated by the semiconductor element 40 can be efficiently released to the outside of the semiconductor device 20.

[0192] In this embodiment, the back surface metal body 53 is exposed from the sealing body 30. This improves heat dissipation compared to a configuration in which the back surface metal body 53 is covered by the sealing body 30. Similarly, the back surface metal body 63 is exposed from the sealing body 30. This improves heat dissipation compared to a configuration in which the back surface metal body 63 is covered by the sealing body 30.

[0193] <Modification> Although an example of a double-sided heat dissipation structure has been shown, this is not limiting. It is desirable for the semiconductor device 20 to efficiently dissipate heat mainly from the substrate 50 side. Therefore, the cooler 120 (heat exchange unit 121) may be disposed only on the substrate 50 side in the Z direction of the semiconductor device 20. Even in such a single-sided heat dissipation structure, by satisfying the relationship T1≧T2, a convex warp occurs toward the substrate 50 side at high temperatures. This reduces the thermal resistance between the semiconductor device 20 and the cooler 120. Therefore, the heat generated by the semiconductor element 40 can be efficiently dissipated.

[0194] Although an example has been shown in which both the back surface metal bodies 53 and 63 are exposed from the sealing body 30, the present invention is not limited to this. For example, a configuration in which only the back surface metal body 53 is exposed may also be used.

[0195] Although an example has been shown in which the semiconductor device 20 includes a semiconductor element 40H that configures the upper arm 9H and a semiconductor element 40 that configures the lower arm 9L, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40. The semiconductor device 20 may include the semiconductor element 40, a pair of substrates 50, 60 arranged to sandwich the semiconductor element 40, and a conductive spacer 70 interposed between the semiconductor element 40 and the substrates 60.

[0196] No particular mention has been made of the relationship between the thicknesses of the metal bodies 52, 53 in the substrate 50. For example, as shown in FIG. 44, the front surface metal body 52 may be thicker than the back surface metal body 53. The drain electrode 40D, which is the first main electrode of the semiconductor element 40, is joined to the front surface metal body 52. ​​The thermal resistance between the front surface metal body 52 and the semiconductor element 40 is small. By thickening the front surface metal body 52 closer to the semiconductor element 40, the heat generated by the semiconductor element 40 can be effectively diffused. In other words, the heat of the semiconductor element 40 can be efficiently dissipated. FIG. 44 is a cross-sectional view showing a modified example. FIG. 44 corresponds to FIG. 41.

[0197] 44, the front surface metal body 62 may be thicker than the back surface metal body 63. By making the front surface metal body 62 closer to the semiconductor element 40 thicker, the heat generated by the semiconductor element 40 can be diffused more effectively.

[0198] As described above, heat from a semiconductor element 40 having main electrodes on both sides is mainly conducted to the substrate 50, which has a lower thermal resistance. For this reason, as shown in FIG. 45, the front surface metal body 62 may be thinner than the back surface metal body 63. This allows the thickness of the substrate 60 to be reduced, thereby making it possible to downsize the size of the semiconductor device 20. Since thick metal bodies are no longer necessary, costs can also be reduced. FIG. 45 is a cross-sectional view showing a modified example. FIG. 45 corresponds to FIG. 44. In FIG. 45, the front surface metal body 52 is thicker than the back surface metal body 53, and the front surface metal body 62 is thinner than the back surface metal body 63. Therefore, it is possible to efficiently dissipate heat from the semiconductor element 40 while achieving downsizing and cost reduction.

[0199] The configuration described in this embodiment can be combined with any of the configurations described in the first embodiment, second embodiment, and modified examples.

[0200] (Fourth embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. To improve connection reliability, the substrate and the signal terminals may be configured to satisfy a predetermined positional relationship, as described in this embodiment.

[0201] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 46 and Fig. 47. Fig. 46 shows the periphery of a signal terminal 93 in the semiconductor device 20 of this embodiment. In Fig. 46, some elements of the semiconductor device 20 are omitted to show the positional relationship between the substrate 50 and the signal terminal 93. Fig. 47 is a cross-sectional view taken along line XLVII-XLVII in Fig. 46. In Fig. 46 and Fig. 47, the signal terminal 93L on the lower arm 9L side will be described as an example.

[0202] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 46, the semiconductor device 20 includes two semiconductor elements 40L. Each semiconductor element 40L has a drain electrode 40D, which is a first main electrode, on one surface, and a source electrode 40S, which is a second main electrode, and a signal pad 40P on the back surface. The semiconductor device 20 includes four signal terminals 93L. Each signal terminal 93L extends in the Y direction and protrudes to the outside from the side surface 30d of the sealing body 30. The four signal terminals 93L are arranged side by side in the X direction between the output terminals 92 in a plan view in the Z direction.

[0203] <Shape and arrangement of signal terminals> Next, the shape and arrangement of the signal terminals 93 will be described with reference to FIGS.

[0204] 46, each signal terminal 93L has an overlapping portion 930 that overlaps with the substrate 50 in a plan view, and a non-overlapping portion 931 that does not overlap with the substrate 50. The overlapping portion 930 faces the substrate 50 in the Z direction.

[0205] The overlapping portion 930 is a portion of the signal terminal 93L within a predetermined range from the end portion on the semiconductor element 40L side. The non-overlapping portion 931 is a portion excluding the overlapping portion 930. The overlapping portion 930 overlaps the insulating base material 51 of the substrate 50 to which the drain electrode 40D is electrically connected. The entire overlapping portion 930 overlaps the insulating base material 51. The overlapping portion 930 overlaps an exposed portion 510 of the insulating base material 51 that is exposed from the surface metal body 52. ​​In this way, the signal terminal 93L is extended onto the substrate 50. In other words, the signal terminal 93L is inserted and arranged up to a position where it overlaps the substrate 50 in a plan view.

[0206] Of the four signal terminals 93L, the overlapping portion 930 of two signal terminals 93L has a main portion 930a and a protruding portion 930b. The other two signal terminals 93L do not have a protruding portion 930b. The main portion 930a extends in the Y direction, which is the main extension direction of the signal terminal 93L. The protruding portion 930b is connected to the main portion 930a and protrudes from the main portion 930a. The protruding portion 930b extends in a different direction from the main portion 930a. The protruding portion 930b is sometimes referred to as a branch portion. The planar shape of the main portion 930a can be various shapes, such as a generally L-shaped, a generally Y-shaped, or a generally T-shaped. In the example shown in FIG. 46, one signal terminal 93L has a generally L-shaped planar shape, and the other signal terminal 93L has a generally T-shaped planar shape.

[0207] As described in the previous embodiment (see FIG. 11 ), the relay wiring 55 of the surface metal body 52 has a notch 550. The overlapping portion 930 of the signal terminal 93L overlaps the portion of the insulating base material 51 that is exposed through the notch 550. The four signal terminals 93L are arranged side by side in the X direction between the output terminals 92 in a plan view. Each signal terminal 93L has a tie bar mark 93a. As described in the previous embodiment (see FIG. 10 ), the tie bar mark 93a is a mark left on the side surface of the signal terminal 93L when the tie bar 94a of the lead frame 94 is cut off. The tie bar mark 93a is sometimes referred to as a cut mark. Each signal terminal 93L has the tie bar mark 93a on both side surfaces in the X direction. The tie bar mark 93a is provided in the non-overlapping portion 931 at a position outside the sealing body 30.

[0208] As shown in FIG. 47, each signal terminal 93L has a joint portion 93b, a tip portion 93c, a bent portion 93d, and an extension portion 93e. The joint portion 93b is a portion to which a bonding wire 110, which is a connecting member, is joined. The joint portion 93b preferably includes a portion that is approximately parallel to the XY plane. The joint portion 93b is the portion of the signal terminal 93L that is closest to the surface of the insulating base material 51 (exposed portion 510). In this embodiment, the joint portion 93b is floating above the surface of the insulating base material 51. The joint portion 93b does not contact the insulating base material 51, and the sealing body 30 fills the gap between the lower surface of the joint portion 93b and the surface of the insulating base material 51. The bonding wire 110 electrically connects the signal terminal 93L to a pad 40P formed on the same surface as the source electrode 40S.

[0209] The tip portion 93c is located closer to the tip of the joint portion 93b, i.e., closer to the semiconductor element 40 (40L). The tip portion 93c is located higher than the joint portion 93b, i.e., farther from the surface of the insulating base material 51 in the Z direction. The tip portion 93c rises upward as it moves away from the joint portion 93b. The tip portion 93c has an R-shape in the ZY cross section. The bent portion 93d is located between the joint portion 93b and the extended portion 93e, which is located rearward of the joint portion 93b. The bent portion 93d is bent so that the extended portion 93e is located higher than the joint portion 93b, i.e., farther from the surface of the insulating base material 51. Due to the bending process, the bent portion 93d has a smaller cross-sectional area than the other portions of the signal terminal 93, specifically the joint portion 93b, the tip portion 93c, and the extended portion 93e. In other words, the bent portion 93d is thinner. The extended portion 93e is located rearward of the joint portion 93b. The extension portion 93e extends in the Y direction and is disposed across the inside and outside of the sealing body 30.

[0210] At least a portion of the joint portion 93b, the tip portion 93c, and the bent portion 93d are included in the overlapping portion 930. At least a portion of the extended portion 93e is included in the non-overlapping portion 931. In this embodiment, the entire extended portion 93e is included in the non-overlapping portion 931. Each signal terminal 93L is formed by press punching. In the signal terminal 93L, the surface facing the insulating substrate 51 is a pressed round surface 93f, and the back side of the facing surface is a burr surface 93g on which burrs are generated by punching. The configuration other than the above is the same as the configuration described in the first embodiment.

[0211] <Bonding wire connection method> Next, a method of connecting the signal terminal 93 having the above-described structure to the bonding wire 110 will be described with reference to Fig. 48. Fig. 48 is a diagram illustrating wire bonding. Reference numeral 111 in Fig. 48 denotes a jig that holds down the signal terminal 93L. Reference numeral 112 denotes a tool for ultrasonic bonding. The tool 112 is sometimes referred to as an ultrasonic bonding device. The dashed dotted line in Fig. 48 indicates the position of the signal terminal 93L that has been bent by being pressed by the jig 111.

[0212] 48, first, the signal terminal 93L is positioned so that the overlapping portion 930 overlaps the insulating base material 51, and the wire 110a is set in the portion to be joined. Then, pressure is applied in the Z direction by a jig 111 to elastically deform the signal terminal 93L, and the overlapping portion 930 is brought into contact with the surface of the insulating base material 51. The jig 111 presses the overlapping portion 930 of the signal terminal 93L or the vicinity thereof.

[0213] Then, with the signal terminal 93L in contact with the insulating base material 51, ultrasonic bonding is performed using the tool 112. Because the signal terminal 93L is received by the insulating base material 51, a separate receiving jig is not required. When ultrasonic bonding is completed and the tool 112 and jig 111 are released from the signal terminal 93L, the signal terminal 93L is released from its elastically deformed state and returns to the position it was in before pressure was applied. The signal terminal 93L is part of the lead frame 94. Because the signal terminal 93L is supported by the tie bars 94a on the outer peripheral frame 94b, it returns to its original position when pressure is released.

[0214] The above description has been given taking the signal terminal 93L as an example. However, the above configuration may also be applied to the signal terminal 93H on the upper arm 9H side. Both the signal terminals 93H and 93L may have the above configuration. In the configuration described in the previous embodiment (see FIG. 11 ), the signal terminals 93H and 93L each overlap an exposed portion of the insulating base material 51. The P wiring 54 of the front surface metal body 52 has a notch 540, and the signal terminal 93H overlaps the surface of the insulating base material 51 exposed from the notch 540.

[0215] <Summary of the Fourth Embodiment> In this embodiment, the signal terminal 93 (93L) overlaps the exposed portion 510 of the insulating base material 51. However, the signal terminal 93 is not bonded to the exposed portion 510. In other words, the signal terminal 93 is not fixed to the insulating base material 51, or to the substrate 50. This allows the signal terminal 93 to absorb dimensional variations within the tolerances of the elements constituting the semiconductor device 20, as well as assembly variations when assembling the elements. Therefore, when molding the sealing body 30, stress concentration at the electrical connection portion (joint) of the signal terminal 93 with the semiconductor element 40 can be suppressed. As a result, a semiconductor device 20 with high connection reliability can be provided.

[0216] In this embodiment, the signal terminals 93 are inserted and arranged up to a position where they overlap the substrate 50, that is, onto the substrate 50. By adopting such an arrangement, the signal terminals 93 are closer to the pads 40P of the semiconductor element 40 (40L) in the Y direction. Therefore, the length of the bonding wires 110, which are connecting members, can be made shorter than in a configuration in which the signal terminals 93 are arranged only in positions that do not overlap the substrate 50. Because the length of the bonding wires 110 can be made shorter, it is possible to prevent wire sweep, short circuits due to wire sweep, wire breakage, and the like, when molding the encapsulant 30 by a transfer molding method or the like.

[0217] In this embodiment, the overlapping portion 930 of the signal terminal 93 is floating above the surface of the exposed portion 510 of the insulating base material 51. The sealing body 30 is interposed between the lower surface of the overlapping portion 930 and the surface of the exposed portion 510. The sealing body 30 is also interposed between the joint portion 93b and the exposed portion 510. This makes it possible to absorb large manufacturing variations in the plate thickness direction. Furthermore, because the signal terminal 93 is located above the insulating base material 51, it is easy to ensure an insulating distance from the back surface metal body 53.

[0218] In this embodiment, the surface metal body 52 has a notch 550 (540). The notch 550 opens at an end in the Y direction, which is a direction perpendicular to the Z direction. The overlapping portion 930 of the signal terminal 93 overlaps the surface of the exposed portion 510 exposed through the notch 550. By providing the notch 550 in the surface metal body 52 of the substrate 50 in this way, it is possible to ensure an insulation distance between the surface metal body 52 and the signal terminal 93 while suppressing an increase in the size of the substrate 50.

[0219] In this embodiment, the non-overlapping portion 931 of the signal terminal 93 has a tie bar mark 93a. As described above, the signal terminal 93L is part of the lead frame 94 and is supported by the tie bar 94a on the outer peripheral frame 94b. Therefore, the signal terminal 93 is bent by applying pressure and brought into contact with the exposed portion 510 of the insulating base material 51, and in this contact state, the bonding wire 110 can be joined by ultrasonic bonding. Then, after joining is completed, the pressure is released and the signal terminal 93L returns to its original position.

[0220] In this embodiment, the signal terminal 93 has a bent portion 93d between the joint portion 93b and the extension portion 93e. Due to the bent portion 93d, the extension portion 93e is positioned farther from the exposed portion 510 (insulating base material 51) in the Z direction than the joint portion 93b. By having the bent portion 93d in this manner, it is possible to ensure an insulation distance between the signal terminal 93 and the back surface metal body 53 while suppressing an increase in the physical size in the Z direction.

[0221] In this embodiment, the signal terminal 93 has a tip portion 93c. The tip portion 93c is farther from the exposed portion 510 (insulating base material 51) in the Z direction than the joint portion 93b. This makes it possible to prevent the tip of the signal terminal 93 from scratching the insulating base material 51 during the above-mentioned joining (ultrasonic joining), etc. In other words, it is possible to prevent a decrease in insulating performance. Particularly in this embodiment, the tip portion 93c is raised upward as it is farther away from the joint portion 93b, making it more difficult for the tip portion 93c to come into contact with the insulating base material 51. Furthermore, because the tip portion 93c has an R-shape in the ZY cross section, it is possible to prevent the insulating base material 51 from being scratched even if it does come into contact.

[0222] If the opposing surface is a burred surface 93g, the insulating base material 51 may be scratched, resulting in a deterioration in insulating performance. In this embodiment, the signal terminal 93 is configured so that the surface opposing the exposed portion 510 is a pressed round surface 93f and the back side of the opposing surface is a burred surface 93g. This makes it possible to prevent the insulating performance of the insulating base material 51 from being deteriorated.

[0223] <Modification> The non-bonding configuration between the signal terminal 93 and the exposed portion 510 is not limited to the above example. For example, in FIG. 49, the overlapping portion 930 of the signal terminal 93 is floating above the insulating base material 51, with a slight gap between it and the surface of the exposed portion 510 that is small enough to prevent the sealing body from entering. The sealing body 30 has a gap 31 between the underside of the overlapping portion 930 and the surface of the exposed portion 510. The signal terminal 93 is not fixed to the insulating base material 51 (exposed portion 510). Therefore, the same effect as the configuration shown in FIG. 47 can be achieved. FIG. 49 is a cross-sectional view showing a modified example, and corresponds to FIG. 47.

[0224] In FIG. 50, the overlapping portion 930 of the signal terminal 93 is in contact with the surface of the exposed portion 510. The signal terminal 93 is in contact with the insulating base material 51 (exposed portion 510) but is not fixed thereto. Therefore, the same effect as the configuration shown in FIG. 47 can be achieved. FIG. 50 is a cross-sectional view showing a modified example and corresponds to FIG. 47. Note that a configuration may be adopted in which part of the lower surface of the joint portion 93b is in contact with the insulating base material 51 and the other part is not in contact therewith.

[0225] In the example shown in FIG. 47 , the substrate 60 is positioned so as not to overlap the signal terminal 93 in a plan view. In other words, the substrate 60 is not positioned above the signal terminal 93. Adopting such an arrangement allows the size of the substrate 60 to be reduced. Furthermore, it is easier to ensure an insulating distance between the surface metal body 62 and the signal terminal 93. However, the positional relationship between the signal terminal 93 and the substrate 60 is not limited to the example shown in FIG. 47 . For example, as shown in FIG. 51 , the overlapping portion 930 of the signal terminal 93 also overlaps with the substrate 60. The surface metal body 62 of the substrate 60 overlaps the overlapping portion 930 and the exposed portion 510 of the insulating base material 51 in a plan view. This improves heat dissipation. FIG. 51 is a cross-sectional view showing a modified example, corresponding to FIG. 47 .

[0226] 52, unlike FIG. 51, the front surface metal body 62 is patterned so as not to overlap the overlapping portion 930 of the signal terminal 93. The insulating base material 61 and the back surface metal body 63 are located above the overlapping portion 930. By making the front surface metal body 62 smaller, it becomes easier to ensure an insulating distance between the front surface metal body 62 and the signal terminal 93. Since the back surface metal body 63 is large, heat dissipation can be improved. FIG. 52 is a cross-sectional view showing a modified example and corresponds to FIG. 47.

[0227] An example has been shown in which the length of the bonding wire 110 (connecting member) can be shortened by inserting the signal terminal 93 into the substrate 50. Alternatively, the length of the bonding wire 110 may be shortened by using an interconnection substrate 150 shown in FIGS. 53 to 55. FIG. 53 is a plan view showing a modified example and corresponds to FIG. 46. In FIG. 53, some elements of the semiconductor device 20 are omitted to show the positional relationship between the substrate 50, the signal terminal 93, and the interconnection substrate 150. FIG. 54 is a cross-sectional view showing the interconnection substrate. FIG. 55 is a cross-sectional view taken along the line LV-LV in FIG. 53. Here, the interconnection wiring 55 and the signal terminal 93L are shown as an example, but a similar configuration can also be adopted for the P wiring 54 and the signal terminal 93H.

[0228] The semiconductor device 20 further includes a relay substrate 150. As shown in FIGS. 53 and 55, the relay substrate 150 is disposed on the surface metal body 52 (relay wiring 55) of the substrate 50. As shown in FIG. 54, the relay substrate 150 has an insulating base material 151 and a conductor portion 152 disposed on the insulating base material 151. A portion of the conductor portion 152 provides a wiring function. The relay substrate 150 is sometimes referred to as a printed circuit board or a wiring board.

[0229] The conductor portion 152 has lands 152a and 152b. The lands 152a and 152b are exposed on one surface of the relay substrate 150. Specifically, the lands 152a and 152b are exposed from a solder resist 153 provided on one surface 151a of the insulating base material 151. The land 152a is electrically connected to the pad 40P via a bonding wire 110. The signal terminal 93 overlaps with the substrate 50 in a plan view. The signal terminal 93 is connected to the land 152b.

[0230] The conductor portion 152 has wiring 152c and a via conductor 152d in addition to the lands 152a and 152b. At least a portion of the wiring 152c is an inner layer wiring disposed inside the insulating substrate 151. The land 152a and the land 152b are electrically connected via the wiring 152c and the via conductor 152d. The multiple lands 152a include two lands 152a individually connected to pads 40P for the gate electrodes of two semiconductor elements 40. The two lands 152a for the gate electrodes are electrically connected to one land 152b for the gate electrode via the wiring 152c and the via conductor 152d.

[0231] In this way, by using the relay substrate 150, the connection target (land 152a) of the bonding wire 110 can be brought closer to the pad 40P. This allows the length of the bonding wire 110 that electrically connects the pad 40P and the signal terminal 93 to be shortened. Furthermore, the wiring 152c can be routed freely within the relay substrate 150. This prevents the bonding wires 110 from crossing each other in a configuration in which the semiconductor elements 40 are connected in parallel. Therefore, contact between the wires can be suppressed when the sealing body 30 is formed. Furthermore, by using fine wiring technology for printed circuit boards, it is possible to achieve a size reduction similar to that of the configuration shown in FIG. 47.

[0232] The conductor portion 152 further has a fixing land 152e. The fixing land 152e is a land for fixing the relay substrate 150 to the substrate 50. The fixing land 152e does not provide an electrical connection function, i.e., a wiring function. The fixing land 152e is disposed on the back surface 151b of the insulating base material 151. The fixing land 152e (relay substrate 150) is bonded to the front surface metal body 52 via a bonding material 154. The bonding material 154 may be, for example, solder.

[0233] In this way, since the relay substrate 150 is fixed to the front surface metal body 52, wire bonding can be performed stably. Solder containing Ni balls may be used as the bonding material 154. In this case, the Ni balls can control the thickness of the bonding material 154. Also, tilting of the relay substrate 150 can be suppressed.

[0234] The wiring function provided by the conductor portion 152 is electrically separated from the surface metal body 52 by the insulating base material 151. For example, the insulating base material 151 may have, in the Z direction, a non-arrangement region 151c where the conductor portion 152 is not arranged and an arrangement region 151d where the conductor portion 152 is arranged. In the Z direction, the non-arrangement region 151c is provided in the center of the insulating base material 151, and the arrangement region 151d is provided on the surface layer of both sides. The non-arrangement region 151c is sometimes referred to as a core layer. In this way, by having the non-arrangement region 151c in the insulating base material 151, the conductor portion 152 that provides the wiring function and is arranged on the one surface 151a side can be electrically separated from the fixing land 152e and ultimately from the surface metal body 52.

[0235] The solder resist 153 has low adhesion to the sealant 30. Peeling of the sealant 30 due to thermal stress begins at the outer circumferential edge of the relay substrate 150. For example, the insulating base material 151 may have an exposed portion 151e exposed from the solder resist 153. The exposed portion 151e is provided on the outer circumferential edge of one surface 151a of the insulating base material 151. The insulating base material 151 has higher adhesion to the sealant 30 than the solder resist 153. At the exposed portion 151e, the sealant 30 is in close contact with the relay substrate 150. This makes it possible to prevent the sealant 30 from peeling off from the relay substrate 150. Because the sealant 30 is in close contact at the outer circumferential edge, the conductor portions 152, such as the lands 152a and 152b, exposed from the solder resist 153 can be protected.

[0236] As shown in FIG. 55, the signal terminal 93 (93L) has a first extension portion 93h, a second extension portion 93i, and a bent portion 93j. The first extension portion 93h and the second extension portion 93i extend in the Y direction. The first extension portion 93h is disposed inside the sealing body 30. The second extension portion 93i is disposed both inside and outside the sealing body 30. The bent portion 93j is provided between the first extension portion 93h and the second extension portion 93i. The first extension portion 93h is a portion closer to the tip end than the bent portion 93j, and the second extension portion 93i is a portion closer to the rear end than the bent portion 93j.

[0237] The signal terminal 93 may have a protrusion 93k. The protrusion 93k is provided near the tip of the signal terminal 93. The protrusion 93k protrudes from the first extension 93h toward the land 152b in the Z direction. The protrusion 93k is joined to the land 152b. In the signal terminal 93, the tip of the first extension 93h and the protrusion 93k overlap with the land 152b in a plan view in the Z direction. The portion where the tip of the first extension 93h and the protrusion 93k join is a thick portion, and the other portions of the signal terminal 93 are thin portions. By providing the protrusion 93k in this manner, the signal terminal 93 (first extension 93h) is spaced away from the surface metal body 52, making it easier to ensure an insulation distance between the signal terminal 93 (first extension 93h) and the surface metal body 52.

[0238] FIG. 56 shows another example different from FIG. 54. FIG. 56 corresponds to FIG. 54. In FIG. 56, relay board 150 is fixed to exposed portion 510 of insulating base material 51. In this case, the thickness of bonding material 154 and relay board 150 ensures an insulation distance between signal terminal 93 and rear surface metal body 53. If the above-mentioned solder containing Ni balls is used as bonding material 154, a predetermined thickness can be ensured, making it easier to ensure an insulation distance. In addition, tilting of relay board 150 can be suppressed.

[0239] The surface metal body 52 (relay wiring 55) has a notch 550 as shown in FIG. 46 , for example, to expose the insulating base material 51. For example, the surface metal body 52 may have a chamfered portion 554. The chamfered portion 554 is provided at least on a surface of the end face defining the notch 550 where an imaginary line connecting the semiconductor element 40 and the relay substrate 150 intersects. The chamfered portion 554 is provided on the upper end of the end face. This makes it possible to ensure an insulating distance between the bonding wire 110 and the surface metal body 52.

[0240] An example has been shown in which the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S. That is, an example of a semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, this is not a limitation. The present invention is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only a substrate 50 to which the drain electrode 40D (first main electrode) is connected. An example has been shown in which both rear surface metal bodies 53, 63 are exposed from the sealing body 30, but this is not a limitation.

[0241] Although an example has been shown in which the semiconductor device 20 includes the semiconductor element 40H that configures the upper arm 9H and the semiconductor element 40 that configures the lower arm 9L, the present invention is not limited to this. The semiconductor device 20 may include only the semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0242] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, and third embodiments and the modified examples.

[0243] (Fifth embodiment) This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to ensure insulation reliability while reducing the overall size, the connection between the metal member and the surface metal body via the bonding material may have a predetermined structure, as described in this embodiment.

[0244] <Semiconductor device> First, the semiconductor device 20 of this embodiment will be described with reference to Fig. 57. Fig. 57 corresponds to Fig. 5.

[0245] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 57, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is connected to a drain electrode 40D, which is a main electrode of the semiconductor element 40. The surface metal body 52 is connected to a P terminal 91P, which is a main terminal, and an output terminal 92 via a bonding material 104. The surface metal body 62 of the substrate 60 is electrically connected to a source electrode 40S, which is a main electrode of the semiconductor element 40. The surface metal body 62 is connected to an N terminal 91N (not shown), which is a main terminal, via a bonding material 104. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, portions of the main terminals, and the bonding material 104.

[0246] <Main terminal joint structure> Next, the joining structure of the main terminal will be described with reference to Figs. 57 to 60. Fig. 58 is a plan view of the periphery of the output terminal 92 of Fig. 57 as viewed from the LVIII direction. In Fig. 58, some areas are hatched for clarity. Fig. 59 is an enlarged view of the area LVIX indicated by the dashed line in Fig. 57. Fig. 60 is a view showing the state in which the joining material 104 has been removed from Fig. 59. For convenience, the sealing body 30 is omitted from Figs. 59 and 60.

[0247] As shown in FIG. 57, the joining structure of the P terminal 91P, which is a main terminal, and the output terminal 92, with the substrate 50 differs from the structure described in the preceding embodiment (see FIG. 5). Although not shown, the joining structure of the N terminal 91N, which is a main terminal, is also different. The other structures are the same as those described in the preceding embodiment. The following description will be given using the output terminal 92 as an example. The joining material 104 wets and spreads over the metal surface during joining. As an example, the joining material 104 is solder.

[0248] As shown in Fig. 57, the substrate 50 has ends 50c and 50d in the Y direction. End 50c is the end on the side surface 30c side of the sealing body 30, and end 50d is the end on the side surface 30d side. The output terminal 92 extends in the Y direction, straddling end 50d of the substrate 50. In a plan view in the Z direction, a portion of the output terminal 92 overlaps with the surface metal body 52 (relay wiring 55), and another portion does not. As shown in Figs. 58 to 60, the output terminal 92 has an opposing surface 920 and an accommodating portion 921.

[0249] The facing surface 920 is a portion of the lower surface of the output terminal 92 that faces the surface metal body 52 (relay wiring 55) of the substrate 50 in the Z direction. Macroscopically, the facing surface 920 is a flat surface, and ideally, the entire surface is in contact with the upper surface 52a of the surface metal body 52. ​​Microscopically, the facing surface 920 has minute irregularities on its surface, and at least a portion is in contact with the upper surface 52a. The facing surface 920 is sometimes referred to as a metal touch surface. In a plan view, the facing surface 920 is a portion that extends within a predetermined range in the Y direction from a position that overlaps with the end 52b of the surface metal body 52. ​​The end 52b is an end face (side surface) on the side of the side surface 30d of the sealing body 30 in the Y direction, and is continuous with the upper surface 52a. The end 52b forms a part of the end 50d. The facing surface 920 is substantially rectangular in plan view.

[0250] The accommodation portion 921 is provided adjacent to the facing surface 920 and provides a space for accommodating the bonding material 104. For example, the accommodation portion 921 is a recess recessed relative to the facing surface 920 in a direction away from the upper surface 52a. The recessed accommodation portion 921 is a surface including a Z-direction component and has a side surface 921a continuing to the facing surface 920 and a bottom surface 921b continuing to the side surface 921a. The side surface 921a is, for example, a surface approximately parallel to the Z direction. The accommodation portion 921 opens to a tip surface 922, which is a side surface on the leading side of the output terminal 92 in the Y direction. The accommodation portion 921 opens to side surfaces 923 and 924 on both sides of the output terminal 92 in the X direction. The accommodation portion 921 is provided within a predetermined range from the tip surface 922 of the output terminal 92 in the Y direction. The accommodation portion 921 has an approximately rectangular planar shape. The accommodation portion 921 is provided in the Y direction aligned with the X direction.

[0251] The output terminal 92 accommodates the bonding material 104 in the accommodation portion 921 with the opposing surface 920 in contact with the front surface metal body 52. ​​The bonding material 104 may be disposed only within the accommodation portion 921, or as shown in FIG. 59 , a portion of the bonding material 104 may be disposed outside the accommodation portion 921. In FIG. 59 , the bonding material 104 forms a fillet with respect to the tip surface 922. The output terminal 92 is connected (joined) to the front surface metal body 52 via the bonding material 104 disposed in the accommodation portion 921.

[0252] <Main terminal joining method> The bonding structure between the output terminal 92 and the surface metal body 52 is formed, for example, as follows. With the bonding material 104 (solder) placed in the accommodation portion 921, the upper portion of the facing surface 920 of the output terminal 92 is pressed in the Z direction toward the substrate 50 so that the facing surface 920 is in strong contact with the upper surface 52a. Reflow is performed with the facing surface 920 in strong contact with the upper surface 52a. For this reason, during reflow, the bonding material 104 does not wet and spread toward the facing surface 920, or if it does, it only wets and spreads to the extent that it fills in the minute concaves and convexes on the surface of the facing surface 920.

[0253] <Summary of the Fifth Embodiment> In this embodiment, the facing surface 920 of the output terminal 92, which is a metal member, comes into contact (metal touch) with the upper surface 52a of the front surface metal body 52. ​​This makes it possible to prevent the bonding material 104 from overflowing from the accommodation portion 921 toward the facing surface 920. This prevents the bonding material 104 from spreading in unintended directions, ensuring insulation reliability. Furthermore, the output terminal 92, which is a single member, has both the accommodation portion 921 and the facing surface 920. As a result, it is possible to provide a semiconductor device 20 that can achieve both insulation reliability and a compact size.

[0254] In a configuration including a substrate 50, when the bonding material 104 spreads over the end 52b (end face) of the front-surface metal body 52 and thus over the insulating base material 51, a portion having the same potential as the front-surface metal body 52 spreads, thereby reducing the distance to the back-surface metal body 53. There is a risk that the bonding material 104 may come into contact with the back-surface metal body 53. In this embodiment, the facing surface 920 is located closer to the end 50d of the substrate 50, i.e., the end 52b of the front-surface metal body 52, than the housing portion 921. By positioning the facing surface 920 closer to the end 52b, it is possible to prevent the bonding material 104 from spreading over the surface of the output terminal 92 and / or the front-surface metal body 52 and reaching the end 52b and thus the insulating base material 51. This improves insulation reliability without increasing the overall size.

[0255] As described above, the metal member having an opposing surface and a housing portion can also be applied to other main terminals, such as the P terminal 91P and the N terminal 91N. The P terminal 91P is connected to the front surface metal body 52 (P wiring 54) of the substrate 50 via the bonding material 104. The opposing surface of the P terminal 91P comes into contact with the front surface metal body 52, thereby preventing the bonding material 104 from overflowing from the housing portion of the P terminal 91P toward the opposing surface. As shown in FIG. 57, providing the opposing surface on the end portion 50c side of the substrate 50 prevents the bonding material 104 from wetting and spreading onto the end portion of the front surface metal body 52 and the insulating base material 51.

[0256] The N terminal 91N is connected to the front surface metal body 62 (N wiring 64) of the substrate 60 via a bonding material 104. The opposing surface of the N terminal 91N comes into contact with the front surface metal body 62, thereby preventing the bonding material 104 from overflowing from the accommodation portion of the N terminal 91N to the opposing surface side. Furthermore, by providing the opposing surface on the side of the end 60c of the substrate 60 shown in FIG. 57, the bonding material 104 can be prevented from spreading onto the end of the front surface metal body 62 and the insulating base material 61. The end 60c is the end face (side face) on the side of the side surface 30c of the sealing body 30 in the Y direction.

[0257] <Modification> The arrangement of the opposing surface 920 and the accommodating portion 921 is not limited to the example described above. For example, the configurations shown in Figs. 61 and 62 may be adopted. Fig. 61 is a plan view showing a modified example and corresponds to Fig. 58. Fig. 62 is a plan view seen from the LXII direction shown in Fig. 61. In this example, the accommodating portion 921 does not open to the side surfaces 923 and 924, but only to the tip surface 922. The accommodating portion 921 has an opening 921c in the tip surface 922, which is a side surface.

[0258] The opposing surface 920 has a first opposing portion 920a and a second opposing portion 920b. The first opposing portion 920a is provided on the opposite side of the accommodation portion 921 from the opening 921c. The first opposing portion 920a is adjacent to the accommodation portion 921 in the Y direction, which is the extension direction of the output terminal 92. The second opposing portion 920b is adjacent to the accommodation portion in the X direction. In the example shown in FIGS. 61 and 62, the opposing surface 920 has a pair of second opposing portions 920b. The pair of second opposing portions 920b sandwich the accommodation portion 921 in the X direction. The opposing surface 920 has a substantially U-shaped planar shape. Since the opposing surfaces 920 are arranged on three sides with respect to the accommodation portion 921, the overflow direction of the bonding material 104 from the accommodation portion 921 can be limited to one direction toward the opening 921c. This further improves insulation reliability.

[0259] The opposing surface 920 may have only one second opposing portion 920b. In this case, the opposing surface 920 has a generally L-shaped planar shape. Since the opposing surface 920 is disposed on two sides of the accommodation portion 921, the direction in which the bonding material 104 overflows from the accommodation portion 921 can be restricted compared to the arrangement shown in FIG. 58. This can improve insulation reliability.

[0260] Although an example has been shown in which the accommodation portion 921 opens on a side surface of the output terminal 92, this is not limiting. Furthermore, the planar shape of the accommodation portion 921 is not limited to a substantially rectangular shape. For example, as shown in FIG. 63, an accommodation portion 921 without an opening on a side surface may be provided. FIG. 63 is a plan view showing a modified example and corresponds to FIG. 58. In FIG. 63, the accommodation portion 921 has a substantially circular planar shape. The accommodation portion 921 is a hole that opens on the lower surface of the output terminal 92. The accommodation portion 921 shown in FIG. 63 is a blind hole. The blind hole accommodation portion 921 has a side surface 921a and a bottom surface 921b that are continuous with the opposing surface 920, similar to the accommodation portion 921 described above. Alternatively, a through hole that opens on the upper surface of the output terminal 92 may be employed. The accommodation portion 921 that is a through hole does not have a bottom surface 921b but has a side surface 921a.

[0261] The metal member having an opposing surface and a housing portion is not limited to a main terminal. For example, as shown in Figures 64 and 65, in a semiconductor device 20 constituting an upper and lower arm circuit 9, a joint portion 81 may be provided with an opposing surface and a housing portion. Figure 64 is a cross-sectional view showing a modified example and corresponds to Figure 57. Figure 65 is an enlarged view of the area LXV indicated by the dashed line in Figure 64. For convenience, the sealing body 30 is omitted from Figure 65.

[0262] As described in the preceding embodiment, the semiconductor device 20 includes a semiconductor element 40H, which is a first semiconductor element constituting the upper arm 9H, and a semiconductor element 40L, which is a second semiconductor element constituting the lower arm 9L. The joint portion 81 electrically connects the source electrode 40S of the semiconductor element 40H to the drain electrode 40D of the semiconductor element 40L. The joint portion 81 is a metal pillar extending in the Z direction. An end portion 81a of the joint portion 81 is connected to a relay wiring 55, which is a first wiring of the substrate 50, via a bonding material 103. An end portion 81b opposite to the end portion 81a is connected to a relay wiring 65, which is a third wiring of the substrate 60, via the bonding material 103. The surface metal body 52 includes a P wiring 54, which is a second wiring, provided with a predetermined distance from the relay wiring 55. The surface metal body 62 includes an N wiring 64, which is a fourth wiring, provided with a predetermined distance from the relay wiring 65.

[0263] In the example shown in Figures 64 and 65, an opposing surface 810 and a storage portion 811 are provided at each of the end portions 81a, 81b of the joint portion 81. The configurations of the opposing surface 810 and the storage portion 811 are similar to those of the opposing surface 920 and the storage portion 921 described above. At the end portion 81a, the opposing surface 810 faces the upper surface 52a of the surface metal body 52 (relay wiring 55). The opposing surface 810 is in contact with the upper surface 52a. The storage portion 811 is a recess that is recessed relative to the opposing surface 810. The storage portion 811 has a side surface 811a that is continuous with the opposing surface 810, and a bottom surface 811b. The storage portion 811 stores the bonding material 103.

[0264] The opposing surface 810 and the accommodating portion 811 are arranged side by side in the Y direction. The opposing surface 810 is provided on the side of the wiring gap 52G that separates the relay wiring 55 and the P wiring 54, that is, at a position close to the P wiring 54, which is a wiring separate from the relay wiring 55 to which the joint portion 81 is connected. The accommodating portion 811 opens to a side surface 812 of the joint portion 81 in the Y direction, but does not open to a side surface 813 opposite the side surface 812. The accommodating portion 811 may open only to the side surface 812, or may open to three side surfaces including two side surfaces adjacent to the side surface 812.

[0265] In this way, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 52. ​​This makes it possible to prevent the bonding material 103 from overflowing from the accommodation portion 811 to the opposing surface 810. Therefore, it is possible to provide a semiconductor device 20 that can achieve both insulation reliability and a compact size.

[0266] Furthermore, when the bonding material 103 spreads into the inter-wire gap 52G of the front surface metal body 52, the portion having the same potential as the relay wiring 55 expands, and the distance to the P wiring 54 decreases. There is a risk that the bonding material 103 may come into contact with the P wiring 54. In contrast, in the example described above, the opposing surface 810 is located closer to the P wiring 54, i.e., the inter-wire gap 52G, than the housing portion 811. This prevents the bonding material 103 from reaching the inter-wire gap 52G. Therefore, insulation reliability can be improved without increasing the physical size.

[0267] The configuration of the end 81b is the same as that of the end 81a. In the end 81b, the opposing surface 810 faces the upper surface 62a of the surface metal body 62 (relay wiring 65). The opposing surface 810 is in contact with the upper surface 52a. The accommodating portion 811 is a recess. The accommodating portion 811 accommodates the bonding material 103. The opposing surface 810 and the accommodating portion 811 are arranged side by side in the Y direction. The opposing surface 810 is arranged on the side of the wiring gap 62G separating the relay wiring 65 and the N wiring 64, that is, in a position close to the N wiring 64, which is a wiring separate from the relay wiring 65 to which the joint portion 81 is connected. The accommodating portion 811 is open to a side surface 813 of the joint portion 81 in the Y direction, but is not open to a side surface 812. The accommodating portion 811 may be open only to the side surface 813, or may be open to three side surfaces including two side surfaces adjacent to the side surface 813.

[0268] In this way, the opposing surface 810 of the joint portion 81 comes into contact (metal touch) with the surface metal body 62. This makes it possible to prevent the bonding material 103 from overflowing from the accommodation portion 811 toward the opposing surface 810. Therefore, it is possible to provide a semiconductor device 20 that can achieve both insulation reliability and a compact size. Furthermore, the opposing surface 810 is located closer to the N wiring 64, i.e., the inter-wiring gap 62G, than the accommodation portion 811. This makes it possible to prevent the bonding material 103 from reaching the inter-wiring gap 62G. Therefore, it is possible to improve insulation reliability without increasing the size.

[0269] In the above example, overflow of the bonding material was suppressed by contact of the surface metal body with the opposing surfaces of the metal members. The function of suppressing overflow may be enhanced by further adding a rough oxide film formed by laser irradiation to this configuration. An example is shown in FIGS. 66 and 67. FIG. 66 is a cross-sectional view corresponding to FIG. 65, and for convenience, the sealing body 30 is omitted. FIG. 67 is an enlarged view of the area LXVII indicated by the dashed line in FIG. 66, showing only the surface metal body 52.

[0270] In the example shown in FIG. 66, uneven oxide films 520, 620 are provided on the surface metal bodies 52, 62, respectively, corresponding to the joint portion 81. The uneven oxide film 520 will be described below as an example. As shown in FIG. 67, the surface metal body 52 has a base material 521, and a metal film 522 and an uneven oxide film 520 provided on the surface of the base material 521. The base material 521 forms the main part of the surface metal body 52. ​​The base material 521 is formed using, for example, a Cu-based material. The metal film 522 is formed containing a material that has higher wettability with solder than the base material 521. The metal film 522 is formed over the entire upper surface 52a. The metal film 522 of this embodiment is formed over the entire surface of the base material 521. The uneven oxide film 520 is formed locally on the upper surface 52a.

[0271] The uneven oxide film 520 is locally formed on the metal film 522 on the upper surface 52a by irradiating the metal film 522 with laser light. The metal film 522 has an underlayer film mainly composed of Ni (nickel) and an overlayer film mainly composed of Au (gold). In this embodiment, an electroless Ni plating film containing P (phosphorus) is used as the underlayer film. When the bonding material 103 is solder, the overlayer film (Au) of the metal film 522 exposed from the uneven oxide film 520 in the portion that comes into contact with the bonding material 103 diffuses into the solder during reflow. The overlayer film (Au) of the metal film 522 in the portion where the uneven oxide film 520 is to be formed is removed by irradiation with laser light when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film mainly composed of Ni. For example, of the components that make up the uneven oxide film 520, 80% is NI2O3, 10% is NiO, and 10% is Ni.

[0272] The recesses 523 on the surface of the metal film 522 are formed by irradiation with pulsed laser light. One recess 523 is formed for each pulse. The uneven oxide film 520 is formed when the surface portion of the metal film 522 is melted, vaporized, and deposited by irradiation with laser light. The uneven oxide film 520 is an oxide film derived from the metal film 522. The uneven oxide film 520 is a film of oxide of the metal (Ni), which is the main component of the metal film 522. The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the recesses 523. The unevenness is formed on the surface of the uneven oxide film 520 at a pitch finer than the width of the recesses 523. In other words, very fine unevenness (roughened portions) is formed.

[0273] Such an uneven oxide film 520 can be formed by the following process. First, a pulsed laser beam is irradiated onto the upper surface 52a of the surface metal body 52, which has a metal film 522 formed on a base material 521, to melt and evaporate the surface of the metal film 522. The pulsed laser beam has an energy density of 0 J / cm. 2 Greater than 100J / cm 2 The pulse width is adjusted to be 1 μs or less. To meet this condition, a YAG laser, YVO4 laser, fiber laser, etc. can be used. For example, in the case of a YAG laser, the energy density is 1 J / cm 2 In the case of electroless Ni plating, for example, 5 J / cm 2 The metal film 522 can be processed even if the thickness is small.

[0274] At this time, the laser light source and the surface metal body 52 are moved relative to each other, whereby the laser light is scanned and sequentially irradiated at multiple positions. By irradiating the surface of the metal film 522 with the laser light and melting and vaporizing it, recesses 523 are formed on the surface of the metal film 522. The average thickness of the portions of the metal film 522 irradiated with the laser light is thinner than the average thickness of the portions not irradiated with the laser light. Furthermore, the multiple recesses 523 formed corresponding to the laser light spots are connected together, for example, in a scale-like shape. A spot is the area irradiated by one pulse. For example, the laser light is scanned so that adjacent laser light spots partially overlap in the X direction and adjacent laser light spots partially overlap in the Y direction.

[0275] Next, the melted metal film 522 is solidified. Specifically, the melted and vaporized metal film 522 is deposited on the portion irradiated with the laser light and its surrounding area. By depositing the melted and vaporized metal film 522 in this manner, an uneven oxide film 520 is formed on the surface of the metal film 522.

[0276] In Figure 66, the uneven oxide film 520 is not provided in a first region 524 of the upper surface 52a of the front surface metal body 52 that overlaps with the accommodation portion 811 of the joint part 81 in a plan view. The uneven oxide film 520 is selectively provided in a second region 525 that overlaps with the opposing surface 810. The configurations of the front surface metal body 62 and the uneven oxide film 620 are similar to those of the front surface metal body 52 and the uneven oxide film 520. The uneven oxide film 620 is not provided in a first region 624 of the upper surface 62a of the front surface metal body 62 that overlaps with the accommodation portion 811 of the joint part 81 in a plan view. The uneven oxide film 620 is selectively provided in the second region 625 that overlaps with the opposing surface 810.

[0277] The oxide film (rough oxide film 520, 620) has lower wettability with respect to the bonding material 103 than a metal film. Because the rough oxide films 520, 620 have fine irregularities on their surfaces, the contact area with the bonding material 103 is reduced, and part of the bonding material 103 becomes spherical due to surface tension. In other words, the contact angle is increased. This results in lower wettability with respect to the bonding material 103. Therefore, due to the effect of reduced wettability by the rough oxide films 520, 620 and the effect of contact with the opposing surface 810, the bonding material 103 is less likely to pass between the opposing surface 810 and the second region 525, 625. This makes it possible to more effectively prevent the bonding material 103 from overflowing. The rough oxide films 520, 620 are formed using laser light as described above, which facilitates patterning.

[0278] As shown in FIG. 68, the uneven oxide films 520, 620 may be provided in peripheral regions 526, 626. The peripheral region 526 is the region surrounding the second region 525 in a plan view, excluding the first region 524. The peripheral region 626 is the region surrounding the second region 625 in a plan view, excluding the first region 624. Even if the bonding material 103 passes directly below the opposing surface 810 of the joint portion 81, it can be blocked by the uneven oxide films 520, 620. Furthermore, since the surfaces of the uneven oxide films 520, 620 have very fine unevenness, the plug 30 becomes entangled therewith, creating an anchor effect. Furthermore, the contact area with the plug 30 is increased. This increases the adhesion of the surface metal bodies 52, 62 to the plug 30.

[0279] The uneven oxide films 520, 620 may be provided in the second regions 525, 625 and the peripheral regions 526, 626. Only one of the uneven oxide films 520, 620 may be provided. The uneven oxide films 520, 620 may be used at the junctions with the main terminals, which are metal members, that is, the P terminal 91P, the N terminal 91N, and the output terminal 92.

[0280] In the example shown, the semiconductor device 20 includes a substrate 60 electrically connected to the source electrode 40S (second main electrode). That is, an example of a semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown. However, the present invention is not limited to this example. The present invention is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only a substrate 50 to which the drain electrode 40D (first main electrode) is connected. In the semiconductor device 20 including a pair of substrates 50, 60, the above structure may be applied only to the joint between one of the substrates 50, 60 and the metal member. In the example shown, both back surface metal bodies 53, 63 are exposed from the sealing body 30, but the present invention is not limited to this example.

[0281] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0282] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, and fourth embodiments and the modified examples.

[0283] (Sixth embodiment) This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to improve the reliability of the semiconductor device, as described in this embodiment, the physical properties of the sealing body and the physical properties of the insulating base material may satisfy a predetermined relationship.

[0284] <Semiconductor device and heat dissipation structure> The semiconductor device 20 and its heat dissipation structure according to this embodiment will be described with reference to Fig. 69. Fig. 69 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 69 is an enlarged view of a portion of Fig. 5. For convenience, the external connection terminals 90 are omitted from Fig. 69.

[0285] The semiconductor device 20 of this embodiment has a structure similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 69, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front surface metal body 62 of the substrate 60 is connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The back surface metal bodies 53 and 63 are exposed from the sealing body 30. The insulating base materials 51 and 61 contain resin. The sealing body 30 contains resin. Although not shown, the semiconductor device 20 also includes a semiconductor element 40L.

[0286] 69 shows the semiconductor device 20 together with the heat exchanger 121 of the cooler 120 and a heat conduction member 130 such as a heat dissipation gel. That is, FIG. 69 shows a semiconductor module 140 including the semiconductor device 20, the cooler 120, and the heat conduction member 130. As an example, the semiconductor module 140 has a double-sided cooling structure in which the semiconductor device 20 is sandwiched between a pair of heat exchangers 121. The semiconductor device 20 is arranged alongside the cooler 120 (heat exchanger 121) in the Z direction, which is a predetermined direction. The coolers 120 are arranged on both sides of the semiconductor device 20.

[0287] The back surface metal bodies 53, 63 are exposed from the sealing body 30 as back surfaces 50b, 60b of the substrates 50, 60. One of the heat exchanger sections 121 of the cooler 120 is disposed facing one surface 30a and the back surface 50b of the sealing body 30, and the other of the heat exchanger sections 121 is disposed facing the back surfaces 30b and 60b of the sealing body 30. Heat conduction members 130 are disposed between the opposing surfaces of the semiconductor device 20 and the heat exchanger sections 121. The heat conduction members 130 are in close contact with the semiconductor device 20 and the heat exchanger sections 121.

[0288] <Relationship with glass transition temperature> Next, the relationship between the glass transition points of the sealing body 30 and the insulating base materials 51 and 61 will be described with reference to FIGS.

[0289] FIG. 70 is a diagram showing an example of the relationship between the glass transition point Tgs and linear expansion coefficient αs of the sealing body 30 and the glass transition point Tgi and linear expansion coefficient αi of the insulating base materials 51 and 61. In FIG. 70, the vertical axis represents the linear expansion coefficient α, and the horizontal axis represents temperature. In FIG. 70, the solid line represents the linear expansion coefficient αs of the sealing body 30, and the dashed line represents the linear expansion coefficient αi of the insulating base materials 51 and 61. Of the linear expansion coefficients αs, α1s represents the linear expansion coefficient at temperatures lower than the glass transition point Tgs, i.e., the linear expansion coefficient in the α1 region. α2s represents the linear expansion coefficient at temperatures higher than the glass transition point Tgs, i.e., the linear expansion coefficient in the α2 region. The same is true for the linear expansion coefficient αi, where α1i represents the linear expansion coefficient in the α1 region and α2s represents the linear expansion coefficient in the α2 region.

[0290] As shown in Fig. 69, the sealing body 30 is in close contact with the semiconductor element 40. The insulating base materials 51, 61 are thermally connected to the semiconductor element 40 via the bonding materials 100, 101, 102 and the surface metal bodies 52, 62. Therefore, when the semiconductor element 40 is operating (generating heat), the temperature of a position MP1 in the sealing body 30 surrounding the semiconductor element 40 is higher than the temperatures of positions MP2, MP3 in the insulating base materials 51, 61 that overlap with the semiconductor element 40. In this way, the sealing body 30 has a higher temperature than the insulating base materials 51, 61.

[0291] When the temperature of the sealing body 30 exceeds the glass transition temperature Tgs, the Young's modulus decreases, and the sealing function of the sealing body 30 deteriorates. This deterioration in sealing function may cause thermal stress to concentrate on the drain electrode 40D, the source electrode 40S, and their junctions, potentially resulting in cracks or other problems. In other words, this may result in a decrease in connection reliability. In contrast, in this embodiment, the relationship Tgs>Tgi is satisfied, as shown in FIG. 70 .

[0292] <Relationship between linear expansion coefficients> Next, the relationship between the linear expansion coefficients of the sealing body 30 and the insulating base materials 51 and 61 will be described with reference to Figures 70 to 72. Figures 71 and 72 are conceptual diagrams showing warping of the semiconductor device 20. Figures 71 and 72 show only the resin elements that make up the semiconductor device 20, that is, only the sealing body 30 and the insulating base materials 51 and 61.

[0293] When the semiconductor element 40 is in operation (heat generation), if the linear expansion coefficient αs of the sealing body 30 is larger than the linear expansion coefficient αi of the insulating base materials 51 and 61, the amount of expansion of the sealing body 30 will be larger than the amount of expansion of the insulating base materials 51 and 61, as shown by the dashed arrows in Fig. 71. In other words, the amount of expansion will be larger at the center in the Z direction and smaller at both ends. Therefore, both ends in the Z direction will have a concave shape.

[0294] In this embodiment, as shown in FIG. 70, the relationship αi > αs is satisfied. Specifically, the relationship α1i > α1s is satisfied in the α1 region, and the relationship α2i > α2s is satisfied in the α2 region. As described above, the relationship Tgs > Tgi is satisfied, and therefore the relationship αi > αs is satisfied throughout the entire operating temperature range. Therefore, when the semiconductor element 40 is operating (heat generation), the amount of expansion of the insulating base materials 51 and 61 is greater than the amount of expansion of the sealing body 30, as shown by the dashed arrows in FIG. 72. In other words, the amount of expansion is smaller at the center in the Z direction and greater at both ends. Therefore, as shown in FIG. 72, the shape of the semiconductor device 20 is convex at both ends in the Z direction.

[0295] <Summary of the Sixth Embodiment> According to this embodiment, the glass transition point Tgs of the sealing body 30 is higher than the glass transition points Tgi of the insulating substrates 51 and 61. As a result, when the semiconductor element 40 operates, it becomes difficult for the temperature of the sealing body 30, which reaches a higher temperature, to exceed the glass transition point Tgs. The temperature of the sealing body 30 either does not exceed the glass transition point Tgs or, if it does, only slightly. Therefore, the Young's modulus of the sealing body 30 decreases, and it is possible to suppress a decrease in the sealing function. Since a decrease in the sealing function can be suppressed, it is possible to suppress stress concentration at the drain electrode 40D, source electrode 40S, and their joint portions, which are the main electrodes. That is, the connection reliability can be enhanced.

[0296] The glass transition point Tgs of the sealing body 30 may be made substantially equal to the glass transition points Tgi of the insulating substrates 51 and 61. Compared with Tgs < Tgi, it becomes difficult for the temperature of the sealing body 30, which reaches a higher temperature during heat generation, to exceed the glass transition point Tgs.

[0297] Also, the linear expansion coefficients αi of the insulating substrates 51 and 61 are greater than the linear expansion coefficient αs of the sealing body 30. As a result, when the semiconductor element 40 operates, the expansion amount of the insulating substrates 51 and 61 becomes greater than the expansion amount of the sealing body 30. That is, the expansion amount is small at the center in the Z direction and large at both ends. Thereby, a convex warp occurs on the outside of the semiconductor device 20 in the Z direction. Thus, the facing distance between the semiconductor device 20 and the cooler 120(121) becomes narrow, and the thermal resistance between the semiconductor device 20 and the cooler 120 becomes small. Specifically, the thickness of the heat conducting member 130 becomes thin, and the thermal resistance becomes small. Since the heat of the semiconductor element 40 can be efficiently released, it is possible to suppress the semiconductor element 40 from being in an overheated state. That is, the heat dissipation performance can be enhanced.

[0298] The linear expansion coefficients αi of the insulating substrates 51 and 61 may be made substantially equal to the linear expansion coefficient αs of the sealing body 30. In this case, the expansion amounts at the center and both ends in the Z direction become substantially equal, and it is possible to suppress the formation of a concave shape in which both ends in the Z direction are recessed. That is, it is possible to suppress an increase in the thermal resistance between the semiconductor device 20 and the cooler 120 due to the formation of the concave shape.

[0299] In this way, by satisfying the relationships Tgs≧Tgi and αi≧αs, it is possible to provide a highly reliable semiconductor device 20.

[0300] <Modification> Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, the present invention is not limited to this. The present invention can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected.

[0301] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0302] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, and fifth embodiments and the modified examples.

[0303] (Seventh embodiment) This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In order to suppress peeling of the sealing body, the surface metal body may have a predetermined structure as described in this embodiment.

[0304] <Semiconductor device> 73 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. FIG. 73 corresponds to FIG.

[0305] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 73, the semiconductor device 20 includes two semiconductor elements 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front surface metal body 52 of the substrate 50 is connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40, via a bonding material 100. The front surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40, via a bonding material 102. The sealing body 30 seals the semiconductor elements 40, the substrates 50 and 60, and the bonding materials 100 and 102. The back surface metal bodies 53 and 63 of the substrates 50 and 60 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 includes two semiconductor elements 40L.

[0306] As shown in FIG. 73, the surface metal bodies 52, 62 have roughened portions 527, 627 and non-roughened portions 528, 628.

[0307] <Uneven oxide film> Next, uneven oxide film 520 constituting roughened portion 527 will be described in detail with reference to Figures 74 and 75. Figure 74 is an enlarged view of region LXXIV in Figure 73. Figure 75 is a view showing a method for forming a roughened portion.

[0308] The surface metal bodies 52, 62 have uneven oxide films 520, 620, similar to the configuration described in the modified example of the fifth embodiment (see FIGS. 66 and 67). The uneven oxide films 520, 620 provide roughened portions 527, 627 on the surfaces of the surface metal bodies 52, 62. Portions of the surfaces of the surface metal bodies 52, 62 where the uneven oxide films 520, 620 are not formed provide non-roughened portions 528, 628. The following description will be given taking the surface metal body 52 as an example.

[0309] As shown in FIG. 74, the surface metal body 52 has a base material 521, and a plating film 522p and an uneven oxide film 520 provided on the surface of the base material 521. The base material 521 forms the main part of the surface metal body 52. ​​The base material 521 is formed using, for example, a Cu-based material. The plating film 522p is formed containing a material that has higher wettability with respect to a bonding material 100 such as solder than the base material 521. The plating film 522p is formed over the entire upper surface 52a and the entire side surface 52c of the surface metal body 52. ​​The side surface 52c is a surface of the surface metal body 52 that connects the upper surface 52a and the lower surface 52d that faces the insulating base material 51.

[0310] The uneven oxide film 520 is formed by irradiating the plating film 522p with laser light, as described in the modified example of the fifth embodiment. In this embodiment, the laser light is irradiated onto the upper surface 52a and the side surface 52c of the front-surface metal body 52. ​​The roughened portion 527 provided by the uneven oxide film 520 is the portion of the upper surface 52a excluding the non-roughened portion 528. The roughened portion 527 is formed over the entire side surface 52c, for example. At the end of the front-surface metal body 52, the roughened portion 527 is provided continuously from the side surface 52c to the upper surface 52a. The roughened portion 527 is provided on a portion of the upper surface 52a and on the side surface 52c. The roughened portion 527 may be provided only on the edge of the upper surface 52a. The non-roughened portion 528 is provided on a portion of the upper surface 52a and includes at least the arrangement area (bonding area) of the bonding material 100. The non-roughened portion 528 may be provided only in the bonding region, or may include a region other than the bonding region. The roughened portion 527 is provided on at least a portion of the side surface 52c. The roughened portion 527 may be provided on only a portion of the side surface 52c. For example, the roughened portion 527 may be provided on only a portion of the side surface 52c so that the uneven oxide film 520 does not come into contact with the insulating base material 51.

[0311] The plating film 522p of this embodiment has an underlayer film mainly composed of Ni (nickel) and an upper layer film mainly composed of Au (gold). Specifically, an electroless Ni plating film containing P (phosphorus) is used as the underlayer film. When the bonding material 100 is solder, the upper layer film (Au) of the plating film 522p exposed from the uneven oxide film 520, which contacts the bonding material 100, diffuses into the solder during reflow. The upper layer film (Au) of the plating film 522p, where the uneven oxide film 520 is to be formed, is removed by irradiation with laser light when the uneven oxide film 520 is formed. The uneven oxide film 520 is an oxide film mainly composed of Ni. The uneven oxide film 520 is continuously provided from the side surface 52c to the upper surface 52a at the end of the surface metal body 52.

[0312] As described in the modified example of the fifth embodiment, the uneven oxide film 520 is formed by melting, vaporizing, and depositing the surface portion of the plating film 522p by irradiation with laser light. The uneven oxide film 520 is an oxide film derived from the plating film 522p. The uneven oxide film 520 is a film of oxide of the metal (Ni) that is the main component of the plating film 522p. Fine unevenness (roughened portions) is always formed on the surface of the uneven oxide film 520. The uneven oxide film 520 has a continuously uneven surface.

[0313] In this embodiment, the area of ​​the lower surface 52d of the front surface metal body 52 is larger than the area of ​​the upper surface 52a. Therefore, as shown in Fig. 74, the lower surface 52d protrudes from the upper surface 52a. In other words, in a plan view in the Z direction, at least a portion of the side surface 52c is located outside the upper surface 52a. Therefore, as shown in Fig. 75, by irradiating the laser light in the Z direction, it is possible to form an uneven oxide film 520 on the upper surface 52a and the side surface 52c.

[0314] <Summary of the Seventh Embodiment> In a configuration in which the plating film 522p is provided on the top surface 52a and side surface 52c of the surface metal body 52, thermal stress tends to cause peeling of the sealing body 30 from the end of the surface metal body 52, i.e., the side surface 52c. In contrast, in this embodiment, the roughened portion 527 is provided on the top surface 52a and the side surface 52c, excluding the non-roughened portion 528. This increases the adhesion between the sealing body 30 and the side surface 52c of the surface metal body 52 compared to a configuration in which the roughened portion 527 is not provided. Therefore, peeling of the sealing body 30 at the side surface 52c of the surface metal body 52 can be suppressed. Suppressing peeling can suppress concentration of thermal stress at the bonding portion of the surface metal body 52, such as the bonding material 100. As a result, a highly reliable semiconductor device 20 can be provided.

[0315] The surface metal body 62 has the same configuration as the surface metal body 52. ​​The surface metal body 62 has a roughened portion 627 on the side surface 62c and on a portion of the top surface 62a excluding the non-roughened portion 628. This makes it possible to prevent peeling of the sealing body 30 from occurring on the side surface 62c of the surface metal body 62.

[0316] In this embodiment, the roughened portions 527, 627 are provided continuously over the side surfaces 52c, 62c and the upper surfaces 52a, 62a. This makes it possible to prevent peeling of the sealing body 30 near the ends of the surface metal bodies 52, 62.

[0317] The roughening treatment for forming the roughened portions 527, 627 can be roughening plating, sandblasting, chemical treatment, etc. In this embodiment, laser roughening is used. The uneven oxide films 520, 620 are formed by irradiating the plating film with laser light. The surface metal bodies 52, 62 have the uneven oxide films 520, 620 on the roughened portions 527, 627.

[0318] The surfaces of the uneven oxide films 520 and 620 have continuous irregularities, which allow the sealant 30 to become entangled, creating an anchor effect. Furthermore, the contact area with the sealant 30 is increased. This increases the adhesion of the roughened portions 527 and 627 to the sealant 30. Furthermore, the uneven oxide films 520 and 620 have lower wettability with the bonding materials 100 and 102 than the plating film (plating film 522p). Because the uneven oxide films 520 and 620 have fine irregularities on their surfaces, the contact area with the bonding materials 100 and 102 is reduced, and portions of the bonding materials 100 and 102 become spherical due to surface tension. In other words, the contact angle increases. This prevents the bonding materials 100 and 102 from overflowing. Thus, the uneven oxide films 520 and 620 increase the adhesion to the sealant 30 and prevent the bonding materials 100 and 102 from overflowing from the bonding portion.

[0319] In this embodiment, the area of ​​the surface metal bodies 52, 62 is larger on the lower surfaces 52d, 62d than on the upper surfaces 52a, 62a. The lower surfaces 52d, 62d protrude relative to the upper surfaces 52a, 62a. This makes it easier to physically roughen the side surfaces 52c, 62c in the Z direction. In the case of the laser roughening described above, by irradiating laser light in the Z direction, it is possible to form the uneven oxide films 520, 620 not only on the upper surfaces 52a, 62a but also on the side surfaces 52c, 62c.

[0320] <Modification> The side shape of the surface metal bodies 52, 62 is not limited to the above examples. When patterning the surface metal bodies 52, 62 by press working, etching, cutting, or the like, the side surfaces can be processed into a predetermined shape. FIG. 76 is a cross-sectional view showing a modified side surface shape. In FIG. 76, the surface metal body 52 is shown as an example, and for convenience, the plating film 522p is omitted from the illustration. Although not shown, a similar configuration can also be adopted for the surface metal body 62.

[0321] In the example shown in FIG. 76, the surface metal body 52 has a side surface 52c that is approximately parallel to the Z direction. In other words, the area of ​​the surface metal body 52 is approximately constant in the Z direction. To physically roughen such a surface metal body 52, for example, the top surface 52a and the side surface 52c may be roughened separately. In the case of laser roughening, the side surface 52c is irradiated with laser light from a direction different from the direction of irradiation of the top surface 52a, for example, from a direction tilted with respect to the Z direction. This allows a rough oxide film 520 to be formed on the side surface 52c.

[0322] FIG. 77 is a cross-sectional view showing a modified example of the side surface shape, and corresponds to FIG. 76. In the example shown in FIG. 77, the area of ​​the surface metal body 52 perpendicular to the Z direction increases toward the lower surface 52d. The side surface 52c has an R-shape. In this case, the entire side surface 52c is located outside the upper surface 52a in a plan view. Therefore, it is easier to perform physical roughening of the side surface 52c from the Z direction, for example, laser roughening, than with the configuration shown in FIG. 75.

[0323] Figure 78 is a cross-sectional view showing a modified example of the side surface shape, and corresponds to Figure 76. In the example shown in Figure 78, the area of ​​the front surface metal body 52 perpendicular to the Z direction increases as it approaches the lower surface 52d. The front surface metal body 52 has a substantially trapezoidal shape in the ZY plane, for example. In this case, too, the entire side surface 52c is located outside the upper surface 52a in plan view, making it easy to physically roughen the side surface 52c from the Z direction.

[0324] Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, the present invention is not limited to this. The present invention can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50, 60, the roughened portion including the side surface described above may be applied to only one of the substrates 50, 60.

[0325] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0326] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, and sixth embodiments, and the modified examples.

[0327] (Eighth embodiment) This embodiment is a modification of the previous embodiment, and the description of the previous embodiment can be used. To reduce inductance, the thickness of the surface metal body and the spacing between the wirings may satisfy a predetermined relationship, as described in this embodiment.

[0328] <Semiconductor device> First, the semiconductor device 20 according to this embodiment, particularly the circuit pattern of the surface metal bodies 52, 62, will be described with reference to Fig. 79. Fig. 79 is a cross-sectional view showing the semiconductor device 20 according to this embodiment. Fig. 79 illustrates a portion of the configuration described in the preceding embodiment (see Fig. 8).

[0329] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 79, the semiconductor device 20 includes a semiconductor element 40 (40H), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The front surface metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The front surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102. Of the substrates 50 and 60, the back surface metal bodies 53 and 63 are exposed from the sealing body 30. Although not shown, the semiconductor device 20 includes a semiconductor element 40L that constitutes a lower arm 9L.

[0330] <Relationship between wiring interval and thickness> Next, based on FIGS. 79 and 80, the relationship between the wiring interval and the thickness will be described. FIG. 80 is an enlarged view of region LXXX in FIG. 79. In FIG. 80, only the substrate 60 is illustrated.

[0331] The surface metal bodies 52 and 62 have wiring gaps 52G and 62G, similar to the configuration described in the previous embodiment (see FIG. 65). As shown in FIGS. 79 and 80, the wiring gap 62G separates the adjacent N-wiring 64 and the relay wiring 65. The wiring gap 62G is a predetermined gap provided between wirings having different potentials in the surface metal body 62.

[0332] As shown in FIG. 80, in the present embodiment, the interval L10 between the N-wiring 64 and the relay wiring 65 is equal to or less than the thickness T10 of the surface metal body 62 (L10 ≦ T10). The interval L10 is the length of the wiring gap 62G, that is, the pattern interval between the N-wiring 64 and the relay wiring 65. In FIGS. 79 and 80, the interval L10 and the thickness T10 in the surface metal body 62 satisfy the relationship of L10 < T10. Although illustration is omitted, the substrate 50 provided with the surface metal body 52 has the same configuration as the substrate 60. In the surface metal body 52, the interval L10 between the P-wiring 54 and the relay wiring 55 is equal to or less than the thickness T10 of the surface metal body 52 (L10 ≦ T10).

[0333] <Simulation results> Figures 81 to 83 show the results of electromagnetic field simulation. Figure 81 is a diagram summarizing the simulation results in terms of the relationship between length (spacing, thickness) and inductance. The circles (○) at the measurement points show the results for three levels of thickness T10 (0.3 mm, 1.5 mm, 2.5 mm) when the spacing L10 is fixed at 1.5 mm. The solid line in the figure shows the change in inductance accompanying the change in thickness T10 when the spacing L10 is fixed. The squares (□) at the measurement points show the results for three levels of spacing L10 (0.5 mm, 1.5 mm, 2.5 mm) when the thickness T10 is fixed at 1.5 mm. The dashed line in the figure shows the change in inductance accompanying the change in spacing L10 when the thickness T10 is fixed. The length on the horizontal axis shown in Figure 81 indicates the length of thickness T10 when the spacing L10 is fixed, and indicates the length of spacing L10 when the thickness T10 is fixed.

[0334] Figure 82 is a diagram showing the simulation results when L10 > T10. Figure 82 shows the simulation results under the first condition C1 shown in Figure 81, specifically when the spacing L10 = 1.5 mm and the thickness T10 = 0.3 mm. Figure 83 is a diagram showing the simulation results when L10 < T10. Figure 83 shows the simulation results under the second condition C2 shown in Figure 81, specifically when the spacing L10 = 1.5 mm and the thickness T10 = 2.5 mm. In the simulation, the conditions other than the spacing L10 and the thickness T10 are common.

[0335] From the results shown in Figure 81, it is clear that the inductance can be reduced within the range satisfying the relationship L10 ≤ T10. In particular, it is clear that the inductance can be effectively reduced within the range satisfying the relationship L10 < T10.

[0336] As shown in FIG. 82, when L10 > T10, although the current is dispersed in the width direction in the extended portion 641 of the N wiring 64, it flows biased toward the end side of the surface metal body 62 (substrate 60). For this reason, the PN current loop (see FIG. 17) described in the previous embodiment is large. Since the current path flowing through the extended portion 421 is far from the relay wiring 65, the canceling effect of the magnetic flux by the current of the reverse direction component is weakened. FIG. 82 shows that the inductance becomes larger compared with the case where the relationship of L10 ≤ T10 is satisfied.

[0337] As shown in FIG. 83, when L10 < T10, the current flows biased toward the end on the relay wiring 65 side in the width direction of the extended portion 641. For this reason, the PN current loop is small. Since the current path flowing through the extended portion 421 is close to the relay wiring 65, the canceling effect of the magnetic flux by the current of the reverse direction component is strengthened. FIG. 83 shows that the inductance becomes smaller compared with the case where the relationship of L10 > T10 is satisfied.

[0338] <Summary of the Eighth Embodiment> In the present embodiment, the surface metal body 52 has a P wiring 54 which is a first wiring and a relay wiring 55 which is a second wiring having a different potential from the first wiring. And the interval L10 between the P wiring 54 and the relay wiring 55 and the thickness T1 of the surface metal body 52 satisfy the relationship of L10 ≤ T10. Similarly, the surface metal body 62 has an N wiring 64 which is a first wiring and a relay wiring 65 which is a second wiring having a different potential from the first wiring. And the interval L10 between the N wiring 64 and the relay wiring 65 and the thickness T1 of the surface metal body 62 satisfy the relationship of L10 ≤ T10.

[0339] When the relationship of L10≦T10 is satisfied, the distance between adjacent wirings is narrow, so the cancellation effect between the magnetic flux due to the current flowing through the first wiring and the magnetic flux due to the current flowing through the second wiring is enhanced, and the inductance can be reduced. Also, since the surface metal body is thick, the cross-sectional area of the current path becomes large, and the inductance can be reduced. As described above, the semiconductor device 20 of the present embodiment can reduce the inductance. In particular, when the relationship of L1<T10 is satisfied, the above-described effect is enhanced, and the inductance can be more effectively reduced.

[0340] <Modification example> Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50 and 60 has been shown, it is not limited thereto. It is also applicable to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50 and 60, only one of the surface metal bodies 52 and 62 may satisfy the above-described relationship of L10≦T10. That is, in at least one substrate electrically connected to the main electrode of the semiconductor element, if the surface metal body has the first wiring and the second wiring and satisfies the relationship of L10≦T10. Also, although an example in which the relationship of L10≦T10 is satisfied in all of the opposing regions between the N wiring 64 as the first wiring and the relay wiring 65 as the second wiring having a different potential from the first wiring has been shown, it is not limited thereto. In at least a part of the opposing region, the relationship of L10≦T10 may be satisfied. The same applies to the opposing region between the P wiring 54 as the first wiring and the relay wiring 55 as the second wiring having a different potential from the first wiring.

[0341] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been shown, it is not limited thereto. It may include only the semiconductor element 40 that constitutes one arm. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0342] The configuration described in the present embodiment can be combined with any of the configurations described in the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, the seventh embodiment, and the modification example.

[0343] (Ninth embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. To improve heat dissipation and reliability, the side surface of the substrate may have a predetermined shape, as described in this embodiment.

[0344] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 84. Fig. 84 is a cross-sectional view corresponding to Fig. 5. In Fig. 84, the external connection terminals 90 are not shown for the sake of convenience.

[0345] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 84, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. The surface metal body 52 of the substrate 50 is electrically connected to the drain electrode 40D, which is the main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is electrically connected to the source electrode 40S, which is the main electrode of the semiconductor element 40. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the bonding materials 100 and 102.

[0346] <Substrate> Next, the substrates 50 and 60 will be described with reference to Figures 84 to 86. Figure 85 is a plan view showing the center of the substrate. Figure 85 corresponds to Figure 12. Figure 86 is an enlarged view of the area LXXXVI indicated by the dashed line in Figure 84. In the following, the terms "inside" and "outside" refer to the relative positional relationship with the centers 50sc and 60sc of the substrates 50 and 60 as the reference positions when viewed from above in the Z direction. The side closer to the center is the inside, and the side further from the center is the outside. Figure 85 shows the center 50sc of the substrate 50 as an example. Although Figure 84 is a cross-sectional view, the centers 50sc and 60sc are shown for the sake of explanation.

[0347] In the substrates 50 and 60 of this embodiment, the insulating base material 51 and 61 contain resin. The surface metal bodies 52 and 62 are disposed on the surfaces 51a and 61a of the insulating base material 51 and 61. The surface metal bodies 52 and 62 are patterned as described in the preceding embodiment. As a result, the insulating base material 51 and 61 have exposed portions 510 and 610 exposed from the surface metal bodies 52 and 62. The exposed portion 510 of the insulating base material 51, which is the first exposed portion, and the exposed portion 610 of the insulating base material 61, which is the second exposed portion, at least partially overlap each other in a plan view in the Z direction. The exposed portions 510 and 610 overlap each other. That is, at least a portion of the exposed portion 510 faces the exposed portion 610 in the Z direction.

[0348] The back surface metal bodies 53, 63 are disposed on the back surfaces 51b, 61b of the insulating base material 51, 61. The back surface metal bodies 53, 63 are exposed from the sealing body 30. The surfaces of the back surface metal bodies 53, 63 opposite the surfaces 53a, 63a facing the insulating base material 51 are exposed surfaces 53b, 63b. The exposed surfaces 53b are exposed and substantially flush with the one surface 30a of the sealing body 30. The exposed surfaces 63b are exposed and substantially flush with the back surface 30b of the sealing body 30. The exposed surfaces 53b, 63b form the back surfaces 50b, 60b of the substrates 50, 60. The sealing body 30 has a side surface 30e as a second surface continuing from the one surface 30a, which is the first surface, and the back surface 30b. The side surface 30e includes the side surfaces 30c, 30d in the Y direction and also includes the side surfaces in the X direction. The side surface 30e includes all side surfaces. The side surface 30e, which is the second surface, is a tapered surface that is inclined with respect to the Z direction for removal from the mold during molding. The side surface 30e has a draft angle. In the preceding embodiment, the draft angle is omitted from the illustration for convenience. The side surface 30e has a bent portion approximately in the center in the Z direction, and the closer to the one surface 30a and the back surface 30b from the bent portion, the closer to the semiconductor element 40 in a plan view in the Z direction. In other words, in a plan view, the bent portion is on the outside, and the one surface 30a and the back surface 30b are on the inside. Hereinafter, the one surface 30a and the back surface 30b of the encapsulant 30 may be referred to as the first surfaces 30a and 30b.

[0349] As shown in FIGS. 84 and 86, the substrates 50 and 60 have laminates 500 and 600. The laminate 500 is a two-layer laminate made of an insulating base material 51 and a back surface metal body 53. Similarly, the laminate 600 is a two-layer laminate made of an insulating base material 61 and a back surface metal body 63. In the laminates 500 and 600, the side surfaces connecting the surfaces 51a and 61a of the insulating base materials 51 and 61 to the exposed surfaces 53b and 63b of the back surface metal bodies 53 and 63 have a so-called V-cut shape. The side surfaces of the laminates 500 and 600 have a shape in which the central portions are convex outward relative to the surfaces 51a and 61a at the upper ends and the exposed surfaces 53b and 63b at the lower ends.

[0350] The side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601, second inclined portions 502 and 602, and intermediate portions 503 and 603. First, the laminate 500 will be described.

[0351] The first inclined portion 501 is a portion within a predetermined range from the surface 51a. In a plan view, the first inclined portion 501 has an inclination such that the distance to the center 50sc is closest at the upper end on the surface 51a side and farther at the lower end than at the upper end. In other words, the lower end of the first inclined portion 501 is located outside the upper end. As shown in FIG. 85, the first inclined portion 501 is provided on the edge of the substrate 50. The first inclined portion 501 is annular so as to surround the surface metal body 52.

[0352] In this embodiment, the first inclined portion 501 has an inclination that increases in distance from the center 50sc in a plan view as it moves away from the surface 51a in the Z direction. That is, in the upper portion of the laminate 500 including the first inclined portion 501, the area perpendicular to the Z direction at the surface 51a is smallest, and the area increases as it moves away from the surface 51a. The inclination of the first inclined portion 501 can tolerate manufacturing variations. The first inclined portion 501 has the inclination described above from a macroscopic perspective. The first inclined portion 501 is a tapered surface.

[0353] The second inclined portion 502 is a portion within a predetermined range from the exposed surface 53b. In a plan view, the second inclined portion 502 has an inclination such that the distance to the center 50sc is closest at the lower end on the exposed surface 53b side and farther at the upper end than at the lower end. In other words, the upper end of the second inclined portion 502 is located outside the lower end. Like the first inclined portion 501, the second inclined portion 502 is provided on the edge portion of the substrate 50. The second inclined portion 502 is annular so as to surround the back surface metal body 53.

[0354] In this embodiment, the second inclined portion 502 has an inclination that increases in a direction away from the center 50sc in a plan view as it moves away from the exposed surface 53b in the Z direction. That is, in the lower portion of the laminate 500 including the second inclined portion 502, the area is smallest at the exposed surface 53b, and the area increases as it moves away from the exposed surface 53b. The inclination of the second inclined portion 502 can tolerate manufacturing variations. The second inclined portion 502 has the inclination described above from a macroscopic perspective. The second inclined portion 502 is a tapered surface. If the first inclined portion 501 is a forward taper, the second inclined portion 502 is a reverse taper.

[0355] The intermediate portion 503 is connected to the first inclined portion 501 and the second inclined portion 502. The intermediate portion 503 is a portion that connects the first inclined portion 501 and the second inclined portion 502, and has a predetermined length in the Z direction. The intermediate portion 503 is the apex portion of the side surface of the laminate 500. The side surface of the laminate 500 is farthest from the center 50sc at the intermediate portion 503. The intermediate portion 503 is the outermost portion of the laminate 500 in a planar view. The area of ​​the laminate 500 perpendicular to the Z direction is largest at the intermediate portion 503. The area of ​​the laminate 500 is approximately constant at the intermediate portion 503. The distance between the first inclined portion 501 and the center 50sc in a planar view decreases as the first inclined portion 501 moves away from the intermediate portion 503. The distance between the second inclined portion 502 and the center 50sc in a planar view decreases as the second inclined portion 502 moves away from the intermediate portion 503.

[0356] The laminate 600 has the same configuration as the laminate 500. The first inclined portion 601 is a portion within a predetermined range from the surface 61a. In a plan view, the first inclined portion 601 has an inclination such that the distance to the center 60sc is closest at the upper end on the surface 61a side and farther at the lower end than at the upper end. In other words, the lower end of the first inclined portion 601 is located outside the upper end. The first inclined portion 601 is provided on the edge of the substrate 60. The first inclined portion 601 is annular so as to surround the surface metal body 62.

[0357] In this embodiment, the first inclined portion 601 has an inclination that increases in distance from the center 60sc in a plan view as it moves away from the surface 61a in the Z direction. That is, in the upper portion of the laminate 600 including the first inclined portion 601, the area perpendicular to the Z direction at the surface 61a is smallest, and the area increases as it moves away from the surface 61a. The inclination of the first inclined portion 601 can tolerate manufacturing variations. The first inclined portion 601 has the inclination described above from a macroscopic perspective. The first inclined portion 601 is a tapered surface.

[0358] The second inclined portion 602 is a portion within a predetermined range from the exposed surface 63b. In plan view, the second inclined portion 602 has an inclination such that the distance to the center 60sc is closest at the lower end on the exposed surface 63b side and farther at the upper end than at the lower end. In other words, the upper end of the second inclined portion 602 is located outside the lower end. Like the first inclined portion 501, the second inclined portion 602 is provided at the edge of the substrate 60. The second inclined portion 602 is annular so as to surround the back surface metal body 63.

[0359] In this embodiment, the second inclined portion 602 has an inclination that increases in distance from the center 60sc in a plan view as it moves away from the exposed surface 63b in the Z direction. That is, in the lower portion of the laminate 600 including the second inclined portion 602, the area is smallest at the exposed surface 63b, and the area increases as it moves away from the exposed surface 63b. The inclination of the second inclined portion 602 can tolerate manufacturing variations. The second inclined portion 602 has the inclination described above from a macroscopic perspective. The second inclined portion 602 is a tapered surface. If the first inclined portion 601 is a forward taper, the second inclined portion 602 is a reverse taper.

[0360] The intermediate portion 603 is connected to the first inclined portion 601 and the second inclined portion 602. The intermediate portion 603 is a portion that connects the first inclined portion 601 and the second inclined portion 602, and has a predetermined length in the Z direction. The intermediate portion 603 is the apex portion of the side surface of the laminate 600. The side surface of the laminate 600 is farthest from the center 60sc at the intermediate portion 603. The intermediate portion 603 is the outermost portion of the laminate 600 in a planar view. The area of ​​the laminate 600 is largest at the intermediate portion 603. The area of ​​the laminate 600 is approximately constant at the intermediate portion 603. The distance between the first inclined portion 601 and the center 60sc in a planar view decreases as the first inclined portion 601 moves away from the intermediate portion 603. The distance between the second inclined portion 602 and the center 60sc in a planar view decreases as the second inclined portion 602 moves away from the intermediate portion 603.

[0361] <Dimensions and angles> Next, the dimensions and angles of the laminated bodies 500 and 600 will be described with reference to Fig. 87. Fig. 87 is a diagram corresponding to Fig. 86, and shows the dimensions and angles. The following description will be given taking the laminated body 500 as an example.

[0362] The length L11 shown in FIG. 87 is the length of the first inclined portion 501 in a plan view, that is, the width of the annular first inclined portion 501. The length L12 is the length of the second inclined portion 502 in a plan view, that is, the width of the annular second inclined portion 502. The length L21 is the length of the first inclined portion 501 in the Z direction, that is, the height of the first inclined portion 501. The length L22 is the length of the second inclined portion 502 in the Z direction, that is, the height of the second inclined portion 502. The length L23 is the length of the intermediate portion 503 in the Z direction, that is, the height of the intermediate portion 503. The length L24 is the length of the insulating base material 51 in the Z direction, that is, the thickness of the insulating base material 51. The length L25 is the length of the back surface metal body 53 in the Z direction, that is, the thickness of the back surface metal body 53.

[0363] The angle R1 is the inclination angle of the back surface metal body 53 with respect to the Z direction, which is the thickness direction of the semiconductor element 40, in the first inclined portion 501. The angle R2 is the inclination angle of the back surface metal body 53 with respect to the Z direction in the second inclined portion 502. The angle R3 is the inclination angle of the insulating base material 51 with respect to the Z direction in the first inclined portion 501. The angle R4 is the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back surface metal body 53. The angle R5 is the inclination angle of the side surface 30e with respect to one surface 30a of the sealing body 30.

[0364] As shown in FIG. 87, in the present embodiment, the length of the second inclined portion 502 is shorter than the length of the first inclined portion 501. That is, the relationship L11 > L12 is satisfied. The angle R1 satisfies the relationship 0° < R1 ≤ 45°, and the angle R2 satisfies the relationship 0° < R2 < 45°. The closer the angle R1 is to 45°, the more effectively the heat generated by the semiconductor element 40 can be diffused. The closer the angle R2 is to 45°, the lower the thermal resistance can be, as will be described later.

[0365] Furthermore, the first inclined portion 501 is provided from the insulating base material 51 to the back surface metal body 53, and the second inclined portion 502 is provided on the back surface metal body 53. That is, the relationship of L21 > L24 and L22 < L25 is satisfied. In the configuration including the intermediate portion 503, the intermediate portion 503 is provided on the back surface metal body 53. That is, the relationship of L24 < (L24 + L25 - L23) / 2 is satisfied.

[0366] Furthermore, in the configuration where the first inclined portion 501 is provided from the insulating base material 51 to the back surface metal body 53, the inclination angle of the back surface metal body 53 and the inclination angle of the insulating base material 51 are substantially equal. That is, the relationship of R1 = R3 is satisfied.

[0367] Furthermore, the inclination angle of the second inclined portion 502 with respect to the exposed surface 53b of the back surface metal body 53 is smaller than the inclination angle of the side surface 30e (second surface) with respect to the one surface 30a (first surface) of the sealing body 30. That is, the relationship of R4 < R5 is satisfied. Although the description is omitted, the laminate 600 also has the same configuration as the laminate 500.

[0368] <Manufacturing method of laminate> Next, an example of the manufacturing method of the above-described laminate 500 will be described. First, a mother substrate having a two-layer structure of an insulating base material 51 containing resin and a back surface metal body 53 is formed. Next, the blade simultaneously cuts (V-cut) from both sides of the surface 51a of the insulating base material 51 and the exposed surface 53b. In this cutting, the first inclined portion 501 and the second inclined portion 502 are formed without completely separating the mother substrate. In the mother substrate, adjacent laminates 500 are connected at the intermediate portion 503. Then, by separating (cutting off) the adjacent laminates 500 at the intermediate portion 503, a laminate 500 having a V-cut-shaped side surface can be obtained.

[0369] 88 is a side view of the laminate 500 obtained by the above-described manufacturing method. The first inclined portion 501 has cutting marks 501a along the circumferential direction due to cutting (machining) using a blade. Similarly, the second inclined portion 502 has cutting marks 502a along the circumferential direction. Since adjacent laminates 500 are separated at the intermediate portion 503, the intermediate portion 503 has an uneven portion 503a. Although a detailed description will be omitted, the laminate 600 is also formed by the same method as the laminate 500.

[0370] <Summary of the ninth embodiment> In this embodiment, the side surfaces of the laminates 500 and 600 have first inclined portions 501 and 601 and second inclined portions 502 and 602. That is, the side surfaces are curved (substantially V-shaped). As a result, even if delamination that occurs in the sealing body 30 starting from the interface with the exposed surface 53b and 63b progresses along the second inclined portions 502 and 602, the curved shape can suppress the progression to the first inclined portions 501 and 601. Therefore, it is possible to suppress the progression of delamination to the surface metal bodies 52 and 62, the semiconductor element 40, and the joints between the surface metal bodies 52 and 62 and the semiconductor element 40. In other words, it is possible to suppress the concentration of thermal stress on the surface metal bodies 52 and 62, the semiconductor element 40, and the like, which would otherwise cause a decrease in connection reliability. This ensures reliability.

[0371] The presence of the second inclined portions 502, 602 can also prevent the back surface metal bodies 53, 63 from falling off (falling off) from the sealing body 30 when the above-described peeling occurs.

[0372] Ideally, heat spreads at an angle of 45 degrees. In this embodiment, the stacked bodies 500 and 600 have first inclined portions 501 and 601 on the semiconductor element 40 side in the Z direction. This allows heat generated by the semiconductor element 40 to diffuse above the bent portion, i.e., in the portions corresponding to the first inclined portions 501 and 601. On the other hand, by having the second inclined portions 502 and 602, the heat conduction path in the portions corresponding to the second inclined portions 502 and 602 is narrower than the heat conduction path in the portions corresponding to the first inclined portions 501 and 601. The narrower heat conduction path increases thermal resistance. In this embodiment, the length L12 of the second inclined portions 502 and 602 is set shorter than the length L11 of the first inclined portions 501 and 601 (L11>L12). This allows the length L22 of the second inclined portions 502, 602 in the Z direction to be shorter than in a configuration where L11≦L12 is satisfied, thereby reducing the thermal resistance below the bent portion. In other words, heat diffused in the upper portion of the laminated bodies 500, 600 can be efficiently dissipated from the exposed surfaces 53b, 63b. As a result, the semiconductor device 20 of this embodiment can ensure reliability while improving heat dissipation.

[0373] The first inclined portions 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portions 502, 602 may be provided on the back surface metal body 53, 63. The first inclined portions 501, 601 may be provided on the insulating substrate 51, 61, and the second inclined portions 502, 602 may be provided across the insulating substrate 51, 61 and the back surface metal body 53, 63. In this embodiment, the first inclined portions 501, 601 are provided across the insulating substrate 51, 61 and the back surface metal body 53, 63, and the second inclined portions 502, 602 are provided on the back surface metal body 53, 63. In other words, a bent portion exists within the back surface metal body 53, 63. Therefore, even if delamination that occurs in the sealing body 30 originates at the interface with the exposed surface 53b, 63b and progresses along the second inclined portions 502, 602, it is possible to prevent the delamination from progressing to the interface with the insulating substrate 51, 61. This makes it possible to prevent thermal stress from concentrating on the insulating base materials 51 and 61 and reducing the insulation reliability, thereby further improving the reliability.

[0374] The first inclined portions 501 and 601 and the second inclined portions 502 and 602 may be configured to be continuous. In the present embodiment, intermediate portions 503 and 603 are provided between the first inclined portions 501 and 601 and the second inclined portions 502 and 602. In this configuration, the intermediate portions 503 and 603 form bent portions. By providing the intermediate portions 503 and 603, as described above, even when cutting (machining) simultaneously from both the front surfaces 51a and 61a of the insulating substrates 51 and 61 and the exposed surfaces 53b and 63b of the back surface metal bodies 53 and 63, contact between the blades can be avoided. Further, since the intermediate portions 503 and 603 are provided on the back surface metal bodies 53 and 63, it is possible to suppress the peeling from progressing to the interface with the insulating substrates 51 and 61 as described above.

[0375] In a configuration in which the first inclined portions 501 and 601 are provided across the insulating substrates 51 and 61 to the back surface metal bodies 53 and 63, the inclination angle R1 of the back surface metal bodies 53 and 63 and the inclination angle R3 of the insulating substrates 51 and 61 may be made different. For example, when R1 < R3, since thermal stress concentrates at the ends of the insulating substrates 51 and 61 containing resin, there is a risk of deterioration of the insulation performance. When R1 > R3, thermal stress concentrates at the interface between the insulating substrates 51 and 61 and the back surface metal bodies 53 and 63, and there is a risk of interface peeling. In the present embodiment, the inclination angle R1 and the inclination angle R3 are made substantially equal (R1 = R3). That is, in the first inclined portions 501 and 601, the inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back surface metal bodies 53 and 63 are substantially flush and continuous. The inclined surfaces of the insulating substrates 51 and 61 and the inclined surfaces of the back surface metal bodies 53 and 63 are continuous and form a single flat surface. Thereby, it is possible to suppress the concentration of thermal stress at the triple point of the sealing body 30, the insulating substrates 51 and 61, and the back surface metal bodies 53 and 63.

[0376] The inclination angle R4 of the second inclined portions 502 and 602 with respect to the exposed surfaces 53b and 63b may be set to be equal to or greater than the inclination angle R5 of the side surface 30e (the second surface) with respect to the first surfaces 30a and 30b of the sealing body 30. In the present embodiment, the inclination angle R4 is made smaller than the inclination angle R5 (R4 < R5). As described in the previous embodiment (see, for example, FIG. 72), when the semiconductor element 40 generates heat, the semiconductor device 20 warps. As described above, if a configuration is adopted that results in a warped shape with high heat dissipation, peeling is likely to occur at the interface between the back surface metal bodies 53 and 63 and the sealing body 30 due to the warp convex in the Z direction. By adopting a configuration that satisfies the relationship of R4 < R5, even if peeling occurs, it is possible to suppress the back surface metal bodies 53 and 63 from falling off from the sealing body 30.

[0377] In the present embodiment, the exposed portion 510 of the insulating base material 51 which is the first exposed portion and the exposed portion 610 of the insulating base material 61 which is the second exposed portion overlap with each other in a plan view in the Z direction. Thereby, it is possible to suppress the imbalance in the arrangement of the surface metal body 52 of the substrate 50 which is the first substrate and the surface metal body 62 of the substrate 60 which is the second substrate, and thus suppress the imbalance in the warp of the semiconductor device 20. It is possible to suppress the occurrence of interface peeling between the back surface metal bodies 53 and 63 and the sealing body 30 on the side where the deformation is large due to the uneven warp.

[0378] In the present embodiment, the first inclined portion 501 and the second inclined portion 502 have cutting marks 501a and 502a along the circumferential direction. By having the cutting marks 501a and 502a, an anchor effect occurs and the adhesion force with the sealing body 30 increases. Thereby, it is possible to suppress the peeling of the sealing body 30 from the laminate 500 and 600. Note that cutting marks along the circumferential direction may be provided only on one of the first inclined portion 501 and the second inclined portion 502. In the present embodiment, since the intermediate portion 503 also has the concavo-convex portion 503a, peeling suppression due to the anchor effect can be expected.

[0379] <Modification Example> Although an example of the semiconductor device 20 having a double-sided heat dissipation structure including a pair of substrates 50, 60 has been shown, the present invention is not limited to this. The present invention can also be applied to a semiconductor device 20 having a single-sided heat dissipation structure including only the substrate 50 to which the drain electrode 40D (first main electrode) is connected. In a configuration including a pair of substrates 50, 60, the above-described structure (V-cut shape) may be applied to only one of the substrates 50, 60.

[0380] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0381] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, and eighth embodiments, and the modified examples.

[0382] (Tenth embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve connection reliability, the sintered members, which are joining materials, may be arranged in a predetermined manner, as described in this embodiment.

[0383] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 89. Fig. 89 is a cross-sectional view corresponding to Fig. 5. In Fig. 89, for the sake of convenience, the external connection terminals 90 are not shown.

[0384] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 89, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 serving as wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. A surface metal body 52 of the substrate 50 serving as a first wiring member is connected to a drain electrode 40D serving as a first main electrode of the semiconductor element 40. A surface metal body 62 of the substrate 60 serving as a second wiring member is connected to a source electrode 40S serving as a second main electrode of the semiconductor element 40 via a conductive spacer 70 serving as a second wiring member. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The source electrode 40S and the conductive spacer 70 are bonded together by a sintered member 101A serving as a bonding material 101.

[0385] <Semiconductor element> Next, semiconductor element 40 will be described with reference to Figures 90 and 91. Figure 90 is a plan view showing semiconductor element 40 (40H). Figure 91 is an enlarged view of region XCI in Figure 89. Figure 91 is a cross-sectional view corresponding to line XCI-XCI in Figure 90. Although Figure 91 illustrates semiconductor element 40H, semiconductor element 40L also has a similar configuration, and therefore will be described below as semiconductor element 40.

[0386] As described above, the semiconductor element 40 has a semiconductor substrate 41 on which a switching element is formed. The semiconductor substrate 41 has a generally rectangular shape in plan view. The drain electrode is provided on one surface of the semiconductor substrate 41, and the source electrode 40S and the pad 40P are provided on the back surface of the semiconductor substrate 41. The source electrode 40S has a multi-layer structure. The source electrode 40S has a base electrode 42 and a connection electrode 43. The pad 40P has a similar configuration to the source electrode 40S.

[0387] The semiconductor element 40 further has a protective film 44. The protective film 44 is an insulating film provided on the back surface of the semiconductor substrate 41 so as to cover the peripheral edge of the source electrode 40S. For example, polyimide, silicon nitride, or the like can be used as the insulating film material. The protective film 44 has an opening 440 that defines a connection region of the source electrode 40S. The opening 440 exposes the source electrode 40S so as to be bondable. The protective film 44 has an opening 441 that defines a connection region of the pad 40P. Both the openings 440 and 441 are through-holes that penetrate the protective film 44 in the Z direction. The portion of the source electrode 40S (connection electrode 43) exposed from the opening 440 of the protective film 44 forms a bond with the sintered member 101A.

[0388] The protective film 44 in this embodiment is made of polyimide. The protective film 44 covers a peripheral edge 420 (described later) of the base electrode 42. The protective film 44 is not provided, for example, in a scribe region within a predetermined range from the outer peripheral edge of the semiconductor substrate 41. The opening shape of the opening 440, i.e., an inner peripheral surface 442 of the protective film 44 that defines the opening 440, is generally rectangular in plan view. The inner peripheral surface 442 may be referred to as the inner peripheral edge or the opening edge.

[0389] The base electrode 42 is a metal layer formed adjacent to the semiconductor substrate 41 in the multi-layered source electrode 40S. The base electrode 42 may also be referred to as a lower electrode, a lower-layer electrode, a wiring electrode, a base layer, a first metal layer, etc. The base electrode 42 is connected to the rear surface of the semiconductor substrate 41. The base electrode 42 is formed using a material containing Al (aluminum) as a main component, for example. In this embodiment, an AlSi-based alloy such as AlSi or AlSiCu is used as the material.

[0390] In plan view, the base electrode 42 encompasses an element region (active region) (not shown) of the semiconductor substrate 41 and extends onto an outer peripheral region surrounding the element region. A peripheral portion 420 of the base electrode 42 has a generally rectangular ring shape in plan view. The peripheral portion 420 is covered with a protective film 44.

[0391] The connection electrode 43 is laminated on the base electrode 42. The connection electrode 43 is also referred to as an upper electrode, an upper electrode, an upper layer electrode, an upper layer, or a second metal layer. The connection electrode 43 contains at least a noble metal such as Au (gold), Ag (silver), Pt (platinum), or Pd (palladium) for bonding to the sintered member 101A. The connection electrode 43 may contain a base metal in addition to the noble metal.

[0392] The connection electrode 43 of this embodiment contains Ni (nickel). Ni is harder than the Al alloy that constitutes the base electrode 42. The connection electrode 43 contains Ni and a noble metal, such as Au or Ag. The connection electrode 43 is formed in multiple layers by, for example, a plating method. At least a part of the noble metal of the connection electrode 43 diffuses into the sintered member 101A during bonding.

[0393] The connection electrode 43 is disposed on the base electrode 42 in the opening 440 of the protective film 44. The outer peripheral end of the connection electrode 43 is in contact with the inner peripheral surface 442 of the protective film 44 along the entire periphery.

[0394] <Joining structure> Next, the joining structure of the semiconductor element 40 will be described with reference to Figures 90 to 92. In Figure 90, the outer peripheral edge of the sintered member 101A is indicated by a dashed line, and the outer peripheral edge of the conductive spacer 70 is indicated by a two-dot chain line. Figure 92 is a cross-sectional view showing the arrangement of the sintered member 101A. Figure 92 corresponds to Figure 91. In the following, the terms "inside" and "outside" refer to the relative positional relationship with the center of the semiconductor element 40 as the reference position. The side closer to the center is the inside, and the side farther from the center is the outside.

[0395] In this embodiment, the substrate 60 and the conductive spacer 70 are a wiring member (second wiring member) electrically connected to the source electrode 40S. As shown in FIGS. 90 and 91, the sintered member 101A is interposed between the source electrode 40S of the semiconductor element 40 and the conductive spacer 70. The sintered member 101A joins the source electrode 40S and the conductive spacer 70.

[0396] The sintered member 101A is made of Ag or Cu. The sintered member 101A is a sintered body made of Ag particles or Cu particles. The sintered member 101A can be bonded at a lower temperature than solder. As shown in FIG. 92, the sintered member 101A is disposed at a predetermined distance L30 from the inner peripheral surface 442 of the protective film 44. As shown in FIGS. 90 to 92, the sintered member 101A is disposed inside the inner peripheral surface 442. The sintered member 101A has, for example, a substantially rectangular shape in plan view. The outer peripheral edge of the sintered member 101A is not in contact with the protective film 44 along its entire circumference. In other words, the inner peripheral surface 442 of the protective film 44 encloses the sintered member 101A in a plan view.

[0397] The conductive spacer 70 has a metal film (not shown) on the bonding surface with the sintered member 101A. The metal film contains at least a noble metal, similar to the connection electrode 43. In this embodiment, the metal film is a plating film containing Ni and a noble metal, for example, Au or Ag.

[0398] As shown in FIGS. 90 to 92, the conductive spacer 70 is disposed inside the inner peripheral surface 442. The conductive spacer 70 has, for example, a substantially rectangular shape in plan view. The outer peripheral edge of the conductive spacer 70 is disposed outside the outer peripheral edge of the sintered member 101A in plan view, or so as to be substantially aligned with the outer peripheral edge of the sintered member 101A. In other words, the conductive spacer 70 is disposed so as to enclose the sintered member 101A or so as to be substantially aligned with the sintered member 101A in plan view. In this embodiment, the conductive spacer 70 encloses the sintered member 101A.

[0399] <Joining method> Next, a method for forming the above-mentioned bonded structure, that is, a bonding method, will be described with reference to Fig. 93. Fig. 93 is a cross-sectional view showing the bonding method. Fig. 93 corresponds to Fig. 91.

[0400] In this embodiment, a sintered sheet 105 is used to form the sintered member 101A. The sintered sheet 105 is sometimes referred to as a sintered film. The sintered sheet 105 contains Ag or Cu. As shown in FIG. 93, the sintered sheet 105 is placed on the source electrode 40S (connection electrode 43) of the semiconductor element 40. The sintered sheet 105 has a predetermined size that does not contact the protective film 44 in a plan view.

[0401] Next, the conductive spacer 70 is placed on the sintered sheet 105. Then, while heating, pressure is applied from the conductive spacer 70 side using a pressure device (not shown). As a result, the sintered sheet 105 is pressed and spread between the opposing surfaces of the connection electrode 43 and the conductive spacer 70, reducing its thickness, and is sintered into the sintered member 101A. The size of the sintered sheet 105 is determined so that the sintered member 101A has the predetermined positional relationship described above with respect to the inner circumferential surface 442 of the protective film 44 and the conductive spacer 70.

[0402] <Simulation results> FIG. 94 shows the results of a thermal stress simulation. In this simulation, the strain amplitude generated in the base electrode 42 was measured in a power cycle test in which room temperature and 150°C were alternately repeated. FIG. 94 shows the relationship between the distance L30 and the strain amplitude. In FIG. 94, when the distance L30 is 0 (zero), it corresponds to the position that coincides with the inner circumferential surface 442 of the protective film 44 in a plan view. Negative values ​​for the distance L30 indicate the distance inward from the inner circumferential surface 442, and positive values ​​indicate the distance outward.

[0403] 94, it has been revealed that when the distance L30 is 5 μm or more, the strain amplitude generated in the base electrode 42 becomes almost 0 (zero). Based on this finding, in this embodiment, the predetermined distance L30 is set to 5 μm.

[0404] <Summary of the Tenth Embodiment> FIG. 95 shows a connection structure using solder 101B as the bonding material 101. FIG. 95 corresponds to FIG. 93. In the case of solder 101B, bonding is performed by reflowing the solder 101B. During bonding, the molten solder 101B wets and spreads over the surface of the connection electrode 43. Therefore, as shown by the dashed-dotted line in FIG. 95, a triple junction is formed between the sealing body 30, the source electrode 40S (connection electrode 43), and the solder 101B (bonding material 101). Thermal stress due to the difference in linear expansion coefficients is concentrated at the triple junction. The thermal stress is concentrated in the portion of the base electrode 42 directly below the outer circumferential edge of the connection electrode 43. This may cause cracks in the base electrode 42 and ultimately damage the semiconductor substrate 41.

[0405] In this embodiment, a sintered member 101A is used instead of the solder 101B. The sintered member 101A is formed by heating at a temperature lower than the melting point. Unlike the solder 101B, the sintered member 101A does not become molten during bonding. Compared to the solder 101B, the sintered member 101A has lower wettability with respect to the connection electrodes 43 and the conductive spacer 70. Therefore, unlike the solder 101B, the sintered member 101A does not wet and spread over the surfaces of the connection electrodes 43 and the conductive spacer 70 during bonding.

[0406] The sintered member 101A can be easily held in place and positioned at a predetermined distance L30 from the inner circumferential surface 442 of the protective film 44. This prevents a triple point between the sealing body 30, the source electrode 40S (connection electrode 43), and the sintered member 101A (bonding material 101). This prevents the concentration of thermal stress and provides a semiconductor device 20 with high connection reliability. The sintered member 101A also has a higher thermal conductivity than the solder 101B. This also improves heat dissipation.

[0407] The distance L30 is not particularly limited. The sintered member 101A only needs to be spaced apart from the inner peripheral surface 442. In this embodiment, the distance L30 between the sintered member 101A and the inner peripheral surface 442 of the protective film 44 is set to 5 μm or more. This effectively reduces the distortion amplitude of the base electrode 42 due to thermal stress. In other words, the connection reliability can be further improved.

[0408] In plan view, the positional relationship between the conductive spacer 70 and the sintered member 101A is not particularly limited. For example, the sintered member 101A may protrude from the conductive spacer 70 in plan view. As described above, the sintered member 101A is formed by sintering Ag particles or Cu particles by applying heat and pressure. The protruding portion of the conductive spacer 70 is not pressurized, and therefore may remain unsintered and fall off as conductive foreign matter. In other words, there is a risk of short circuiting or the like occurring.

[0409] In this embodiment, in plan view, the inner circumferential surface 442 of the protective film 44 contains the conductive spacer 70, and the conductive spacer 70 is flush with or contains the sintered component 101A. This allows pressure to be applied to the entire area of ​​the sintered component 101A (sintered sheet 105) before sintering via the conductive spacer 70. Therefore, contact between the sintered component 101A and the protective film 44 can be avoided, and the occurrence of unsintered portions can be suppressed.

[0410] <Modification> While the sintered sheet 105 is used to form the sintered component 101A, this is not limiting. For example, a sintering paste containing Ag or Cu particles dispersed in a solvent may be used. The sintered sheet 105 is easier to hold in place than the sintering paste.

[0411] Although an example has been shown in which the second wiring member to which the source electrode 40S is connected includes the substrate 60, which is a wiring board, and the conductive spacer 70, the present invention is not limited to this. Instead of the conductive spacer 70, a convex portion may be provided on the front surface metal body 62. In other words, the second wiring member may be configured to include only the substrate 60 without including the conductive spacer 70. In this case, the sintered member 101A is interposed between the tip surface of the convex portion of the front surface metal body 62 and the source electrode 40S (connection electrode 43).

[0412] Although the example of the substrate 50 is shown as the first wiring member, it is not limited to this. A metal plate (lead frame) may be used instead of the substrate 50. Although the example of the substrate 60 is shown as the second wiring member, it is not limited to this. A metal plate (lead frame) may be used instead of the substrate 60. The second wiring member may have a metal plate and a conductive spacer 70, or a convex portion may be provided on the metal plate instead of the conductive spacer 70.

[0413] Although an example in which the semiconductor device 20 includes the semiconductor elements 40H and 40L has been described, the present invention is not limited to this. The semiconductor device 20 may include only a semiconductor element 40 that configures one of the arms. The semiconductor device 20 may include, for example, only one semiconductor element 40.

[0414] The configuration described in this embodiment can be combined with any of the configurations described in the first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth embodiments, and the modified examples.

[0415] (Eleventh embodiment) This embodiment is a modification of the preceding embodiment, and the description of the preceding embodiment can be used. In order to improve heat dissipation, a sintered member may be used at the joint between the main electrode and the wiring member, as described in this embodiment.

[0416] <Semiconductor device> First, the semiconductor device 20 according to this embodiment will be described with reference to Fig. 96. Fig. 96 is a cross-sectional view corresponding to Fig. 5. In Fig. 96, the external connection terminals 90 are not shown for the sake of convenience.

[0417] The semiconductor device 20 of this embodiment has a configuration similar to that described in the preceding embodiment (see FIGS. 2 to 13). As shown in FIG. 96, the semiconductor device 20 includes a semiconductor element 40 (40H, 40L), substrates 50 and 60 serving as wiring members arranged to sandwich the semiconductor element 40 in the Z direction, and a sealing body 30. A surface metal body 52 of the substrate 50 is connected to a drain electrode 40D, which is a first main electrode of the semiconductor element 40. The surface metal body 62 of the substrate 60 is connected to a source electrode 40S, which is a second main electrode of the semiconductor element 40, via a conductive spacer 70. The sealing body 30 seals the semiconductor element 40, the substrates 50 and 60, and the conductive spacer 70. The drain electrode 40D and the surface metal body 52 of the substrate 50 are joined by a sintered member 100A, which is a joining material 100.

[0418] <Arrangement of sintered components and uneven oxide film> Next, the arrangement of the sintered member 100A and the uneven oxide film 520 relative to the semiconductor element 40 will be described with reference to Figures 97 to 99. Figure 97 is an enlarged view of region XCVII in Figure 96. Figure 98 is a plan view showing the positional relationship between the semiconductor element 40, the sintered member 100A, and the uneven oxide film 520. Figure 99 is an enlarged view of region XCVIX in Figure 97.

[0419] 97 and 98, the upper surface 52a of the surface metal body 52 has a mounting portion 529a, an outer periphery 529b, and an intermediate portion 529c. The uneven oxide film 520 is not provided on the mounting portion 529a, but is provided on the outer periphery 529b and the intermediate portion 529c.

[0420] The mounting portion 529a includes a portion overlapping with the semiconductor element 40 (drain electrode 40D) in a plan view in the Z direction, and is a portion to which the drain electrode 40D is joined via the sintered member 100A. The outer peripheral portion 529b includes a portion outer than the outer peripheral edge 402 of the semiconductor element 40 in a plan view, and is a portion surrounding the semiconductor element 40. The intermediate portion 529c is a portion between the mounting portion 529a and the outer peripheral portion 529b, and surrounds the mounting portion 529a. In this embodiment, the mounting portion 529a substantially coincides with the semiconductor element 40 (drain electrode 40D) in a plan view. The intermediate portion 529c has a substantially rectangular ring shape in a plane, and the inner peripheral edge of the intermediate portion 529c substantially coincides with the outer peripheral edge 402 of the semiconductor element 40. The entire intermediate portion 529c is located outside the semiconductor element 40 in a plan view.

[0421] 97 to 99, similar to the configuration described in the preceding embodiment (see FIGS. 67 and 74), the surface metal body 52 of the substrate 50 has an uneven oxide film 520. As shown in FIG. 99, the surface metal body 52 has a base material 521, and a metal film 522 and uneven oxide film 520 provided on the surface of the base material 521.

[0422] The metal film 522 of this embodiment includes a base film primarily composed of Ni and a top film primarily composed of a precious metal, such as Au or Ag, that can be bonded to the sintered member 100A. Specifically, a P-containing Ni plating film and an Au plating film are used as the base film. A plurality of recesses 523 are formed in an outer peripheral portion 529b of the upper surface 52a of the metal film 522. No recesses 523 are formed in the mounting portion 529a or the intermediate portion 529c. In the portion where no recesses 523 are formed, the film thickness of the metal film 522 is, for example, approximately 10 μm. In other words, the film thickness before irradiation with the laser light is approximately 10 μm. The recesses 523 are formed by irradiation with pulsed laser light. One recess 523 is formed for each pulse. In the outer peripheral portion 529b, the surface of the metal film 522 has a scale-like shape due to the plurality of recesses 523. The outer peripheral portion 529b is an area to be irradiated with laser light, and the mounting portion 529a and the intermediate portion 529c are areas not to be irradiated with laser light.

[0423] The uneven oxide film 520 is formed on the metal film 522. The uneven oxide film 520 is not formed on the mounting portion 529a, but is formed on the outer peripheral portion 529b and the intermediate portion 529c, which are portions surrounding the mounting portion 529a. As described in the preceding embodiment, the uneven oxide film 520 is formed by irradiating the metal film 522 with laser light. The uneven oxide film 520 is a laser-irradiated film formed by irradiating with laser light. The main component of the uneven oxide film 520 is an oxide of the main component metal of the metal film 522.

[0424] In the outer peripheral portion 529b, i.e., the area irradiated with the laser beam, the average film thickness of the uneven oxide film 520 is 10 nm to several hundred nm. The uneven oxide film 520 is formed following the unevenness of the surface of the metal film 522 having the recesses 523. The unevenness is formed on the surface of the uneven oxide film 520 at a pitch finer than the width of the recesses 523. That is, a very fine unevenness (roughened portion) is formed. In other words, a plurality of protrusions 520a (columnar bodies) are formed at a fine pitch. For example, the average width of the protrusions 520a is 1 nm to 300 nm, and the average spacing between the protrusions 520a is 1 nm to 300 nm. The average height of the protrusions 520a is 10 nm to several hundred nm.

[0425] The uneven oxide film 520 is formed by irradiating the metal film 522 with laser light and melting and vapor-depositing the surface layer of the metal film 522, and is therefore formed not only in the outer peripheral portion 529b, which is the area irradiated with the laser light, but also in the periphery (vicinity) of the outer peripheral portion 529b. In this embodiment, the uneven oxide film 520 is formed over the entire intermediate portion 529c, which is an area not irradiated with the laser light, and is not formed on the mounting portion 529a. The width of the intermediate portion 529c, which has the uneven oxide film 520 over its entire area, is, for example, 0.2 mm to 0.3 mm.

[0426] The average thickness of the uneven oxide film 520 in the intermediate portion 529c is thinner than the average thickness of the uneven oxide film 520 in the outer peripheral portion 529b, because the intermediate portion 529c is not directly irradiated with laser light, and is thicker than the native oxide film. Specifically, it is 0.1 nm to 10 nm. Furthermore, the height of the protrusions 520a on the surface of the uneven oxide film 520 is also lower than that of the outer peripheral portion 529b. Specifically, it is 0.1 nm to 10 nm. The average width and average spacing of the protrusions 520a are similar to those of the outer peripheral portion 529b.

[0427] As described above, the uneven oxide film 520 has a thick film portion 520X and a thin film portion 520Y. The thick film portion 520X is a portion of the uneven oxide film 520 that is provided in the laser light irradiated area, i.e., the outer peripheral portion 529b. The thin film portion 520Y is a portion of the uneven oxide film 520 that is provided in the laser light non-irradiated area, i.e., the intermediate portion 529c. The thin film portion 520Y has a thinner film thickness of the uneven oxide film 520 and a lower height of the convex portions 520a than the thick film portion 520X. The thick film portion 520X is provided in the outer peripheral portion 529b. The thin film portion 520Y is provided in the intermediate portion 529c.

[0428] Since the protrusions 520a of the thick film portion 520X are higher than those of the thin film portion 520Y, the plug 30 becomes entangled therewith, creating an anchor effect. This also increases the contact area with the plug 30. This allows the plug 30 to adhere closely to the outer periphery 529b. The thick film portion 520X is sometimes referred to as a roughened portion or an adhesive portion.

[0429] The sintered member 100A is made of Ag or Cu, similar to the sintered member 101A described in the previous embodiment. The sintered member 100A is a sintered body made of Ag particles or Cu particles. The sintered member 100A can be bonded at a lower temperature than solder. The sintered member 100A is formed by heating and pressurizing a sintered sheet or sintering paste. In a plan view, the sintered member 100A extends beyond the outer peripheral edge 402 of the semiconductor element 40. The sintered member 100A is arranged so as to overlap the mounting portion 529a and the intermediate portion 529c. In this embodiment, the outer peripheral edge of the sintered member 100A is substantially aligned with the outer peripheral edge of the intermediate portion 529c. In a plan view, the sintered member 100A overlaps the entire mounting portion 529a and the entire intermediate portion 529c.

[0430] <Summary of the eleventh embodiment> As described above, the intermediate portion 529c has the thin film portion 520Y of the uneven oxide film 520. Due to the presence of the thin film portion 520Y, the intermediate portion 529c has lower wettability with solder than the mounting portion 529a. This makes it difficult for the solder to wet and spread from the mounting portion 529a toward the intermediate portion 529c.

[0431] In this embodiment, a sintered member 100A is used instead of solder. The sintered member 100A is formed by heating at a temperature lower than the melting point. Unlike solder, the sintered member 100A does not become molten during joining. Unlike solder, the sintered member 100A does not wet and spread over the surface of the surface metal body 52 during joining.

[0432] During pressure sintering, the sintered member 100A is spread between the opposing surfaces of the drain electrode 40D and the surface metal body 52. ​​By spreading, the sintered member 100A is positioned not only on the mounting portion 529a but also on the intermediate portion 529c. The sintered member 100A does not wet and spread, but is spread by pressure and comes into contact with the thin film portion 520Y. This allows not only the joint between the sintered member 100A and the mounting portion 529a, but also the contact portion between the sintered member 100A and the intermediate portion 529c to function as a heat dissipation path. As a result, a semiconductor device 20 with high heat dissipation properties can be provided. Furthermore, the sintered member 100A has a higher thermal conductivity than solder. This also enhances heat dissipation.

[0433] Furthermore, the height of the convex portion 520a of the thin film portion 520Y is lower than that of the thick film portion 520X. In other words, the adhesion of the intermediate portion 529c to the sealing body 30 is lower than that of the outer periphery 529b. This makes it difficult for the sealing body 30 to adhere to the intermediate portion 529c. In this embodiment, the sintered member 100A is in contact with the intermediate portion 529c. The sintered member 100A covers the portion of the upper surface 52a where the adhesion is low. This prevents the sealing body 30 from peeling off from the upper surface 52a around (near) the semiconductor element 40. This prevents thermal stress from concentrating on the joint portion of the sintered member 100A and the drain electrode 40D, thereby improving connection reliability.

[0434] In this embodiment, the entire intermediate portion 529c is located outside the semiconductor element 40. This allows the joint between the sintered member 100A and the mounting portion 529a to be larger. In addition, the contact portion between the sintered member 100A located outside the semiconductor element 40 and the intermediate portion 529c also functions as a heat dissipation path. This further improves heat dissipation.

[0435] <Modification> Although an example has been shown in which the sintered member 100A overlaps the entire intermediate portion 529c, this is not limiting. The sintered member 100A only needs to overlap at least a portion of the intermediate portion 529c. In other words, the sintered member 100A only needs to be in contact with at least a portion of the thin film portion 520Y of the uneven oxide film 520. This expands the heat dissipation path and improves heat dissipation.

[0436] The arrangement of the intermediate portion 529c is not limited to the above example. Only a portion of the intermediate portion 529c in the width direction may be located outside the semiconductor element 40. By providing at least a portion of the intermediate portion 529c in the width direction outside the semiconductor element 40, the joint area can be enlarged and the heat dissipation path can be expanded. This improves heat dissipation.

[0437] Furthermore, at least a portion of the intermediate portion 529c in the width direction may be located inside the outer peripheral edge 402 of the semiconductor element 40. In this way, the sintered member 100A comes into contact with the thin film portion 520Y (intermediate portion 529c), thereby improving heat dissipation, and the position of the outer peripheral portion 529b can be brought closer to the semiconductor element 40. In other words, peeling of the sealing body 30 around the semiconductor element 40 can be suppressed.

[0438] In the example shown in FIGS. 100 and 101, the intermediate portion 529c straddles the outer peripheral edge 402 of the semiconductor element 40 in a plan view. That is, a portion of the intermediate portion 529c in the width direction is located outside the outer peripheral edge 402, and another portion is located inside the outer peripheral edge 402. The sintered member 100A overlaps the entire mounting portion 529a and the entire intermediate portion 529c in a plan view. This makes it possible to improve heat dissipation as described above and prevent peeling of the sealing body 30 around the semiconductor element 40. FIGS. 100 and 101 are diagrams showing modified examples. FIG. 100 corresponds to FIG. 97, and FIG. 101 corresponds to FIG. 98.

[0439] In the example shown in FIGS. 102 and 103, the outer peripheral edge of the intermediate portion 529c substantially coincides with the outer peripheral edge 402 of the semiconductor element 40 in a planar view. The outer peripheral edge of the sintered member 100A also substantially coincides with the outer peripheral edge 402 of the semiconductor element 40 in a planar view. This positions the outer peripheral portion 529b (thick film portion 520X) adjacent to the semiconductor element 40 in a planar view. Therefore, contact of the sintered member 100A with the intermediate portion 529c improves heat dissipation, while more effectively preventing peeling of the sealing body 30 around the semiconductor element 40. FIGS. 102 and 103 are diagrams showing modified examples. FIG. 102 corresponds to FIG. 97, and FIG. 103 corresponds to FIG. 98.

[0440] In the example shown in FIG. 104, a part of the outer peripheral portion 529b overlaps with the semiconductor element 40 in a plan view. The middle portion 529c is located inside the outer peripheral edge 402 of the semiconductor element 40. FIG. 104 is a diagram showing a modified example. FIG. 104 corresponds to FIG. 98. In this case, the sintered member 100A may be in contact with only the thin film portion 520Y. The sintered member 100A may be in contact with the thin film portion 520Y and the portion of the thick film portion 520X directly below the semiconductor element 40.

[0441] Although the example has been shown in which the uneven oxide film 520 is provided only on the surface metal body 52 to which the drain electrode 40D is connected, this is not limiting. In addition to the surface metal body 52, the uneven oxi...

Claims

1. a wiring member (50) having an insulating substrate (51), a front metal body (52) disposed on a front surface of the insulating substrate, and a back metal body (53) disposed on a surface of the insulating substrate opposite to the front surface; a semiconductor element (40) disposed on the wiring member, the semiconductor element having: a first main electrode (40D) provided on one surface and electrically connected to the front surface metal body; a second main electrode (40S) provided on a back surface opposite to the one surface in the plate thickness direction; and a plurality of signal pads (40P) provided on the back surface at positions different from the second main electrode; A plurality of signal terminals (93); an interconnection substrate (150) disposed on the wiring member, having a plurality of surface lands (152a) provided on a surface opposite to a surface facing the wiring member, and positioned midway between the semiconductor element and the signal terminal; a bonding wire (110) electrically connecting the pad and the corresponding surface land; a resin molded body, and a sealing body (30) that seals the semiconductor element, at least a portion of the wiring member, a portion of the signal terminal, the relay substrate, and the bonding wires; The surface metal body has a wiring portion (54, 55) on which the semiconductor element is disposed and to which the first main electrode is electrically connected, and an island portion (58) on which the relay substrate is disposed and which is electrically isolated from the wiring portion, the relay board has a plurality of the front surface lands, a back surface land (152e) provided on a surface facing the island portion and electrically connected to the island portion, and connection portions (152c, 152d, 152f) that electrically connect some of the plurality of front surface lands to the back surface lands, The island portion is fixed to a predetermined potential via the back surface land, the connection portion, and a part of the front surface land.

2. a plurality of the semiconductor elements; The plurality of semiconductor elements are arranged on the common wiring portion and are electrically connected in parallel to one another, 2. The semiconductor device according to claim 1, wherein the pads of the plurality of semiconductor elements are electrically connected to the surface lands of the common relay substrate.

3. The plurality of semiconductor elements are arranged in a first direction perpendicular to the plate thickness direction, the relay substrate is arranged to be aligned with the semiconductor element in a second direction perpendicular to the plate thickness direction and the first direction, In each semiconductor element, the pads are arranged side by side in the first direction along the side of the intermediate substrate, the plurality of surface lands are provided to correspond one-to-one to the pads of the plurality of semiconductor elements; 3. The semiconductor device according to claim 2, wherein the connection positions of the bonding wires on the plurality of surface lands are set so that the closer the connection positions of the bonding wires to the corresponding pads in the first direction, the farther the connection positions are from the corresponding pads in the second direction.

4. the plurality of surface lands each have a shape whose longitudinal direction is in the second direction in a plan view in the plate thickness direction and are arranged in a line along the first direction, 4. The semiconductor device according to claim 3, wherein the closer the connection positions of the bonding wires on the plurality of surface lands are to the corresponding pads in the first direction, the farther the connection positions are from the corresponding pads in the second direction.

5. 4. The semiconductor device according to claim 3, wherein the front surface lands are provided at positions farther from the corresponding pads in the second direction as the front surface lands are closer to the corresponding pads in the first direction.

6. The plurality of semiconductor elements are arranged in a first direction perpendicular to the plate thickness direction, the pads are arranged along opposing sides of the adjacent semiconductor elements in a second direction perpendicular to the thickness direction and the first direction, The relay substrate has a plurality of surface lands, each of which includes a plurality of first lands provided to correspond one-to-one with the pads of the plurality of semiconductor elements, a plurality of second lands (152b) provided separately from the first lands on a surface opposite to the surface facing the wiring member and electrically connected to the corresponding first lands, a base (151h) on which the second lands are provided and arranged to be aligned with the semiconductor elements in the second direction, and an extension (151i) extending from the base in the second direction, arranged between adjacent semiconductor elements, and on which the first lands are provided, The semiconductor device according to claim 2 , wherein the signal terminal is electrically connected to the second land.

7. 7. The semiconductor device according to claim 4, wherein the lengths of the bonding wires are equal to each other in the relay substrate common to the semiconductor elements.

8. The plurality of semiconductor elements are arranged in a first direction perpendicular to the plate thickness direction, the relay substrate is arranged to be aligned with the semiconductor element in a second direction perpendicular to the plate thickness direction and the first direction, In each semiconductor element, the pads are arranged side by side in the first direction along the side of the intermediate substrate, the relay board has a plurality of surface lands, the number of which is the same as the number of types of pads that the plurality of semiconductor elements have; Each of the plurality of surface lands extends in the first direction, and the plurality of surface lands are arranged side by side in the second direction, 3. The semiconductor device according to claim 2, wherein the pads of the same type in the plurality of semiconductor elements are connected to the common surface land via the bonding wires, respectively.

9. The relay substrate is connected to the island portion via a bonding material (154), 9. The semiconductor device according to claim 1, wherein the back surface land has a slit (152s).

10. a second bonding wire (114) that electrically connects the relay substrate and the signal terminal and is sealed in the sealing body, in addition to the first bonding wire that electrically connects the semiconductor element and the relay substrate; 10. The semiconductor device according to claim 1, wherein the second bonding wire is thicker than the first bonding wire.

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