Electro-optical device and electronic apparatus

Abstract

To provide an electro-optical device that can achieve a high-definition electro-optical device, and an electronic apparatus.SOLUTION: An electro-optical device 1 comprises: a supply circuit 40a that corresponds to one light emitting element; and a supply circuit 40b that corresponds to the other light emitting element and is provided in a first direction with respect to the supply circuit 40a in plan view, and each of the supply circuits 40a, 40b includes a transistor 121 that drives the corresponding light emitting element. The electro-optical device 1 includes a conductive layer 60 that is electrically connected with the two transistors 121, supplied with a potential Vel being a constant potential, and provided along a second direction intersecting with the first direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] Conventionally, as shown in Patent Document 1, a display device is known in which pixels, each having a light-emitting section and a drive circuit for driving the light-emitting section, are arranged in a matrix, and the mth pixel and the (m+1)th pixel in the column direction are arranged symmetrically with respect to a boundary line extending in the row direction between the mth pixel and the (m+1)th pixel, and a shield wall is formed on the boundary line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-102319 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the display device described in Patent Document 1, wiring electrically connected to the drive circuit, such as control lines and power supply wiring, is provided for each column or each row, which poses the problem that it is not possible to provide a higher-resolution display device. [Means for solving the problem]

[0005] The electro-optical device comprises a first light-emitting element and a second light-emitting element, a first driving transistor corresponding to the first light-emitting element, a second driving transistor corresponding to the second light-emitting element and arranged in a first direction relative to the first driving transistor in a planar view, and a first conductive layer electrically connected to the first driving transistor and the second driving transistor, supplied with a constant potential, and arranged along a second direction intersecting the first direction.

[0006] An electronic device includes the electro-optical device described above. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing the configuration of an electro-optical device according to a first embodiment. [Figure 2] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of a pixel circuit in the electro-optical device. [Figure 3] FIG. 2 is a plan view showing the layout of gate electrodes and impurity regions in a supply circuit. [Figure 4] FIG. 4 is a plan view showing the layout of a first wiring layer in a supply circuit. [Figure 5] 5 is a cross-sectional view taken along line AA in FIG. 4. [Figure 6] FIG. 5 is a cross-sectional view taken along line BB in FIG. 4. [Figure 7] 5 is a cross-sectional view taken along line CC in FIG. 4. [Figure 8] FIG. 5 is a cross-sectional view taken along line DD in FIG. [Figure 9] FIG. 10 is a plan view showing the layout of gate electrodes and impurity regions in a supply circuit according to the second embodiment. [Figure 10] FIG. 10 is a plan view showing the layout of a first wiring layer in a supply circuit according to a second embodiment. [Figure 11] 11 is a cross-sectional view taken along line AA in FIG. 10. [Figure 12] FIG. 10 is a plan view showing the layout of gate electrodes and impurity regions in a supply circuit according to a third embodiment. [Figure 13] FIG. 11 is a plan view showing the layout of a first wiring layer in a supply circuit according to a third embodiment. [Figure 14] 14 is a cross-sectional view taken along line AA in FIG. 13. [Figure 15] FIG. 1 is a plan view schematically showing a part of a virtual image display device that is an example of an electronic device. [Figure 16] FIG. 1 is a perspective view showing a personal computer as an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are examples of the present invention. The present invention is not limited to the following embodiments.

[0009] In the following drawings, the scale of each layer and each component is different from the actual size in order to make each layer and each component large enough to be recognizable. In the following description, for example, the expression "on the substrate" with respect to a substrate means that the layer and each component are disposed in contact with the substrate, that the layer and each component are disposed on the substrate via another structure, or that the layer and each component are disposed on the substrate in contact with the substrate and via another structure.

[0010] 1A. Embodiment 1 An organic EL (electroluminescence) device is exemplified as the electro-optical device according to embodiment 1. This organic EL device is suitable for use in, for example, a head mounted display (HMD) as an electronic device, which will be described later. An overview of the electro-optical device 1 according to this embodiment will be described with reference to FIGS. 1 and 2.

[0011] As shown in FIG. 1, the electro-optical device 1 of this embodiment includes a display panel 10 having a plurality of pixel circuits 100 (described later), and a control circuit 20 that controls the operation of the display panel 10.

[0012] Digital image data Video is supplied to the control circuit 20 from a higher-level device (not shown) in synchronization with a synchronization signal. Here, the image data Video is digital data that defines the gradation level to be displayed by each pixel circuit 100 of the display panel 10. The synchronization signal is a signal that includes a vertical synchronization signal, a horizontal synchronization signal, a dot clock signal, etc.

[0013] The control circuit 20 generates a control signal Ctr that controls the operation of the display panel 10 based on the synchronization signal, and supplies the generated control signal Ctr to the display panel 10. The control circuit 20 also generates an analog image signal Vid based on image data Video, and supplies the generated image signal Vid to the display panel 10. Here, the image signal Vid is a signal that defines the brightness of the light-emitting element provided in each pixel circuit 100 so that the pixel circuit 100 displays the gradation specified by the image data Video.

[0014] The display panel 10 includes a display section 13 having M scanning lines 12 extending along the X axis, 3N data lines 14 extending along the Y axis intersecting the X axis, and M×3N pixel circuits 100 arranged corresponding to the intersections of the M scanning lines 12 and the 3N data lines 14, and a drive circuit 11 that drives the display section 13. Here, M and N are each independent natural numbers greater than or equal to 1.

[0015] In the following description, in order to distinguish the multiple pixel circuits 100, the multiple scanning lines 12, and the multiple data lines 14 from one another, they will be referred to as the first row, the second row, ..., the Mth row in the -Y direction, and as the first column, the second column, ..., the 3Nth column in the +X direction.

[0016] The plurality of pixel circuits 100 provided in the display unit 13 include pixel circuits 100 capable of displaying red (R), pixel circuits 100 capable of displaying green (G), and pixel circuits 100 capable of displaying blue (B). In the electro-optical device 1, it is assumed, as an example, that, of the 1st to 3Nth columns, pixel circuits 100 capable of displaying R are arranged in the (3n-2)th column, pixel circuits 100 capable of displaying G are arranged in the (3n-1)th column, and pixel circuits 100 capable of displaying B are arranged in the 3nth column, where n is a natural number satisfying 1≦n≦N. The drive circuit 11 includes a scanning line drive circuit 111 and a data line drive circuit 112.

[0017] The scanning line driving circuit 111 sequentially selects the scanning lines 12 from the first row to the Mth row. Specifically, during one frame period, the scanning line driving circuit 111 sets the scanning signals / Gwr(1) to / Gwr(M) output to each of the scanning lines 12 from the first row to the Mth row to a predetermined selection potential in turn for each horizontal scanning period, thereby sequentially selecting the scanning lines 12 row by row for each horizontal scanning period. In other words, during the mth horizontal scanning period of one frame period, the scanning line driving circuit 111 sets the scanning signal / Gwr(m) output to the mth scanning line 12 to a predetermined selection potential, thereby selecting the mth scanning line 12. Note that one frame period is the period during which the electro-optical device 1 displays one image.

[0018] The data line driving circuit 112 outputs analog data signals Vd(1) to Vd(3N) that define the gradation to be displayed by each pixel circuit 100 to 3N data lines 14 for each horizontal scanning period, based on the image signal Vid and the control signal Ctr supplied from the control circuit 20. In other words, the data line driving circuit 112 outputs a data signal Vd(k) to the data line 14 of the kth column in each horizontal scanning period.

[0019] In this embodiment, the image signal Vid output by the control circuit 20 is an analog signal, but the image signal Vid output by the control circuit 20 may be a digital signal. In this case, the data line driving circuit 112 performs D / A conversion on the image signal Vid to generate analog data signals Vd(1) to Vd(3N).

[0020] As shown in FIG. 2, the pixel circuit 100 includes a light-emitting element 3 and a supply circuit 40 that supplies a current to the light-emitting element 3. The light-emitting element 3 includes a pixel electrode 31, a light-emitting functional layer 32, and a counter electrode 33. The pixel electrode 31 functions as an anode that supplies holes to the light-emitting functional layer 32. The counter electrode 33 is electrically connected to a power supply wiring 118 that is set to a potential Vct, which is the power supply potential on the low potential side of the pixel circuit 100, and functions as a cathode that supplies electrons to the light-emitting functional layer 32. The holes supplied from the pixel electrode 31 and the electrons supplied from the counter electrode 33 recombine in the light-emitting functional layer 32, causing the light-emitting functional layer 32 to emit light.

[0021] Although details are omitted, a red color filter is disposed over the light-emitting element 3 of the pixel circuit 100 capable of emitting R. A green color filter is disposed over the light-emitting element 3 of the pixel circuit 100 capable of emitting G. A blue color filter is disposed over the light-emitting element 3 of the pixel circuit 100 capable of emitting B.

[0022] The supply circuit 40 includes P-channel transistors 121 to 124 and a capacitance element 132. In addition to the scanning signal / Gwr(i), control signals / Gcmp(i) and / Gel(i) are supplied to the supply circuit 40 in the i-th row from the scanning line drive circuit 111. The display panel 10 is provided with M-th row control lines 143 and M-th row control lines 144, and the scanning line drive circuit 111 supplies control signals / Gcmp(1), / Gcmp(2), / Gcmp(3), ..., / Gcmp(M) to the 1st, 2nd, 3rd, ..., Mth row control lines 143, respectively, and supplies control signals / Gel(1), / Gel(2), / Gel(3), ..., / Gel(M) to the 1st, 2nd, 3rd, ..., Mth row control lines 144, respectively.

[0023] A gate electrode G1 of the transistor 121 is electrically connected to one of the source / drain regions of the transistor 122. One of the source / drain regions of the transistor 121 is electrically connected to a power supply wiring 116 serving as a second conductive layer to which a constant potential Vel is supplied, and the other of the source / drain region of the transistor 121 is electrically connected to one of the source / drain regions of the transistor 123 and one of the source / drain regions of the transistor 124. One end of the capacitance element 132 is electrically connected to the gate electrode G1 of the transistor 121, and the other end of the capacitance element 132 is electrically connected to the power supply wiring 116 having a constant potential, for example, the potential Vel. Therefore, the capacitance element 132 holds the voltage between the gate electrode G1 and one of the source / drain regions of the transistor 121. The transistor 121 is an example of a drive transistor that passes a current according to the voltage between the gate electrode G1 and one of the source / drain regions of the transistor 121.

[0024] The capacitive element 132 may be, for example, a capacitance parasitic on the gate electrode G1 of the transistor 121, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate.

[0025] The transistor 122 of the supply circuit 40 in the i-th row and any column has a gate electrode G2 electrically connected to the i-th row scanning line 12, one of the source / drain regions electrically connected to the gate electrode G1 of the transistor 121, and the other of the source / drain region connected to the data line 14 of the column.

[0026] The transistor 123 of the supply circuit 40 in the i-th row and in any column has a gate electrode G3 electrically connected to a control line 143 to which a control signal / Gcmp(i) is supplied, one of the source / drain regions electrically connected to the other of the source / drain region of the transistor 121 and one of the source / drain regions of the transistor 124, and the other of the source / drain region electrically connected to the data line 14 of the column.

[0027] The transistor 124 of the supply circuit 40 in the i-th row and in any column has a gate electrode G4 electrically connected to a control line 144 to which a control signal / Gel(i) is supplied, one of the source / drain regions electrically connected to the other of the source / drain region of the transistor 121 and one of the source / drain regions of the transistor 123, and the other of the source / drain region electrically connected to the pixel electrode 31 which is the anode of the light-emitting element 3.

[0028] The counter electrode 33, which functions as the cathode of the light-emitting element 3, is electrically connected to a power supply wiring 118 at a potential Vct. Since the display panel 10 is formed on a silicon substrate, the substrate potential of the transistors 121 to 124 is set to a potential equivalent to, for example, the potential Vel.

[0029] The source and drain regions of the transistors 121 to 124 may be interchanged depending on the channel type and potential relationship of the transistors 121 to 124. The transistors 121 to 124 may be thin film transistors or field effect transistors.

[0030] Next, the structure of the pixel circuit 100, particularly the supply circuit 40, will be described with reference to Figures 3 to 8. In this embodiment, a P-type semiconductor substrate, which is a silicon substrate, is used as the substrate. An N-well 170 is formed over almost the entire surface of the substrate.

[0031] A potential Vel is supplied to the N-well 170 via an N-type diffusion region. In addition, a plurality of P-type diffusion regions are formed by doping impurities into the surface of the N-well 170. The P-type diffusion regions can function as one or the other of the source / drain regions of the transistors 121 to 124. In this embodiment, the P-type diffusion regions and the N-type diffusion regions are collectively referred to as impurity regions 180.

[0032] 3 is a plan view showing the layout of gate electrodes G1 to G4 and impurity regions 180 in three supply circuits 40a to 40f arranged adjacent to each other in the X-axis direction and two supply circuits 40a to 40f arranged adjacent to each other in the Y-axis direction. The gate electrodes G1 to G4 are formed on a partial region of a silicon semiconductor substrate via a gate insulating film L0, and impurity regions 180 that become source / drain regions are formed in the semiconductor substrate on both sides of the gate electrodes G1 to G4, thereby forming transistors 121 to 124.

[0033] FIG. 4 is a plan view showing the layout of the first wiring layer M1 (see FIG. 5) in the supply circuits 40a to 40f shown in FIG. 3, with the layout of the first wiring layer M1 shown on the layout of the gate electrodes G1 to G4 and the impurity region 180. The first wiring layer M1 is formed on a semiconductor substrate on which the transistors 121 to 124 are formed, with an interlayer insulating layer L1 interposed therebetween. For example, the interlayer insulating layer L1 is formed of silicon dioxide, and the first wiring layer M1 is formed of aluminum. In addition, the squares with crosses in the figure represent contact holes provided in the interlayer insulating layer L1 to connect the wiring of each layer to the upper layer.

[0034] FIG. 5 is a cross-sectional view taken along line AA in FIG. 4. FIG. 6 is a cross-sectional view taken along line BB in FIG. 4. FIG. 7 is a cross-sectional view taken along line CC in FIG. 4. FIG. 8 is a cross-sectional view taken along line DD in FIG. 4. In FIGS. 5 to 8, up to the first wiring layer M1 is shown, and upper layer structures are omitted. Furthermore, since the configuration of the six supply circuits 40a to 40f is substantially the same in each row, the reference numerals assigned to the components are omitted as appropriate. Note that, from here on, of the supply circuits 40a to 40f, the explanation will be mainly focused on supply circuits 40a and 40b, but supply circuits 40c and 40d and supply circuits 40e and 40f also have similar configurations.

[0035] As shown in FIGS. 3 to 8, the supply circuits 40a to 40f include transistors 121 to 124, respectively. Furthermore, in a plan view, a conductive layer 60 is provided as a first conductive layer along the X-axis direction between the supply circuits 40a and 40b, which are adjacent to each other in the Y-axis direction. That is, the conductive layer 60 is provided across both the supply circuits 40a and 40b. The conductive layer 60 is a conductive layer to which a constant potential Vel is supplied and is electrically connected to the transistor 121 included in the supply circuit 40a and the transistor 121 included in the supply circuit 40b. The conductive layer 60 is provided in the same layer as the gate electrodes G1 to G4 of the transistors 121 to 124. Hereinafter, the Y-axis direction will also be referred to as the "first direction," and the X-axis direction intersecting the Y-axis direction will also be referred to as the "second direction."

[0036] Specifically, the conductive layer 60 is electrically connected to a power supply wiring 116 provided in the first wiring layer M1 via a contact hole Ha1. That is, the same potential is supplied to the conductive layer 60 and the power supply wiring 116. Furthermore, the power supply wiring 116 is electrically connected to a region SD1 of the impurity region 180, which will become one of the source / drain regions of the transistor 121, via a contact hole Ha2. That is, the conductive layer 60 is electrically connected to the region SD1, which will become one of the source / drain regions of the transistor 121, via the power supply wiring 116.

[0037] In addition, in plan view, the conductive layer 60 is provided between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b.

[0038] In addition, in a plan view, the distance H1 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40a is equal to the distance H2 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40b.

[0039] In addition, in two supply circuits 40a, 40b arranged adjacent to each other in the first direction in a plan view, the transistors 121 to 124 are arranged symmetrically with respect to an imaginary line P that overlaps with the conductive layer 60 and extends in the second direction. In the present disclosure, the imaginary line P refers to an imaginary straight line that passes through the center of the conductive layer 60 and extends along the second direction in a plan view. However, the imaginary line P may also be a straight line that passes through a position shifted from the center of the conductive layer 60.

[0040] Of the four transistors 121 to 124 included in each of the supply circuits 40a and 40b, it is desirable that the transistors 121 are arranged line-symmetrically with respect to the imaginary line P, but the transistors 122 to 124 do not have to be line-symmetrical.

[0041] In addition, in plan view, a portion of the impurity region 180 overlaps with the conductive layer 60 and extends along the second direction.

[0042] 3 and 5, the impurity region 180 includes a region SD1 that becomes one of the source / drain regions of the transistors 121 included in the supply circuits 40a to 40f, and is electrically connected to the power supply wiring 116 via a contact hole Ha2. That is, the impurity region 180 is electrically connected to the conductive layer 60 via the power supply wiring 116, and a potential Vel is supplied to the impurity region 180. Although not shown in the drawings, the impurity region 180 is provided across the second direction of the display unit 13.

[0043] 4 to 8, the scanning lines 12, the control lines 143 and 144, the relay lines 64, and the power supply lines 16 are formed in a first wiring layer M1 together with the power supply lines 116. The scanning lines 12 are provided for each row along the second direction, and are electrically connected to the gate electrodes G2 of the transistors 122 included in each of the supply circuits 40a to 40f via contact holes Ha3.

[0044] The control line 143 is provided for each row along the second direction, and is electrically connected to the gate electrode G3 of the transistor 123 included in each of the supply circuits 40a to 40f via a contact hole Ha4.

[0045] The control line 144 is provided for each row along the second direction, and is electrically connected to the gate electrode G4 of the transistor 124 included in each of the supply circuits 40a to 40f via a contact hole Ha5.

[0046] The relay wiring 64 is provided for each supply circuit 40. The relay wiring 64 is electrically connected to the gate electrode G1 of the transistor 121 via a contact hole Ha7, and is electrically connected to one of the source / drain regions of the transistor 122 via a contact hole Ha8.

[0047] The power supply wiring 16 is a conductive layer to which a constant potential, for example, a potential Vel, is supplied. The power supply wiring 16 is provided for each row along the second direction, and a portion of the power supply wiring 16 extends in the first direction and is arranged between the relay wirings 64 of the supply circuits 40 adjacent to each other in the second direction in plan view. That is, in plan view, the power supply wiring 16 is arranged between the relay wirings 64 of the supply circuits 40a and 40c, and between the relay wirings 64 of the supply circuits 40a and 40e, and further between the relay wirings 64 of the supply circuits 40b and 40d, and between the relay wirings 64 of the supply circuits 40b and 40f.

[0048] The power supply wiring 116 is provided in the second direction across both the row including the supply circuit 40a and the row including the supply circuit 40b. In plan view, the power supply wiring 116 is electrically connected to a region SD1 that serves as one of the source / drain regions of the transistors 121 included in each of the supply circuits 40a to 40f via a contact hole Ha2. In plan view, the power supply wiring 116 overlaps with the conductive layer 60. In plan view, the power supply wiring 116 overlaps with the impurity region 180.

[0049] Furthermore, in a plan view, at least a part of the power supply wiring 116 is provided between the gate electrode G1 of the transistor 121 included in each of the supply circuits 40a, 40c, and 40e provided along the second direction and the gate electrode G1 of the transistor 121 included in each of the supply circuits 40b, 40d, and 40f provided along the second direction. That is, in a plan view, at least a part of the power supply wiring 116 is provided between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b.

[0050] 3 and 4 show two supply circuits 40 arranged adjacent to each other in the first direction, but the layout of the other supply circuits 40 is similar to that of two supply circuits 40 arranged adjacent to each other in the first direction. Two supply circuits 40 arranged adjacent to each other in the second direction may have the same pattern repeated, or may be arranged symmetrically with respect to a virtual line. Note that the first and second directions in the layout of the supply circuits 40 are not limited to the X-axis and Y-axis directions shown in FIG. 1.

[0051] 5, the power supply wiring 116 is provided in the first wiring layer M1, and the conductive layer 60 is provided in a layer between the power supply wiring 116 and the impurity region 180. In other words, the power supply wiring 116 is provided on the opposite side of the conductive layer 60 from the impurity region 180. As described above, the impurity region 180 and the power supply wiring 116 are electrically connected via a contact hole Ha2. That is, the impurity region 180 and the power supply wiring 116 are electrically connected via a plurality of contact holes Ha2 provided at regular intervals in the second direction. As a result, the contact hole Ha2 is arranged between the conductive layers 60 of two supply circuits 40 adjacent to each other in the second direction.

[0052] 6, the relay wiring 64 is electrically connected to the gate electrode G1 of the transistor 121 included in each supply circuit 40 via a contact hole Ha7. In addition, a power supply wiring 16 is disposed between the relay wirings 64 of two supply circuits 40 adjacent to each other in the second direction. Note that the three power supply wirings 16 shown in FIG. 6 are the same wiring as shown in FIG. 4.

[0053] 7 and 8, the conductive layer 60 is provided in the same layer as the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b, and is provided between these two gate electrodes G1 in a planar view. However, the conductive layer 60 may be provided in a different layer from the gate electrode G1. In this case, it is also possible for a portion of the conductive layer 60 to overlap the gate electrode G1 in a planar view. In other words, it is sufficient that at least a portion of the conductive layer 60 is provided between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b in a planar view.

[0054] Although not shown, above the first wiring layer M1, there are provided a second wiring layer in which various signal lines and control lines such as the data lines 14 are arranged, a layer in which the pixel electrodes 31 of the light-emitting elements 3 are arranged, a layer in which the light-emitting functional layers 32 of the light-emitting elements 3 are arranged, and a layer in which the counter electrodes 33 of the light-emitting elements are arranged. However, the configuration is not limited to the above, and wiring layers may be added or deleted as appropriate.

[0055] As described above, the electro-optical device 1 includes a conductive layer 60 that is electrically connected to the transistor 121 included in the supply circuit 40a and the transistor 121 included in the supply circuit 40b and that is supplied with a constant potential Vel. In other words, the two supply circuits 40 provided along the first direction are electrically connected to the same conductive layer, which reduces the number of wires provided in the electro-optical device 1 and enables the overall size of the supply circuit 40 to be reduced, thereby achieving a high-definition electro-optical device 1.

[0056] Furthermore, as described above, in plan view, at least a portion of the conductive layer 60 is provided between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b. This makes it possible to suppress the influence of interference occurring between the two gate electrodes G1 provided along the first direction, thereby improving the display quality of the electro-optical device 1.

[0057] Furthermore, as described above, in plan view, the distance H1 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40a is equal to the distance H2 between the conductive layer 60 and the gate electrode G1 of the transistor 121 included in the supply circuit 40b. Therefore, it is possible to reduce variations in the degree to which the conductive layer 60 suppresses the parasitic capacitance generated in each supply circuit 40.

[0058] Furthermore, as described above, in plan view, the transistor 121 included in the supply circuit 40a and the transistor 121 included in the supply circuit 40b are arranged symmetrically with respect to the imaginary line P that overlaps the conductive layer 60 and extends in the second direction, thereby enabling an efficient layout.

[0059] As described above, the conductive layer 60 is provided in the same layer as the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40b. This makes it possible to suppress the influence of interference occurring between the two gate electrodes G1 provided along the first direction, thereby improving the display quality of the electro-optical device 1.

[0060] As described above, the electro-optical device 1 includes the impurity region 180 to which the same potential as that of the conductive layer 60 is supplied, and in plan view, the impurity region 180 overlaps with the conductive layer 60. Therefore, the conductive layer 60 and the impurity region 180 suppress the influence of interference occurring between the two gate electrodes G1 provided along the first direction, thereby improving the display quality of the electro-optical device 1.

[0061] As described above, the electro-optical device 1 includes the power supply wiring 116, which is supplied with the same potential as the conductive layer 60 and is provided on the opposite side of the conductive layer 60 from the impurity region 180, and the power supply wiring 116 overlaps the conductive layer 60 in plan view. Therefore, the conductive layer 60, the impurity region 180, and the power supply wiring 116 suppress the influence of interference occurring between the two gate electrodes G1 provided along the first direction, thereby improving the display quality of the electro-optical device 1.

[0062] As described above, the power supply wiring 116 is electrically connected to the conductive layer 60 through the contact hole Ha1, and is electrically connected to the impurity region 180 through the contact hole Ha2. Therefore, the contact holes Ha1 and Ha2 suppress the influence of interference occurring between the two gate electrodes G1 provided along the first direction, thereby improving the display quality of the electro-optical device 1.

[0063] As described above, the impurity region 180 includes one of the source / drain regions of the transistor 121 included in the supply circuit 40a and one of the source / drain regions of the transistor 121 included in the supply circuit 40b. Therefore, there is no need to provide a separate region, which makes it possible to reduce the size of the entire supply circuit 40 and realize a high-definition electro-optical device 1.

[0064] In the above embodiment, if the transistor 121 included in the supply circuit 40a is a first drive transistor, the light-emitting element 3 corresponding to this transistor 121 corresponds to the first light-emitting element, and the gate electrode G1 of this transistor 121 corresponds to the first gate electrode. In this case, the transistor 121 included in the supply circuit 40b provided in the first direction with respect to the supply circuit 40a corresponds to the second drive transistor, the light-emitting element 3 corresponding to this transistor 121 corresponds to the second light-emitting element, and the gate electrode G1 of this transistor 121 corresponds to the second gate electrode. In addition, the contact hole Ha1 corresponds to the first contact hole, and the contact hole Ha2 corresponds to the second contact hole.

[0065] 1B. Embodiment 2 A description will be given of embodiment 2. In the following examples, for components whose functions are similar to those of embodiment 1, the reference numerals used in the description of embodiment 1 will be used and detailed description of each will be omitted as appropriate.

[0066] Fig. 9 is a plan view showing the layout of gate electrodes G1 to G4 and impurity regions 180 in three supply circuits 40a to 40f arranged adjacent to each other in the X-axis direction and two supply circuits 40a to 40f arranged adjacent to each other in the Y-axis direction in the electro-optical device 1 of Embodiment 2. Fig. 10 is a plan view showing the layout of a first wiring layer M1 in the supply circuits 40a to 40f shown in Fig. 9, with the layout of the first wiring layer M1 shown on the layout of the gate electrodes G1 to G4 and the impurity regions 180. Fig. 11 is a cross-sectional view taken along line AA in Fig. 10. In Embodiment 1, the conductive layer 60 was divided into columns in which the supply circuits 40 are provided. However, in this embodiment, a conductive layer 61 is provided whose width along the second direction in plan view corresponds to the width of the three supply circuits 40a, 40c, and 40e.

[0067] As shown in Figures 9 to 11, in a planar view, the conductive layer 61 is a conductive layer to which a potential Vel is supplied, and is electrically connected to the transistor 121 included in the supply circuit 40a, the transistor 121 included in the supply circuit 40b, the transistor 121 included in the supply circuit 40c, the transistor 121 included in the supply circuit 40d, the transistor 121 included in the supply circuit 40e, and the transistor 121 included in the supply circuit 40f.

[0068] Specifically, the width of the conductive layer 61 in the second direction corresponds to the width of the three supply circuits 40a, 40c, and 40e arranged side by side in the second direction. That is, in this embodiment, the conductive layer 61 is divided into three columns, each column including the supply circuits 40.

[0069] In this embodiment, the width of the conductive layer 61 in the second direction is wider than that of the conductive layer 60 in the first embodiment, and therefore the number of contact holes Ha2 for electrically connecting the impurity region 180 and the power supply wiring 116 is reduced.

[0070] According to this embodiment, the conductive layer 61 has a wide width along the second direction, which can suppress the influence of interference between two gate electrodes G1 arranged along the first direction in plan view and the influence of interference between two gate electrodes G1 arranged along the third direction (the A-axis direction shown in FIG. 1 ) and the fourth direction (the B-axis direction shown in FIG. 1 ) in plan view. For example, the conductive layer 61 can suppress the influence of interference between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40d. Furthermore, for example, the conductive layer 61 can suppress the influence of interference between the gate electrode G1 of the transistor 121 included in the supply circuit 40a and the gate electrode G1 of the transistor 121 included in the supply circuit 40f.

[0071] 1C. Embodiment 3 A description will be given of embodiment 3. In the following examples, for components whose functions are similar to those of embodiment 1, the reference numerals used in the description of embodiment 1 will be used and detailed description of each will be omitted as appropriate.

[0072] 12 is a plan view showing the layout of gate electrodes G1 to G4 and impurity regions 180 in a plurality of supply circuits 40 arranged in the X-axis direction in the display unit 13 and in two supply circuits 40 arranged adjacent to each other in the Y-axis direction in the electro-optical device 1 of Embodiment 3. FIG. 13 is a plan view showing the layout of a first wiring layer M1 in the supply circuit 40 shown in FIG. 12, with the layout of the first wiring layer M1 shown on the layout of the gate electrodes G1 to G4 and the impurity regions 180. FIG. 14 is a cross-sectional view taken along line AA in FIG. 13. In Embodiment 1, the conductive layer 60 was divided into columns in which the supply circuits 40 are provided, but this embodiment includes a conductive layer 62 whose width in the second direction in a plan view corresponds to the width of the display unit 13.

[0073] As shown in Figures 12 to 14, the conductive layer 62 is a conductive layer to which a potential Vel is supplied, and in a planar view, is provided across the second direction of the display unit 13 and is provided between the gate electrodes G1 of the transistors 121 included in each of two supply circuits 40 adjacent to each other in the first direction.

[0074] Since the conductive layer 62 is provided across the display unit 13 in the second direction, the impurity region 180 and the power supply wiring 116 are not electrically connected within the display unit 13. The impurity region 180 and the power supply wiring 116 are electrically connected outside the display unit 13 via contact holes Ha10 or the like.

[0075] According to this embodiment, since the width of the conductive layer 62 in the second direction is large, it is possible to suppress the influence of interference occurring between two gate electrodes G1 provided along the first direction in plan view and the influence of interference occurring between two gate electrodes G1 provided along the third direction (the A-axis direction shown in FIG. 1) or the fourth direction (the B-axis direction shown in FIG. 1) in plan view. Furthermore, the conductive layer 62 can suppress the influence of interference occurring in the gate electrodes G1 of the transistors 121 included in each of the plurality of supply circuits 40 provided on opposite sides of the conductive layer 62.

[0076] It should be noted that the "electro-optical device" is not limited to an organic EL device, but may also be an inorganic EL device using inorganic materials, or a μLED device.

[0077] 2.Electronic equipment The electro-optical device 1 of the above-described embodiment can be applied to various electronic devices.

[0078] 2-1. Head-mounted display Fig. 15 is a plan view schematically showing a portion of a virtual image display device 700, which is an example of an electronic device. The virtual image display device 700 shown in Fig. 15 is a head-mounted display that is worn on the viewer's head to display an image. The virtual image display device 700 includes the electro-optical device 1 described above, a collimator 71, a light guide 72, a first reflective volume hologram 73, a second reflective volume hologram 74, and a control unit 79. The light emitted from the electro-optical device 1 is emitted as image light LL.

[0079] The control unit 79 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 1. The collimator 71 is disposed between the electro-optical device 1 and the light guide 72. The collimator 71 converts the light emitted from the electro-optical device 1 into parallel light. The collimator 71 is composed of a collimator lens or the like. The light converted into parallel light by the collimator 71 enters the light guide 72.

[0080] The light guide 72 has a flat plate shape and is disposed so as to extend in a direction intersecting the direction of light incident through the collimator 71. The light guide 72 reflects and guides light therein. A light entrance through which the light enters and a light exit through which the light exits are provided on a surface 721 of the light guide 72 facing the collimator 71. A first reflection volume hologram 73 serving as a diffractive optical element and a second reflection volume hologram 74 serving as a diffractive optical element are disposed on a surface 722 of the light guide 72 opposite the surface 721. The second reflection volume hologram 74 is disposed closer to the light exit than the first reflection volume hologram 73. The first reflection volume hologram 73 and the second reflection volume hologram 74 have interference fringes corresponding to predetermined wavelength ranges and diffract and reflect light within the predetermined wavelength ranges.

[0081] In the virtual image display device 700 having such a configuration, the image light LL that enters the light guide 72 from the light inlet is repeatedly reflected and guided to the observer's pupil EY from the light outlet, allowing the observer to observe an image composed of a virtual image formed by the image light LL.

[0082] The virtual image display device 700 includes the aforementioned electro-optical device 1. The aforementioned electro-optical device 1 is small and has high definition. Therefore, by including the electro-optical device 1, it is possible to provide a virtual image display device 700 that is small, lightweight, and has excellent display quality.

[0083] 2-2.Personal Computers Fig. 16 is a perspective view showing a personal computer 400, which is an example of an electronic device of the present invention. The personal computer 400 shown in Fig. 16 includes an electro-optical device 1, a main body 403 provided with a power switch 401 and a keyboard 402, and a control unit 409. The control unit 409 includes, for example, a processor and memory, and controls the operation of the electro-optical device 1. The personal computer 400 includes the electro-optical device 1 described above. The electro-optical device 1 described above is small and has high resolution. Therefore, by including the electro-optical device 1, it is possible to provide a personal computer 400 that is small, lightweight, and has excellent display quality.

[0084] Examples of "electronic devices" equipped with the electro-optical device 1 include the virtual image display device 700 illustrated in FIG. 15 and the personal computer 400 illustrated in FIG. 16, as well as devices placed close to the eyes, such as digital scopes, digital binoculars, digital still cameras, and video cameras. Furthermore, "electronic devices" equipped with the electro-optical device 1 are applicable as mobile phones, smartphones, PDAs (Personal Digital Assistants), car navigation devices, and in-vehicle displays. Furthermore, "electronic devices" equipped with the electro-optical device 1 are applicable as lighting devices that emit light.

[0085] Although the present invention has been described above based on the illustrated embodiments, the present invention is not limited to these. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-described embodiments, and any configuration can be added. Furthermore, the present invention may be realized by combining any configuration of the above-described embodiments. [Explanation of symbols]

[0086] 1...electro-optical device, 3...light-emitting element, 10...display panel, 11...drive circuit, 12...scanning line, 13...display unit, 14...data line, 16...power supply wiring, 20...control circuit, 31...pixel electrode, 32...light-emitting functional layer, 33...counter electrode, 40, 40a, 40b, 40c, 40d, 40e, 40f...supply circuit, 60, 61, 62...conductive layer, 64...relay wiring, 71...collimator, 72...light guide, 73...first reflection type volume hologram, 74...second reflection type volume hologram, 79...control unit, 100...pixel circuit, 111...scanning line drive circuit, 112...data line drive circuit, 116, 118...power supply wiring, 121, 122, 123, 124...transistor, 132...capacitive element, 143, 144...control line, 170...N well, 180...impurity region, 400...personal computer, 401...power switch, 402...keyboard, 403...main body, 409...control unit, 700...virtual image display device, 721, 722...surface, G1, G2, G3, G4...gate electrode, Ha1, Ha2, Ha3, Ha4, Ha5, Ha7, Ha8, Ha10...contact hole, H1, H2...distance, L0...gate insulating film, L1...interlayer insulating layer, LL...image light, M1...first wiring layer, P...virtual line, SD1...area, Vct, Vel...potential.

Claims

1. a first light-emitting element and a second light-emitting element; a first driving transistor corresponding to the first light emitting element; a second driving transistor corresponding to the second light emitting element and provided in a first direction relative to the first driving transistor in a plan view; a first conductive layer electrically connected to the first driving transistor and the second driving transistor, to which a constant potential is supplied, and which is provided along a second direction intersecting the first direction; An electro-optical device comprising:

2. In a plan view, at least a portion of the first conductive layer is provided between a first gate electrode of the first driving transistor and a second gate electrode of the second driving transistor.

2. The electro-optical device according to claim 1.

3. In a plan view, a distance between the first conductive layer and the first gate electrode is equal to a distance between the first conductive layer and the second gate electrode.

3. The electro-optical device according to claim 2.

4. the first conductive layer is provided in the same layer as the first gate electrode and the second gate electrode; 4. The electro-optical device according to claim 2, wherein the first and second electrodes are electrically connected to each other.

5. In a plan view, the first driving transistor and the second driving transistor are arranged symmetrically with respect to a virtual line extending in the second direction and overlapping the first conductive layer.

5. The electro-optical device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. an impurity region provided along the second direction and supplied with the same potential as that of the first conductive layer; the impurity region overlaps with the first conductive layer in a plan view.

6. The electro-optical device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. a second conductive layer that is supplied with the same potential as that of the first conductive layer and is provided on the opposite side of the first conductive layer from the impurity region; In a plan view, the second conductive layer overlaps the first conductive layer.

7. The electro-optical device according to claim 6.

8. the second conductive layer is electrically connected to the first conductive layer through a first contact hole and is electrically connected to the impurity region through a second contact hole; 8. The electro-optical device according to claim 7.

9. the impurity region includes one of the source / drain regions of the first drive transistor and one of the source / drain regions of the second drive transistor; 9. The electro-optical device according to claim 6, wherein the first and second electrodes are arranged parallel to each other.

10. 10. An electronic device comprising the electro-optical device according to claim 1.

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