Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device having a structure capable of suppressing breakdown of a field insulating film and suppressing discontinuity of a gate lead portion.SOLUTION: A gate electrode 109 includes a gate extension 109a extending from an active region Ra to a peripheral region Rb, and thus extending onto an end 110a of a field insulating film 110. The end 110a of the field insulating film 110 onto which the gate extension 109a extends is inclined such that the thickness of the field insulating film 110 gradually increases from the active region Ra toward the peripheral region Rb.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a switching element having a gate electrode and a method for manufacturing the same. [Background technology]

[0002] Conventionally, Patent Document 1 discloses a technique for preventing a gate insulating film from being destroyed due to a high voltage generated during switching.

[0003] When switching a MOSFET from the on state to the off state, a current equivalent to the capacitance between the p-type base region and the n-type drift layer flows between the source and drain. This current increases as the time change in the drain voltage increases, i.e., as dV / dt increases. On the source electrode side, this current flows through the p-type base region and the p + The current flows through the p-type contact region, but not through the p-type base region or p + If the resistance of the p-type contact region is high, the resistance of the p-type base region and p-type + The potential of the p-type contact region rises. In other words, compared to the state where the gate voltage is 0V, the potential of the p-type base region and p + The potential of the type contact region becomes higher than that. This rise in potential applies a high voltage to the gate insulating film, which may destroy the gate insulating film. For this reason, Patent Document 1 devisees a structure in which the source contact hole is positioned to penetrate the field insulating film, thereby reducing the electric field strength applied to the gate insulating film and preventing the gate insulating film from being destroyed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-5278 Summary of the Invention [Problem to be solved by the invention]

[0005] Depending on the semiconductor device's structure and switching conditions, the potential rise can cause a potential difference between the top and bottom of the field insulating film, enough to destroy not only the gate insulating film but also the field insulating film formed on the semiconductor surface. In other words, a potential difference can occur between the semiconductor surface and the portion of the gate electrode that is disposed on the field insulating film, specifically, the gate lead portion that constitutes part of the gate liner of the gate electrode. While thickening the field insulating film is effective in preventing field insulating film breakdown, the gate lead portion is positioned so that it extends from the edge of the gate electrode onto the field insulating film due to the layout of the semiconductor device. Therefore, if the field insulating film is thick, the gate lead portion may become thin at the step during the formation of the gate electrode including the gate lead portion, potentially resulting in a step or discontinuity.

[0006] In view of the above, an object of the present invention is to provide a semiconductor device having a structure that can suppress breakdown of the field insulating film while suppressing discontinuity of the gate lead portion, and a method for manufacturing the same. [Means for solving the problem]

[0007] In order to achieve the above object, the invention described in claim 1 is a semiconductor device having an active region (Ra) in which a switching element is formed, a peripheral region (Rb) surrounding the periphery of the active region, and a pad arrangement region (Rc) in which pads (12a to 12d) are arranged, and the semiconductor substrate (101 to 106) in which a switching element having a gate electrode (109) with one direction as its longitudinal direction is formed in the active region, a field insulating film (110) formed on the semiconductor substrate in the peripheral region and pad arrangement region and having an end (110a) extending in a direction intersecting the longitudinal direction of the gate electrode, a gate extension portion (109a) extended from the gate electrode and extending from the active region to the peripheral region, thereby riding on the end of the field insulating film, and a gate pad (12d) included in a pad arranged in the pad arrangement region and connected to the gate electrode through the gate extension portion. The end of the field insulating film on which the gate lead-out portion rides is inclined so that the thickness of the field insulating film gradually increases from the active region toward the peripheral region, and the field insulating film arranged in the pad arrangement region has an end that extends along the active region, and the end that extends along the active region is not inclined with respect to the thickness direction of the field insulating film.

[0008] In this way, the end of the field insulating film located below the gate lead portion is inclined. This prevents the gate lead portion from becoming thin at the step at the end of the field insulating film. This prevents the gate lead portion from being disconnected by the step at the end of the field insulating film. This makes it possible to provide a semiconductor device with a structure that prevents the gate lead portion from being disconnected while maintaining a film thickness that does not cause dielectric breakdown in the field insulating film.

[0009] In addition, in the invention described in claim 1, the field insulating film arranged in the pad arrangement region has an end portion extending along the active region, and the end portion extending along the active region is not inclined with respect to the thickness direction of the field insulating film.

[0010] In this way, the end of the field insulating film arranged in the pad arrangement region that extends along the active region does not have the gate lead-out portion riding on it, and therefore the end can be structured not to be inclined with respect to the thickness direction of the field insulating film, i.e., can be oriented along the thickness direction of the field insulating film.

[0011] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 2 is a top view of the layout of a semiconductor chip that constitutes the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] This is a diagram showing the current flowing during switching and the portion where the highest voltage is applied to the field insulating film in the cross section shown in FIG. [Figure 6] 10 is a cross-sectional view showing the relationship between the width L of the thickness transition region at the end of the field insulating film and the thickness Tg of the gate electrode. FIG. [Figure 7A] 10A to 10C are cross-sectional views showing a step of forming a field insulating film in the method for manufacturing a semiconductor device. [Figure 7B] FIG. 7B is a cross-sectional view showing a patterning step of the field insulating film subsequent to FIG. 7A. [Figure 8] 5 is a cross-sectional view of a semiconductor device according to a second embodiment, corresponding to FIG. 3. FIG. [Figure 9A] 10A and 10B are cross-sectional views of a portion of the outer periphery region adjacent to the active region and a portion adjacent to the pad placement region in a process of forming the edge of the field insulating film into a stepped shape. [Figure 9B]9B is a cross-sectional view of a portion of the outer periphery region adjacent to the active region and a portion adjacent to the pad placement region in a gate electrode formation process performed after the process of FIG. 9A. FIG. [Figure 10] 10 is a cross-sectional view of a portion of the outer peripheral region adjacent to the active region and a portion adjacent to the pad arrangement region in a semiconductor device according to a third embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0014] (First embodiment) First, the configuration of a semiconductor device according to the first embodiment will be described with reference to FIGS.

[0015] 1, the semiconductor device of this embodiment is a semiconductor chip 10, in which a MOSFET with a trench gate structure is formed as a switching element. The semiconductor device has an active region Ra, a peripheral region Rb located outside the active region Ra, and a pad arrangement region Rc in which pads 12a to 12d are arranged, and a switching element is formed as a semiconductor element in the active region Ra.

[0016] As shown in Fig. 1, the semiconductor chip 10 has a rectangular plate-like top surface. An internal region including the central portion of the semiconductor chip 10, specifically the region surrounded by a rectangular shape in Fig. 1, is defined as an active region Ra. An outer peripheral region Rb is defined as an outer edge portion of the semiconductor chip 10 that is outside the active region Ra. Furthermore, an area outside the active region Ra and inside the peripheral region Rb that follows one side of the rectangular shape formed by the active region Ra is defined as a pad arrangement region Rc.

[0017] A temperature sensing element region 11 in which a temperature sensing element is formed is provided within the pad arrangement region Rc of the semiconductor chip 10, and a temperature rise caused by the heat generating element can be grasped based on the temperature detected by the temperature sensing element.

[0018] The portion indicated by a thick solid line in the peripheral region Rb surrounding the active region Ra is a gate liner 13 configured by a gate lead portion 109a of a gate electrode 109 (described later) in a vertical MOSFET and a gate wiring layer 113. In this embodiment, the gate liner 13 is disposed in the peripheral region Rb located on the periphery of the active region Ra.

[0019] The pad arrangement region Rc is provided with a plurality of pads 12a to 12d. In this embodiment, the pad arrangement region Rc is provided with, from the left side of the drawing, a cathode pad 12a, an anode pad 12b, a sense pad 12c, and a gate pad 12d. These are electrically connected to each part of the temperature sensor provided in the temperature sensor region 11 and each part of the vertical MOSFET provided in the active region Ra. Each of these pads 12a to 12d is connected to a bonding wire (not shown), thereby enabling electrical connection to the outside.

[0020] 2 to 4 show cross-sectional configurations of various parts of the semiconductor chip 10. FIG.

[0021] The semiconductor chip 10 has an n-type semiconductor layer made of SiC or Si. + A type substrate 101 is used, and n + On the main surface of the mold substrate 101, various components constituting the vertical MOSFET and the thermosensitive element are formed.

[0022] Specifically, as shown in Figure 2, + On the main surface of the substrate 101, n + The n-type substrate 101 has a lower impurity concentration than the n-type substrate 101. - A low concentration layer 102 is epitaxially grown. - n in the surface layer of the low concentration layer 102 +P-type deep layers 103 are formed at predetermined intervals at positions away from the n-type substrate 101. - A p-type base region 104 is formed on the low concentration layer 102 and the p-type deep layer 103, and an n-type base region 104 is formed on the p-type base region 104. + type source region 105 and p + A contact region 106 is formed. + The n-type source region 105 - The p-type low concentration layer 102 is formed on a portion corresponding to a region where the p-type deep layer 103 is not formed, and the p-type low concentration layer 102 is formed on a portion corresponding to a region where the p-type deep layer 103 is not formed. + The p-type contact region 106 is formed on a portion corresponding to the p-type deep layer 103 .

[0023] These n + Mold substrate 101, n - a p-type low concentration layer 102, a p-type deep layer 103, a p-type base region 104, and an n + type source region 105 and p + The n-type contact region 106 is a semiconductor substrate made of a semiconductor, and a gate trench 107 is formed in the surface layer of the semiconductor substrate. + through the p-type source region 105 and the p-type base region 104; - A gate trench 107 is formed so as to reach the low concentration layer 102. The p-type base region 104 and the n-type base region 105 are in contact with the side surfaces of the gate trench 107. + 2 is a vertical direction of the drawing, the direction normal to the drawing is the longitudinal direction, and the vertical direction of the drawing is the depth direction. Although only one gate trench 107 is shown in FIG. 2, multiple gate trenches 107 are arranged at equal intervals in the horizontal direction of the drawing, and are sandwiched between p-type deep layers 103 to form a stripe pattern.

[0024] Furthermore, the portion of the p-type base region 104 located on the side of the gate trench 107 becomes n-type when the vertical MOSFET is in operation. + type source region 105 and n -The gate trench 107 has a channel region connecting the low-concentration layer 102 and the gate insulating film 108. A gate electrode 109 made of doped poly-Si is formed on the surface of the gate insulating film 108, and the gate insulating film 108 and the gate electrode 109 are buried in the gate trench 107. Therefore, the gate electrode 109 also extends in the same direction as the longitudinal direction of the gate trench 107. This structure forms a trench gate structure.

[0025] 3, the trench gate structure extends in the left-right direction of the paper surface of FIG. 1. As shown in FIG. 3, the trench gate structure is formed so as to extend beyond the active region Ra. Also, n + The n-type source region 105 is formed. + The type source region 105 is formed in the active region Ra and not outside of it, so that a channel region is formed only within the active region Ra.

[0026] Furthermore, as shown in FIG. 3 , a field insulating film 110 is formed on the surface of the p-type base region 104 at a position away from both ends of the gate trench 107, at least on the sides of the rectangular active region Ra that are located at the ends of the trench gate structure. The field insulating film 110 has ends 110a that extend in a direction intersecting the longitudinal direction of the trench gate structure. In this embodiment, the field insulating film 110 is opened in the active region Ra, and the portions of this opening that are located on the left and right sides of the paper surface of FIG. 1 face the ends of each trench gate structure. Although not shown in FIG. 3 , the opening ends of the field insulating film 110 are located along the top and bottom sides of the rectangular active region Ra in FIG. 1 .

[0027] The field insulating film 110 is thick enough to withstand high voltages. The gate insulating film 108 formed in the gate trench 107 is also formed outside the gate trench 107 and on the surface of the field insulating film 110. At least the end 110a of the field insulating film 110 on the active region Ra side, i.e., on the trench gate structure side, is formed as an obliquely inclined surface. At this end 110a, the thickness of the field insulating film 110 gradually increases from the active region Ra toward the peripheral region Rb. The gate electrode 109 extends not only inside the gate trench 107 but also from both longitudinal ends of the gate trench 107 to the outside of the gate trench 107, reaching a position above the field insulating film 110. The portion of the gate electrode 109 extended outside the gate trench 107 constitutes a gate extension portion 109a, which is part of the gate liner 13.

[0028] The gate lead portion 109a is disposed so as to ride over the thick field insulating film 110. In other words, the end 110a of the field insulating film 110 is located below the gate lead portion 109a. Therefore, if the end 110a of the field insulating film 110 were not sloped, the gate lead portion 109a would be thin at the step of the end 110a of the field insulating film 110, which could result in a step discontinuity. However, in this embodiment, the end 110a of the field insulating film 110 is sloped, which can prevent the gate lead portion 109a from being discontinuous due to the step of the end 110a of the field insulating film 110. In particular, a step discontinuity is likely to occur when the thickness of the gate electrode 109, including the gate lead portion 109a, is thinner than the thickness of the field insulating film 110. However, even in such a case, the configuration of this embodiment can prevent a step discontinuity.

[0029] Note that the gate insulating film 108 can be appropriately patterned, and therefore does not necessarily have to be formed on the surface of the field insulating film 110, and may be formed up to the edge of the field insulating film 110. Alternatively, the gate insulating film 108 may be formed on the p-type base region 104, and the field insulating film 110 may be formed on the gate insulating film 108.

[0030] 4, in a cross section passing through the pad placement region Rc, the active region Ra in which the trench gate structure is formed is separated from the field insulating film 110, and the gate lead-out portion 109a does not extend over the field insulating film 110. In other words, the gate lead-out portion 109a does not extend over the end of the field insulating film 110 arranged in the pad placement region Rc that extends along the active region Ra. Therefore, the end of the field insulating film 110 does not necessarily have to be inclined in this portion.

[0031] As shown in Figs. 2 to 4, n + type source region 105, p + An interlayer insulating film 111 is formed on the surface of the gate electrode 109, including the contact region 106 and the gate lead portion 109a. A source electrode 112 corresponding to a surface electrode and a gate wiring layer 113 as shown in FIGS. 3 and 4 are formed as conductor patterns on the interlayer insulating film 111. The gate wiring layer 113 here constitutes a part of the gate liner 13, and the gate wiring layer 113 and the gate lead portion 109a constitute the gate liner 13. Contact holes 111a and 111b are also formed in the interlayer insulating film 111. As a result, the source electrode 112 is connected to the n-type contact region 106 through the contact hole 111a, as shown in FIG. 2. + The source region 105 and p + 3, the gate wiring layer 113 is electrically connected to the gate lead portion 109a, that is, the gate electrode 109, through the contact hole 111b.

[0032] Also, n + The back side of the substrate 101, that is, the surface opposite to the side on which the source electrode 112 is formed, is provided with an n-type + A drain electrode 114 corresponding to a back electrode electrically connected to the mold substrate 101 is formed. With this structure, a vertical MOSFET with an n-channel inversion trench gate structure is formed. An active region Ra is formed by arranging a plurality of such vertical MOSFET cells. As shown in FIG. 3, the surface of the semiconductor chip 10 is covered with a passivation film 115, and portions of the passivation film 115 corresponding to the source electrode 112 are removed to form openings. Although only a portion of the passivation film 115 is shown in FIG. 4, portions of the passivation film 115 corresponding to the pads 12a to 12d provided in the pad arrangement region Rc are also removed to form openings. In this manner, the semiconductor chip 10 equipped with a vertical MOSFET is formed.

[0033] In addition, for example, a temperature sensing diode is formed as a temperature sensing element in the temperature sensing element region 11. The temperature sensing diode is configured by providing multiple stages of PN diodes each made of a p-type layer and an n-type layer formed by ion implantation of p-type impurities and n-type impurities into polysilicon, for example. The cathode of this temperature sensing diode is connected to the cathode pad 12a, and the anode is connected to the anode pad 12b.

[0034] The other pads 12c and 12d provided in the pad arrangement region Rc are electrically connected to various parts of the vertical MOSFET. The sense pad 12c extracts a portion of the current flowing through the element, allowing the current flowing through the main cell to be measured. The gate pad 12d is electrically connected to the gate electrode 109 via the gate liner 13. This allows a gate voltage to be applied to the gate electrode 109 through the gate pad 12d.

[0035] In this manner, the semiconductor chip 10, which is the semiconductor device of this embodiment, is configured.

[0036] In a semiconductor device configured in this manner, the end 110a of the field insulating film 110 located below the gate lead portion 109a is inclined obliquely. This prevents the gate lead portion 109a from becoming thin at the step portion of the end 110a of the field insulating film 110. This prevents the gate lead portion 109a from being disconnected by the step of the end 110a of the field insulating film 110. This makes it possible to provide a semiconductor device having a structure in which the field insulating film 110 has a thickness that does not cause dielectric breakdown, while preventing the gate lead portion 109a from being disconnected.

[0037] Specifically, in the cross section shown in FIG. 4, the current flowing during switching is as shown in FIG. 5. That is, the current flows below the field insulating film 110. If the current at this time is I and the resistance of the semiconductor at the portion through which the current I flows is R, a high potential difference, indicated by the arrow Vb in the figure, is generated between the gate wiring layer 113, which is at ground potential, and the semiconductor surface, and is the product of the current I and the resistance R. To prevent dielectric breakdown due to this high potential difference, it is necessary to thicken the field insulating film 110. Furthermore, with the structure of this embodiment, the gate lead portion 109a can be prevented from being disconnected, making it possible to thicken the field insulating film 110 and suppress dielectric breakdown.

[0038] Here, if the end of the field insulating film 110 located under the gate extraction portion 109a is inclined, it is possible to suppress the thinning of the gate extraction portion 109a at the step portion of the end of the field insulating film 110. However, as the angle formed by the surface of the end of the field insulating film 110 and the surface of the semiconductor located below approaches perpendicular, the gate extraction portion 109a is more likely to be interrupted by the step of the end of the field insulating film 110. For this reason, in the cross section shown in FIG. 6, that is, in the cross section perpendicular to the direction in which the end 110a of the field insulating film 110 extends when the semiconductor chip 10 is viewed from above, it is preferable to satisfy Tg < L. Tg is the thickness of the gate extraction portion 109a. L is the width of the thickness transition region, which is the region where the film thickness of the end 110a of the field insulating film 110 changes, that is, the length of the thickness transition region in the direction perpendicular to the extending direction of the end of the field insulating film 110 when the semiconductor chip 10 is viewed from above. Thus, by making L larger than Tg, it is possible to make the thickness of the portion of the gate extraction portion 109a formed above the thickness transition region and the portion formed above the other portion substantially the same, and it is possible to more reliably suppress the interruption of the gate extraction portion 109a.

[0039] Subsequently, a method for manufacturing the semiconductor device of the present embodiment configured as described above will be described. However, for the formation process of the switching element including the trench gate structure and the like in the method for manufacturing the semiconductor device, a known method may be used, and any method may be used. For this reason, the formation process of the field insulating film 110 will be mainly described, and the other processes will be briefly described.

[0040] First, an + n-type low-concentration layer 102 is formed on the main surface of the n-type substrate 101. Then, a p-type deep layer 103 is formed by ion implantation or the like, and further a p-type base region 104 and an - n-type source region 105 are formed. Also, p-type impurities are ion-implanted into the + n-type source region 105 to form a + p-type contact region 106. And an + n-type+ through the p-type source region 105 and the p-type base region 104; - A gate trench 107 is formed so as to reach the low concentration type layer 102 .

[0041] 7A, the p-type base region 104 and the n-type + type source region 105 and p + A field insulating film 110 made of an oxide film or the like is deposited on the surface of the semiconductor, such as the contact region 106. Then, as shown in FIG. 7B, the region to be left as the field insulating film 110 is covered with a photoresist mask 200 by photolithography, and in this state, the field insulating film 110 is patterned by wet etching. At this time, the lateral wet etching results in an obliquely inclined end 110a of the field insulating film 110. After this, although not shown, the following steps are performed: forming a gate insulating film 108; forming a gate electrode 109 including a gate lead portion 109a by forming and patterning a polysilicon film; forming an interlayer insulating film 111; and forming contact holes 111a and 111b. Furthermore, the following steps are performed: forming a source electrode 112 and a gate wiring layer 113 by depositing and patterning a wiring electrode material; forming and patterning a passivation film 115; and forming an n-type insulating film 111b. + A step of forming a drain electrode 114 is carried out on the back surface side of the mold substrate 101. In this way, the semiconductor device of this embodiment can be manufactured.

[0042] (Second embodiment) The second embodiment will be described. This embodiment differs from the first embodiment in the shape of the end 110a of the field insulating film 110, but is otherwise similar to the first embodiment, so only the differences from the first embodiment will be described.

[0043] In the first embodiment, the end 110a of the field insulating film 110 is formed into an obliquely inclined shape by wet etching as shown in Fig. 7B. In this case, the end 110a of the field insulating film 110 is configured as an inclined surface as a whole.

[0044] In contrast, in the present embodiment, as shown in FIG. 8, the end portion 110a of the field insulating film 110 is formed into a shape in which the thickness gradually increases stepwise, that is, the end portion 110a has a stepped inclination. Such a shape can be obtained by, as shown in FIG. 9A, patterning the field insulating film 110 by dry etching and then dry etching the vicinity of the end portion 110a of the field insulating film 110 once again. Specifically, a resist mask 210 is disposed such that only the vicinity of the end portion 110a of the field insulating film 110 is opened by photolithography, and the vicinity of the end portion of the field insulating film 110 is dry etched in a state covered with the resist mask 210. As a result, as shown in FIG. 9B, when the gate electrode 109 including the gate lead-out portion 109a is formed as a subsequent process, the gate lead-out portion 109a can also be formed into a shape inclined stepwise along the shape of the end portion 110a of the field insulating film 110, and the step break is suppressed. Even with such a structure, the same effect as that of the first embodiment can be obtained. When the end portion 110a of the field insulating film 110 is inclined stepwise as described above, regarding the relationship of Tg < L, a straight line connecting the tip positions of each step of the stepwise shape may be assumed as an inclined surface, and the inclined surface may be considered as a thickness transition region.

[0045] (Third Embodiment) The third embodiment will be described. This embodiment is different from the first embodiment in that the structure of the field insulating film 110 is changed, and since the other aspects are the same as those of the first embodiment, only the differences from the first embodiment will be described.

[0046] As shown in FIG. 10 , in this embodiment, the film thickness of the field insulating film 110 varies depending on whether or not the end of the field insulating film 110 is located under the gate lead-out portion 109a. Specifically, the field insulating film 110 located in the portion of the peripheral region Rb adjacent to the active region Ra, i.e., the portion of the field insulating film 110 that constitutes the end 110a on which the gate lead-out portion 109a runs, is made thin, i.e., a thin film portion 110b. The thickness of the thin film portion 110b is preferably thinner than that of the gate electrode 109. Furthermore, the field insulating film 110 located in the pad arrangement region Rc or the portion of the peripheral region Rb adjacent to the pad arrangement region Rc, i.e., the portion of the field insulating film 110 that constitutes the end of the field insulating film 110 on which the gate lead-out portion 109a does not run, is made thick, i.e., a thick film portion 110c. The thick film portion 110c is thicker than the thin film portion 110b. With this structure, the step formed by the end of the field insulating film 110 below the gate lead-out portion 109a can be lowered, so that even if the gate lead-out portion 109a is positioned so as to climb over the step, the gate lead-out portion 109a will not be disconnected. Furthermore, in the portion away from the active region Ra where a high potential difference occurs between the gate wiring layer 113 and the semiconductor surface during switching, the field insulating film 110 can be made thick enough to withstand dielectric breakdown. This provides the same effects as the first embodiment.

[0047] The method for manufacturing a semiconductor device having such a structure is basically the same as that of the first embodiment, but after preparing a semiconductor substrate on which each part is formed and forming the gate trench 107, the thin film part 110b and the thick film part 110c are formed when the field insulating film 110 is formed. For example, when forming the field insulating film 110, it is preferable to use a film formation process, such as plasma CVD (chemical vapor deposition), in which the film thickness of the field insulating film 110 varies depending on the surface area of ​​the device.

[0048] Specifically, when a vertical MOSFET is formed as a switching element, the surface area of ​​the device in the active region Ra is larger than that in the pad placement region Rc due to the formation of the gate trench 107. Similarly, the regions of the peripheral region Rb adjacent to the active region Ra, i.e., the regions located at both ends of the trench gate structure where the gate lead-out portion 109a rides on the end 110a of the field insulating film 110, are closer to the gate trench 107 and therefore have a larger surface area per unit area. Furthermore, in the peripheral region Rb, the portions away from the active region Ra, i.e., the portions located below the pad placement region Rc in FIG. 1, have fewer surface irregularities and therefore a smaller surface area of ​​the device.

[0049] Therefore, when the field insulating film 110 is formed by plasma CVD or the like, the active region Ra and the peripheral region Rb, in the region adjacent to the active region Ra, become thinner than the pad arrangement region Rc, forming thin film portions 110b. Furthermore, in the pad arrangement region Rc and the peripheral region Rb, in the portions away from the active region Ra, the field insulating film 110 becomes thicker, forming thick film portions 110c. Thereafter, by patterning the field insulating film 110 by dry etching or the like using a photomask (not shown), the structure shown in FIG. 10 can be formed.

[0050] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment and encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0051] For example, in the above-described embodiments, a vertical MOSFET is used as an example of a switching element provided in the active region Ra, but the switching element may be a switching element having another gate electrode, such as a vertical IGBT, or may be a combination of a plurality of types of elements. Furthermore, the present invention is not limited to switching elements with a trench gate structure, and may also be applied to planar switching elements in which a gate lead-out portion 109a led from a gate electrode 109 extending in one direction rides on an end of a field insulating film 110.

[0052] Although the above embodiments have shown exemplary layouts of the active region Ra, the peripheral region Rb, and the pad placement region Rc, the layout is not limited to these. For example, the trench gate structure does not necessarily need to extend from one side of the semiconductor chip 10 in FIG. 1 to the other side, but may be divided in the left-right direction. In this case, the gate liner 13 can be laid out so as to pass between each divided trench gate structure in the left-right direction. In such a configuration, a field insulating film 110 can be formed between each divided trench gate structure, and the gate extension portion 109a can be arranged to extend over the end of the field insulating film 110. Therefore, the effects of the above embodiments can be achieved by sloping the end of the field insulating film 110 as in the first and second embodiments, or by forming a thin film portion 110b as in the third embodiment.

[0053] Furthermore, while the pads 12a to 12d are arranged in the pad arrangement region Rc, the number of pads is arbitrary and may be any number depending on the functions to be provided. In each of the above embodiments, the active region Ra and the pad arrangement region Rc are surrounded by the peripheral region Rb and are arranged in different positions so as not to overlap, but these regions may also be laid out so as to overlap. However, in the third embodiment, when the field insulating film 110 is formed based on a manufacturing process in which the thickness varies depending on the surface area of ​​the device, the field insulating film 110 provided in the pad arrangement region Rc is formed at a position away from the active region Ra.

[0054] Furthermore, although the above embodiments have exemplified SiC and Si as semiconductor materials, other semiconductor materials may be used. However, when SiC is used, it is preferable to apply the present invention, since the operating voltage is high and a high voltage is applied to the field insulating film 110. [Explanation of symbols]

[0055] Ra: active area, Rb: peripheral area, Rc: pad placement area 10...semiconductor chip, 12a to 12d...pads, 13...gate liner 109...gate electrode, 109a...gate lead portion, 110...field insulating film 110a...end portion, 112...source electrode, 114...drain electrode

Claims

1. A semiconductor device having an active region (Ra) in which switching elements are formed, an outer periphery region (Rb) surrounding the outer periphery of the active region, and a pad arrangement region (Rc) in which pads (12a to 12d) are arranged, a semiconductor substrate (101 to 106) in which the switching element having a gate electrode (109) with one direction as a longitudinal direction is formed in the active region; a field insulating film (110) formed on the semiconductor substrate in the peripheral region and the pad placement region, the field insulating film having an end (110a) extending in a direction intersecting the longitudinal direction of the gate electrode; a gate lead portion (109a) that is led out from the gate electrode and extends from the active region to the peripheral region, thereby running onto the end portion of the field insulating film; a gate pad (12d) included in the pad arranged in the pad arrangement region and connected to the gate electrode through the gate lead portion, an end portion of the field insulating film on which the gate lead portion is formed is inclined so that the thickness of the field insulating film gradually increases from the active region toward the outer peripheral region; the field insulating film disposed in the pad placement region has an end portion extending along the active region, and the end portion extending along the active region is not inclined with respect to a thickness direction of the field insulating film.

2. 2. The semiconductor device according to claim 1, wherein an end of said field insulating film on which said gate lead portion is formed is formed as an obliquely inclined surface.

3. 2. The semiconductor device according to claim 1, wherein an end of said field insulating film on which said gate lead portion is formed is inclined in a stepped manner.

4. 4. The semiconductor device according to claim 1, wherein the thickness of said gate electrode is thinner than the thickness of said field insulating film.

Images