Semiconductor device

Abstract

To provide a semiconductor device with a large ON-state current.SOLUTION: In a semiconductor device, a transistor 200 includes a first insulator 224, a first oxide 230a on the first insulator, a second oxide 230b on the first oxide, a third oxide 230c, a first conductor 242a and a second conductor 242b on the second oxide, a second insulator 250, a third conductor 260a, a fourth insulator 254 on the first conductor and the second conductor, and a third insulator 280 on the fourth insulator. The third insulator and the fourth insulator include an opening that reaches the second oxide. The third oxide is disposed to cover an inner wall of the opening. The second insulator is disposed to cover the inner wall of the opening through the third oxide. The third conductor is disposed to embed the opening through the third oxide and the second insulator. In a channel length direction of the transistor, an angle between a bottom surface of the first insulator and each of side surfaces of the opposing first and second conductors is less than 90 degrees.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, electronic device etc. may be said to have a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an object, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter (This is related to the above.) [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. For example, not only oxides of single metals such as indium oxide and zinc oxide, but also oxides of multi-component metals Among the oxides of multi-component metals, In-Ga-Zn oxide (hereinafter referred to as In-Ga-Zn oxide) is particularly Research into IGZO (Inorganic Glycerol, also known as IGZO) is currently being actively conducted.

[0005] Research on IGZO has revealed that, among oxide semiconductors, it is neither single crystal nor amorphous. AAC (c-axis aligned crystalline) structure and nc(n A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. Furthermore, a technique for fabricating a transistor using a CAAC structure and an nc structure has also been disclosed. Even oxide semiconductors with lower crystallinity than those described above have minute crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non- See Patent Document 6.) LSIs and displays that utilize these properties have been reported ( See Non-Patent Document 7 and Non-Patent Document 8. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-patent document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-patent document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-patent document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another embodiment of the present invention provides a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor having favorable electrical characteristics. Another object of the present invention is to provide a semiconductor device with high productivity. One of the objectives is to provide a device.

[0009] One embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. One object of one embodiment of the present invention is to provide a semiconductor device with a high data writing speed. One object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. One object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device. This is one of the challenges.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a transistor, the transistor comprising: an insulator of the first insulator, a first oxide on the first insulator, a second oxide on the first oxide, and a second a third oxide on the first oxide, a first conductor and a second conductor on the second oxide, and a second insulator on the oxide of the third, a third conductor on the second insulator, and a first conductor and a fourth insulator on the second conductor and a third insulator on the fourth insulator, The insulator and the fourth insulator have openings that reach the second oxide, and the third oxide has The second insulator is disposed so as to cover the inner wall of the opening, and the second insulator is disposed so as to cover the inner wall of the opening through the third oxide. The third conductor is disposed so as to cover the opening through the third oxide and the second insulator. The first insulator is disposed so as to fill the opening of the first insulator in the channel length direction of the transistor. a first angle formed by a plane parallel to the bottom surface and a side surface of the first conductor facing the second conductor; is less than 90 degrees.

[0012] In the semiconductor device, the fourth insulator is formed on a side surface of the first conductor and a side surface of the second oxide. a region in contact with the surface and a side surface of the first oxide, and In this case, a surface parallel to the bottom surface of the first insulator and a second conductive layer of the fourth insulator in the region Preferably, the second angle formed by the side edge facing the body and a plane parallel to the side edge is less than 90 degrees. I wish.

[0013] In the semiconductor device, the first angle and the second angle are the same angle. It is preferable.

[0014] Another embodiment of the present invention is a semiconductor device including a transistor, a first insulator, a first oxide on the first insulator, and a second oxide on the first oxide; a third oxide on the second oxide, and a first conductor and a second conductor on the second oxide. a second insulator on the third oxide; a third conductor on the second insulator; and a first conductor. and a fourth insulator on the second conductor and a third insulator on the fourth insulator, The third insulator and the fourth insulator have openings that reach the second oxide, and the third oxide The second insulator is disposed so as to cover the inner wall of the opening, and the second insulator is disposed so as to cover the inner wall of the opening via the third oxide. The third conductor is disposed so as to cover the inner wall of the insulating film, and the third conductor is disposed so as to cover the inner wall of the insulating film via the third oxide and the second insulator. The first insulating film is disposed so as to fill the opening, and is arranged in the channel width direction of the transistor. The bottom surface of the third conductor in the region that does not overlap with the second oxide is determined based on the bottom surface of the conductor. The height is lower than the height of the bottom surface of the second oxide in the channel length direction of the transistor. The length of the bottom surface of the third conductor in the region that does not overlap with the second oxide is The length is shorter than the length of the bottom surface of the third conductor in the overlapping region.

[0015] Another embodiment of the present invention is a semiconductor device including a transistor, a first insulator, a first oxide on the first insulator, and a second oxide on the first oxide; a third oxide on the second oxide, and a first conductor and a second conductor on the second oxide. a second insulator on the third oxide; a third conductor on the second insulator; and a first conductor. and a fourth insulator on the second conductor and a third insulator on the fourth insulator, The third insulator and the fourth insulator have openings that reach the second oxide, and the third oxide The second insulator is disposed so as to cover the inner wall of the opening, and the second insulator is disposed so as to cover the inner wall of the opening via the third oxide. The third conductor is disposed so as to cover the inner wall of the insulating film, and the third conductor is disposed so as to cover the inner wall of the insulating film via the third oxide and the second insulator. When the transistor is viewed from above, the fourth insulating layer is The side edges have a curved shape.

[0016] In the above semiconductor device, the fourth insulator preferably contains an oxide of aluminum. It's nice.

[0017] In the semiconductor device, the second oxide contains In and an element M (M is Al, Ga, It is preferable that the alloy contains at least one of Y and Sn, and Zn. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. .

[0019] In addition, a semiconductor device capable of retaining data for a long period of time can be provided. This makes it possible to provide a semiconductor device with a high data writing speed. In addition, a semiconductor device capable of reducing power consumption can be provided. Furthermore, a novel semiconductor device can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above will be self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0021] [Figure 1] 1A to 1E are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 1 is a schematic top view of a transistor according to one embodiment of the present invention. [Figure 4] 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 5] 10A, 10B, and 10C are graphs showing electrical characteristics of a transistor according to one embodiment of the present invention and an operating frequency of a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A, 1B, and 1C are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 16] 1A and 1B are a block diagram and a perspective view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 17] 1A to 1H are circuit diagrams illustrating configuration examples of memory devices according to one embodiment of the present invention. [Figure 18] 1A and 1B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 20] 1A to 1F are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 21] (A) and (B) are a cross-sectional STEM image and an EDX map according to an embodiment of the present invention. [Figure 22] (A) and (B) are a planar STEM image and an EDX map according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be practiced in various different ways without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in the drawings as a schematic illustration, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this may not be reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals between different drawings. In addition, when referring to similar functions, In such cases, the hatch pattern may be the same and no particular reference numeral may be assigned.

[0024] In addition, the invention can be easily understood, especially in top views (also called "plan views") and perspective views. In order to simplify the description, some components may be omitted. The information may be omitted.

[0025] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" The term "the" or "third" can be used interchangeably in the description. The ordinal numbers listed may not match the ordinal numbers used to identify an aspect of the present invention. There may be cases where this is the case.

[0026] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in describing the same with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those described above, and can be rephrased appropriately depending on the situation.

[0027] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also disclosed in the drawings or text. It shall be.

[0028] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0029] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The channel forming region is formed in the channel. A current can be passed between the source and the drain through the channel forming region. In this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0030] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0031] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source electrode) in the region where the source is formed or the channel forming region This refers to the distance between the transistor and the drain (drain region or drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of the transistor may not be determined to a single value. In the case of the channel formation region, the channel length is either one value, a maximum value, a minimum value, or is the average value.

[0032] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor where current flows when the semiconductor is on). The vertical length of the channel formation region or the channel length direction is called It should be noted that the channel width of a single transistor does not necessarily have the same value in all regions. In other words, the channel width of a transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one of the widths in the channel forming region. The value, maximum value, minimum value or average value.

[0033] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in a top view of the star (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective When the channel width becomes larger than the apparent channel width and its effect cannot be ignored For example, in a transistor that is miniaturized and in which the gate electrode covers the side of the semiconductor, The proportion of the channel formation region formed on the side surface may become large. The effective channel width is larger than the upper channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, the effective Channel width is difficult to measure accurately.

[0035] In this specification, when simply referring to the channel width, it refers to the apparent channel width. In this specification, when simply referred to as a channel width, it means an effective channel The channel length, channel width, effective channel width, apparent channel width, The channel width and other parameters can be determined by analyzing cross-sectional TEM images. can.

[0036] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. This can cause problems such as an increase in the density of defect levels in semiconductors and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxides There are transition metals other than the main components of semiconductors, such as hydrogen, lithium, sodium, and silicon. In the case of oxide semiconductors, water also functions as an impurity. In the case of an oxide semiconductor, for example, oxygen vacancies can be created by the inclusion of impurities. In addition, when the semiconductor is silicon, there are cases where an impurity that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0037] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains a large amount of silicon dioxide rather than oxygen. It has a high nitrogen content.

[0038] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be replaced with "semiconductor film" or "semiconductor layer." can.

[0039] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes cases where the angle is between -5 degrees and 5 degrees. "Almost parallel" means that the two lines are arranged at an angle of between -30 degrees and 30 degrees. "Perpendicular" means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. " refers to a state in which two straight lines are arranged at an angle of between 60 degrees and 120 degrees.

[0040] In this specification, the term "barrier film" refers to a film that prevents impurities such as water and hydrogen from permeating, and oxygen. If the barrier film has conductivity, it is called a conductive barrier. It is sometimes called the membrane.

[0041] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the semiconductor layer of a transistor, Such a metal oxide may be referred to as an oxide semiconductor. In this case, the transistor can be referred to as a transistor including an oxide or an oxide semiconductor. Cut.

[0042] In this specification, normally off means that no potential is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate is 1×10 at room temperature -20 A or less, 1 x 10 at 85°C -18 A or below, or 1 x 10 at 125°C -16 This means that it is A or below.

[0043] (Embodiment 1) An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below. I will explain.

[0044] <Configuration example of semiconductor device> 1A to 1E illustrate a transistor 200 according to one embodiment of the present invention and a transistor 2A and 2B are a top view and a cross-sectional view of the periphery of a transistor 200. FIG.

[0045] FIG. 1A is a top view of a semiconductor device including a transistor 200. 1(B) to 1(E) are cross-sectional views of the semiconductor device. 1A) is a cross-sectional view of the portion indicated by the dashed line L1-L2, showing the channel of the transistor 200. FIG. 1(C) is also a longitudinal cross-sectional view. 1 is a cross-sectional view of a portion of the transistor 200 taken along the channel length direction. FIG. 1(D) is a cross-sectional view of the area indicated by the dashed line W1-W2 in FIG. 1(A), and 1(E) is also a cross-sectional view of the channel width direction of the sinter 200. 1 is a cross-sectional view of a portion indicated by a dashed line in the direction of the channel width of the transistor 200. In the top view of Figure 1(A), some elements have been omitted for clarity. In addition, the conductor 240 and the insulator 241 are omitted from FIG.

[0046] The semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator serving as an interlayer film. 214, an insulator 280, an insulator 274, and an insulator 281. The conductor 240 (conductor 240a, and conductor 240b). An insulator 241 (insulator 241a and insulator 241b) is provided thereon.

[0047] In addition, the side walls of the openings of the insulators 254, 280, 274, and 281 An insulator 241 is provided in contact with the first conductor of the conductor 240, and the first conductor of the conductor 240 is provided in contact with the side surface of the insulator 241. The second conductor of the conductor 240 is provided further inside. The height of the upper surface of the transistor 200 and the height of the upper surface of the insulator 281 can be made to be approximately the same. In FIG. 00, a first conductor of the conductor 240 and a second conductor of the conductor 240 are stacked. However, the present invention is not limited to this configuration. The structure may be a single layer or a laminated structure of three or more layers. If they have such structures, they may be distinguished by assigning ordinal numbers in the order of their formation.

[0048] [Transistor 200] As shown in FIG. 1, transistor 200 comprises an insulating substrate (not shown) disposed above the substrate. the insulator 216, the conductor 205 disposed so as to be embedded in the insulator 216, and the insulator 21 6 and the conductor 205, and an insulator 222 disposed on the insulator 222. The insulator 224 is made of a metal, and the oxide 230 (oxide 230a, oxide) is disposed on the insulator 224. oxide 230b, and oxide 230c), and an insulator 250 disposed on the oxide 230. and a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250. ), conductors 242a and 242b in contact with a portion of the top surface of oxide 230b, and an insulating A part of the upper surface of the edge 224, a side surface of the oxide 230a, a side surface of the oxide 230b, and the conductor 242 a side surface of conductor 242a, the top surface of conductor 242a, the side surface of conductor 242b, and the top surface of conductor 242b and an insulator 254 disposed in contact with the

[0049] Conductor 260 functions as the gate electrode of the transistor, and conductors 242a and The body 242b functions as a source electrode or a drain electrode, respectively. In 00, a conductor 260 that functions as a gate electrode is formed on an insulator 280 or the like. The conductor 260 is formed in a self-aligned manner so as to fill the opening. conductor 260 is aligned in the region between conductor 242a and conductor 242b. It can be positioned reliably without any trouble.

[0050] The conductor 260 is composed of a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260 preferably has a bottom surface of the conductor 260b and a bottom surface of the conductor 260b. It is preferable that the conductor 260a is arranged so as to wrap around the top and sides. As shown, the top surface of conductor 260 is in contact with the top surface of insulator 250 and the top surface of oxide 230c. In the transistor 200, the conductor 260 has a two-layer stacked structure. For example, the conductor 260 may have a single-layer structure. It may have a laminated structure of three or more layers.

[0051] The insulators 222, 254, and 274 are hydrogen (e.g., hydrogen atoms, hydrogen It is preferable that the insulating material has a function of suppressing the diffusion of at least one of molecules. 222, insulator 254, and insulator 274 are oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 , insulator 254, and insulator 274 have higher hydrogen and oxygen content than insulator 224, respectively. Preferably, one or both of the insulators have low permeability. The insulator 274 is more permeable to one or both of hydrogen and oxygen than the insulator 250, respectively. The insulators 222, 254, and 274 are each an insulator It is preferable that the permeability to one or both of hydrogen and oxygen is lower than that of the insulator 280 .

[0052] As shown in FIG. 1B, the insulator 254 is formed between the conductor 242a and the conductor 242b. b and the opposing side surfaces of the conductors 242a and 242b. The side surfaces of the conductive body 242a and the conductive body 242b and the side surfaces of the oxide 230a and the oxide 230b and a part of the upper surface of the insulator 224. is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254. Therefore, impurities such as hydrogen contained in the insulator 280 are separated from the insulator 224. , and can be prevented from being mixed into oxide 230a and oxide 230b.

[0053] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the insulator 224. and an oxide 230b disposed on the oxide 230b, at least a portion of which is oxide. and an oxide 230c in contact with the upper surface of the oxide 230b.

[0054] In the transistor 200, the oxide 23 is formed in the channel formation region and in the vicinity thereof. 2 shows a structure in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked. However, the present invention is not limited to this. For example, a single layer of oxide 230b, oxide 23 a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, or A laminated structure of four or more layers may be provided.

[0055] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, and oxide 230c) are added with a metal oxide (hereinafter It is preferable to use a semiconductor material other than a metal oxide semiconductor (also called an oxide semiconductor).

[0056] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be deposited using a sputtering method or the like, making them suitable for highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0057] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, magnesium, etc. It is preferable to use a metal oxide. In particular, the element M is aluminum (Al), gallium (Ga), , yttrium (Y), or tin (Sn) may be used. In-Ga oxide and In-Zn oxide may also be used.

[0058] In addition, a transistor using an oxide semiconductor has an insufficient region in a channel formation region of the oxide semiconductor. The presence of impurities and oxygen vacancies can cause fluctuations in electrical characteristics and reduce reliability. Furthermore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, Therefore, oxygen vacancies in the channel formation region are unlikely to occur. For example, the oxide 23 is formed by interposing an insulator 250 or the like therebetween. By supplying oxygen to the SiO2 layer, the oxygen vacancies can be compensated for. This suppresses fluctuations in electrical properties. It is possible to provide a transistor having stable electrical characteristics and improved reliability. can.

[0059] Also, the oxide 230 is provided on the substrate 230 so as to be in contact with the oxide 230, and functions as a source electrode and a drain electrode. The elements contained in the conductor 242 (conductor 242a and conductor 242b) are oxides. When the oxide 230 has a function of absorbing oxygen, the oxide 230 is formed between the conductor 242 or between the oxide 230 and the conductor 242. In some cases, a low resistance region may be formed in part near the surface of the oxide 230. In the low resistance region, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered oxygen vacancies act as donors. In the following, hydrogen atoms are added to the oxygen vacancies, and the carrier density may increase. V O It may be called H.

[0060] 2A is an enlarged view of a portion of the transistor 200 shown in FIG. 1B. As shown in FIG. 2(A), a conductor 242 is provided on the oxide 230b so as to be in contact with the oxide 230b. The oxide 230b has a low resistance region at the interface with the conductor 242 and its vicinity. 43 (region 243a and region 243b) may be formed. The region 234 that functions as a channel forming region of the transistor 200 and the region 243 are and a region 231 (region 23) which functions as a source region or a drain region. 1a and region 231b). In the following drawings, the regions are shown in enlarged views. Even when the area 243 is not shown, a similar area 243 may be formed.

[0061] The region 243a and the region 243b are formed in the vicinity of the conductor 242 of the oxide 230b. In this example, the electrons are diffused in the depth direction, but the present invention is not limited to this. The regions 243a and 243b are appropriately selected according to the desired electrical characteristics of the transistor. Furthermore, in the oxide 230, the boundaries of the respective regions can be clearly detected. The concentrations of elements detected within each region are not limited to gradual changes from region to region. Furthermore, the color may change continuously (also called gradation) within each region.

[0062] The insulator 274 is formed on each of the conductor 260, the oxide 230c, and the insulator 250. The transistor 200 of one embodiment of the present invention is in contact with the surface as shown in FIG. In this structure, the insulator 274 and the insulator 250 are in contact with each other. By this, impurities (such as hydrogen) contained in the insulator 281 etc. are mixed into the insulator 250. Therefore, the electrical characteristics and signal quality of the transistor can be improved. This can suppress the adverse effects on reliability.

[0063] 2A, the bottom surface of the insulator 224 is used as a reference, and the area overlapping the region 234 is The height of the bottom surface of the conductor 260 in the area is equal to that of the conductors 242a and 242b. For example, in the area overlapping with the area 234, The height of the bottom surface of the conductor 260 and the height of the top surfaces of the conductors 242a and 242b are The difference in height is set to 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less.

[0064] As shown in FIG. 1D, the insulating layer 204 is formed in the channel width direction of the transistor 200. The oxide 230a and the oxide 230b, the conductor 260, and the conductor 260 are arranged on the bottom surface of the body 224. However, the height of the bottom surface of the conductor 260 in the non-overlapping region is the height of the bottom surface of the oxide 230b. The conductor 260 that functions as a gate electrode is located in the channel forming region. The side and top surfaces of the oxide 230b are covered with the oxide 230c and the insulator 250. By forming the oxide 230b in this manner, the electric field of the conductor 260 can be easily applied to the entire region 234 of the oxide 230b. Therefore, the on-state current of the transistor 200 is increased, and the frequency characteristics are improved. The oxide 230a and the oxide 230b do not overlap with the conductor 260. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region is 0 nm. or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or less The upper limit is 20 nm or less.

[0065] Here, the surface parallel to the bottom surface of the insulator 224 and the conductor 242 facing the conductor 242b are The angle formed by the bottom surface of the insulator 224 and the side surface of the conductor 24 is defined as angle 244a. If the bottom surface of the conductor 242 is parallel to the bottom surface of the conductor 242, the angle 244a is a and the side of the conductor 242a facing the conductor 242b. In addition, the surface parallel to the bottom surface of the insulator 224 and the conductor 242a facing the conductor 242b may be The angle formed by the bottom surface of the insulator 224 and the side surface of the conductor 42b is defined as angle 244b. If the bottom surface of the conductor 242b is parallel to the bottom surface of the conductor 242b, the angle 244b is The angle between the bottom surface of the conductor 242b and the side surface of the conductor 242b facing the conductor 242a is In this case, the angle 244a and the angle 244b are preferably smaller than 90 degrees. By adopting such a structure, in the channel length direction of the transistor 200, Compared to when the angle 244 (angle 244a and angle 244b) is 90 degrees, 31, the width of the region that does not overlap with the conductor 260, the so-called offset region, is narrowed. This increases the on-state current of the transistor 200, thereby improving the frequency characteristics. In addition, the oxide 230c, the insulator 250, and the conductor 260, which will be formed in a later step, are formed. This can improve the coverage of the opposing side surfaces of the conductive body 242a and the conductive body 242b. The angle 244a or the angle 244b can be appropriately set depending on the desired transistor characteristics. In addition, the change in the on-current of the transistor 200 when the angle 244 is changed is The change in the operating frequency of a semiconductor device having the transistor 200 will be described later. do.

[0066] 2B is an enlarged view of a portion of the transistor 200 shown in FIG. 1C. In FIG. 2B, the conductor 240 and the insulator 241 are omitted. As shown in FIG. 2B, the side surface of the conductor 242a in the insulator 254 and the oxide 2 The region in contact with the side of the oxide 230a and the side of the oxide 30b is referred to as region 256a. In the insulator 254, the side of the conductor 242b, the side of the oxide 230b, and the oxide 230 The region in contact with the side surface of the transistor 200 is referred to as region 256b. In the longitudinal direction, a plane parallel to the bottom surface of the insulator 224 and a plane parallel to the bottom surface of the insulator 254 in the region 256a The angle formed by the conductor 242b and a plane parallel to the side end facing the conductor 242b is defined as angle 258a. If the bottom surface of the insulator 224 and the bottom surface of the insulator 254 in the region 256a are parallel to each other, For example, as shown in FIG. 2B, angle 258a is the angle between the bottom of insulator 254 in region 256a and the bottom of insulator 254 in region 256a. and parallel to the side edge of the insulator 254 in the region 256a that faces the conductor 242b. The angle between the plane parallel to the bottom surface of the insulator 224 and the area 25 6b, the angle between the insulator 254 and a plane parallel to the side end portion facing the conductor 242a. The angle 258b is the angle between the bottom surface of the insulator 224 and the insulator 225 in the region 256b. 2B, the angle 258b is parallel to the bottom surface of the area 256b. the bottom surface of the insulator 254 in the region 256b and the conductor 242a of the insulator 254 in the region 256b. and a plane parallel to the opposite side edge.

[0067] In this case, it is preferable that the angle 258a and the angle 258b are smaller than 90 degrees. When the oxide 230 comes into contact with the insulator 254, a region with low resistance may be formed. Therefore, by adopting such a structure, the region 256a and the region 256b of the insulator 254 The resistance of the region where the oxide 230b contacts the region 234 can be reduced. The channel length of the transistor 200 can be controlled by the oxide 230. The insulating material that forms the resistive region is, for example, aluminum oxide. The angle 258a or the angle 258b may be appropriately designed depending on the desired transistor characteristics. In addition, the angle 244a or the angle 244b and the angle 258a or the angle 258b are The angles may be the same or different.

[0068] The side edges of the insulator 254 facing the regions 256a and 256b are The shape can be determined by, for example, energy dispersive X-ray spectroscopy (EDX). EDX maps obtained using IVD X-ray spectroscopy For example, when an insulator containing aluminum oxide is used for the insulator 254, In this case, the shape can be evaluated by obtaining a cross-sectional EDX map of the Al-K line. .

[0069] In addition, an opening (oxide 230b) formed in the insulator 280 or the like that reaches the oxide 230b The opening (exposing the insulating film) preferably has a tapered shape. In this way, in the channel length direction of the transistor 200, the insulator 280 or the like is formed The sidewalls of the opening and the bottom surface of the opening that do not overlap with the oxide 230a and the oxide 230b are The angle formed by the bottom surface of the opening and the surface extending outward from the opening is defined as angle 248. For example, it is preferable that angle 248 approximately coincides with angle 244 or angle 258. By using this structure, the angle 244 or the angle 258 can be made smaller than 90 degrees. In addition, the oxide 23 disposed on the inner wall of the opening can be easily processed. The coverage of Oc, the insulator 250, and the conductor 260 can be improved.

[0070] The oxide 230c and the insulator 25 are formed so as to fill the tapered opening. By providing the conductor 260 through the conductor 260, the length LG2 shown in FIG. The length LG1 can be shorter than the length LG1 shown in In the channel length direction of 00, the bottom surface of the conductor 260 in the region overlapping with the region 234 The length LG2 is the length of the oxide film in the channel length direction of the transistor 200. The length of the bottom surface of the conductor 260 in the area that does not overlap with the oxide 230a and the oxide 230b. be.

[0071] 3 shows an enlarged view of a region 239 of the transistor 200 shown in FIG. 1A. The region 239 is formed in the insulator 254 and is located near an opening formed in the insulator 280. 3 shows the insulator 254 and the top view omitting other elements. 3, the insulator 254, the oxide 230a, and the oxide In the region where the insulating body 254 does not overlap with the object 230b, the opposing side ends of the insulating body 254 are The shortest distance is defined as distance LE2. The side edge of the insulator 254 in the region in contact with the top surface of the conductor 242b is closest to the side edge of the insulator 254. The shortest distance is defined as distance LE1.

[0072] As shown in FIG. 1(E), a gap is formed between the side surface of the conductor 242b and the top surface of the conductor 242b. In addition, the conductive body 242a may have a curved surface. The conductive body 242a may have a curved surface. The conductive body 242b has a curved surface between the side surface and the top surface thereof, and is formed on the insulator 280 or the like. The tapered shape of the opening allows the channel of the transistor 200 to be In the longitudinal direction, the side end of the insulator 254 has a shape in which the distance LE2 is shorter than the distance LE1. When the insulator 254 of the transistor 200 is viewed from above, The end portion has a curved shape.

[0073] The shape of the side end of the insulator 254 can be determined by, for example, an EDX map obtained using EDX. For example, if aluminum oxide is used for the insulator 254, In the planar EDX map of the K line, the distance LE2 is shorter than the distance LE1, and / or In some cases, a shape in which the side edge has a curve may be observed.

[0074] 1 and 2, the angle 244, the angle 258, and the angle 248 are approximately the same. However, the present invention is not limited to this example. For example, the insulating layer 280 and the insulating layer 254 may be different. The layer is processed to form openings that expose the conductive layer that will become conductors 242a and 242b. Then, the conductive layer is etched using a gas capable of generating an organic substance. , the angle 244 can be controlled. This allows the angle 244 and the angles 258 and The angle 248 can be different.

[0075] As described above, a semiconductor device including a transistor with large on-state current can be provided. Furthermore, a semiconductor device having a transistor with high frequency characteristics can be provided. In addition, fluctuations in electrical characteristics are suppressed, resulting in stable electrical characteristics and improved reliability. In addition, a semiconductor device having a transistor with low off-state current can be provided. It is possible to provide a semiconductor device.

[0076] <<Estimating the operating frequency of a semiconductor device through calculations using a device simulator>> Here, calculations are performed using a device simulator to determine whether the transistor according to one embodiment of the present invention is The results of estimating the operating frequency of a semiconductor device having a transistor are shown in Figs. and explain.

[0077] In this section, the semiconductor device refers to a memory cell that uses one OS transistor and one capacitor element. It is a DRAM that uses a memory cell with one OS transistor and one capacitor element. M is a product of DOSRAM® (Dynamic Oxide Semiconductor) It is also called DOSRAM. Details will be explained in the following embodiments.

[0078] The data retention time of DOSRAM is the time it takes for the charge stored in the storage capacitor of DOSRAM to The time it takes for the size to decrease from "size after data writing" to "certain size" In this embodiment, the above-mentioned "certain size" is The potential applied to the RAM's capacitance element (storage capacitance 3.5 fF) after data is written is The time required for the voltage to drop by 0.2 V from the DO When SRAM data retention is 1 hour, the potential applied to the capacitance element of DOSRAM is This means that it takes 1 hour for the voltage to drop by 0.2V from the state after data is written. .

[0079] The data retention time of DOSRAM is determined by the off-leak current of the transistors in the DOSRAM. Here, the off-leak current of a transistor depends on the magnitude of the gate In other words, the drain current (Id) (i.e., Icut) when the gate voltage (Vg) is 0V. For example, the data retention characteristics of DOSRAM can be calculated by If it depends only on the size of the transistor Icut, the data retention time of DOSRAM is as follows: It is inversely proportional to the size of Icut of the transistors in the DOSRAM.

[0080] Icut is the sum of the shift value (Vsh) and the subthreshold swing value (Svalu Based on e), it can be estimated by extrapolating using the following formula (1), where: Vsh is the point where the slope of the curve in the Id-Vg characteristics of a transistor is maximum. Vg is defined as the point where the tangent line at Id = 1pA intersects with the line at Id = 1pA. The value is a subthreshold voltage that changes the drain current by one order of magnitude at a constant drain voltage. This refers to the amount of change in gate voltage in the V region. Monotonically decreasing according to the S value obtained by Vg-Id measurement until g=0V is reached This is an equation that holds true when we assume that:

[0081]

number

[0082] From the above, the data retention time of DOSRAM is determined by Vsh and It can be estimated by calculating the S value.

[0083] Also, the DOSRAM operating frequency is the inverse of the DOSRAM data write cycle time. The data write cycle time of DOSRAM is defined as the number of This parameter is set based on the charging time of the quantum element. Equivalent to 40% of the RAM data write cycle time (the inverse of the DOSRAM operating frequency) The time required for this was set to be the charging time of the capacitance element of the DOSRAM.

[0084] As mentioned above, the operating frequency of the DOSRAM depends on the charging time of the capacitance element of the DOSRAM. Therefore, when estimating the DOSRAM operating frequency, first In this embodiment, it is necessary to know in advance the charging time of the capacitance element of the DOSRAM. The state in which a potential of 0.55 V or more is applied to the capacitance element (storage capacitance 3.5 fF) of The capacitance element is defined as being in a "charged state." Therefore, in this embodiment, After the data write operation of the AM starts, the potential applied to the capacitor element reaches 0.55V. The time it takes to charge the capacitor element of the DOSRAM corresponds to the charging time.

[0085] By the way, the charge stored in the storage capacitor Cs [F] of the DOSRAM is Q [C], charging time is t [sec], and the potential applied to the capacitance element by charging is Vcs (=Vs ) [V], and the drain current of the transistor in the DOSRAM is Id [A]. The relationship between the parameters is expressed by the following equation (2).

[0086]

number

[0087] Therefore, by modifying equation (2), the charging time t can be expressed by the following equation (3).

[0088]

number

[0089] As described above, in this embodiment, the potential applied to the capacitance element with a storage capacitance of 3.5 fF is 0 The state in which the capacitance element is in a "charged state" is defined as the state in which the voltage reaches 0.55V or more. Therefore, in equation (3), 3.5 fF is set for Cs, +0.55 V for Vcs, and the value of the present invention is set for Id. By substituting the measured or calculated values ​​of the transistor according to the embodiment of the present invention, the DOSRAM The charging time t of the capacitance element can be calculated.

[0090] The charging time of the capacitance element of DOSRAM is , depends on the size of Id of the transistors in the DOSRAM. The operating frequency can be estimated by obtaining the Id-Vs characteristics.

[0091] Therefore, in this section, we will explain how to write data to DOSRAM using the transistors in DOSRAM. A potential that is supposed to be applied to a transistor according to one embodiment of the present invention is actually applied to the transistor. By applying a voltage to the transistor, the DOSRAM data write operation is reproduced. Specifically, the gate potential of the transistor was fixed at +2.97 V, and the drain The gate potential is fixed at +1.08V, the back gate potential is set arbitrarily, and the source potential is varied from 0V to The Id of the transistor was measured by sweeping the voltage up to +0.55V. The measurement temperature was The temperature was set to 27°C.

[0092] In addition, the Id-Vg of the transistor according to one embodiment of the present invention was calculated using the above conditions. The DOS characteristics and Id-Vs characteristics were calculated using a device simulator. The RAM data retention time and operating frequency were calculated. does not take into account current leakage and deterioration of element characteristics due to long-term storage.

[0093] The transistors assumed in the calculation using the device simulator are shown in Figs. 4(A) to 4(D) ) is shown in FIG. 4A. FIG. 4B is a top view of the transistor. (D) is a cross-sectional view of the transistor. Here, FIG. 4(B) shows the L1 1 is a cross-sectional view of a portion indicated by a dashed line in the direction of the channel length of the transistor; FIG. 4(C) is a cross-sectional view of the portion indicated by the dashed line L3-L4 in FIG. 4(A). 4(D) is a cross-sectional view of the transistor in the channel length direction. FIG. 4(A) is a cross-sectional view of a portion indicated by a dashed line W1-W2 in the transistor. It is also a cross-sectional view in the width direction of the panel. In the top view of FIG. 4(A), some parts are omitted for clarity. The element of is omitted.

[0094] In FIG. 4, the conductor BGE is the back gate electrode, and the transistor 20 shown in FIG. The insulators BGI1 and BGI2 correspond to the conductor 205 of the gate insulating layer 200. 1. The insulator 222 and the insulator 224 of the transistor 200 shown in FIG. The semiconductor SEM1, the semiconductor SEM2, and the semiconductor SEM3 are semiconductor layers. 1. Therefore, the oxide 230a, the oxide 230b, and the oxide 230c of the transistor 200 shown in FIG. The conductor SE is the source electrode, and corresponds to the transistor 2 shown in FIG. The conductor DE corresponds to either the conductor 242a or the conductor 242b of the drain electrode 242. 1. The other of the conductor 242a or conductor 242b of the transistor 200 shown in FIG. The insulator CAP is a barrier film, and corresponds to the insulator 2 in the transistor 200 shown in FIG. The insulator TGI is the top gate insulator, which corresponds to transistor 2 shown in Figure 1. The conductor TGE corresponds to the insulator 250 in FIG. This corresponds to the conductor 260 of the transistor 200. In the transistor structure shown in FIG. 1(C), angle 248 shown in FIG. 2(A), and angle 244 shown in FIG. 2(B). All angles 258 are the same.

[0095] In this calculation, the transistors shown in FIG. 4 are structured with different sizes (structure 1A to structure 1B). The values ​​of each parameter assumed in the calculation using the device simulator were Among these, the parameter values ​​that differ between Structures 1A to 3A are shown in Table 1.

[0096] [Table 1]

[0097] The angle θ shown in Table 1 is the angle between the plane parallel to the bottom surface of the conductor SE and the conductor facing the conductor DE. The angle between the side of SE and the plane parallel to the bottom of the conductor DE and the plane facing the conductor SE. The angle θ is also the angle formed by the side of the conductor DE that is facing the conductor DE. 244. The length LG2 shown in Table 1 corresponds to the length of the transistor as shown in FIG. In the channel length direction of the transistor, the semiconductor SEM2 and the semiconductor SEM1 are connected to the conductor TGE. The length LG2 is the length of the bottom surface of the conductor TGE in the area where the and do not overlap. The calculation is performed using the angle θ and the parameters shown in Table 2. From Table 1, it can be seen that when the angle θ is small, It can be seen that the smaller the distance, the shorter the length LG2.

[0098] Calculations were carried out using a device simulator for Structures 1A to 3A. The device simulator used is Silvaco's Atlas3D. Among the parameter values ​​assumed in the calculation using the device simulator, the values ​​of Structure 1A Table 2 shows the values ​​of parameters common to Structures 1 to 3A.

[0099] [Table 2]

[0100] IGZO(134) shown in Table 2 is an In:Ga:Zn=1:3:4 composition. In addition, IGZO(423) shown in Table 2 is assumed to be an In:G The In-Ga-Zn oxide with a composition of a:Zn=4:2:3 is assumed. The parameters listed in the SEMs shown in 2 are Semiconductor SEM1, Semiconductor SEM2, and This is a parameter common to the semiconductor SEM3.

[0101] DOSRAM with structure 1A, DOSRAM with structure 2A, and DOSRAM with structure 3A The operating frequency of the DOSRAM is 3.3V at 27℃. The estimated operating frequency of the DOSRAM shown in Fig. 5(A) is The DOSRAM operating frequency at 1A is normalized to 1. The axis represents the angle θ [°], and the vertical axis represents the normalized DOSRAM operating frequency. From A), it can be seen that the smaller the angle θ, the higher the DOSRAM frequency.

[0102] <<Evaluation of transistor electrical characteristics through calculations using a device simulator>> Next, the on-current of the transistor 200 when the angle 244 shown in FIG. 2(A) is changed is shown. The changes were evaluated by calculation using a device simulator. The S value and on-current of structures 1A to 3A were calculated. Then, the Id-Vg characteristics at drain voltage Vd=1.2V were calculated, and the S value and The on-state current Ion was calculated. Here, Ion is the gate voltage Vg = Vsh + 3.0V. The back gate voltage Vbg was set to an arbitrary value.

[0103] FIG. 5(B) shows the Ion calculated for each of Structures 1A to 3A. In Fig. 5(B), the horizontal axis is the angle θ [°] and the vertical axis is Ion [A]. B) It can be seen that the smaller the angle θ, the larger Ion becomes.

[0104] FIG. 5C shows the Svalu calculated for each of the structures 1A to 3A. In FIG. 5(C), the horizontal axis represents the angle θ [°], and the vertical axis represents the S value [ mV / dec.]. From Figure 5(C), the change in S value with respect to the change in angle θ is small compared to the change in Ion. Therefore, the angle θ has a large contribution to Ion. , it can be seen that the contribution to the S value is small.

[0105] As a result of the above, the smaller the angle θ, the larger the Ion of the transistor. It can be seen that the operating frequency of a semiconductor device having a transistor is improved. The smaller the area of ​​the conductor SE or conductor DE that does not overlap with the conductor TGE, This is presumably because the width of the offset region becomes narrower.

[0106] <<Detailed configuration of semiconductor device>> The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0107] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 216 .

[0108] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also serve as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. By changing the threshold voltage of the transistor 200 independently of the applied voltage, In particular, applying a negative potential to the conductor 205 can control the voltage (Vth). This makes it possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 is more effective than not applying a negative potential. The drain current when the potential applied to the conductor 260 is 0 V can be reduced.

[0109] As shown in FIG. 1(A), the conductor 205 is formed in a region 234 of the oxide 230. In particular, as shown in FIG. 1(D), the conductor 205 is made of oxide 2 The region 234 of the region 30b also extends in the region outside the end portion intersecting with the channel width direction. That is, it is preferable that the oxide 230 is formed on the outer side of the side surface in the channel width direction. In this case, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator. .

[0110] With the above-described configuration, the electric field of the conductor 260 functioning as the first gate electrode and the The electric field of the conductor 205, which functions as the gate electrode of the second electrode, forms a channel in the region 234. The first gate electrode and the second gate electrode can electrically surround the region. The electric field of the gate electrode of the transistor electrically surrounds the channel forming region. This structure is called a surrounded channel (S-channel) structure.

[0111] The conductor 205 is a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a single layer, it may be a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0112] The insulator 214 prevents impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side. Therefore, the insulator 214 preferably functions as a barrier insulating film that suppresses the , hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, N O2, etc.), and copper atoms, etc. It is preferable to use an insulating material. Alternatively, oxygen (for example, oxygen atoms, oxygen molecules) The insulating material has a function of suppressing the diffusion of at least one of oxygen and oxygen atoms (the oxygen is less likely to permeate). Preferably, a soluble material is used.

[0113] For example, it is preferable to use silicon nitride or the like as the insulator 214. Impurities such as water and hydrogen diffuse from the substrate side to the transistor 200 side through the insulator 214. Alternatively, oxygen contained in the insulator 224 or the like can be prevented from being absorbed by the insulator 21. 4 can be prevented from diffusing toward the substrate side.

[0114] In addition, the insulators 216, 280, and 281 have a higher dielectric strength than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic For example, the capacitance can be reduced by removing the insulators 216, 280, and 28 1. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen Silicon, silicon oxide having vacancies, etc. may be used appropriately.

[0115] The insulator 222 and the insulator 224 function as gate insulators.

[0116] Here, it is preferable that the insulator 224 in contact with the oxide 230 releases oxygen by heating. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide, silicon oxynitride, or the like. By providing the insulating layer in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced, and the The reliability of the transistor 200 can be improved.

[0117] Specifically, the insulator 224 is made of an oxide material from which part of the oxygen is released by heating. The oxide film that releases oxygen when heated is called a TDS (Thermal Distribution System). Oxygen converted to oxygen atoms in the ion absorption spectroscopy analysis The amount of desorption is 1.0×10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 at oms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 That's all, is 3.0 x 10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the film at this time is 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower. ° C. or less is preferred.

[0118] As shown in FIG. 1D, the insulator 224 does not overlap with the insulator 254 and is oxidized. The film thickness in the region not overlapping with the object 230b may be thinner than the film thickness in the other region. In the insulator 224, a region that does not overlap with the insulator 254 and does not overlap with the oxide 230b The thickness of the film is preferably a thickness that allows sufficient diffusion of the oxygen.

[0119] The insulator 222 prevents impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side. For example, the insulator 222 is preferably an insulating material. It is preferable that the hydrogen permeability is lower than that of the insulator 224. Therefore, by surrounding the insulator 224, oxide 230, etc., impurities such as water and hydrogen are Diffusion from the outside into the transistor 200 can be suppressed.

[0120] Furthermore, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). The insulator 222 preferably has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of atoms and impurities, and the oxygen contained in the oxide 230 acts as an insulator. 220. 24 and the oxygen contained in the oxide 230 can be prevented.

[0121] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230 is prevented. It acts as a suppressing layer.

[0122] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0123] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST). As miniaturization and high integration of transistors progress, If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as an insulator, the physical thickness can be maintained. This makes it possible to reduce the gate potential during transistor operation.

[0124] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. good.

[0125] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b. The oxide 230c is located on the surface of the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0126] It is preferable that the oxide 230 has a layered structure made up of oxides with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the constituent element that is the main component The atomic ratio of element M to oxide 230b is the main component in the metal oxide used for oxide 230b. It is preferable that the atomic ratio of element M to the constituent elements is larger than that of oxide 230. In the metal oxide used in the oxide 230a, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In in the metal oxide is larger than that of element M to In. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is In the metal oxide used for the oxide 230a, the atomic ratio of In to the element M is greater than that of In. In addition, the oxide 230c is preferably used for the oxide 230a or the oxide 230b. Metal oxides that can be used can be used.

[0127] In addition, the oxide 230b preferably has crystallinity. -OS(c-axis aligned crystalline oxide sem It is preferable to use a crystalline silicon such as CAAC-OS. Oxides have few impurities and defects (such as oxygen vacancies), and have a highly crystalline, dense structure. Therefore, the source electrode or the drain electrode draws oxygen from the oxide 230b. This prevents the oxide 230b from being oxidized by the heat treatment. Since the transistor 200 can be manufactured at high temperatures, the It is stable against temperature (so-called thermal budget).

[0128] In addition, the conduction band minimums of the oxides 230a and 230c are greater than the conduction band minimum of the oxide 230b. It is preferable that the oxide 230a and the oxide 230b are closer to the vacuum level than the lower end. Preferably, the electron affinity of the oxide 230c is smaller than the electron affinity of the oxide 230b.

[0129] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, In other words, the oxide 230a, the oxide 230b, and the The conduction band edge at the junction of the oxide 230c and the silicon dioxide 230c changes continuously or is called a continuous junction. In order to achieve this, the interface between the oxide 230a and the oxide 230b , and the defect levels of the mixed layer formed at the interface between oxide 230b and oxide 230c. It is better to lower the density.

[0130] Specifically, the oxide 230a is composed of In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide having an atomic ratio of 1:1:0.5 may be used. In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] The oxide 230c may be a metal oxide of In:Ga:Zn=1:3:4. [Atomic ratio], In:Ga:Zn=4:2:3 [Atomic ratio], Ga:Zn=2:1 [Atomic ratio] The metal oxide having a Ga:Zn=2:5 atomic ratio or a Ga:Zn=2:5 atomic ratio may be used. A specific example of the compound 230c having a layered structure is In:Ga:Zn=4:2:3[ In:Ga:Zn=1:3:4 [atomic ratio] and In:Ga: Layer structure of Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], In :Layered structure of Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio] Examples include a laminated structure with In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide. It can be obtained.

[0131] At this time, the main path of the carriers is the oxide 230b. By configuring 30c as described above, the interface between oxide 230a and oxide 230b and the oxide This can reduce the defect state density at the interface between the oxide 230b and the nitride 230c. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 has high It is possible to obtain a high on-state current and high frequency characteristics. In this structure, the defect level density at the interface between the oxide 230b and the oxide 230c is In addition to the effect of lowering the temperature, the constituent elements of the oxide 230c diffuse into the insulator 250. More specifically, the oxide 230c has a laminated structure, and the laminated In diffuses into the insulator 250 to place an In-free oxide above the structure. The insulator 250 functions as a gate insulator, so that In can be suppressed. If it gets mixed into the insulator 250, the transistor characteristics will be impaired. By forming 230c into a laminated structure, it is possible to provide a highly reliable semiconductor device. .

[0132] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the metal oxide that becomes the region 234 has a band gap of 2 eV or more, preferably It is preferable to use a material with a band gap of 2.5 eV or more. By using a metal oxide, the off-state current of a transistor can be reduced. By using a transistor, a semiconductor device with low power consumption can be provided.

[0133] On the oxide 230b, a conductor 242 is formed, which functions as a source electrode and a drain electrode. The thickness of the conductor 242 is, for example, For example, it may be 1 nm or more and 50 nm or less, and preferably 2 nm or more and 25 nm or less.

[0134] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from rontium and lanthanum, or an alloy containing the above metal elements Alternatively, it is preferable to use an alloy of the above-mentioned metal elements. tantalum, titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum, an oxide containing lanthanum and nickel, or the like. Tantalum oxide, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Nitrides containing strontium, ruthenium oxide, ruthenium nitride, and oxides containing strontium and ruthenium The oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. This is preferable because it is a material that maintains its conductivity even when absorbed.

[0135] The insulator 254, like the insulator 214, is a material that prevents impurities such as water and hydrogen from penetrating the insulator 280. It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion from the side into the transistor 200. For example, it is preferable that the insulator 254 has a lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 1B and 1D, the insulator 254 is The top and side surfaces of the conductor 242b, the top and side surfaces of the oxide 230a and the oxide 230b. It is preferable that the insulating layer 224 contacts the side surface of the insulating layer 224 and the upper surface of the insulating layer 224. As a result, hydrogen contained in the insulator 280 is absorbed into the conductor 242a, the conductor 242b, the oxide 23 0a, oxide 230b, and the top or side of insulator 224 diffuse into oxide 230. This can suppress the

[0136] In this way, the insulator 254 having a barrier property against hydrogen prevents the insulator 224 and By covering the oxide 230, the insulator 280 is protected from the insulator 224 by the insulator 254. , and oxide 230. This prevents impurities such as hydrogen from Since the diffusion from the outside of the transistor 200 to the transistor 200 is suppressed, the transistor 200 can be given good electrical properties and reliability.

[0137] Furthermore, the insulator 254 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). The rim 254 preferably has a lower oxygen permeability than the insulator 224 .

[0138] The insulator 254 is preferably formed by sputtering. The insulating film of the insulator 224 is formed by sputtering in an atmosphere containing oxygen. Oxygen can be added to the area adjacent to the body 254. This allows oxygen to be released from the area. Oxygen can be supplied to the oxide 230 through the insulator 224. 54 has the function of suppressing the upward diffusion of oxygen, and oxygen is isolated from the oxide 230. The insulator 222 can prevent oxygen from diffusing downward. By having the function of suppressing diffusion, oxygen is prevented from diffusing from the oxide 230 into the insulator 216. In this way, the oxide 230 serving as a channel forming region can be prevented from being broken down. Oxygen is supplied to the region 234 where the oxide 230 is present. This reduces the oxygen vacancies in the oxide 230 and This can prevent the transistor from becoming normally on.

[0139] The insulator 254 may be, for example, an oxide of one or both of aluminum and hafnium. It is preferable to form a film of an insulator containing a fluorine compound.

[0140] The insulator 254 may have a multi-layer structure of two or more layers. 4, the first layer is formed using the sputtering method in an oxygen-containing atmosphere, and then the second layer is formed using the ALD method. The ALD method is a film formation method with good coating properties. Therefore, it is possible to prevent the formation of discontinuities due to the unevenness of the first layer. When the edge 254 has a multi-layer structure of two or more layers, the multi-layer structure may be made of different materials. For example, silicon oxide, silicon oxynitride, silicon nitride oxide or silicon nitride, As a laminated structure with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen In addition, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, For example, an insulator containing oxides of one or both of aluminum and hafnium is used. It is possible.

[0141] The insulator 250 functions as a gate insulator. The insulator 250 is preferably made of silicon oxide or silicon oxynitride. , silicon oxynitride, silicon nitride, silicon oxide with fluorine addition, carbon-added oxide silicon oxide, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, etc. In particular, silicon oxide and silicon oxynitride are stable to heat. This is preferable.

[0142] Like the insulator 224, the insulator 250 is made of an insulator that releases oxygen when heated. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing the oxide 230c in contact with the upper surface thereof, the region 234 of the oxide 230b is effectively In addition, like the insulator 224, the water in the insulator 250 can be supplied with oxygen. It is preferable that the concentration of impurities such as silicon is reduced. It is preferable that the upper limit is 20 nm or less.

[0143] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0144] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant. By making the insulating layer 250 and the metal oxide into a laminated structure, the insulating layer 250 is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0145] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, selected from tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. Metal oxides containing one or more of these metals can be used. aluminum oxide, which is an insulator containing oxides of one or both of aluminum and hafnium; Hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate ) is preferably used.

[0146] Although the conductor 260 is shown as having a two-layer structure in FIG. 1, it may have a single layer structure or a structure having three or more layers. The above laminated structure may also be used.

[0147] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of at least (i).

[0148] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can prevent the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0149] In addition, since the conductor 260 also functions as wiring, a conductor with high conductivity should be used. For example, the conductor 260b is preferably made primarily of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure. For example, a laminated structure of titanium, titanium nitride and the above conductive material may be used.

[0150] The insulator 280 is connected to the insulator 224, the oxide 230, and the conductor via the insulator 254. 242. For example, the insulator 280 may be silicon oxide or silicon oxynitride. , silicon oxide nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, carbon It is preferable to use silicon oxide doped with hydrogen and nitrogen, silicon oxide having vacancies, etc. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are This is preferable because it makes it possible to easily form a region containing oxygen that is desorbed by heat.

[0151] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. The top surface of the insulator 280 may be planarized.

[0152] The insulator 274, like the insulator 210, prevents impurities such as water and hydrogen from entering from above. It is preferable that the insulator 2 functions as a barrier insulating film that suppresses diffusion into the insulator 280. As 74, for example, an insulator that can be used for the insulator 210, the insulator 254, etc. is used. That's good enough.

[0153] In addition, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. The insulator 281, like the insulator 224, has a low concentration of impurities such as water and hydrogen in the film. It is preferable that it is reduced.

[0154] Also, the insulating material 281, the insulating material 274, the insulating material 280, and the insulating material 254 are formed. The conductor 240a and the conductor 240b are placed in the opening. 240b are provided facing each other with the conductor 260 in between. The height of the upper surface of 240b may be flush with the upper surface of the insulator 281.

[0155] The side walls of the openings of the insulators 281, 274, 280, and 254 The insulator 241a is provided in contact with the first conductor of the conductor 240a. A conductor 242a is located at least partially on the bottom of the opening. , the conductor 240a contacts the conductor 242a. Similarly, the insulator 281, the insulator 274, the insulator An insulator 241b is provided in contact with the edge 280 and the side wall of the opening of the insulator 254, and The first conductor of the conductor 240b is formed in contact with the side surface of the opening. The conductor 242b is located at least in a part of the area where the conductor 240b is in contact with the conductor 242b. do.

[0156] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing the conductive material 240a. 0b may have a laminated structure.

[0157] In addition, when the conductor 240 has a laminated structure, the oxide 230a, the oxide 230b, the conductor 242, insulator 254, insulator 280, insulator 274, and conductive material in contact with insulator 281. The body can be made of conductive materials that have the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, It is preferable to use ruthenium or the like. In addition, it is preferable to use a material that has a function of suppressing the permeation of impurities such as water and hydrogen. The conductive material having the function may be used in a single layer or a multilayer structure. The oxygen added to the insulator 280 is absorbed by the conductors 240a and 240b. In addition, impurities such as water and hydrogen contained in the layer above the insulator 281 can be prevented. is prevented from diffusing into the oxide 230 through the conductor 240a and the conductor 240b. It is possible.

[0158] The insulators 241a and 241b may be used, for example, as the insulator 254. The insulator 241a and the insulator 241b are made of an insulator 254. Since the insulator 280 is provided in contact with the conductor, impurities such as water and hydrogen contained in the insulator 280 can be easily absorbed by the conductor. 240a and the conductor 240b, the diffusion of the oxide 230 can be suppressed. In addition, oxygen contained in the insulator 280 is absorbed into the conductors 240a and 240b. This can prevent the

[0159] Although not shown, the conductive material 240a and the conductive material 240b are arranged in contact with each other on their upper surfaces. A conductor functioning as a wire may be disposed. The conductor functioning as a wiring may be made of tungsten. It is preferable to use a conductive material containing copper or aluminum as a main component. The conductor may have a laminated structure, for example, a layer of titanium, titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator. You may do so.

[0160] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0161] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and silicon substrates. Fire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin substrate The semiconductor substrate may be a semiconductor such as silicon or germanium. Body substrate, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of zinc oxide, gallium oxide, etc. A semiconductor substrate having an insulating region inside the substrate, such as SOI (Silicon On Insulator) Conductive substrates include graphite substrates, metal substrates, and alloy substrates. substrates, conductive resin substrates, etc. Or, substrates with metal nitrides, metal oxides, etc. Furthermore, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, A substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductive substrate Alternatively, a substrate on which an element is provided may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a recording element, and the like. There are memory elements, etc.

[0162] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0163] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. Therefore, materials should be selected accordingly.

[0164] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides with aluminum, aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium, Examples include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0165] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, Silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resin be.

[0166] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. Insulators having a function of controlling the temperature (insulators 214, 222, 254, and By surrounding the transistor with a metal layer (such as 274), the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include porosity. Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators including titanium, hafnium, or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or thiamin oxide Metal oxides such as tantalum, aluminum nitride, titanium aluminum nitride, titanium nitride, and nitride Metal nitrides such as silicon oxide or silicon nitride can be used.

[0167] In addition, the insulator that functions as the gate insulator has a region containing oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, the oxide The oxygen deficiency of 230 can be compensated for.

[0168] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, Zirconium, Beryllium, Indium, Ruthenium, Iridium, Strontium Metal elements selected from ammonium, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel, or an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. It is a material that maintains conductivity even after oxidation, and is therefore preferred. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, Silicide may also be used.

[0169] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0170] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which a conductive material containing oxygen is used. It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0171] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Conductive materials containing nitrogen, such as indium tin oxide and tungsten oxide, may also be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0172] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0173] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that the alloy contains boron, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or One or more types may be included.

[0174] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M can be aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, a combination of the aforementioned elements may be used.

[0175] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0176] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors are, for example, CAAC-OS, polycrystalline nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) and amorphous oxide semiconductors There is the body.

[0177] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0178] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have a lattice arrangement such as a pentagon or heptagon. In CAAC-OS, clear grain boundaries are observed even near the strain. It is difficult to confirm the grain boundary due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high solubility in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is because distortion can be tolerated by, for example, adjusting the distortion.

[0179] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0180] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of metal oxides with CAAC-OS are stable. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0181] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0182] Indium gallium oxide, a type of metal oxide containing indium, gallium, and zinc, is used. The IGZO nanocrystals mentioned above are stable. In particular, IGZO tends to have difficulty growing crystals in the atmosphere. , small crystals (e.g., crystals of several mm or several cm) are more likely to be formed than large crystals (here, crystals of several mm or several cm). For example, the nanocrystals mentioned above may be structurally more stable.

[0183] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0184] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0185] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0186] When alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed, Therefore, alkali metals or alkaline earth metals may generate carriers. Transistors that use metal oxides in the channel formation region have normally-on characteristics. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxides is low. Specifically, it is preferable to reduce the amount of alkali metal in the metal oxide obtained by SIMS. Metal or alkaline earth metal concentrations (Secondary Ion Mass Spectroscopy (SIMS) The concentration obtained by ion mass spectrometry was calculated as 1 × 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0187] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, metal oxides containing hydrogen can be used. Such a transistor is likely to have normally-on characteristics.

[0188] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, stable electrical properties can be imparted.

[0189] It is preferable to use a thin film with high crystallinity as the metal oxide used as the semiconductor of a transistor. Use of the thin film can improve the stability or reliability of the transistor. The thin film may be, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, thin films of single crystal metal oxides or thin films of polycrystalline metal oxides are Formation on a substrate requires high temperature or laser heating processes. This increases the cost of the process and also reduces throughput.

[0190] In 2009, we developed an In-Ga-Zn oxide (CAAC-IGZO) with a CAAC structure. The discovery of the compound α-hydroxybenzoic acid (α-hydroxybenzoic acid) is reported in Non-Patent Document 1 and Non-Patent Document 2. In this case, CAAC-IGZO has a c-axis orientation, the grain boundaries are not clearly visible, and the It has been reported that it can be formed on a substrate at low temperatures. The transistors made using this method have been reported to have excellent electrical properties and reliability.

[0191] In 2013, we also developed an In-Ga-Zn oxide (nc-IGZO) with an nc structure. nc-IGZO is a material that can be grown in a small area. The atomic arrangement has periodicity in the region (for example, the region of 1 nm or more and 3 nm or less), and different It has been reported that there is no regularity in the crystal orientation between the regions.

[0192] In Non-Patent Documents 4 and 5, the above-mentioned CAAC-IGZO, nc-IGZO, The average crystal size of IGZO thin films and low-crystalline IGZO thin films was measured by electron beam irradiation. The change in the thickness is shown in Fig. 1. For a thin film of IGZO with low crystallinity, before irradiation with an electron beam, Even in thin films, crystalline IGZO of about 1 nm has been observed. In this case, completely amorphous structure Furthermore, it has been reported that the presence of IGZO with low crystallinity could not be confirmed. Compared with the thin films of CAAC-IGZO and nc-IGZO, the thin films of CAAC-IGZO and nc-IGZO are more resistant to electron beam irradiation. Therefore, CAA is a promising semiconductor for transistors. It is preferable to use a thin film of C-IGZO or a thin film of nc-IGZO.

[0193] Transistors using metal oxides have extremely low leakage current when they are off. Specifically, the off-state current per 1 μm of the transistor channel width is yA / μm (10 -2 4 A / μm) order is shown in Non-Patent Document 6. For example, Low-power CPUs that utilize the low leakage current characteristics of the transistors used has been disclosed (see Non-Patent Document 7).

[0194] In addition, by utilizing the characteristics of transistors using metal oxides, which have low leakage current, The application of this transistor to a display device has been reported (see Non-Patent Document 8). In this case, the displayed image changes several dozen times per second. The number of times is called the refresh rate. The refresh rate is also called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, can cause eye fatigue. Therefore, the refresh rate of the display device is reduced to improve image quality. It has been proposed to reduce the number of times the image is rewritten. By driving in this manner, it is possible to reduce the power consumption of the display device. This is called Idling Stop (IDS) driving.

[0195] The discovery of the CAAC and nc structures was based on the discovery of metal oxides with the CAAC or nc structures. The electrical characteristics and reliability of the transistor using the material are improved, and the manufacturing process cost is reduced. This contributes to lowering the power consumption and improving throughput. Taking advantage of this property, research is being conducted into the application of this transistor to display devices and LSIs. It is being done.

[0196] <Method for manufacturing semiconductor device> Next, a semiconductor device having a transistor 200 according to the present invention shown in FIG. 1 will be fabricated. The manufacturing method will be described with reference to Figs. 6 to 13. In Figs. 6 to 13, (A ) shows a top view. Also, (B) in each figure shows the part indicated by the dashed line L1-L2 in (A). 1. This is a cross-sectional view corresponding to the position of the transistor 200, and is also a cross-sectional view taken along the channel length direction of the transistor 200. In addition, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line W1-W2 in (A). 1 and 2, which are cross-sectional views of the transistor 200 in the channel width direction. In the figure, some elements have been omitted for clarity.

[0197] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The 214 film is formed by sputtering, chemical vapor deposition (CVD), or Deposition), Molecular Beam Epitaxy (MBE) Beam Epitaxy, Pulsed Laser Deposition (PLD) Atomic Layer Deposition (ALD) method, Atomic Layer Deposition (ALD) method This can be done using the osition method or the like.

[0198] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0199] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0200] In addition, the ALD method utilizes the self-regulating properties of atoms to deposit atoms one layer at a time. This allows for ultra-thin film deposition, film deposition on structures with high aspect ratios, and pinholes. It is possible to form films with few defects such as holes, and to form films with excellent coverage, and to form films at low temperatures. In addition, the ALD method uses plasma, which is called PEALD (Plasma ALD). The use of plasma allows for growth at lower temperatures. The precursors used in the ALD method include carbon and other Some films contain impurities. Therefore, films formed by ALD may be damaged by other film formation methods. The film may contain more impurities such as carbon than the film that was provided. X-ray Photoelectron Spectroscopy (XPS) This can be done using fluoroscopy.

[0201] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0202] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transport or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0203] In this embodiment, the insulator 214 is formed by depositing silicon nitride by the CVD method. In this way, an insulator that is difficult for copper to penetrate, such as silicon nitride, is used as the insulator 214. Therefore, a metal that easily diffuses, such as copper, is used for the conductor layer (not shown) below the insulator 214. Even if the metal is present, the metal can be prevented from diffusing into layers above the insulator 214.

[0204] Next, a conductive film that will become the conductor 205 is formed on the insulator 214. The deposition of the conductive film is performed using methods such as sputtering, CVD, MBE, PLD, and ALD. The conductive film that becomes the conductor 205 can be a multilayer film. In this embodiment, a tungsten film is formed as the conductive film that becomes the conductor 205.

[0205] Next, a conductive film that will become the conductor 205 is processed using lithography. Form.

[0206] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the resist patterned area using a developer. By etching through the resist mask, conductors, semiconductors, insulators, etc. are formed as desired. For example, KrF excimer laser light, ArF excimer laser light, etc. Laser light, EUV (Extreme Ultraviolet) light, etc. are used to A resist mask can be formed by exposing the substrate to light. It is also possible to use a liquid immersion technique in which the substrate is exposed to light by filling it with a liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. dry etching, wet etching, or wet etching after dry etching wet etching, or wet etching followed by dry etching. This can be removed.

[0207] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating layer that is a hard mask material is formed on the conductive film that is to be the conductor 205. An insulating film or a conductive film is formed, a resist mask is formed on it, and a hard mask material is etched. By this etching, a hard mask of a desired shape can be formed. The etching of the conductive film may be carried out after removing the resist mask, or after removing the resist mask. In the latter case, the resist mask may be removed during etching. After etching the conductive film that will become the conductor 205, the hard mask is removed by etching. On the other hand, if the hard mask material does not affect the subsequent process or can be used in the subsequent process, If the hard mask can be removed, it is not necessarily required to remove the hard mask.

[0208] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency voltage may be applied to one of the parallel plate electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a high frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0209] Next, an insulating film that will become the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film that becomes the body 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, Then, a silicon oxide film is formed by the CVD method.

[0210] Here, the thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is In this embodiment, the thickness of the conductor 205 is set to 150 nm. The thickness of the insulating film that becomes the insulator 216 is set to 350 nm.

[0211] Next, the insulating film that will become the insulator 216 is subjected to CMP (chemical mechanical polishing). By performing a polishing process, a part of the insulating film that will become the insulator 216 is removed, The surface of the conductor 205 is exposed. This allows the conductor 205 and the insulating material to be exposed. A body 216 can be formed (see FIG. 6).

[0212] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0213] An insulator 216 is deposited on the insulator 214. The insulator 216 is deposited by a sputtering method. The deposition can be carried out by using a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0214] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening may be, for example, a groove or This also includes slits. The area where an opening is formed may also be referred to as an opening. The openings may be formed by wet etching, but it is more preferable to use dry etching. Insulator 214 is preferably formed by etching insulator 216 to form grooves. It is preferable to select an insulator that functions as an etching stopper film when etching. When a silicon oxide film is used for the insulator 216 forming the groove, the insulator 214 is made of silicon nitride. It is preferable to use a tantalum oxide film, an aluminum oxide film, or a hafnium oxide film.

[0215] After the opening is formed, a conductive film is formed to become the conductor 205. The conductive film has properties to suppress the permeation of oxygen. It is desirable to include a conductor having a function of controlling the temperature. For example, tantalum nitride, tungsten nitride, etc. Titanium, tungsten, titanium nitride, etc. can be used. Alternatively, tantalum, tungsten, titanium It is a laminated film of tungsten, molybdenum, aluminum, copper, and molybdenum-tungsten alloy. The conductive film that becomes the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, or the like. The deposition can be carried out by using a PLD method, an ALD method, or the like.

[0216] In this embodiment, the conductive film that becomes the conductor 205 has a multi-layer structure. A tantalum nitride film is formed by a deposition method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductive film that becomes the conductor 205, The conductive film on the upper layer of the conductive film that becomes the conductor 205 is made of a metal that easily diffuses, such as copper. This also prevents the metal from diffusing out of the conductor 205.

[0217] Next, a conductive film is formed on the conductive film that will become the conductor 205. The conductive film is formed by plating. This can be done using methods such as the CVD method, MBE method, PLD method, and ALD method. In this embodiment, the conductive film on the conductive film that becomes the conductor 205 is made of a material such as copper. A low resistance conductive material is deposited.

[0218] Next, by performing CMP processing, the upper layer of the conductive film that will become the conductor 205 and the conductor 20 5, a portion of the lower layer of the conductive film is removed to expose the insulator 216. As a result, only the opening The conductive film that will become the conductor 205 remains on the surface of the conductor 205. It should be noted that the CMP process removes a part of the insulator 216. The above are the different methods for forming the conductor 205.

[0219] Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulating layer, an insulating film containing oxides of one or both of aluminum and hafnium is formed. It is recommended to use an insulator containing oxides of either or both of aluminum and hafnium. Examples include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium. It is preferable to use aluminum and hafnium. Insulators containing oxides of one or both of these metals have barrier properties against oxygen, hydrogen, and water. The insulator 222 has a barrier property against hydrogen and water, and thus the transistor The hydrogen and water contained in the structure provided around the rotor 200 pass through the insulator 222. Diffusion into the inside of the transistor 200 is suppressed, and oxygen vacancies are generated in the oxide 230. can be suppressed.

[0220] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using, for example.

[0221] Next, the insulator 224 is deposited on the insulator 222. The insulator 224 is deposited by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0222] Subsequently, it is preferable to carry out a heat treatment. The heat treatment is preferably carried out at a temperature of 250°C or higher and 650°C or lower. Preferably, the temperature is 300°C or higher and 500°C or lower, more preferably 320°C or higher and 450°C or lower. The heat treatment is carried out in an atmosphere of nitrogen gas or inert gas, or in an atmosphere of oxidizing gas for 10 minutes. The heat treatment is carried out in an atmosphere containing more than ppm, more than 1%, or more than 10%. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere. After treatment, oxidizing gas is added at 10 ppm or more, 1% or more, or The heat treatment may be carried out in an atmosphere containing 10% or more of silicon.

[0223] In this embodiment, after performing the treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, Then, the insulating film is heated in an oxygen atmosphere at 400°C for 1 hour. Impurities such as water and hydrogen contained in the body 224 can be removed.

[0224] The heat treatment may be performed after the formation of the insulator 222. Heat treatment conditions can be used.

[0225] Here, in order to form an excess oxygen region in the insulator 224, a plasma containing oxygen is used under reduced pressure. The oxygen-containing plasma treatment may be, for example, a high-density plasma treatment using microwaves. It is preferable to use a device having a power source that generates plasma. Alternatively, RF ( The plasma may have a power source that applies high-density plasma. By doing so, high density oxygen radicals can be generated, and by applying RF to the substrate side, As a result, oxygen radicals generated by the high-density plasma are efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, In order to compensate for the desorbed oxygen, a plasma treatment containing oxygen may be performed. By appropriately selecting the processing conditions, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, the heat treatment is not necessary.

[0226] Here, aluminum oxide is deposited on the insulator 224 by, for example, a sputtering method. After the film formation, a CMP process may be performed until the insulator 224 is reached. By performing this, the surface of the insulator 224 can be flattened and smoothed. By placing the silicon on the insulator 224 and performing the CMP process, the end point of the CMP process can be easily detected. Furthermore, the CMP process polishes a portion of the insulator 224, and the insulator 224 The thickness of the insulator 224 may be adjusted when the insulator 224 is formed. 224 Planarizing and smoothing the surface prevents a decrease in the coverage of the oxide film that will be formed later. This may prevent a decrease in the yield of the semiconductor device. By forming an aluminum oxide film on the insulating layer 224 by sputtering, This is preferable because oxygen can be added to the

[0227] Next, on the insulator 224, an oxide film 230A which becomes an oxide 230a and an oxide film 230b which becomes an oxide 230b are formed. An oxide film 230B is then formed on the surface of the silicon dioxide film 230B (see FIG. 6). It is preferable to form the oxide film 230 continuously without exposing it to the atmosphere. A, and prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230B. This allows the vicinity of the interface between the oxide film 230A and the oxide film 230B to be kept clean.

[0228] The oxide film 230A and the oxide film 230B are formed by sputtering, CVD, MBE, or the like. The method can be carried out using a method such as a PLD method or an ALD method.

[0229] For example, the oxide film 230A and the oxide film 230B are formed by sputtering. In this case, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the oxygen ratio in the sputtering gas, the excess oxygen in the oxide film to be formed can be reduced. In addition, when the oxide film is formed by sputtering, In this case, the above-mentioned In-M-Zn oxide target can be used.

[0230] In particular, when forming the oxide film 230A, part of the oxygen contained in the sputtering gas becomes an insulator. Therefore, the oxide film 230A may be sputtered with the oxide film 230A. The proportion of oxygen contained in the gas should be 70% or more, preferably 80% or more, and more preferably 100%. That's fine.

[0231] In addition, when the oxide film 230B is formed by sputtering, the oxide film 230B is formed by sputtering. The film is formed by setting the ratio of oxygen to be contained at 1% or more and 30% or less, preferably 5% or more and 20% or less. The oxygen-deficient oxide semiconductor is formed in the channel formation region. A transistor used in this region can achieve relatively high field-effect mobility.

[0232] In this embodiment, the oxide film 230A is formed by sputtering In:Ga: Zn=1:1:0.5 (2:2:1), or 1:3:4 The film is formed using an In-Ga-Zn oxide target with an atomic ratio of 230. B was prepared by sputtering with In:Ga:Zn=4:2:4.1 [atomic ratio] The films are formed using an In-Ga-Zn oxide target. Each oxide film is formed under the following conditions: By appropriately selecting the atomic ratio, the oxide 230 can be formed to suit the desired properties. good.

[0233] Next, a heat treatment may be carried out. The heat treatment may be carried out under the heat treatment conditions described above. By the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B are removed. In this embodiment, the wafer is heated at 400° C. in a nitrogen atmosphere. After one hour of treatment, the sample was treated in an oxygen atmosphere at 400°C for one hour. cormorant.

[0234] Next, a conductive film 242A is formed on the oxide film 230B. This can be done using a deposition method, CVD method, MBE method, PLD method, ALD method, etc. See Figure 6.

[0235] Next, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into islands. The oxide 230a, the oxide 230b, and the conductive layer 242B are formed. In this case, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may be thin (see FIG. See 7.).

[0236] Here, the oxide 230a, the oxide 230b, and the conductive layer 242B are at least partially The oxide 230a, the oxide 230b, and the conductor 205 are formed so as to overlap with each other. The side surfaces of the conductive layer 242B are preferably approximately perpendicular to the upper surface of the insulator 222. The oxide 230a, the oxide 230b, and the side of the conductive layer 242B are on the insulator 222. By being approximately perpendicular to the surface, when providing a plurality of transistors 200, the area can be reduced, Alternatively, the oxide 230a, the oxide 230b, and the conductive layer 242 may be formed in a single layer. The angle formed by the side surface of B and the top surface of the insulator 222 may be small. In this case, the oxide 230a, the oxide 230b, and the side surfaces of the conductive layer 242B and the insulator 222 The angle formed with the upper surface is preferably 60 degrees or more and less than 70 degrees. In the subsequent process, the covering property of the insulator 254 etc. is improved, and defects such as voids are reduced. can be done.

[0237] In addition, a curved surface is provided between the side surface of the conductive layer 242B and the upper surface of the conductive layer 242B. It is preferable that the end of the side surface and the end of the top surface are curved (hereinafter referred to as "round"). The curved surface has a radius of curvature of, for example, 3 nm at the end of the conductive layer 242B. The thickness is from 10 nm to 100 nm, preferably from 5 nm to 6 nm. This improves the film coverage in the subsequent film formation process.

[0238] The oxide film 230A, the oxide film 230B, and the conductive film 242A are processed by lithography. The processing can be performed using a dry etching method or a wet etching method. Dry etching is suitable for microfabrication.

[0239] Next, on the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B, An insulating film 254A is formed (see FIG. 8).

[0240] The insulating film 254A is preferably an insulating film having a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by sputtering. Depositing an aluminum oxide film by sputtering using a gas containing oxygen This allows oxygen to be implanted into the insulator 224. That is, the insulator 224 is made of excess It can have oxygen.

[0241] Next, an insulating film that will become the insulator 280 is formed on the insulating film 254A. The insulating film is formed by the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Next, the insulating film that will become the insulator 280 is subjected to CMP processing, so that the upper surface A flat insulator 280 is formed (see FIG. 8).

[0242] Next, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are heated. The opening is formed so as to overlap the conductor 205. The openings allow the conductors 242a, 242b, and and an insulator 254 is formed (see FIG. 9).

[0243] In addition, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are heated. For example, a part of the insulator 280 may be dry etched. The insulating film 254A is processed by a wet etching method, and a part of the insulating film 254B is processed by a wet etching method. A part of 2B may be processed by dry etching.

[0244] By using conventional dry etching and other processes, the etching gas The resulting impurities adhere to or diffuse into the surface or interior of the oxide 230a, oxide 230b, etc. Impurities include, for example, fluorine and chlorine.

[0245] Washing is carried out to remove the above impurities. These include wet cleaning, plasma treatment using plasma, and cleaning by heat treatment. Washing may be carried out in combination as appropriate.

[0246] For wet cleaning, oxalic acid, phosphoric acid, hydrofluoric acid, etc. are diluted with carbonated water or pure water. Alternatively, the cleaning process may be carried out using an aqueous solution of purified water or carbonated water. Wave washing may also be performed.

[0247] Next, a heat treatment may be carried out. The heat treatment is carried out under reduced pressure without exposure to the atmosphere. The oxide film 230C may be formed continuously. The moisture and hydrogen adsorbed on the surface of 230b are removed, and the oxide 230 The moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. is set to 200°C (see Figure 10).

[0248] Oxide film 230C is formed by sputtering, CVD, MBE, PLD, and ALD methods. The oxide film 230C can be formed by using the following method. A film that becomes the oxide film 230C is formed using the same film formation method as that for the oxide film 230B. In this embodiment, the oxide film 230C is formed by sputtering. In:Ga:Zn=1:3:4 [atomic ratio] or 4:2:4.1 [atomic ratio] The film is formed using an n-Ga-Zn oxide target.

[0249] In particular, when forming the oxide film 230C, part of the oxygen contained in the sputtering gas is converted into the oxide. 230a and oxide 230b. The proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, and more preferably Preferably, it should be 100%.

[0250] Next, a heat treatment may be carried out. The heat treatment is carried out under reduced pressure without exposure to the atmosphere. The insulating film 250A may be formed continuously. Remove the moisture and hydrogen adsorbed on the surface of 230C, etc., and further remove the oxide 230 a, oxide 230b, and oxide film 230C. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower (see FIG. 11). ).

[0251] The insulating film 250A can be formed by a method such as sputtering, CVD, MBE, PLD, or ALD. The insulating film 250A can be formed by using a silicon oxynitride film by a CVD method. It is preferable to form a film of the insulating film 250A. The temperature is preferably 0° C. or higher and lower than 450° C., and particularly preferably around 400° C. By forming the film at 00°C, an insulating film with few impurities can be formed.

[0252] Next, the conductive film 260A and the conductive film 260B are formed. 260B can be formed by sputtering, CVD, MBE, PLD, ALD, etc. For example, it is preferable to use a CVD method. The conductive film 260A is formed by the ALD method, and the conductive film 260B is formed by the CVD method. (See Figure 12.)

[0253] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and The oxide 230c is then removed by polishing the conductive film 260B until the insulator 280 is exposed. , the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) are formed. (See FIG. 13.) As a result, the oxide 230c is formed in the opening that reaches the oxide 230b. The insulator 250 is disposed so as to cover the inner wall (side wall and bottom surface). The conductor 260 is disposed so as to cover the inner wall of the opening via the oxide. 230c and the insulator 250 are disposed to fill the opening.

[0254] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is carried out for 1 hour. The moisture concentration in the insulators 250 and 280 is reduced by the heat treatment. The degree and hydrogen concentration can be reduced.

[0255] Next, the insulator 274 may be formed on the insulator 280. The insulator 274 may be formed by It can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. The insulator 274 is, for example, an aluminum oxide film formed by sputtering. The aluminum oxide film formed by sputtering is preferably Therefore, the sputtering method may extract hydrogen from the film-forming structure. By forming an aluminum oxide film, hydrogen contained in the insulator 280 is transferred to the insulator 250. In some cases, it may be possible to suppress diffusion into the oxide 230 (see FIG. 13). .

[0256] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is carried out for 1 hour. The oxygen added by the formation of the insulator 274 is removed by the heat treatment. can be injected into insulator 250 and insulator 280.

[0257] Next, an insulator 281 may be deposited on the insulator 274. The deposition of the insulator 281 may be performed by a spat This can be done using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (See Figure 13.)

[0258] Next, conductor 2 is applied to insulator 254, insulator 280, insulator 274, and insulator 281. An opening is formed that reaches the conductive material 42a or the conductive material 242b. The opening is formed by lithography. This can be done using the - method.

[0259] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator The insulating film 241 is formed by sputtering, CVD, MBE, PL The insulating film can be formed by a method such as ALD or ALD. For example, an insulating film made of aluminum oxide by the ALD method is preferably used. It is preferable to form a silicon film by anisotropic etching, for example, dry etching. By configuring the side wall of the opening in this way, oxygen from the outside can be prevented from entering. This suppresses the permeation of the conductor 240a and the conductor 240b to be formed next, thereby preventing oxidation. Furthermore, impurities such as water and hydrogen can be removed from the conductors 240a and 240b. It can prevent the spread to the outside.

[0260] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the permeation of impurities such as water and hydrogen. It is desirable to use a laminated structure containing a conductive material such as tantalum nitride or titanium nitride. The conductor 24 may be a laminate of tungsten, molybdenum, copper, or the like. The conductive film that becomes the conductor 240a and the conductor 240b can be formed by a sputtering method, a CVD method, an MBE method, or the like. The method can be carried out using a method such as a PLD method or an ALD method.

[0261] Next, a CMP process is performed to remove the conductive film that will become the conductors 240a and 240b. A portion of the insulating film is removed to expose the insulator 281. As a result, the conductive film remains only in the opening. By doing so, it is possible to form the conductors 240a and 240b with flat upper surfaces ( (See FIG. 1.) Note that the CMP process may remove a part of the insulator 281. do.

[0262] Through the above steps, a semiconductor device including the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 6 to 13, by using the manufacturing method of the semiconductor device described in this embodiment mode, In this way, the transistor 200 can be manufactured.

[0263] According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. .

[0264] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments and examples. It can be used in combination with other methods as appropriate.

[0265] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0266] [Storage device 1] FIG. 14 shows an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is disposed above the transistor 300. The capacitor element 100 is provided above the transistor 300 and the transistor 200. The transistor 200 may be the same as the transistor described in the previous embodiment. Sta 200 can be used.

[0267] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This allows the memory contents to be retained for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0268] In the semiconductor device shown in FIG. 14, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0269] In addition, the memory device shown in FIG. 14 has a memory cell array arranged in a matrix. It can be configured.

[0270] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 312 serving as a gate electrode. 16, an insulator 315 serving as a gate insulator, and a semiconductor region consisting of a portion of the substrate 311 313, and low resistance regions 314a which function as source or drain regions, and low resistance region 314b. The transistor 300 may be a p-channel or n-channel. Either a channel type or a

[0271] Here, the transistor 300 shown in FIG. 14 has a semiconductor region 313 ( The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the edge 315. Materials for adjusting the work function may also be used. It is also called a FIN type transistor because it uses a convex part. In addition, the insulating layer may have an insulating material that functions as a mask for forming the convex portions. Here, we have shown a case where a protrusion is formed by processing a part of a semiconductor substrate, but it is also possible to process an SOI substrate. A semiconductor film having a convex shape may be formed by the above process.

[0272] The transistor 300 shown in FIG. 14 is an example, and the structure is not limited to this. Appropriate transistors may be used depending on the structure and driving method.

[0273] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. Conductor 110 functions as the first electrode, conductor 120 functions as the second electrode, and It has an insulator 130 that functions as a conductor.

[0274] Also, for example, the conductor 112 provided on the conductor 246 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used in the capacitor 100, the transistor 200, and has a function as a plug or wiring electrically connected to the transistor 300.

[0275] In FIG. 14, the conductor 112 and the conductor 110 are shown as single-layer structures, but the present invention is not limited to this configuration. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties between weak conductors and highly conductive conductors with good adhesion may form a highly conductive material.

[0276] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride oxide, nitride Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride The material may be aluminum or the like, and may be provided as a laminated layer or a single layer.

[0277] For example, the insulator 130 may be made of a material with high dielectric strength such as silicon oxynitride and a material with high dielectric strength such as silicon oxynitride. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, which ensures sufficient capacitance. By using an insulator with a high dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0278] In addition, oxide is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium; oxide nitrides having silicon and hafnium; Nitrides containing ammonium.

[0279] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. silicon dioxide, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, silicon oxide with vacancies There are various types of resins, such as kon and resin.

[0280] <Wiring layer> Between each structure, a wiring layer including an interlayer film, wiring, plugs, etc. may be provided. In addition, multiple wiring layers can be provided depending on the design. Conductors that function as lines may have multiple structures collectively assigned the same symbol. In addition, in this specification and the like, the wiring and the plug electrically connected to the wiring are integrated. That is, when a part of the conductor functions as a wiring, or when a part of the conductor It may also function as a plug.

[0281] For example, an insulator 320, an insulator 322, an insulator 323, and an insulator 324 are provided over the transistor 300 as interlayer films. The insulating member 320, the insulating member 324, and the insulating member 326 are stacked in this order. The insulators 322, 324, and 326 are connected to the capacitive element 100 or the transistor. Conductors 328 and 330 are embedded in the substrate 200. The conductors 328 and 330 function as plugs or wiring.

[0282] In addition, the insulator that functions as an interlayer film acts as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be subjected to chemical mechanical polishing (CMP) to improve flatness. The surface may be planarized by a planarization process using a CMP method or the like.

[0283] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In this case, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0284] Similarly, the insulators 210, 212, 214, and 216 are electrically conductive. The conductive material 218 and the conductive material (conductive material 205) that constitutes the transistor 200 are embedded. Note that the conductor 218 is electrically connected to the capacitor 100 or the transistor 300. The conductor 120 and the insulator 130 function as a plug or wiring. An insulator 150 is provided on 130 .

[0285] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides that have insulating properties. Examples of such materials include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0286] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0287] For example, the insulators 150, 212, 352, and 354 have a relative dielectric constant It is preferable to use an insulator with a low resistance. For example, the insulator may be silicon oxide, oxynitride, or the like. Silicon, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and carbon doped silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies Preferably, the insulator comprises silicon oxide, oxynitride, or the like. Silicon, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and carbon doped silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies. It is preferable that the insulating film has a laminated structure of silicon oxide and resin. Silicon is thermally stable, so by combining it with resin, it is possible to achieve thermal stability and a dielectric constant As the resin, for example, polyester, polyolefin, Polyimide, polycarbonate, acrylic Examples include:

[0288] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, the insulators 210, 350, etc. contain impurities such as hydrogen and oxygen. An insulator having a function of suppressing the transmission of light may be used.

[0289] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide Metal oxides such as silicon nitride oxide, silicon nitride, etc. can be used.

[0290] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as silicon dioxide, Silicides such as nickel silicide may also be used.

[0291] For example, conductor 328, conductor 330, conductor 356, conductor 218, conductor 112, etc. Examples of the materials include metal materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above materials. Conductive materials such as acrylic resin can be used in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum, which has a high melting point. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. It is preferable to use a low-resistance conductive material to reduce the wiring resistance.

[0292] <<Wiring or plug in a layer provided with an oxide semiconductor>> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In this case, the insulator having the excess oxygen region An insulating material having a barrier property is provided between the insulating material and the conductor provided on the insulator having the excess oxygen region. It is preferable to provide a body.

[0293] For example, in FIG. 14, an insulating layer is formed between the insulator 224 having excess oxygen and the conductor 246. The insulator 276 is preferably provided in contact with the insulator 222 and the insulator 274. By providing the insulator 224, the transistor 200 has an insulating property having a barrier property. Furthermore, the insulator 276 can be formed into a sealing structure by the insulator 280. It is preferable that the insulator 276 also contacts a part of the insulator 280. This makes it possible to further suppress the diffusion of oxygen and impurities.

[0294] In other words, by providing the insulator 276, the excess oxygen contained in the insulator 224 is absorbed by the conductor 24 Furthermore, the presence of the insulator 276 can prevent impurities from being absorbed by the insulator 276. The diffusion of hydrogen, which is a substance, into the transistor 200 via the conductor 246 is suppressed. It is possible.

[0295] The insulator 276 has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. It is advisable to use insulating materials with this property. For example, aluminum oxide, hafnium oxide, etc. It is preferable to use other oxides such as magnesium oxide, gallium oxide, and oxide. Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride, etc. can be used. Cut.

[0296] The above is a description of the configuration example. By using this configuration, In semiconductor devices using transistors, the fluctuation of electrical characteristics is suppressed and reliability is improved. In addition, a transistor including an oxide semiconductor with high on-state current can be provided. In addition, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0297] [Storage device 2] An example of a memory device using a semiconductor device according to one embodiment of the present invention is shown in FIG. The memory device shown in FIG. 1 includes the transistor 200, the transistor 300, and the capacitor In addition to the semiconductor device having the capacitor 100, the semiconductor device also has a transistor 400.

[0298] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are connected to the source and the diode. and connect the source of transistor 400 to the second gate of transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, The first gate-source voltage and the second gate-source voltage of the transistor 400 are In the transistor 400, the second gate voltage and the first gate voltage The drain current at 0V is very small, so the transistor 200 and the transistor Even if power is not supplied to the transistor 400, the negative potential of the second gate of the transistor 200 can be maintained for a long time. This allows the transistor 200 and the transistor 400 to be maintained. A storage device having the above structure can retain stored contents for a long period of time.

[0299] Therefore, in FIG. 15, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the gate of the transistor 200. The back gate of the transistor 300 is electrically connected to the back gate of the transistor 200. The gate and the other of the source and drain of the transistor 200 are connected to the capacitor 100. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400. The wiring 1008 is electrically connected to the gate of the transistor 400, and the wiring 1009 is electrically connected to the gate of the transistor 400. The wiring 1010 is electrically connected to the back gate of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and a wiring 1009 are electrically connected.

[0300] 15 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. 0 can control the second gate voltages of the plurality of transistors 200. It is preferable to provide fewer transistors 400 than transistors 200.

[0301] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and is fabricated in parallel. The transistor 400 has a first gate electrode and a second gate electrode. The conductor 460 (conductor 460a and conductor 460b) functions as a gate electrode. Conductor 405 functions as a gate electrode, insulator 222 functions as a gate insulator, and insulator 2 24, and an insulator 450, an oxide 430c having a region where a channel is to be formed, and The conductor 442a, which functions as either a source or a drain, the oxide 431a, and the oxide The oxide 431b and the conductor 442b functioning as the other of the source and drain are 2a, and oxide 432b, and conductor 440 (conductor 440a, and conductor 440b ) and.

[0302] In the transistor 400, the conductor 405 and the conductor 205 are formed in the same layer. The oxide 431a, the oxide 432a, and the oxide 230a are formed in the same layer. , oxide 431b, oxide 432b, and oxide 230b are formed in the same layer. The conductor 442 and the conductor 242 are formed in the same layer. The insulator 450 and the insulator 250 are formed in the same layer. The conductor 460 and the conductor 260 are formed in the same layer.

[0303] It should be noted that structures formed in the same layer can be formed simultaneously. For example, oxide 4 The oxide 30c can be formed by processing an oxide film that will become the oxide 230c.

[0304] The oxide 430c that functions as the active layer of the transistor 400 is the oxide 230c, etc. Similarly, oxygen vacancies are reduced, and impurities such as water and hydrogen are reduced. The threshold voltage of the transistor 400 is increased, the off-current is reduced, and the second gate voltage Furthermore, the drain current when the first gate voltage is 0V can be made very small.

[0305] <<Dicing line>> In the following, a large-area substrate is divided into individual semiconductor elements to form multiple semiconductor devices. Dicing lines (scribe lines, dividing lines) are provided when extracting chips. The dividing method is as follows: First, grooves (dicing lines) for dividing the semiconductor elements are formed on the substrate, and then the dicing In some cases, the substrate is cut by a grinder and divided (divided) into a plurality of semiconductor devices.

[0306] Here, for example, as shown in FIG. 15, the area where the insulator 254 and the insulator 222 contact each other It is preferable to design the dicing line so that the 200, and a dicing line provided on the outer edge of the transistor 400. An opening is provided in the insulator 224 near the region where the insulator 224 is to be inserted. An insulator 254 is provided to cover the

[0307] That is, the insulator 222 and the insulator 254 are in contact with each other at the opening provided in the insulator 224. For example, the insulator 222 and the insulator 254 are made of the same material and by the same method. The insulator 222 and the insulator 254 may be formed using the same material and method. For example, it is preferable to use aluminum oxide. It's nice.

[0308] With this structure, the insulator 222 and the insulator 254 form a transistor 200, and can encapsulate the transistor 400. Insulator 222, and The body 254 has a function of suppressing the diffusion of oxygen, hydrogen, and water. The substrate is divided into multiple chips by dividing it into circuit regions where semiconductor elements shown in Even if the substrate is processed into a chip, impurities such as water and hydrogen can enter from the side of the divided substrate, causing damage to the transistor. Therefore, diffusion to the transistor 200 and the transistor 400 can be prevented.

[0309] In addition, this structure allows excess oxygen in the insulator 224 to migrate to the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 can be prevented from diffusing to the outside. The oxide on which the channel of the transistor 200 or the transistor 400 is formed is The oxygen is supplied to the transistor 200 or the transistor 400. This reduces the oxygen vacancies in the oxide in which the channel is formed. The oxide on which the channel in transistor 200 or transistor 400 is formed is then subjected to a defect-level An oxide semiconductor having low potential density and stable characteristics can be obtained. The fluctuation of the electrical characteristics of the transistor 200 or the transistor 400 is suppressed, and the reliability is improved. It can be raised.

[0310] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement.

[0311] (Embodiment 3) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 16 and 17. A transistor used as a conductor (hereinafter, sometimes referred to as an OS transistor) and a capacitor The following describes a storage device to which the device is applied (hereinafter, sometimes referred to as an OS memory device). The OS memory device includes at least a capacitance element and an OS transistor that controls charging and discharging of the capacitance element. The off-state current of an OS transistor is extremely small. The OS memory device has excellent retention characteristics and can function as a non-volatile memory. .

[0312] <Storage device configuration example> FIG. 16A shows an example of the configuration of an OS memory device. 411, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 142 0, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460. do.

[0313] The column circuitry 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write The precharge circuit has a function of precharging the wiring. The amplifier has the function of amplifying the data signal read from the memory cell. The lines are wirings connected to memory cells in the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal RDA TA to the outside of the storage device 1400. It has a decoder, a word line driver circuit, etc., and can select a row to be accessed.

[0314] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 The high power supply voltage (VDD) for the 11 and the high power supply voltage (VIL) for the memory cell array 1470 are The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The data signal WDATA is input to the write circuit. do.

[0315] The control logic circuit 1460 receives externally input control signals (CE, WE, R E) to generate control signals for the row decoder and column decoder. The control signal WE is a write enable signal, and the control signal R E is a read enable signal. The signal is not limited to this, and other control signals may be input as required.

[0316] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0317] In FIG. 16A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. Although an example in which the film is formed on a surface has been shown, the present embodiment is not limited to this. For example, as shown in FIG. 16B, the memory cell array 1411 is provided on a part of the peripheral circuit 1411. 70 may be provided so as to overlap the memory cell array 1470. For example, In this way, a sense amplifier may be provided.

[0318] FIG. 17 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0319] [DOSRAM] 17A to 17C show examples of circuit configurations of memory cells in a DRAM. In this case, a DRAM using a memory cell of one OS transistor and one capacitor element type is called DOSRA. The memory cell 1471 shown in FIG. 17A includes a transistor M1 and a , and a capacitance element CA. The transistor M1 has a gate (called a top gate) ) and a back gate.

[0320] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0321] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably used to apply a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, The threshold voltage of M1 can be increased or decreased.

[0322] Furthermore, the memory cells MC are not limited to the memory cells 1471, and the circuit configuration may be changed. For example, the memory cell MC can be configured as a memory cell 1472 shown in FIG. In addition, the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be configured as the memory cell 14 shown in FIG. As shown in 73, a transistor with a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with a resistor M1.

[0323] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This makes it possible to make the leakage current of the transistor M1 very small. The transistor M1 allows the data to be retained for a long time, reducing the frequency of refreshing the memory cells. In addition, the refresh operation of the memory cells can be made unnecessary. In addition, since the leakage current is very small, the memory cells 1471 and 147 2. The memory cell 1473 can store multi-value data or analog data. do.

[0324] In addition, in the DOSRAM, as described above, the memory cell array 1470 is overlapped with the By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0325] [NOSRAM] 17(D) to 17(G) show the structure of a gain cell type memory cell having two transistors and one capacitor. A circuit configuration example is shown in FIG. 17D. A memory cell 1474 shown in FIG. 17D includes a transistor M2 and The transistor M2 is a top gate. In this specification, etc., The memory cell has a gain cell type memory cell using an OS transistor as the transistor M2. The memory device is NOSRAM (Nonvolatile Oxide Semiconductor It is sometimes called tor RAM.

[0326] The first terminal of the transistor M2 is connected to the first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of transistor B is connected to the line CAL. The first terminal of transistor M3 is connected to the line R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to the first terminal of the capacitance element CB.

[0327] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL functions as the second wiring of the capacitance element CB. It functions as a wiring for applying a predetermined potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the The threshold voltage can be increased or decreased.

[0328] Furthermore, the memory cells MC are not limited to the memory cells 1474, and the circuit configuration may be changed as appropriate. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be the memory cell shown in FIG. Like the 1476, it is a single-gate transistor, i.e., it does not have a back gate. The memory cell may be configured with a transistor M2. As shown in FIG. 17(G), the wiring WBL and the wiring RBL are connected in a single line. The wiring BIL may be integrated.

[0329] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as the transistor M2, and the transistor 300 is used as the transistor M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very small. This allows the written data to be stored for a long time by the transistor M2. Since the memory cells can be maintained at the same level, the frequency of refreshing the memory cells can be reduced. Furthermore, the refresh operation of the memory cells can be eliminated. Since the memory cell 1474 is always small, it can store multi-value data or analog data. The same applies to memory cells 1475 to 1477.

[0330] The transistor M3 is a transistor having silicon in the channel forming region (hereinafter referred to as The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. The field effect mobility may be higher than that of a read transistor. A Si transistor may be used as the transistor M3 that functions as a By using a Si transistor for transistor M3, a transistor can be stacked on top of transistor M3. Since the memory cell can be provided with the transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0331] The transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M3, the memory cell array 1470 is The circuit can be constructed using only transistors.

[0332] FIG. 17(H) shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 17(H) includes transistors M4 to M 6 and a capacitor CC. The capacitor CC is provided as appropriate. is electrically connected to the wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. The wiring GNDL is a wiring that applies a low level potential. The wiring 478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

[0333] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0334] The transistors M5 and M6 are n-channel Si transistors. Alternatively, the transistors M4 to M5 may be p-channel Si transistors. The transistor M6 may be an OS transistor. In this case, the memory cell array 1470 is configured as an n-type transistor. The circuit can be constructed using only transistors.

[0335] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor M4 is a transistor 200, and the transistors M5 and M6 are transistors M1 and M2. The transistor 300 can be used as the capacitance element CC, and the capacitance element 100 can be used as the capacitance element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be reduced. The flow can be very small.

[0336] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are These circuits, and the wiring and circuits connected to the circuits, The arrangement or function of road elements etc. may be changed, deleted or added as required.

[0337] The structure shown in this embodiment mode may be combined as appropriate with structures shown in other embodiment modes, examples, etc. It can be used as such.

[0338] (Fourth embodiment) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. A chip 1200 is implemented with multiple circuits (systems). The technology of integrating multiple circuits (systems) on a single chip is called system-on-chip ( It is sometimes called System on Chip (SoC).

[0339] As shown in FIG. 18A, the chip 1200 includes a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing a memory controller 1212, one or more analog calculation units 1213, and one or more memory controllers 1214. controller 1214, one or more interfaces 1215, one or more networks It has a work circuit 1216 and the like.

[0340] The chip 1200 is provided with bumps (not shown), and as shown in FIG. 18(B), Printed Circuit Board (PCB) 1201 No.1 The first surface of the PCB 1201 is connected to the second surface. It is provided and connected to the motherboard 1203.

[0341] The motherboard 1203 is equipped with memory devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be configured as The NOSRAM shown in FIG.

[0342] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CPs 212 may have a memory for temporarily storing data. The memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. The GPU1212 is also suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This becomes possible.

[0343] In addition, the CPU 1211 and GPU 1212 are mounted on the same chip, The wiring between the CPU1211 and GPU1212 can be shortened, and Data transfer from CPU 1211 to GPU 1212, memory After the data transfer between the GPUs and the calculations in GPU1212, the GPU1212 transfers the data to CPU12. The calculation results can be transferred to 11 at high speed.

[0344] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit. The product-sum calculation circuit may be provided in the

[0345] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. , and a circuit that functions as an interface to the flash memory 1222.

[0346] The interface 1215 includes a display device, a speaker, a microphone, a camera, a computer, and the like. The controller has an interface circuit with external devices such as a This includes devices such as mice, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) You can be there.

[0347] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0348] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering iron, and the chip 1200 can be produced at low cost.

[0349] A PCB 1201 on which a chip 1200 having a GPU 1212 is mounted, a DRAM 122 1 and a motherboard 1203 provided with a flash memory 1222. It can be called module 1204.

[0350] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, it has excellent image processing capabilities, making it suitable for smart devices. Phones, tablets, laptops, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep neural networks (DNNs), convolutional neural networks (CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann It can implement techniques such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0351] The structure shown in this embodiment mode may be combined as appropriate with structures shown in other embodiment modes, examples, etc. It can be used as such.

[0352] (Embodiment 5) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, computers include tablet computers, notebook computers, desktop computers, This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment may be used in a memory card (for example, an SD card). Various removable drives such as flash drives, USB flash drives, and SSDs (Solid State Drives) This is applied to removable storage devices. Figure 19 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed and used in various storage devices and removable memory.

[0353] 19A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, the controller chip 1106 is installed. The semiconductor device shown in the embodiment can be incorporated.

[0354] Figure 19(B) is a schematic diagram of the external appearance of an SD card, and Figure 19(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into such a device.

[0355] FIG. 19(D) is a schematic diagram of the external appearance of the SSD, and FIG. 19(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing the memory chip 115, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 4 or the like.

[0356] This embodiment may be implemented by appropriately combining with the configurations described in other embodiments, examples, etc. It is possible to do this.

[0357] (Sixth embodiment) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. FIG. 20 shows a processor such as a CPU or a GPU according to one embodiment of the present invention. Specific examples of electronic devices equipped with the chip are shown below.

[0358] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, and Personal computers, computer monitors, digital signage Digital Signage, pachinko machines and other large game machines. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos Examples include frames, mobile phones, portable game consoles, personal digital assistants, and sound reproduction devices. Furthermore, by providing an integrated circuit or a chip according to one embodiment of the present invention in an electronic device, It is possible to equip the sub-device with artificial intelligence.

[0359] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0360] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Number, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared) It may have.

[0361] The electronic device of one embodiment of the present invention can have various functions. (still images, videos, text images, etc.) on the display, touch panel function, calendar Functions such as displaying date and time, running various software (programs) functions, wireless communication functions, and functions to read programs or data recorded on recording media. It can have functions, etc. Figure 20 shows an example of an electronic device.

[0362] [mobile phone] FIG. 20(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 551. It is provided for 0.

[0363] The information terminal 5500 uses a chip according to one embodiment of the present invention to perform a function using artificial intelligence. It is possible to run applications that utilize artificial intelligence. For example, the application recognizes conversations and displays the conversation contents on the display unit 5511. The display unit 5511 recognizes characters, figures, etc. input by the user on the touch panel. and applications to be displayed on the display unit 5511, applications that perform biometric authentication such as fingerprints and voiceprints, etc. Applications, etc.

[0364] [Information terminal] 20(B) shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard. It has a code 5303.

[0365] The desktop information terminal 5300 is one of the features of the present invention, similar to the information terminal 5500 described above. By applying the chip of the present invention, it is possible to execute applications using artificial intelligence. Examples of applications that use artificial intelligence include design support software. , writing correction software, automatic menu generation software, etc. By using the laptop information terminal 5300, new artificial intelligence can be developed.

[0366] In the above, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Figure 20(A) and (B), the smartphone and desktop Information terminals other than personal information terminals can be applied. Smartphones and desktops Examples of information terminals other than personal information terminals include PDAs (Personal Digital Assistants). Assistant), notebook information terminals, and workstations.

[0367] [electric appliances] FIG. 20(C) shows an electric refrigerator-freezer 5800, which is an example of the electric appliance. The refrigerator 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, etc. do.

[0368] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, an electric refrigerator-freezer 5800 can be realized. The Electric Refrigerator-Freezer 5800 is a refrigerator-freezer that can be used to store food and drink. It has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients stored in the electric refrigerator-freezer 5800. It can have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0369] In this example, an electric refrigerator-freezer was described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water dispenser, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0370] [Game consoles] FIG. 20(D) shows a portable game machine 5200, which is an example of a game machine. The computer includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0371] By applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, It is possible to realize a portable game machine 5200 with low power consumption. Since heat generation from the circuit can be reduced, the circuit itself, peripheral circuits, and The impact on the module can be reduced.

[0372] Furthermore, by applying a GPU or chip according to one embodiment of the present invention to the portable game console 5200, This makes it possible to realize a portable game machine 5200 with artificial intelligence.

[0373] Originally, the progress of the game, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 520 By applying artificial intelligence to 0, it becomes possible to express things that are not limited to game programs. For example, the content of the player's questions, the game progress, the time, and the characters that appear in the game. This makes it possible to express how a person's behavior changes depending on the situation.

[0374] In addition, when playing games that require multiple players on the handheld game console 5200, artificial intelligence This allows you to create anthropomorphic game players, so you can turn your opponents into AI. By using multiple game players, you can play the game alone.

[0375] In FIG. 20(D), a portable game machine is shown as an example of a game machine. The game machine to which the GPU or chip of the present invention is applied is not limited to this. Examples of game machines that apply PU or chips include home-use stationary game machines, Arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), sports facilities Examples include pitching machines for batting practice that are installed in the facility.

[0376] [Moving object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the vicinity of the driver's seat of the automobile. can be applied to.

[0377] FIG. 20(E1) shows an automobile 5700 as an example of a moving object, and FIG. 20(E2) shows an automobile FIG. 20(E2) is a diagram showing the area around the windshield in the interior of a vehicle. Display panels 5701, 5702, and 5703 attached to the board Also shown is a display panel 5704 mounted on the pillar.

[0378] The display panels 5701 to 5703 display a speedometer, a tachometer, It provides various information by displaying the driving distance, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be adjusted by the user. It can be changed as needed to suit your taste, enhancing the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0379] The display panel 5704 displays an image from an imaging device (not shown) provided in the automobile 5700. By projecting the image from the pillar, it is possible to compensate for the blind spot (obstructed view) caused by the pillar. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, This can compensate for blind spots and increase safety. By displaying the image on the display panel 57, safety checks can be performed more naturally and without discomfort. 04 can also be used as a lighting device.

[0380] The GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in the autonomous driving system of the automobile 5700. The chip can be used in systems that provide road guidance, risk prediction, etc. Display panel 57 The display panels 5701 to 5704 are configured to display information such as road guidance and risk prediction. Good too.

[0381] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, These include vehicles such as drones, airplanes, and rockets. Applying the chip of one aspect of the present invention to a moving object and providing it with a system that utilizes artificial intelligence can be done.

[0382] [Broadcasting System] The GPU or chip according to one aspect of the present invention can be applied to a broadcasting system.

[0383] FIG. 20(F) shows a schematic diagram of data transmission in a broadcasting system. 20(F) shows how radio waves (broadcast signals) transmitted from a broadcasting station 5680 are transmitted to televisions in each home. The diagram shows the path the signal takes to reach the TV receiver (TV) 5600. The broadcast signal received by the antenna 5650 is transmitted to the receiving device (not shown). It is sent to the TV5600 via

[0384] In FIG. 20(F), the antenna 5650 is a UHF (Ultra High Frequency) The antenna shown is a BS 110°CS antenna. Antennas, CS antennas, etc. can also be applied.

[0385] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 The received radio wave 5675A is amplified and radio wave 5675B is transmitted. By receiving radio waves 5675B with Na 5650, you can watch terrestrial TV broadcasts on TV 5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 20(F), but may be any other type of broadcasting system. It may also be satellite broadcasting using an industrial satellite, data broadcasting via optical fiber lines, or the like.

[0386] The above-described broadcasting system applies the chip according to one aspect of the present invention to broadcast using artificial intelligence. The broadcasting station 5680 transmits broadcast data to the TV 5600 in each home. When the encoder is activated, the broadcast data is compressed and the antenna 5650 receives the broadcast data. When the data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the compression method of the encoder can be Recognizing display patterns contained in displayed images in motion compensation prediction, which is one of the methods It is also possible to perform intra-frame prediction using artificial intelligence. For example, low-resolution broadcast data is received and then displayed on the TV5600 with high resolution. When displaying the broadcast data, the decoder may perform up-conversion or other operations to restore the broadcast data. Image interpolation can be performed.

[0387] The AI-based broadcasting system described above is expected to be a key component of the ultra-high definition television broadcasting system, which will see an increase in the amount of broadcast data. It is suitable for revision (UHDTV: 4K, 8K) broadcasting.

[0388] In addition, as an application of artificial intelligence on the TV5600 side, for example, By using such a configuration, the recording device By having AI learn user preferences, it can automatically record programs that match the user's preferences. It can be depicted.

[0389] Electronic devices described in the present embodiment, functions of the electronic devices, application examples of artificial intelligence, and their effects etc. can be appropriately combined with descriptions of other electronic devices.

[0390] This embodiment may be implemented by appropriately combining with the configurations described in other embodiments, examples, etc. It is possible to do this. [Example]

[0391] In this example, a transistor 200 (referred to as Sample 1B) according to one embodiment of the present invention was fabricated. The shape of sample 1B was evaluated using a scanning transmission electron microscope. Mirror (STEM:Scanning Transmission Electron Mi croscope and energy dispersive X-ray spectroscopy (EDX). Transverse X-ray spectroscopy was used.

[0392] The method for fabricating Sample 1B will be described below. For details, please refer to the descriptions in FIGS. 6 to 13.

[0393] A tungsten film was used as the conductor 205. An oxynitride film was used as the insulator 216. A silicon film was used. In addition, the insulator 222 functioning as a second gate insulator and the insulating film As the body 224, an aluminum oxide film and a silicon oxynitride film were used, respectively.

[0394] As the first oxide to be the oxide 230a, In-Ga-Z The first oxide was formed from In:Ga:Zn in an atomic ratio of 1:3:4. The film was formed using an n-Ga-Zn oxide target. Then, a second oxide was formed on the first oxide. As the second oxide to be 230b, In-Ga-Zn oxide was deposited by sputtering. The second oxide was an In- Ga -Zn film with an atomic ratio of In:Ga:Zn=4:2:4.1. The film was formed using a Ga-Zn oxide target.

[0395] Next, a heat treatment was carried out at a temperature of 400°C for 1 hour in a nitrogen-containing atmosphere. Then, the substrate was treated in an oxygen-containing atmosphere at 400°C for 1 hour.

[0396] Next, a tantalum nitride film is formed on the second oxide as a conductor to be the conductor 242. Thereafter, the tantalum nitride film, the second oxide, and the first oxide were processed. , conductive layer 242B, oxide 230b, and oxide 230a were formed.

[0397] Next, an aluminum oxide film was formed as an insulator 254 on the conductive layer 242B. In addition, a silicon oxynitride film was formed as an insulator 280. The silicon oxynitride film, the aluminum oxide film, and the conductive layer 242B are heated using the The opening and the conductor 242 were formed.

[0398] Next, in the opening, an In-Ga- Zn oxide was deposited by sputtering with the atomic ratio of In:Ga:Zn=4:2:4.1. The film was formed using an In-Ga-Zn oxide target. As the fourth oxide, In-Ga-Zn oxide was deposited by sputtering. Deposition using an In-Ga-Zn oxide target with an atomic ratio of Ga:Zn=1:3:4 did.

[0399] Next, a silicon oxynitride film was formed as an insulating film to be the insulator 250 .

[0400] Next, a titanium nitride film is formed on the insulating film that will become the insulator 250 as a conductive film that will become the conductor 260a. Next, a tungsten film was formed as a conductive film to become the conductor 260b. The titanium nitride film and the tungsten film were formed by successive film formation. After that, the tungsten film, the titanium nitride film, the insulating film that will become the insulator 250, and the fourth oxide film are The third oxide is processed to form the conductor 260b, the conductor 260a, the insulator 250, and and oxide 230c was formed.

[0401] Next, an aluminum oxide film is formed as an insulator 274, and an aluminum oxide film is formed as an insulator 281. A silicon nitride film was formed.

[0402] Through the above steps, Sample 1B was fabricated.

[0403] <Cross-section observation and elemental analysis of sample 1B> The results of cross-sectional observation and elemental analysis of Sample 1B are described below. The EDX measurement device used was the HD-2300 manufactured by Hitachi High-Technologies Corporation. The device used was an EDX Si(Li) detector manufactured by EDAX. The area of ​​sample 1 located between the dashed line L1-L2 and the dashed line L3-L4 is 21(B) is a cross-sectional STEM image of B. Also, FIG. 21(B) is an EDX map of the Al-K line. The area where the EDX map was obtained was the area where the cross-sectional STEM image shown in FIG. 21(A) was obtained. This is the same area as the area where

[0404] 21(A) and 21(B), the opening formed in the insulator 280 etc. is tapered. It can be seen that the side of the conductor 242a and the side of the oxide 230b have a slender shape. and a surface parallel to the side edge of the insulator 254 in the region 256a that contacts the surface and the side surface of the oxide 230a. The side surfaces of the conductors 242b and the conductors 242a facing each other are approximately aligned. Also, the side of the conductor 242b, the side of the oxide 230b, and the side of the oxide 230a The surface of the insulator 254 in the region 256b that contacts the surface is parallel to the side edge of the conductor 242a. It can be seen that the surface of the conductor 242b is substantially aligned with the side surface of the conductor 242b facing the conductor 242b.

[0405] <Plane observation and elemental analysis of sample 1B> Next, the results of planar observation and elemental analysis of sample 1B will be described. Before performing planar observation and elemental analysis of sample 1B, sample 1B was processed. The upper surface of the sample 1B is flattened until the upper surfaces of the conductive body 242a and the conductive body 242b are exposed. The lower surface of the sample 1B was flattened until the conductor 205 could be removed.

[0406] Planar observation and elemental analysis were performed on the processed sample 1B. The EDX measurement was performed using the above-mentioned equipment. Figure 22(A) shows a planar STEM image of sample 1B. FIG. 22(B) is an EDX map of Al-K line. The area where the planar STEM image was acquired is the same area where the planar STEM image was acquired.

[0407] 22(A) and 22(B), the distance corresponding to the distance LE2 shown in FIG. 3 is It can be seen that the distance is shorter than the distance corresponding to the distance LE1 shown in Fig. It can be seen that the side edges of the mating insulator 254 are curved in shape.

[0408] This embodiment can be implemented by appropriately combining with the configurations described in other embodiment modes. be. [Explanation of symbols]

[0409] BGE: Conductor, BGI1: Insulator, BGI2: Insulator, CAP: Insulator, DE: Conductor Body, LE1: distance, LE2: distance, LG1: length, LG2: length, SE: conductor, SEM 1: Semiconductor, SEM2: Semiconductor, SEM3: Semiconductor, TGE: Conductor, TGI: Insulator, 100: Capacitive element, 110: Conductor, 112: Conductor, 120: Conductor, 130: Insulator , 150: insulator, 200: transistor, 205: conductor, 210: insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 220: Insulator, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 23 0b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 231: region , 231a: area, 231b: area, 234: area, 239: area, 240: conductor, 2 40a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator Edge, 242: Conductor, 242a: Conductor, 242A: Conductive film, 242b: Conductor, 24 2B: Conductive layer, 243: Area, 243a: Area, 243b: Area, 244: Angle, 244 a: angle, 244b: angle, 246: conductor, 248: angle, 250: insulator, 250A : insulating film, 254: insulator, 254A: insulating film, 256a: region, 256b: region, 25 8: Angle, 258a: Angle, 258b: Angle, 260: Conductor, 260a: Conductor, 26 0A: Conductive film, 260B: Conductive film, 260b: Conductor, 274: Insulator, 276: Insulator , 280: insulator, 281: insulator, 300: transistor, 311: substrate, 313: semiconductor Conductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor conductor, 330: conductor, 350: insulator, 352: insulator, 354: insulator, 356: conductor Conductor, 400: transistor, 405: conductor, 430c: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 440: conductor, 440a: Conductor, 440b: Conductor, 442: Conductor, 442a: Conductor, 442b: Conductor, 4 50: insulator, 460: conductor, 460a: conductor, 460b: conductor, 1001: wiring , 1002: Wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring ,1007: Wiring, 1008: Wiring, 1009: Wiring, 1010: Wiring, 1100: US B memory, 1101: housing, 1102: cap, 1103: USB connector, 1104 : Board, 1105: Memory chip, 1106: Controller chip, 1110: SD card 1111: housing, 1112: connector, 1113: board, 1114: memory chip, 1115: Controller chip, 1150: SSD, 1151: Housing, 1152: Connector 1153: board, 1154: memory chip, 1155: memory chip, 1156: Controller chip, 1200: Chip, 1201: PCB, 1202: Bump, 1203 : Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analog calculation unit, 1214: Memory controller, 1215: Interface 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 1400: memory device, 1411: peripheral circuit, 1420: row circuit, 1430: column circuit, 14 40: output circuit, 1460: control logic circuit, 1470: memory cell array, 1471: memory cell, 1472: memory cell, 1473: memory cell, 1474: memory recell, 1475: memory cell, 1476: memory cell, 1477: memory cell, 147 8: Memory cell, 5200: Portable game console, 5201: Housing, 5202: Display unit, 520 3: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display Ray, 5303: Keyboard, 5500: Information terminal, 5510: Housing, 5511: Display unit ,5600:TV, 5650:antenna, 5670:radio tower, 5675A:radio wave, 567 5B: Radio waves, 5680: Broadcasting stations, 5700: Automobiles, 5701: Display panels, 5702: Display panel, 5703: Display panel, 5704: Display panel, 5800: Electric refrigerator-freezer , 5801: Housing, 5802: Refrigerator door, 5803: Freezer door

Claims

1. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second insulator on the first oxide; a third conductor on the second insulator; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with openings that reach the first oxide; the second insulator is disposed so as to cover an inner wall of the opening; the third conductor is disposed so as to fill the opening with the second insulator interposed therebetween; a height of a bottom surface of the third conductor in a region not overlapping with the first oxide, with respect to a bottom surface of the first insulator, being lower than a height of a bottom surface of the first oxide in a channel width direction of the transistor; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

2. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second insulator on the first oxide; a third conductor on the second insulator; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with openings that reach the first oxide; the second insulator is disposed so as to cover an inner wall of the opening; the third conductor is disposed so as to fill the opening with the second insulator interposed therebetween; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; an angle formed by a plane parallel to a bottom surface of the second insulator and a side surface of the first conductor facing the second conductor in the channel length direction of the transistor is smaller than 90 degrees; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

3. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second oxide on the first oxide; a second insulator on the second oxide; a third conductor on the second insulator; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with openings that reach the first oxide; the second oxide is disposed so as to cover an inner wall of the opening; the second insulator is disposed so as to cover an inner wall of the opening with the second oxide interposed therebetween; the third conductor is disposed so as to fill the opening via the second oxide and the second insulator; a height of a bottom surface of the third conductor in a region not overlapping with the first oxide, with respect to a bottom surface of the first insulator, being lower than a height of a bottom surface of the first oxide in a channel width direction of the transistor; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

4. A semiconductor device having a transistor, The transistor is a first insulator; and a first oxide on the first insulator; a first conductor and a second conductor on the first oxide; a second oxide on the first oxide; a second insulator on the second oxide; a third conductor on the second insulator; and a third insulator on the first conductor and the second conductor; a fourth insulator on the third insulator; the third insulator and the fourth insulator are provided with openings that reach the first oxide; the second oxide is disposed so as to cover an inner wall of the opening; the second insulator is disposed so as to cover an inner wall of the opening with the second oxide interposed therebetween; the third conductor is disposed so as to fill the opening via the second oxide and the second insulator; a length of a bottom surface of the third conductor in a region that does not overlap with the first oxide in a channel length direction of the transistor is shorter than a length of a bottom surface of the third conductor in a region that overlaps with the first oxide; an angle formed by a plane parallel to a bottom surface of the second insulator and a side surface of the first conductor facing the second conductor in the channel length direction of the transistor is smaller than 90 degrees; When the transistor is viewed from above, a side end of the third insulator on the first conductor and a side end of the third insulator on the second conductor have a curved shape.

5. In any one of claims 1 to 4, The semiconductor device, wherein the fourth insulator includes an oxide of aluminum.

6. In any one of claims 1 to 5, The semiconductor device, wherein the first oxide contains at least indium or zinc.

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