Burst access memory and method for operating burst access memory

Abstract

To provide an internal mechanism and structure for improving the access speed and / or the power consumption of a burst access memory.SOLUTION: A burst access memory includes a memory array comprising a plurality of memory macros, each including an array of memory cells arranged in rows and columns, and a controller configured to schedule burst accesses of the burst access memory by generating a plurality of macro accesses to the memory macros. The controller is further configured to schedule the plurality of macro accesses to begin with a predetermined delay relative to each other. Each macro access is divided into a plurality of ordered sub-operations. Consecutive macro accesses are directed to different memory macros and different columns, and data for the consecutive macro accesses is arranged in different memory macros and different columns to correspond to the consecutive macro accesses.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present disclosure relates to burst access memories having internal mechanisms and structures for improving access speed and / or power consumption. [Background technology]

[0002] Memories such as static random access memories (SRAMs) are widely used in integrated circuits and may form an important part of the critical timing path in digital designs, for example in digital ASICs (application-specific integrated circuits). A typical memory cell in an SRAM memory is a six-transistor (6T) memory cell, consisting of six MOSFETs. Each bit is stored in four transistors that form two cross-coupled inverters. In addition to the four transistors, the two cross-coupled inverters are connected to a bit line and an inverted bit line via two further access transistors, which are controlled by a common word line in a standard single-port 6T SRAM cell. Other types of SRAMs exist.

[0003] SRAM memory cells are typically accessed using an address that is decoded to provide or access the appropriate word and bit lines. The time required to access memory is often a limiting factor in circuit designs that must be clocked at increasingly higher frequencies. If the time it takes for the memory to output data is longer than the clock period at which the circuit operates, designers can reduce the design's clock frequency, which can affect performance, or apply other techniques, such as dividing the memory into multiple smaller instances. One technique for speeding up memory access is to use burst access. With burst access, the memory begins reading or writing at a given address and then continues reading or writing data from / to consecutive addresses. This saves some decoding time. However, utilizing burst access may not be sufficient to meet design goals for a given process technology's speed (clock frequency) and operating voltage.

[0004] Therefore, it would be advantageous to have a burst access memory that can operate at a higher clock frequency compared to the operating voltage of a given process technology. Summary of the Invention

[0005] The present disclosure relates to a burst access memory with improved relative read and write speeds. When accessing a memory, an external command in the form of an enable signal, an address, and data must be decoded and propagated to the memory array where the access needs to be performed. When data is read, the data must pass through bit lines, sense amplifiers, and output logic. When operating at very high speeds, the entire signal path for access is often a bottleneck. However, in burst mode, the delays resulting from decoding and bit cell access are eliminated. The present disclosure relates to further improvements in burst access of memories. According to a first embodiment, a burst access memory comprises: a memory array including a plurality of memory macros, each including an array of memory cells arranged in rows and columns, the memory cells in each column being connected by at least one local bit line, the array of memory cells and the local bit line defining a memory macro; a plurality of global bit lines and bit line switches, each global bit line being connectable to a corresponding number of local bit lines of a memory macro; a controller configured to schedule burst accesses of a burst access memory by generating multiple macro accesses to a memory macro, the multiple macro accesses being scheduled to begin with a predetermined delay relative to each other; Each macro access may be divided into multiple ordered sub-operations, with successive macro addresses directed to different memory macros and different columns, and data for successive macro accesses arranged in different memory macros and different columns to match the successive macro accesses. A new macro access may be scheduled to begin with each clock cycle of the clock signal, and preferably the multiple ordered sub-operations are executed sequentially, with each sub-operation starting with each cycle of the clock signal. A "clock cycle" in this context may be considered a reference clock or system clock. As will be appreciated by those skilled in the art, if there is another clock signal operating at a different frequency, each sub-operation need not necessarily start with each cycle. As an example, if the system clock operates at 5 GHz and a second, faster clock operates at 10 GHz, a sub-operation may start with every second clock cycle of the 10 GHz clock. It is also possible for different sub-operations to use different numbers of clock cycles to be executed. For such an embodiment, the burst access memory may be configured to take such differences into account. As a result, the stream of starting sub-operations need not be distributed perfectly evenly: for example, a sub-operation associated with a decode task may take, say, one clock cycle, while a sub-operation associated with a bit line may take several clock cycles.

[0006] Macro accesses to memory macros may be read or write accesses. A burst, in the context of this disclosure, may be read accesses only, write accesses only, or a mixture of read and write accesses. As an example, an access may consist of alternating read and write accesses (e.g., read-write-read-write). As a second example, an access may consist of several read accesses followed by several write accesses (e.g., read-read-read-read-write-write-write-write). Memories that support both read and write accesses shall be considered a common option throughout this disclosure. Burst-access memories may further include input and / or output multiplexers shared among memory macros. Multiple global bit lines may be connected directly to the output multiplexer, as shown in FIG. 1A, or may be connected to read or write circuitry, such as sense amplifiers, connected to the multiplexer, as shown in FIG. 1B. Similarly, when a write operation is performed, an input multiplexer or any logic may be used to direct the data to be written to the correct column, optionally through a buffer 113, as shown in FIG. 1C. A memory macro can be considered a subset of memory cells of a memory. Thus, a memory macro includes an array of memory cells arranged in rows and columns. A memory macro may further include local bit lines for the columns, with the memory cells of each column being connected by at least one local bit line. In the context of the present invention, a memory macro does not include local read / write buffers, sense amplifiers, and buffers. The local bit lines of one column of several memory macros may be connected to a global bit line shared by the memory macros.By using this structure and schedule, where each macro access is divided into multiple ordered sub-operations and consecutive macro accesses are directed to different memory macros and different columns, and the data of consecutive macro accesses are arranged in different memory macros and different columns to match consecutive macro accesses, a solution is achieved that allows central multiplexing and reading, as shown in FIG. 1A , for example, where, given an example read operation, sense amplifiers 112 are placed after multiplexer 111 relative to memory array 107. Note that, as defined in this disclosure, a “memory macro” is an array of memory cells without read / write logic. A memory macro may also be referred to as a “plain memory macro.” Therefore, memory macros of the burst access memory of this disclosure may share the same decode unit, sense amplifiers, and / or any other read / write logic.

[0007] The embodiments can be said to break the critical path of memory access. The clock signal, which may be a clock signal used for logic related to input and / or output (I / O) in the memory and / or further peripheral logic, may be a very high-frequency clock signal, such as at least 1 GHz, or at least 2 GHz, or at least 5 GHz, or at least 10 GHz. Accessing the memory cell itself may not be possible within one such clock cycle. Therefore, the controller may be configured to generate multiple macro accesses to the memory macro, each lasting several clock cycles. Thus, the macro access may be referred to as a multi-cycle macro access relative to the high-speed clock signal for the I / O logic. The inventors have realized that a multi-cycle macro access can be divided into multiple ordered sub-operations that are executed consecutively. By initiating one macro access with a predetermined delay relative to the previous macro access—which can be done, for example, by initiating a new macro access every clock cycle of the high-speed clock—parallel utilization of functions related to the memory array is possible. The operating principles and advantages are similar to those of pipeline processing. Pipelining has been applied to memory access in conventional solutions, for example, by dividing the critical path into an address decode stage, an access stage, and an output stage. However, this does not solve the problem that the memory access itself may be a bottleneck. In the burst access memory of the present disclosure, the critical path of memory access is also broken. This is done by using multiple memory macros and dividing each macro access into multiple ordered sub-operations related to the operation of a memory cell, such as, for example, steps for applying voltage levels to word lines and bit lines, bit line precharge steps, and sense amplifier activation steps. One challenge with such parallelism in a memory array is that some of the hardware used may be active and used by several consecutive sub-operations.The inventors have realized that a particular organization of data within a memory array combined with a particular access order can solve such problems. According to a first embodiment, the memory array is divided into a plurality of memory macros, each of which includes an array of memory cells arranged in rows and columns. Successive multi-cycle macro accesses are directed to different memory macros and different columns, and the data of the successive memory accesses are arranged in different memory macros and different columns to match the successive accesses.

[0008] An example is shown in Figure 2. As shown, a first macro access 102 of a first bit cell 1a occurs on a first rising edge 105 on a clock 106. The first bit cell 101 is located within a first macro 104 and within a first column 103 associated with a pair of bit lines. A second bit cell 2a in the burst, which would normally be located next to 1a, is located in a second column 103 within a second memory macro. A second macro access 102' of a second bit cell 2a occurs on a second rising edge 105' of the clock 106. The access may be either a read access or a write access. A macro access may overlap in time with both a read access and a write access.

[0009] The present disclosure further relates to a method of operating a burst access memory including a plurality of memory macros, each memory macro including an array of memory cells arranged in rows and columns, the method including generating a plurality of macro accesses to the memory macros, the plurality of macro accesses being scheduled to begin with a predetermined delay relative to one another, each macro access being divided into a plurality of ordered sub-operations, successive macro accesses being directed to different memory macros and different columns, and data of the successive memory accesses being arranged in the different memory macros and different columns to match the successive macro accesses. The method may be performed in any embodiment of the burst access memory of the present disclosure. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 illustrates an embodiment of a burst access memory of the present disclosure. [Figure 1B] 1 illustrates an embodiment of a burst access memory of the present disclosure. [Figure 1C] 1 illustrates an embodiment of a burst access memory of the present disclosure. [Figure 1D] 1 illustrates an embodiment of a burst access memory of the present disclosure. [Figure 1E] 1 illustrates an embodiment of a burst access memory of the present disclosure. [Figure 1F] 1 illustrates an embodiment of a burst access memory of the present disclosure. [Figure 2] 1 illustrates an example of the operation of a burst access memory of the present disclosure. [Figure 3A] An example of the operation of a burst access memory is shown. [Figure 3B] An example of the operation of a burst access memory is shown. [Figure 4A] 1 illustrates an embodiment of a bitcell. [Figure 4B] 1 illustrates an embodiment of a bitcell. [Figure 4C] 1 illustrates an embodiment of a bitcell. [Figure 5] 1 illustrates an embodiment of a connection between a local bit line and a global bit line. [Figure 6] 1 illustrates an embodiment of multiple memory macros, the memory macros having different sizes. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present disclosure relates to a burst access memory with improved read and write speeds relative to the voltage at which the memory operates. The term "speed relative to voltage" should be interpreted in light of the well-known fact that switching speeds in digital circuits can be improved by providing higher voltage levels. The burst access memory of the present disclosure can accelerate speeds relative to a given voltage level. This also means that if a certain read / write speed can be achieved at a given supply voltage for a conventional memory, the same speed can be achieved at a lower supply voltage by using the memory technology of the present disclosure. A burst access memory includes multiple memory macros, each including an array of memory cells arranged in rows and columns. As will be understood by those skilled in the art, memories typically include several peripheral logic and components in addition to the memory array, such as decoders (row decoder / row select logic, column decoder), sense amplifiers, input / output buffers, ports (data, address, enable signals, reset, clock, etc.), multiplexers, and control circuits. In memories that support burst mode, access does not need to occur in one clock cycle. The memory then begins reading or writing from the address and continues reading or writing from successive addresses, thereby enabling faster data rates. According to one embodiment of the burst access memory of the present disclosure, the controller is configured to schedule burst accesses of the burst access memory by generating multiple macro accesses to a memory macro, the multiple macro accesses being scheduled to begin with a predetermined delay relative to each other. Preferably, each macro access is divided into multiple ordered sub-operations. This has the advantage that the ordered sub-operations can be distributed in time, for example, a first macro access performs a first sub-operation, while a second macro access performs a second sub-operation.The division of a macro access into multiple ordered sub-operations, with successive macro accesses directed to different memory macros and different columns, should not be construed as excluding accesses from resuming at a column that is in use but becomes available again at some point. As an example, accesses may be cyclic in the sense that they access columns starting at column 0, increment upward until the last column is reached, and then accesses resume at 0. The burst access memory of the present disclosure can be said to disrupt the critical path of memory accesses. To avoid internal conflicts in operations on the memory, preferably, data is organized such that successive macro accesses are directed to different memory macros and different columns. In other words, if an access starts at a given address, successive macro accesses with respect to the starting address occur according to a predetermined access pattern as described. Consequently, data is arranged in the memory array to match the predetermined sequence of accesses as described.

[0012] The term "consecutive macro accesses" is intended to be broadly defined in the context of this application, and a macro access under certain circumstances may include several accesses. The following example illustrates how such multiple accesses can be considered consecutive within the scope of the present invention. According to a first typical scenario, the memory cell is a single-port memory cell, such as a 6T memory cell, as shown in FIG. 4A. When this type of cell is accessed, the bit lines BL and BL can be used in a well-known manner. Because the bit lines are occupied, in this embodiment, consecutive macro accesses, i.e., macro accesses following the first macro access, are directed to different memory macros and different columns. However, other types of bit lines can also be used to utilize the techniques of this disclosure. One example is a dual-port memory cell, such as an 8T dual-port memory cell, as shown in the example of FIG. 4B. Note that such a cell has two pairs of bit lines, BL1 / BL2 and BL3 / BL4. In such a cell, there can be two parallel accesses or two consecutive accesses, where the two pairs of bit lines do not interrupt each other. In this situation, each referenced "consecutive macro access" can be considered to have several macro accesses, as long as they use different bit lines. Figure 4C shows a further example of a memory cell in which two sub-accesses can form what is called a macro access. The memory cell may have additional ports, and the macro access may accordingly include additional sub-accesses.

[0013] An example of the operation and access pattern of a burst-access memory is shown in FIG. 3A. The memory array 107 includes four memory macros 104, 104′, 104″, and 104′′, each of which includes columns 103 and rows 115 of bit cells 101. Every memory macro includes 16×8 bit cells 101. The columns within a memory macro include a local bit line 114a, or more typically, a pair of local bit lines 114a. The local bit line 114a of a column 103 is connectable to the global bit line 114b of the same column 103 in all memory macros 104 via bit line switches 116. The switches can therefore control which memory macros 104 have access to the global bit line 114b for each column 103. In the example, a first macro access includes a parallel access of four bit cells in the first memory macro 104 that can be accessed without conflict. This is indicated by enabling four bit line switches 116 for the first memory macro 104. From the left, the bit cells forming columns 0, 4, 8, and 12 are accessed. A second macro access involves a parallel access of four bit cells in the second memory macro 104' that can be accessed without conflicts. The second macro access preferably occurs with a slight delay relative to the first macro access. This is indicated by enabling four bit line switches 116' for the second memory macro 104'. From the left, the bit cells forming columns 1, 5, 9, and 13 are accessed. A third macro access involves a parallel access of four bit cells in the third memory macro 104'' that can be accessed without conflicts. The third macro access preferably occurs with a slight delay relative to the second macro access. This is indicated by enabling four bit line switches 116'' for the third memory macro 104''. From the left, the bit cells forming columns 2, 6, 10, and 14 are accessed. The fourth macro access includes a parallel access of four bit cells within the fourth memory macro 104'' that can be accessed without conflict. The fourth macro access preferably occurs with a slight delay relative to the third macro access.This is indicated by enabling four bit line switches 116''' for the fourth memory macro 104'''. From the left, the bit cells forming column numbers 3, 7, 11, and 15 are accessed.

[0014] The memory array of FIG. 3B shows a further example of a memory array 107 including four memory macros 104, 104′, 104″, and 104′″, where each memory macro 104 includes a column 103 and row 115 of bit cells 101. In this example, each cell, and each corresponding column, has two pairs of bit lines. Column 103 within memory macro 104 has two pairs of local bit lines 114a. These pairs of bit lines may correspond to bit cells of the type shown in FIG. 4B. The local bit lines 114a of column 103 are connectable to global bit lines 114b via bit line switches 116.

[0015] A macro access is divided into multiple sub-operations, and the macro accesses are delayed relative to each other, allowing for parallel utilization of functions associated with the memory array. The operating principles and advantages are similar to those of pipelining, which is made possible by the ordering of data within the memory macro. The ordering is particularly useful when the access latency of the burst-access memory is significantly longer than clock cycles, such as at least 2 clock cycles, or at least 4 clock cycles, or at least 8 clock cycles, or at least 16 clock cycles.

[0016] One way to delay macro accesses is to use a high-speed clock and generate a new macro access every clock cycle. The term "high-speed" in this context can be considered as a clock operating at a frequency at which the memory array cannot deliver data within one clock cycle for a given nominal operating voltage. The clock may have a frequency of, for example, at least 1 GHz, preferably at least 2 GHz, more preferably at least 5 GHz, and even more preferably 10 GHz. Conventional burst memory would not be able to deliver data every clock cycle if the memory array's access latency exceeded 1 ns, 500 ps, ​​200 ps, ​​or 100 ps, ​​respectively. According to one embodiment, the operating frequency, i.e., the frequency of the high-speed clock, is at least 1 GHz if the memory macro's access latency is at least 3 ns; preferably at least 2 GHz if the memory macro's access latency is at least 1.5 ns; more preferably at least 5 GHz if the memory macro's access latency is at least 600 ps; and even more preferably 10 GHz if the memory macro's access latency is at least 300 ps. When data cannot be delivered every clock cycle, macro accesses of the burst access memory of the present disclosure may be referred to as multi-cycle macro accesses. Macro accesses 102, 102′, 102″, and 102′″ in FIG. 2 represent overlapping, delayed multi-cycle addresses. Thus, in one embodiment of the burst access memory of the present disclosure, multiple macro accesses overlap in time. Preferably, data at consecutive memory addresses are arranged in different memory macros and different columns so that there is no memory macro and bit line conflict for the overlapping macro accesses. More specifically, this means that a first piece of data may be arranged in, for example, a first memory macro and a first column, a second piece of data may be arranged in, for example, a second memory macro and a second column, a third piece of data may be arranged in, for example, a third memory macro and a third column, and so on. Consequently, more generally, an Nth piece of data may be arranged in, for example, an Nth memory macro and an Nth column.As will be understood by those skilled in the art, any suitable arrangement and access order of data is possible as long as no collisions occur. The example of Nth data arranged in the Nth memory macro and Nth column can be implemented with other similar arrangements. As an example, if bit line 0 (column) is used for data 0 arranged in memory macro 0, at some predetermined time, bit line 0 becomes available for further access in a different macro, such as macro N+1. Data and data accesses can then be arranged to reuse available bit lines as soon as they become available according to the access scheme used. For example, the first data can be placed in any suitable memory macro. Accesses do not necessarily have to be single-cell accesses. More typically, parallel accesses of multiple interleaved cells, for example constituting a byte or word, can be considered accesses within the scope of this disclosure. In the example of FIG. 3A, four bits 101 are read simultaneously from the first memory macro 104. In one embodiment, the access latency of the burst access memory is significantly greater than one clock cycle, such as at least three clock cycles, or at least four clock cycles, or at least five clock cycles, or at least eight clock cycles.

[0017] In the example of FIG. 3A, the burst access memory is configured to send four bits per clock cycle, with some latency due to the multi-cycle nature of the accesses. The controller 109 is configured to control the output multiplexer 111 via time multiplexing. Thus, in one embodiment, the burst access memory of the present disclosure includes input and / or output multiplexers synchronized with multiple macro accesses such that data read from successive macro accesses is sent to the output and output data of successive macro accesses is sent to the output port on every clock cycle of the clock signal, or such that output data from the input port is written to the memory cells of successive macro accesses on every clock cycle of the clock signal. A further advantage of the combination of time multiplexing and the ordering of data and macro accesses described in this disclosure is that the number of sense amplifiers 112 can be limited, to four in the example of FIG. 3A, since four bits are sent per clock cycle. In this embodiment, the sense amplifiers can be located after the output multiplexer relative to the memory array. Thus, in one embodiment, the burst access memory of the present disclosure is configured to operate without a registered output read buffer. Thus, in one embodiment, the input and / or output logic of the burst access memory of the present disclosure has a data width equal to the internal macro data width of the data accessed in each macro access.

[0018] One embodiment of the burst access memory of the present disclosure further includes at least two parallel input and / or output multiplexers, such that data read from consecutive macro accesses is alternately sent to two parallel output multiplexers, or data written to consecutive macro accesses is alternately sent to, for example, two pairs of bit lines in a column. As mentioned above, when operating at very high speeds, the entire signal path for access often becomes a bottleneck. In the burst access memory of the present disclosure, the critical path of memory access is significantly disrupted and typically may include only a controller with input or output multiplexing. As a non-limiting example, this may enable memory accesses to run at 8 GHz. However, in such a case, instead of running at 8 GHz, a further option may be to use two parallel input or output multiplexers, doubling the number of output ports, and running at 4 GHz. This concept may be further extended to include additional parallel input or output multiplexers and input or output ports and / or additional read logic for specific situations. Additionally, in one embodiment, read data from successive macro accesses is alternately sent to one output multiplexer and / or write data for successive macro accesses is alternately sent from an input port, while in a further embodiment, read data from successive macro accesses is alternately sent to multiple output ports and / or write data is alternately sent from multiple input ports.

[0019] FIG. 1D shows an example in which the bitcell is a dual-port bitcell with two pairs of bitlines A[x] and B[x] per column. In this implementation, data can be read or written alternately, as illustrated by the sequence DataA, DataB, DataA, DataB, etc. FIG. 1E shows a further example in which the bitcell is a dual-port bitcell with two pairs of bitlines A[x] and B[x] per column. In this example, the read logic includes structure for reading or writing Data A and B in parallel. FIG. 1E shows an example in which the bitcell is a single-port bitcell. In this embodiment, the memory structure of the single-port bitcell can be converted to a dual-port memory by adding read and / or write logic that splits accesses among several ports on the memory. In one example, data A, C, etc. from port A is interleaved with data B, D, etc. to create the sequence Data A, B, C, D, etc. For all of the embodiments of FIGS. 1D-1F, the dual-port bitcell and dual memory ports can be generalized to multiple ports.

[0020] The memory cells in each column may be connected by at least one local bit line, and the local bit lines for each column of the plurality of memory macros may be connected to global bit lines, and the memory cell array may further include bit line control logic for selectively connecting the local bit lines of different memory macros to the global bit lines. More typically, each column in a memory macro has a pair of local bit lines. Corresponding local bit lines of several memory macros may be connectable to the global bit lines. The local bit lines may be connected to the global bit lines, for example, using switches. For example, if data is to be read from bit cells in the third column of the second memory macro, the local bit line or bit line pair of the third column of the second memory macro is connected to the global bit line or bit line pair of the third column of all memory macros. According to one embodiment of the burst access memory disclosed herein, the memory cells in each column are connected by at least one local bit line, the memory cells in each row are connected by word lines, and the local bit lines for each column of the plurality of memory macros are connected to global bit lines that are connected to corresponding local bit lines of other memory macros. Similarly, memory cells in each column may be connected by a pair of local bit lines, and each pair of local bit lines in each column of memory macros may be connected to a pair of global bit lines that are connectable to corresponding pairs of local bit lines in other memory macros. Thus, memory macros may share global bit lines. The burst access memory may include bit line switches for controlling connections between the local bit lines and the global bit lines. Furthermore, the burst access memory may include local multiplexing logic or control logic for selecting the local bit lines for different global bit lines. Alternatively or in combination, the global bit lines may also be connected to multiple local bit lines. Because the parallelism proposed in this disclosure may use only some of the bit lines at a time, the number of global bit lines may be less than the number of columns in this configuration. Figure 5A illustrates an embodiment of connections between local bit lines and global bit lines. Note that sense amplifiers can be placed on either the local bit lines or the global bit lines.5B illustrates an embodiment of a connection between a local bit line and a single-ended global bit line including a multiplexer, a sense amplifier controlled by a read enable signal, and a tri-state buffer controlled by a write enable signal. In one embodiment, at least one of the global bit lines can be connected to multiple local bit lines within the same macro. Such a connection can be obtained by using a switch operated by a control signal from a controller. The switch can be activated when accessing the corresponding macro. The switch can be bidirectional, meaning that during a write operation, the switch transfers data from the global bit line to the selected local bit line, and during a read, the switch transfers data from the local bit line to the global bit line.

[0021] The present disclosure also relates to the use of different voltage domains in burst access memories. The inventors have recognized that the burst access memory of the present disclosure, which utilizes parallelism to break the critical path of memory access by dividing memory macro access into sequentially executed sub-operations and special arrangements of data within the memory macro, opens the possibility of achieving several advantages by using different voltage domain configurations. In one embodiment, the burst access memory is configured to operate with different internal voltage domains, where the memory array is supplied with a lower voltage than the rest of the logic of the burst access memory, or the memory array is supplied with a higher voltage than the rest of the logic of the burst access memory. When the memory array is supplied with a lower voltage than the rest of the logic of the burst access memory, this is made possible by improved speed of the burst access memory of the present disclosure. The memory array, which typically accounts for a significant portion of power consumption, can be significantly reduced if the memory array can operate at a lower voltage. While peripheral logic may still need to operate at a higher voltage, the impact may still be relatively low compared to the memory array. If the goal is to achieve extremely fast memory, it may be possible to reduce stability issues in the memory array by working with a partition in which the memory array is supplied with a higher voltage than the rest of the logic of the burst access memory. In this case, the rest of the logic can still operate at a lower voltage, which also saves power. In a third embodiment, multiple memory macros, row select logic, and column logic operate at different voltage levels depending on whether a write or read operation is being performed. This can increase noise margins during read and write operations.

[0022] The present disclosure further relates to an initial burst memory buffer. While the burst access of the present disclosure provides accelerated read and write speeds, there is typically still a latency for the first read or write access. That is, when read data is requested, it typically takes several clock cycles before the first data is available at the output port. Similarly, it takes several clock cycles before the first data is written to the memory array. In one embodiment, the burst access memory of the present disclosure further includes a separate initial burst memory buffer, and the controller is configured to read data from the separate initial burst memory buffer every clock cycle during a latency period corresponding to the time it takes the memory array to send out the read data, or the controller is configured to write data to the separate initial burst memory buffer every clock cycle during a latency period corresponding to the time it takes to write the first data to the memory array. For the separate initial burst memory buffer to function, the initial burst memory buffer needs to be pre-loaded with data intended to be read during the first clock cycle when the first data is not available at the output port. For burst access memories, this can be done in several ways. In this configuration, the initial burst memory buffer can be preloaded with memory data contents starting from a configurable, predetermined location in the memory array. For example, if it is known that a read will start from the beginning every time, or that the entire memory or only a given memory macro will be read, then the initial burst memory buffer can be preloaded with data located at the beginning of the memory array or the beginning of a given memory macro. In situations involving separate initial burst memory buffers, special scheduling can be used. For example, when a memory access, such as a read access, is requested, two parallel operations begin simultaneously. The first operation reads the preloaded data from the separate initial burst memory buffer for the number of cycles it takes the memory array to send the read data. The second operation begins a macro access at an address following the address corresponding to the contents of the separate initial burst memory buffer.Furthermore, according to one embodiment of the burst access memory of the present disclosure, the memory macros have different sizes. More specifically, the memory macros may have different numbers of rows. FIG. 6 shows an example of multiple memory macros (104, 104', 104'', 104'') having different sizes. Having memory macros of different sizes may be particularly advantageous in combination with an initial burst memory buffer. Different sizes of memory macros typically imply different latencies for read or write access. When using an initial burst memory buffer, the buffer can match different latencies and read or write situations.

[0023] In a further embodiment, which may be useful for implementing memory macros of different sizes, but may also be useful in other situations, the controller is configured to generate multiple macro accesses to memory macros in an order based on the timing and / or response time of the individual memory macro accesses and / or the macro access size. This may be advantageous, for example, when one macro is slower than another. If the memory macros are numbered, for example, 0, 1, 2, and 3, and memory macro 3's accesses are slower than the other macro accesses, the memory accesses may be accessed in an order such as 0-1-2-3-0-1-2-0-1-2-3. In this example, macro access 3 would be skipped every second time because the macro may not be ready for access every round. Instead, macros 2 and 3 would be alternately accessed, for example, in the order 0-1-2-0-1-3-0-1-2-0-1-3. In one embodiment, a given macro access is skipped at least every second time, and / or several given macro accesses are alternated in the sequence of macro accesses. In one embodiment, the timing unit is configured to arrange the accesses in an order such that at least every second macro access taking longer than the predetermined access time is skipped.

[0024] The multiple ordered sub-operations may be selected depending on several parameters, including how advantageous the parallelism to use is, timing constraints within the memory, or other constraints such as operating voltage levels. Preferably, the multiple ordered sub-operations for a read operation may be selected from row decode, column decode, word line activation, bit line activation such as local bit line activation and global bit line activation, bit line precharge such as local bit line precharge and global bit line precharge, memory cell discharge, control of bit line switches such as local bit line switches and global bit line switches, sense amplifier activation, and output multiplexing. Preferably, the multiple ordered sub-operations for a write operation may be selected from row decode, column decode, storing write value to buffer, bit line activation such as global bit line and local bit line activation, word line activation, pushing write value to memory cell, etc.

[0025] As one skilled in the art will appreciate, a memory includes several logic functions. Thus, a burst access memory includes, among other things, a decoder unit and read and write logic. An example of an embodiment of a burst access memory of the present disclosure is shown in FIG. 1A. In this example, the burst access memory 100 includes a decode unit 108 and a controller 109 for controlling access of a memory array 107 and output multiplexing of a multiplexer 111. The memory array 107 includes several memory macros 104, each including an array of memory cells 101 arranged in rows and columns. Sense amplifiers 112 are positioned after the multiplexer 111 with respect to the memory array 107. In the example, there is an optional initial read memory buffer 110. In FIG. 1B, the sense amplifiers 112 are positioned before the multiplexer 111. FIG. 1C illustrates a further embodiment in which buffers (registers) can be used to read and write values ​​from / to the memory array. In this embodiment, the controller 109 controls the read, write, and select signals. A multiplexer can be used for both input and output.

[0026] The memory cells in the memory array may be any suitable memory cells, for example, 4T, 5T, 6T, 7T, 8T bit cells, etc. Figure 4A discloses an example of a single-port 6T memory cell. Figure 4B discloses an example of a dual-port 8T memory cell. Figure 4C discloses an example of a dual-port 8T memory cell.

[0027] Although the burst access memory of the present disclosure has a primary burst access mode, it is not excluded that the burst access memory also supports random access. Thus, in one embodiment, the burst access memory has a first burst read and / or write mode and a second random access mode. Consequently, such dual mode memories require at least some additional logic to handle random access.

[0028] The present disclosure further relates to a method of operating a burst access memory including a plurality of memory macros, each including an array of memory cells arranged in rows and columns. The method includes generating a plurality of macro accesses to the memory macros. Preferably, the plurality of macro accesses are scheduled to begin with a predetermined delay relative to each other. Preferably, each macro access is divided into a plurality of ordered sub-operations. Preferably, consecutive multi-cycle macro accesses are directed to different memory macros and different columns, and data of consecutive memory accesses is arranged in different memory macros and different columns to match the consecutive macro accesses. The method may be performed in any embodiment of the burst access memory of the present disclosure. The accesses may be read and / or write operations.

[0029] detail 1. A burst access memory comprising: a memory array including a plurality of memory macros, each including an array of memory cells arranged in rows and columns; a controller configured to schedule burst accesses of the burst access memory by generating multiple macro accesses to the memory macro, the multiple macro accesses being scheduled to begin with a predetermined delay relative to each other; Equipped with Each macro access is divided into a plurality of ordered sub-operations, successive macro accesses are directed to different memory macros and different columns, and data of successive macro accesses are arranged in the different memory macros and the different columns to match the successive macro accesses; The burst access memory.

[0030] 2. The burst access memory of item 1, wherein a new macro access is scheduled to begin on every clock cycle, every second clock cycle, or every fourth clock cycle of the clock signal.

[0031] 3. The burst access memory of item 2, wherein the plurality of ordered sub-operations are performed sequentially, with each sub-operation commencing on every cycle of the clock signal.

[0032] 4. A burst access memory according to any one of the preceding items, wherein the macro access to the memory macro is a multi-cycle macro access.

[0033] 5. A burst access memory according to any one of the preceding items, wherein the burst access memory comprises a decoder unit and read and write logic.

[0034] 6. A burst access memory according to any one of the preceding items, wherein the plurality of memory macros are arranged vertically and bit lines are shared or connectable between columns of the plurality of memory macros.

[0035] 7. The burst access memory according to any one of items 1 to 5, wherein the plurality of memory macros are arranged horizontally and word lines are shared or connectable between rows of the plurality of memory macros.

[0036] 8. A burst access memory according to any one of the preceding items, wherein the burst access memory is configured to operate without a registered output read buffer.

[0037] 9. Preferably, the plurality of ordered sub-operations for a read operation comprises: - Line decoding, - column decoding, - word line activation, Bit line activation, such as local bit line activation and global bit line activation; Bit line precharge, such as local bit line precharge and global bit line precharge; -Memory cell discharge, Controlling bit line switches, such as local bit line switches and global bit line switches; -activating the sense amplifier, -Output multiplexing Item 10. The burst access memory of any one of the preceding items, selected from:

[0038] 10. Preferably, the plurality of ordered sub-operations for a write operation comprises: - Line decoding, - column decoding, -Storing the written values ​​in a buffer, Bit line activation, such as global bit line activation and local bit line activation; - word line activation, - pushing a write value into said memory cell Item 10. The burst access memory of any one of the preceding items, selected from:

[0039] 11. A burst access memory according to any one of the preceding items, wherein the memory cells in each column are connected by at least one local bit line, the memory cells in each row are connected by word lines, and the local bit lines for each column of the plurality of memory macros are connectable to global bit lines that are connectable to corresponding local bit lines of other memory macros.

[0040] 12. A burst access memory according to any one of the preceding items, wherein the memory cells in each column are connected by a pair of local bit lines, and the pair of local bit lines for each column of the plurality of memory macros is connectable to a pair of global bit lines which are connectable to corresponding pairs of local bit lines of other memory macros.

[0041] 13. The burst access memory of any one of items 11 or 12, wherein the memory macros share the global bit lines.

[0042] 14. The burst access memory according to any one of items 11 to 13, further comprising a bit line switch for controlling a connection between the local bit line and the global bit line.

[0043] 15. A burst access memory according to any one of the preceding items, wherein the memory cells of each column are connected by at least one local bit line, the local bit line for each column of the plurality of memory macros being connectable to a global bit line, and further comprising bit line control logic for selectively connecting the local bit lines of different memory macros to the global bit line.

[0044] 16. A burst access memory according to any one of the preceding items, wherein data read from successive macro accesses is time multiplexed.

[0045] 17. A burst access memory according to any one of the preceding items, further comprising an output multiplexer synchronized with said plurality of macro accesses such that data read from said successive macro accesses is sent to an output and output data of said successive macro accesses is sent to an output port on every clock cycle of said clock signal.

[0046] 18. A burst access memory according to any one of the preceding items, wherein the input and / or output logic has a data width equal to the internal macro data width of the data accessed in each macro access.

[0047] 19. A burst access memory according to any one of the preceding items, further comprising a sense amplifier and an output multiplexer for selecting read data from said plurality of macro accesses, said sense amplifier being arranged after said output multiplexer.

[0048] 20. A burst access memory according to any one of the preceding items, wherein the access latency of the burst access memory is significantly longer than one clock cycle, such as at least two clock cycles, or at least four clock cycles, or at least eight clock cycles, or at least 16 clock cycles.

[0049] 21. A burst access memory according to any one of the preceding items, wherein the plurality of macro accesses overlap in time.

[0050] 22. The burst access memory of item 21, wherein the data at consecutive memory addresses are arranged in the different memory macros and the different columns such that no memory macro and bit line collisions occur for overlapping macro accesses.

[0051] 23. A burst access memory according to any one of the preceding items, wherein first data is arranged in a first memory macro and a first column, second data is arranged in a second memory macro and a second column, and third data is arranged in a third memory macro and a third column.

[0052] 24. The burst access memory according to item 23, wherein the Nth data is arranged in the Nth memory macro and the Nth column.

[0053] 25. A burst access memory according to any one of the preceding items, wherein the operating frequency is at least 1 GHz, preferably at least 2 GHz, more preferably at least 5 GHz, and even more preferably 10 GHz.

[0054] 26. A burst access memory according to any one of the preceding items, wherein the operating frequency is at least 1 GHz if the access latency of the memory macro is at least 3 ns, preferably at least 2 GHz if the access latency of the memory macro is at least 1.5 ns, more preferably at least 5 GHz if the access latency of the memory macro is at least 600 ps, ​​and even more preferably 10 GHz if the access latency of the memory macro is at least 300 ps.

[0055] 27. A burst access memory according to any one of the preceding items configured to operate with different internal voltage domains, wherein the memory array is supplied with a lower voltage than the rest of the logic of the burst access memory, or wherein the memory array is supplied with a higher voltage than the rest of the logic of the burst access memory.

[0056] 28. A burst access memory according to any one of the preceding items, wherein the plurality of memory macros, row select logic, and column logic operate at different voltage levels depending on whether a write operation or a read operation is being performed.

[0057] 29. A burst access memory according to any one of the preceding items, wherein the burst access memory has a first burst read and / or write mode and a second random access mode.

[0058] 30. A burst access memory according to any one of the preceding items, further comprising a separate initial burst memory buffer, the controller configured to read data from the separate initial burst memory buffer every clock cycle during a latency period corresponding to the time it takes the memory array to send out read data.

[0059] 31. A burst access memory according to any one of the preceding items, wherein the memory macros have different sizes.

[0060] 32. A burst access memory according to any one of the preceding items, wherein the memory macros have different numbers of rows.

[0061] 33. A method of operating a burst access memory including a plurality of memory macros, comprising: Each memory macro comprises an array of memory cells arranged in rows and columns, and the method includes the step of generating a plurality of macro accesses to the memory macro, the plurality of macro accesses being scheduled to begin with a predetermined delay relative to one another, and each macro access being divided into a plurality of ordered sub-operations. Including, consecutive macro accesses are directed to different memory macros and different columns, and data of consecutive memory accesses are arranged in the different memory macros and the different columns to match the consecutive macro accesses; The method.

[0062] 34. A method of operating a burst access memory including a plurality of memory macros, the access or read operation being as described in item 33.

[0063] 35. A method of operating a burst access memory including a plurality of memory macros, the access or write operation being as described in item 33.

[0064] 36. A method for operating a burst access memory including a plurality of memory macros according to any one of items 33 to 35, wherein the burst access memory is the burst access memory according to any one of items 1 to 32.

Claims

1. 1. A burst access memory, comprising: a memory array comprising a plurality of memory macros, each comprising an array of memory cells without read / write logic arranged in rows and columns; a controller configured to schedule burst accesses of the burst access memory by generating a plurality of macro accesses to the memory macro, the macro accesses being scheduled to begin with a predetermined delay relative to one another; 1. A burst access memory comprising: A burst access memory in which each macro access is divided into a plurality of ordered sub-operations, consecutive macro accesses are directed to different memory macros and different columns, and data of consecutive macro accesses are arranged in the different memory macros and the different columns to match the consecutive macro accesses.

2. 2. The burst access memory of claim 1, wherein said burst access memory further comprises an input and / or output multiplexer, said input and / or output multiplexer being shared between said memory macros.

3. 3. The burst access memory of claim 2, wherein the plurality of global bit lines are connected to the input and / or output multiplexers, or the plurality of global bit lines are connected to read or write circuits such as sense amplifiers connected to the input and / or output multiplexers.

4. 2. The burst access memory of claim 1, wherein a new macro access is scheduled to begin every clock cycle, every second clock cycle, or every fourth clock cycle of the clock signal.

5. 2. The burst access memory of claim 1, wherein the macro access to the memory macro is a multi-cycle macro access.

6. 10. The burst access memory of claim 1, wherein the burst access memory is configured to operate without a registered output read buffer.

7. 2. The burst access memory of claim 1, wherein at least one of said global bit lines is connectable to multiple local bit lines within the same macro.

8. 2. The burst access memory of claim 1, wherein data read from successive macro accesses is time multiplexed.

9. 2. The burst access memory of claim 1, further comprising an input and / or output multiplexer synchronized with the plurality of macro accesses so that data read from the successive macro accesses is sent to an output and output data of the successive macro accesses is sent to an output port at every clock cycle of the clock signal, or so that input data from an input port to an input data sending port at every clock cycle of the clock signal is written to memory cells of the successive macro accesses.

10. 2. The burst access memory of claim 1, further comprising at least two parallel input and / or output multiplexers, and data read from the successive macro accesses is alternately sent to / from the two parallel input and / or output multiplexers.

11. 2. The burst access memory of claim 1, wherein read data from successive macro accesses are alternately sent to one output multiplexer and / or write data for successive macro accesses are alternately sent from an input port.

12. 2. The burst access memory of claim 1, wherein read data from said successive macro accesses are alternately sent to a plurality of output ports, and / or write data are alternately sent from a plurality of input ports.

13. 2. The burst access memory of claim 1, wherein the plurality of macro accesses overlap in time.

14. 2. The burst access memory of claim 1, wherein the burst access memory is configured to operate with different internal voltage domains, and wherein the memory array is supplied with a lower voltage than the rest of the logic of the burst access memory, or the memory array is supplied with a higher voltage than the rest of the logic of the burst access memory.

15. 2. The burst access memory of claim 1, wherein the burst access memory further comprises a separate initial burst memory buffer, and wherein the controller is configured to read data from the separate initial burst memory buffer every clock cycle for a latency period corresponding to the time it takes for the memory array to send out read data, or the controller is configured to write data to the separate initial burst memory buffer every clock cycle for a latency period corresponding to the time it takes for the memory array to write initial data to the memory array.

16. 2. The burst access memory of claim 1, wherein the memory macros have different sizes.

17. 2. The burst access memory of claim 1, wherein the controller is configured to generate multiple macro accesses to the memory macro in an order based on timing and / or response time of individual memory macro accesses and / or macro access size.

18. 18. A burst access memory according to claim 17, wherein a given macro access is skipped at least every second time and / or several given macro accesses are accessed alternately in a sequence of macro accesses.

19. 2. The burst access memory of claim 1, wherein the timing unit is configured to arrange the accesses in an order such that at least every second macro access taking longer than the predetermined access time is skipped.

20. 2. A burst access memory as claimed in claim 1, wherein the plurality of macro accesses consist of alternating read and write accesses or several read accesses followed by several write accesses.

21. 10. The burst access memory of claim 1, wherein the plurality of memory macros, row select logic, and column logic operate at different voltage levels depending on whether a write operation or a read operation is being performed.

22. 1. A method of operating a burst access memory including a plurality of memory macros, each memory macro comprising an array of memory cells without read / write logic arranged in rows and columns, the memory cells in each column being connected by at least one local bit line, the method comprising: generating a plurality of macro-accesses to the memory macro, the plurality of macro-accesses being scheduled to begin with a predetermined delay relative to one another, each macro-access being divided into a plurality of ordered sub-operations; Including, A method in which successive macro accesses are directed to different memory macros and different columns, and data of successive memory accesses are arranged in the different memory macros and the different columns to match the successive macro accesses.

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