Processor executing prefetching for absent area of program memory, program, and method

Abstract

To provide a processor, a method, and a program that minimize the occurrence of interruption processing of a page fault.SOLUTION: A logic circuit of a processor including a program memory, allows an execution thread having a global variable describing a program counter and a preceding memory access thread capable of referencing the global variable to function. An absence flag indicating an absent area of an instruction or data is assigned to the program memory as an attribute value. The preceding memory access thread executes a step 1 of referencing an attribute value of a memory address of the program memory likely to be fetched within a predetermined number of memory addresses from the memory address of the global variable, and a step 2 of, if an absence flag of the referenced attribute value is set, storing a page of an external storage part corresponding to the memory address of the program memory into the memory address of the program memory.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a technology for a processor that configures a program memory and a logic circuit. [Background technology]

[0002] A typical processor architecture is RISC (Reduced Instruction Set Computer). RISC is designed as a reduced instruction set architecture. It reduces the total number, types, and formats of instructions, simplifying the processing of each instruction and the addressing of operands.

[0003] Conventionally, there is a technology for applying the data structure and code of a CISC (Complex Instruction Set Computer) processor to a RISC processor (see, for example, Patent Document 1). According to this technology, machine language instructions are fetched from a series of addresses in program memory and the machine language instructions are decoded. Next, when a jump instruction is detected among the fetched machine language instructions, the address of a register containing the target address of the jump destination is extracted. Then, before executing the jump instruction, the machine language instruction is fetched not from the series of addresses but from the target address pointed to by the register.

[0004] FIG. 1 is a functional block diagram of a processor in the prior art.

[0005] The system of FIG. 1 comprises a processor 1 and an external storage unit 20. [Processor 1] The processor 1 may be a PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), or LSI (Large Scale Integration), and may be described in a hardware description language based on the circuit design of a semiconductor chip. The hardware description language uses syntax and notation similar to programming languages ​​to describe the configuration of elements included in a circuit, their operating conditions, the wiring between elements, and so on. A processor chip can be manufactured by writing the circuit diagram into the PLD, FPGA, or LSI.

[0006] The processor 1 is composed of a program memory 10 for internal storage (main memory) and a combinational logic circuit 11 for arithmetic operations. The processor 1 configures a finite state machine using logic circuits and registers. For example, in the case of RISC-V, the logic circuit is described using source code in a hardware description language or hardwired logic. The processor also has 32 registers, numbered x0 to x31.

[0007] An execution thread 111 in the logic circuit 11 of the processor 1 repeats fetch, decode, execute, and write back. When fetching, the execution thread 111 reads instructions and data from the program memory 10 using a paging method (fixed-length page units (e.g., 4 Kbytes to 16 Mbytes)).

[0008] Many existing processors implement a demand-paged virtual memory scheme, whereby an execution thread 111 reads only the required pages from program memory 10 during a fetch. The following "attributes" are assigned to each page of the program memory 10. Absence flag (absence / presence) Readable / Writable / Executable

[0009] [External storage unit 20] The external storage unit 20 may be a volatile memory that combines a transistor and a capacitor, such as a dynamic random-access memory (DRAM). The external storage unit 20 is placed close to the processor 1 to achieve the fastest possible access speed.

[0010] FIG. 2 is a flow chart of the execution threads that function in the logic circuitry of a processor in the prior art.

[0011] The execution thread 111 first fetches a specified address from the program memory 10. If the "absent flag" for that page is set at this time, a page fault interrupt occurs. A page fault generally occurs during an invalid memory access, and occurs when an attempt is made to read a page of instructions / data from an absent area of ​​the program memory 10.

[0012] (S01) First, the internal information (registers, etc.) of the logic circuit is dumped (saved) to the program memory (stack). This is to restore the original internal information when returning from the page fault interrupt processing. (S02) Next, the process moves to page fault interrupt processing. (S03) In the interrupt process, it is determined which page in the external storage unit 20 should be read into the absent area of ​​the program memory 10. Then, the page where the page fault occurred is read (page in) from the external storage unit 20 (auxiliary storage) to the program memory 10 (main storage). (S04) Next, the process returns from the interrupt process and the internal information (registers, etc.) of the logic circuit is restored from the program memory (stack). Then, the execution thread 111 resumes the processing that was suspended by the interrupt processing. At this time, the execution thread 111 can fetch the instructions / data that have been paged in to the program memory 10. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Publication No. 6-103067 Summary of the Invention [Problem to be solved by the invention]

[0014] However, as described above, in the interrupt processing of a page fault, the external storage unit 20 is accessed and the page is read into the program memory 10, which takes time for the processing of the inter-memory transfer. Also, unlike normal interrupt processing, page fault interrupt processing requires a larger amount of stack memory to be temporarily saved. For example, in the case of the MC68020 32-bit processor, the stack memory size for normal interrupt processing is 8 bytes, but the stack memory size for a page fault is 92 bytes. That is, in the interrupt processing of a page fault, the processing time is long due to the influence of the transfer of pages between memories and the amount of stack memory that is larger than that required in normal interrupt processing.

[0015] Therefore, an object of the present disclosure is to provide a processor, a program, and a method that can prevent page fault interrupt processing from occurring as much as possible. [Means for solving the problem]

[0016] According to the present disclosure, a processor including a program memory that stores a plurality of instructions or data, and a logic circuit that executes the instructions or data, The logic circuit operates an execution thread having a global variable describing a program counter and an advanced memory access thread capable of referencing the global variable, An absence flag indicating an absence area of ​​an instruction or data is assigned as an attribute value to the program memory, The leading memory access thread is a first step of referencing an attribute value of a memory address in program memory that is highly likely to be fetched and is within a predetermined number of addresses from the memory address of the global variable; a second step of storing a page of the external storage unit corresponding to the memory address of the program memory in a case where the absent flag of the referenced attribute value is set, at the memory address of the program memory in question; The present invention is characterized in that it is logically configured to execute the above.

[0017] According to another embodiment of the processor of the present disclosure, In the first step, the preceding memory access thread stores an attribute value at the memory address of the referenced program memory in a register using a predetermined instruction word, and checks whether the attribute value stored in the register is absent. It is also preferable that the logic be structured as follows:

[0018] According to another embodiment of the processor of the present disclosure, The global variable further describes a state value in the execution thread, The leading memory access thread varies a predetermined number of memory addresses in the program memory that it references depending on the state value. It is also preferable that the logic be structured as follows:

[0019] According to another embodiment of the processor of the present disclosure, The attribute value is further provided with a readable and / or writable flag and / or an owner thread number; When fetching from a memory address in program memory, the attribute value can be referenced. It is also preferable that the logic be structured as follows:

[0020] According to another embodiment of the processor of the present disclosure, The logic circuit is described by source code in a hardware description language or hardwired logic to function as a multi-thread or multi-task. It is also preferable.

[0021] According to the present disclosure, in a program that causes a processor to function as a processor configured with a program memory that stores a plurality of instructions or data and a logic circuit that executes the instructions or data, The logic circuit operates an execution thread having a global variable describing a program counter and an advanced memory access thread capable of referencing the global variable, An absence flag indicating an absence area of ​​an instruction or data is assigned as an attribute value to the program memory, The leading memory access thread is a first step of referencing an attribute value of a memory address in program memory that is highly likely to be fetched and is within a predetermined number of addresses from the memory address of the global variable; a second step of storing a page of the external storage unit corresponding to the memory address of the program memory in a case where the absent flag of the referenced attribute value is set, at the memory address of the program memory in question; The present invention is characterized in that the processor is caused to execute the program.

[0022] According to the present disclosure, there is provided a memory access method using a processor that includes a program memory that stores a plurality of instructions or data, and a logic circuit that executes the instructions or data, comprising: The logic circuit operates an execution thread having a global variable describing a program counter and an advanced memory access thread capable of referencing the global variable, An absence flag indicating an absence area of ​​an instruction or data is assigned as an attribute value to the program memory, The leading memory access thread is a first step of referencing an attribute value of a memory address in program memory that is highly likely to be fetched and is within a predetermined number of addresses from the memory address of the global variable; a second step of storing a page of the external storage unit corresponding to the memory address of the program memory in a case where the absent flag of the referenced attribute value is set, at the memory address of the program memory in question; The present invention is characterized by carrying out the following. [Effects of the Invention]

[0023] According to the processor, program, and method disclosed herein, it is possible to prevent page fault interrupt processing from occurring as much as possible. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a functional configuration diagram of a processor according to the prior art. [Figure 2] 1 is a flowchart of an execution thread functioning in the logic circuitry of a processor in the prior art. [Figure 3] FIG. 2 is a functional configuration diagram of a processor according to the present disclosure. [Figure 4] 1 is a flowchart of a speculative memory access thread functioning in the logic circuitry of a processor in the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0026] FIG. 3 is a functional configuration diagram of a processor according to the present disclosure.

[0027] In the present disclosure, both the program memory 10 and the external storage unit 20 are semiconductor memories, and are preferably high-speed accessible static random access memories (SRAMs). It is preferable that the program memory 10 is configured as an internal SRAM, and the external storage unit 20 is configured as an external SRAM. The program memory 10 allows faster access than the external storage unit 20.

[0028] Furthermore, the processor 1 in the present disclosure has a multithreading function (or multicore). This multithreading function is preferably implemented based on a hardware mechanism. Specifically, the logic circuit 11 is written to function as a multithread or multitask by source code in a hardware description language or hardwired logic. This speeds up thread or task switching in a real-time OS.

[0029] 3, in comparison with the above-described FIG. 1, a "precedent memory access thread 112" is executed simultaneously in addition to an execution thread 111 that executes normal processing. The scheduling of the two threads is executed at high speed by the hardware of the logic circuit 11.

[0030] Furthermore, the execution thread 111 of the logic circuit 11 has a "global variable" that describes a program counter. On the other hand, the advance memory access thread 112 can refer to this global variable.

[0031] Furthermore, as in the prior art, an absence flag indicating an absence area of ​​an instruction or data is assigned to the program memory 10 as an attribute value. The attribute value may further be assigned a readable and / or writable flag and / or an owner thread number.

[0032] FIG. 4 is a flowchart of a speculative memory access thread functioning in the logic circuitry of a processor in this disclosure.

[0033] <Advanced memory access thread 112> The advanced memory access thread 112 is logically configured to perform the following two steps.

[0034] (S1) The anticipatory memory access thread 112 refers to (probes) the attribute value of a memory address in the program memory 10 that is highly likely to be fetched and is within a predetermined number of addresses from the memory address of the global variable. Here, a page including a memory address that is within a "predetermined number" (for example, 8192 steps) from the value of the program counter stored in the global variable is referenced. At this time, the advanced memory access thread 112 may store the attribute value at the memory address of the program memory 10 in a register using a predetermined command such as the following: get_address_attribute s,d Register s: Specifies the address (page address of program memory 10) Register d: Stores the attribute value (Absent flag, owner thread number, Readable and / or writable flags) Then, the anticipated memory access thread 112 determines whether or not the "absent flag" is set in the attribute value.

[0035] (S2) If the absent flag is set in the referenced attribute value, the anticipatory memory access thread 112 stores the external storage unit 20 command or data that should be present in the program memory 10 at the memory address in the program memory 10. That is, if the absent flag is set (true), a demand paged virtual storage system is implemented.

[0036] 4, there is no need to generate a page fault interrupt process, as compared to FIG. 2. In other words, there is no need to dump (save) the internal information of the logic circuit to the program memory (stack). The advance memory access thread 112 determines which page to read (page in) from the external storage unit 20 (auxiliary storage) into the program memory 10 (main storage) in the absent area of ​​the program memory 10.

[0037] According to the conventional technique shown in FIG. 2, the execution thread 111 detects the absence flag of the program memory 10 and then executes the page fault interrupt process. 4, the execution thread 111 is prevented from detecting a not-present flag as much as possible. To this end, the leading memory access thread 112 detects in advance whether or not there is a not-present flag at a memory address in the program memory 10 that is likely to be fetched within a predetermined number of times, as viewed from the program counter of the execution thread 111. If a not-present flag is detected at this time, the leading memory access thread 112 pages in instructions / data from the external storage unit 20 to the program memory 10 in advance. This allows the execution thread 111 to fetch the instruction / data paged in to the program memory 10 by the preceding memory access thread 112. In other words, the preceding memory access thread can preload the instruction / data before the execution thread 111 detects the absence flag of the program memory 10.

[0038] <Using the state value of a global variable> In another embodiment, the execution thread 111 may further write the state value to a global variable that stores the program counter. In response to this, the anticipatory memory access thread 112 varies the "predetermined number" of memory addresses in the program memory 10 that are likely to be fetched, depending on the state value. The "predetermined number" is the range of addresses of data that are likely to be referenced in the near future. In other words, the "predetermined number" for detecting an absent area in the program memory 10 is varied.

[0039] The logic circuit of the processor 1 of the present disclosure is described in source code written in a hardware description language. After compiling the source code, it is converted into an executable format by "linking" it with multiple libraries. Of course, it is not limited to being described in a hardware description language, and can also be realized using hardwired logic.

[0040] This disclosure is particularly suitable for accelerating Java (registered trademark) virtual machine (VM) interpreters, Lisp machines, and compiled machine code such as Prolog. These high-level language machine hardware implements a virtual memory system different from that of standard operating systems such as Linux (registered trademark), and the method disclosed here can reduce interruptions in execution caused by demand-paged virtual memory. In other words, it can reduce delays in calling processing routines from the control information of the Java virtual machine.

[0041] As described above in detail, the processor, program, and method disclosed herein can prevent page fault interrupt processing from occurring as much as possible.

[0042] With respect to the various embodiments of the present disclosure described above, various changes, modifications, and omissions within the scope of the technical idea and perspective of the present disclosure can be easily made by those skilled in the art. The above description is merely an example and is not intended to be limiting in any way. The present disclosure is limited only by the scope of the claims and their equivalents. [Explanation of symbols]

[0043] 1 processor 10 Program Memory 11 Logic Circuits 111 Execution Threads 112 Leading Memory Access Threads 20 External memory unit

Claims

1. A processor comprising a program memory for storing a plurality of instructions or data, and a logic circuit for executing the instructions or data, The logic circuit operates an execution thread having a global variable describing a program counter and an advanced memory access thread capable of referencing the global variable, An absence flag indicating an absence area of ​​an instruction or data is assigned as an attribute value to the program memory, The leading memory access thread is a first step of referencing an attribute value of a memory address in program memory that is highly likely to be fetched and is within a predetermined number of addresses from the memory address of a global variable; a second step of storing a page of the external storage unit corresponding to the memory address of the program memory in a case where the absent flag of the referenced attribute value is set, at the memory address of the program memory; 1. A processor logically configured to execute:

2. In the first step, the preceding memory access thread stores an attribute value at the memory address of the referenced program memory in a register using a predetermined instruction word, and checks whether the attribute value stored in the register is absent.

2. The processor according to claim 1, wherein the processor is logically configured as follows:

3. The global variable further describes a state value in the execution thread, The leading memory access thread varies a predetermined number of memory addresses in the program memory that it references depending on the state value.

2. The processor according to claim 1, wherein the processor is logically configured as follows:

4. The attribute value is further provided with a readable and / or writable flag and / or an owner thread number; When fetching from a memory address in program memory, the attribute value can be referenced.

2. The processor according to claim 1, wherein the processor is logically configured as follows:

5. The logic circuit is described by source code in a hardware description language or hardwired logic to function as a multi-thread or multi-task. A processor according to any one of claims 1 to 4.

6. A program that functions as a processor that is configured with a program memory that stores a plurality of instructions or data and a logic circuit that executes the instructions or data, The logic circuit operates an execution thread having a global variable describing a program counter and an advanced memory access thread capable of referencing the global variable, An absence flag indicating an absence area of ​​an instruction or data is assigned as an attribute value to the program memory, The leading memory access thread is a first step of referencing an attribute value of a memory address in program memory that is highly likely to be fetched and is within a predetermined number of addresses from the memory address of a global variable; a second step of storing a page of the external storage unit corresponding to the memory address of the program memory in a case where the absent flag of the referenced attribute value is set, at the memory address of the program memory; and causing a processor to execute the program.

7. A memory access method using a processor that includes a program memory that stores a plurality of instructions or data, and a logic circuit that executes the instructions or data, The logic circuit operates an execution thread having a global variable describing a program counter and an advanced memory access thread capable of referencing the global variable, An absence flag indicating an absence area of ​​an instruction or data is assigned as an attribute value to the program memory, The leading memory access thread is a first step of referencing an attribute value of a memory address in program memory that is highly likely to be fetched and is within a predetermined number of addresses from the memory address of a global variable; a second step of storing a page of the external storage unit corresponding to the memory address of the program memory in a case where the absent flag of the referenced attribute value is set, at the memory address of the program memory; A memory access method comprising:

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