Constant voltage generation circuit

Abstract

To provide a constant voltage generation circuit that offers both stable output and fast startup.SOLUTION: A constant voltage generation circuit 1 is provided, comprising: an output circuit 10 configured to generate a constant output voltage VOUT from an input voltage VIN using a first output transistor DM of a depression type and a second output transistor EM of an enhancement type; a capacitor C1 for smoothing the output voltage VOUT; and a switching circuit 29 configured to switch whether to enable the smoothing according to the output voltage VOUT.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a constant voltage generating circuit. [Background technology]

[0002] Conventionally, an ED type constant voltage source, which combines a depletion type NMOSFET (N-channel type metal oxide semiconductor field effect transistor) and an enhancement type NMOSFET, has been widely known as a type of constant voltage generating circuit.

[0003] As examples of the prior art related to the above, Patent Documents 1 and 2 proposed by the applicant of the present application can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2021 / 172001 [Patent Document 2] International Publication No. 2021 / 241257

[0005] [overview] Conventional constant voltage generating circuits have room for improvement in achieving both stable output and fast startup.

[0006] For example, a constant voltage generation circuit according to the present disclosure includes an output circuit configured to generate a constant output voltage from an input voltage using a first depletion-type output transistor and a second enhancement-type output transistor, a capacitor configured to smooth the output voltage, and a switching circuit configured to enable / disable the smoothing in response to the output voltage or a node voltage that fluctuates depending on the output voltage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a first comparative example of a constant voltage generating circuit. [Figure 2] FIG. 2 is a diagram showing how output fluctuations occur when input fluctuations occur. [Figure 3] FIG. 3 is a diagram illustrating a second comparative example of a constant voltage generating circuit. [Figure 4] FIG. 4 is a diagram showing how output fluctuations are suppressed when input fluctuations occur. [Figure 5] FIG. 5 is a diagram showing the startup behavior of the second comparative example. [Figure 6] FIG. 6 is a diagram showing a first embodiment of a constant voltage generating circuit. [Figure 7] FIG. 7 is a diagram showing the startup behavior of the first embodiment. [Figure 8] FIG. 8 is a diagram showing a second embodiment of the constant voltage generating circuit. [Figure 9] FIG. 9 is a diagram showing a third embodiment of the constant voltage generating circuit. [Figure 10] FIG. 10 is a diagram showing a fourth embodiment of the constant voltage generating circuit. [Figure 11] FIG. 11 is a diagram showing a fifth embodiment of the constant voltage generating circuit. [Figure 12] FIG. 12 is a diagram showing a sixth embodiment of the constant voltage generating circuit. [Figure 13] FIG. 13 is a diagram showing a seventh embodiment of the constant voltage generating circuit. [Figure 14] FIG. 14 is a diagram illustrating an eighth embodiment of the constant voltage generating circuit. [Figure 15] FIG. 15 is a diagram illustrating a ninth embodiment of the constant voltage generating circuit.

[0008] [Detailed explanation] <First Comparative Example> FIG. 1 is a diagram showing a first comparative example of a constant voltage generating circuit 1 (basic configuration to be compared with the embodiments described later). The constant voltage generating circuit 1 of this comparative example is a so-called ED-type reference voltage source. Referring to this diagram, the constant voltage generating circuit 1 includes transistors DM and EM. The transistor DM may be, for example, a depression-type NMOSFET. The transistor DM may be understood as a first output transistor. The transistor EM may be, for example, an enhancement-type NMOSFET. The transistor EM may be understood as a second output transistor.

[0009] The depletion type is a type in which a drain current flows even when the gate-source voltage is 0V, while the enhancement type is a type in which no drain current flows when the gate-source voltage is 0V.

[0010] The drain of transistor DM is connected to the application terminal of input voltage VIN. The source and back gate of transistor EM are connected to the application terminal of ground voltage GND (=ground terminal). The gate, source, and back gate of transistor DM and the gate and drain of transistor EM are connected to the application terminal of node voltage Vx. The application terminal of node voltage Vx is connected to the application terminal of output voltage VOUT.

[0011] In the constant voltage generating circuit 1 of this comparative example, the gate and source of transistor DM are short-circuited. Therefore, the gate-source voltage Vgs1 of transistor DM is 0V. Therefore, transistor DM functions as a constant current source that generates a constant drain current. In other words, a constant bias current (= drain current of transistor DM) flows through transistor EM. As a result, a constant node voltage Vx equivalent to the gate-source voltage Vgs2 of transistor EM, and therefore an output voltage VOUT, are generated.

[0012] As described above, the constant voltage generating circuit 1 of this comparative example includes an output circuit 10 that generates a constant output voltage VOUT from an input voltage VIN using transistors DM and EM. The output voltage VOUT can be used, for example, as a reference voltage VREF for an application.

[0013] 2 is a diagram showing how output fluctuations occur when input fluctuations occur in the constant voltage generating circuit 1 of the first comparative example. In this diagram, from top to bottom, the input voltage VIN and the output voltage VOUT are depicted.

[0014] The constant voltage generating circuit 1 of the first comparative example has a problem in that the output voltage VOUT is easily affected by input fluctuations. Referring to this figure, a sudden drop in the input voltage VIN can cause the output voltage VOUT to drop transiently. In particular, if the current capability of the transistor DM (i.e., the drain current flowing through the transistor DM) is reduced in order to reduce the current consumption of the constant voltage generating circuit 1, the amount of transient fluctuation in the output voltage VOUT increases. Furthermore, the time required for the output voltage VOUT to return to its target value after the fluctuation also increases.

[0015] <Second Comparative Example> 3 is a diagram showing a second comparative example of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this comparative example is based on the first comparative example (FIG. 1) described above, and further includes a capacitor C1 for smoothing the output voltage VOUT. The capacitor C1 is connected between the application terminal of the node voltage Vx and the application terminal of the ground voltage GND.

[0016] FIG. 4 is a diagram showing how output fluctuations are suppressed when input fluctuations occur in the constant voltage generating circuit 1 of the second comparative example. In this diagram, as in the above-mentioned FIG. 2, the input voltage VIN and the output voltage VOUT are depicted from top to bottom. The solid line of the output voltage VOUT shows the behavior of the second comparative example. On the other hand, the dashed line of the output voltage VOUT shows the behavior of the first comparative example.

[0017] As can be seen from this figure, the constant voltage generating circuit 1 of the second comparative example makes the output voltage VOUT less susceptible to input fluctuations than the first comparative example. That is, the amount of transient fluctuation in the output voltage VOUT caused by a sudden drop in the input voltage VIN is suppressed. In addition, the time required for the output voltage VOUT to return to the target value after fluctuation is also shortened.

[0018] 5 is a diagram showing the startup behavior of the constant voltage generating circuit 1 of the second comparative example. The solid line of the output voltage VOUT shows the behavior of the second comparative example, that is, the behavior when the capacitor C1 is introduced. On the other hand, the dashed line of the output voltage VOUT shows the behavior of the first comparative example, that is, the behavior when the capacitor C1 is not introduced.

[0019] As can be seen from this figure, in the constant voltage generating circuit 1 of the second comparative example, the startup time of the output voltage VOUT when the input voltage VIN is applied, that is, the time required for the output voltage VOUT to reach the target value from 0 V, becomes long.

[0020] It should be noted that the same problem as above may become apparent not only when the smoothing capacitor C1 is introduced, but also when a large parasitic capacitor is present at the application terminal of the output voltage VOUT.

[0021] In view of the above considerations, a new embodiment of the constant voltage generating circuit 1 that can achieve both stable output and fast startup will be proposed below.

[0022] First Embodiment 6 is a diagram showing a first embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the second comparative example (FIG. 3) described above, and further includes a switching circuit 20.

[0023] The switching circuit 20 switches between enabling and disabling smoothing by the capacitor C1 depending on the output voltage VOUT. For example, when the output voltage VOUT is lower than the threshold voltage Vth, the switching circuit 20 disables smoothing of the output voltage VOUT by the capacitor C1. On the other hand, when the output voltage VOUT is higher than the threshold voltage Vth, the switching circuit 20 enables smoothing of the output voltage VOUT by the capacitor C1.

[0024] Referring to this figure, the switching circuit 20 includes a transistor M1. The transistor M1 may be, for example, an NMOSFET. The drain of the transistor M1 is connected to one end of a capacitor C1. The source and back gate of the transistor M1 are both connected to an application terminal of a ground voltage GND. The gate of the transistor M1 is connected to an application terminal of a node voltage Vx, and further to an application terminal of an output voltage VOUT. In this way, the transistor M1 is connected in series to the capacitor C1.

[0025] The transistor M1 is turned on when the output voltage VOUT applied to the gate is higher than the on-threshold voltage Vth(M1) of the transistor M1. On the other hand, the transistor M1 is turned off when the output voltage VOUT is lower than the on-threshold voltage Vth(M1). When the transistor M1 is turned on, a current I1 can flow through the capacitor C1.

[0026] 7 is a diagram showing the startup behavior of the constant voltage generating circuit 1 of the first embodiment. The solid line of the output voltage VOUT indicates the behavior of the first embodiment, i.e., the behavior when the switching circuit 20 is introduced. On the other hand, the dashed line of the output voltage VOUT indicates the behavior of the second comparative example, i.e., the behavior when the switching circuit 20 is not introduced.

[0027] After the input voltage VIN is applied, when the output voltage VOUT is lower than a predetermined threshold voltage Vth, specifically, when the output voltage VOUT is lower than the on-threshold voltage Vth(M1) of the transistor M1, the transistor M1 is turned off. Therefore, the current I1 does not flow through the capacitor C1. In other words, the smoothing of the output voltage VOUT by the capacitor C1 is disabled. As a result, the start-up time of the output voltage VOUT, i.e., the time required for it to reach the target value from 0 V, can be significantly reduced.

[0028] After that, when the output voltage VOUT becomes higher than the threshold voltage Vth, the transistor M1 turns on. Therefore, the capacitor C1 is in a state where the current I1 can flow. In other words, the capacitor C1 effectively smooths the output voltage VOUT. As a result, the output voltage VOUT is less susceptible to input fluctuations. For example, as shown in Figure 4 above, the amount of transient fluctuation in the output voltage VOUT caused by a sudden drop in the input voltage VIN is suppressed. In addition, the time required for the output voltage VOUT to return to the target value after fluctuation is also shortened. Therefore, stable output and fast startup can both be achieved.

[0029] After the output voltage VOUT exceeds the threshold voltage Vth, the output voltage VOUT continues to start up at a slope that corresponds to the current capability of the transistor DM and the impedance of the load connected to the application terminal of the output voltage VOUT. After that, the transistor M1 is fixed in the on state. Therefore, the switching circuit 20 does not affect the operation of the constant voltage generating circuit 1 after the output voltage VOUT has started up.

[0030] Second Embodiment 8 is a diagram showing a second embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes a resistor R1 as a component of the switching circuit 20.

[0031] The resistor R1 is connected, for example, between one end of the capacitor C1 and the drain of the transistor M1. That is, the resistor R1 is connected in series with the capacitor C1. The introduction of such a resistor R1 suppresses the current I1 that flows when the transistor M1 turns on. Therefore, even if the capacitance value of the capacitor C1 is large, an excessive current I1 is unlikely to flow. As a result, it is possible to prevent a drop in the output voltage VOUT when the transistor M1 turns on. The resistance value of the resistor R1 may be adjusted as appropriate within a range that does not hinder the smoothing of the output voltage VOUT by the capacitor C1. The resistor R1 may also be connected between the source of the transistor M1 and the application terminal of the ground voltage GND.

[0032] <Third embodiment> 9 is a diagram showing a third embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes a current source CS1 as a component of the switching circuit 20.

[0033] The current source CS1 is connected, for example, between one end of the capacitor C1 and the drain of the transistor M1. That is, the current source CS1 is connected in series with the capacitor C1. By introducing such a current source CS1, the current I1 flowing through the capacitor C1 is maintained at a constant value. Therefore, a decrease in the output voltage VOUT when the transistor M1 is turned on can be prevented. The current capacity of the current source CS1 may be adjusted as appropriate within a range that does not impede the smoothing of the output voltage VOUT by the capacitor C1. The current source CS1 may also be connected between the source of the transistor M1 and the application terminal of the ground voltage GND.

[0034] <Fourth embodiment> 10 is a diagram showing a fourth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes a hysteresis applying circuit HYS as a component of the switching circuit 20.

[0035] The hysteresis-imparting circuit HYS imparts hysteresis to the threshold voltage Vth (see FIG. 7) of the switching circuit 20. Speaking in terms of this figure, the hysteresis-imparting circuit HYS includes a transistor M2, a resistor R2, a Schmitt buffer BUF, and an inverter INV.

[0036] The drain of the transistor M2 is connected to the application terminal of the voltage signal V1. Both the source and the back gate of the transistor M2 are connected to the application terminal of the ground voltage GND. The gate of the transistor M2 is connected to the application terminal of the node voltage Vx, and thus, to the application terminal of the output voltage VOUT. The transistor M2 turns on when the output voltage VOUT applied to its gate is higher than the on-threshold voltage Vth(M2) of the transistor M2. On the other hand, the transistor M2 turns off when the output voltage VOUT is lower than the on-threshold voltage Vth(M2). A current signal I2 flows through the transistor M2 in the on state.

[0037] The resistor R2 is connected between the application terminal of the input voltage VIN and the application terminal of the voltage signal V1. The resistor R2 converts the current signal I2 flowing through the transistor M2 into a voltage signal V1 (= VIN - I2 × R2). The resistor R2 can be understood as a current / voltage conversion circuit.

[0038] The Schmitt buffer BUF receives the input of the voltage signal V1 and outputs a buffer output signal S1. The buffer output signal S1 switches from a low level to a high level when the voltage signal V1 becomes higher than the threshold voltage VthH. On the other hand, the buffer output signal S1 switches from a high level to a low level when the voltage signal V1 becomes lower than the threshold voltage VthL (where VthL < VthH).

[0039] The inverter INV inverts the logic level of the buffer output signal S1 to generate an inverter output signal S2. Therefore, the inverter output signal S2 becomes a low level when the buffer output signal S1 is at a high level. Also, the inverter output signal S2 becomes a high level when the buffer output signal S1 is at a low level.

[0040] The gate of the transistor M1 is connected to the application terminal of the inverter output signal S2, not to the application terminal of the output voltage VOUT. That is, the switching circuit 20 switches the on / off state of the transistor M1 in response to the buffer output signal S1.

[0041] The introduction of the hysteresis applying circuit HYS makes it less susceptible to noise in the switching circuit 20. The hysteresis applying circuit HYS may have a different circuit configuration.

[0042] Fifth Embodiment 11 is a diagram showing a fifth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes resistors R3 and R4 as components of the output circuit 10.

[0043] The drain of transistor DM is connected to the application terminal of input voltage VIN. The source and back gate of transistor DM are both connected to the first terminal of resistor R3. The source and back gate of transistor EM are both connected to the first terminal of resistor R4. The second terminal of resistor R4 is connected to the application terminal of ground voltage GND. The gate of transistor DM, the gate and drain of transistor EM, and the second terminal of resistor R3 are all connected to the application terminal of node voltage Vx. The application terminal of node voltage Vx is directly connected to the application terminal of output voltage VOUT.

[0044] In this way, resistor R3 is connected between the gate and source of transistor DM. Resistor R4 is connected between the source of transistor EM and the terminal to which ground voltage GND is applied. In other words, resistors R3 and R4 are connected in series between the terminal to which input voltage VIN is applied and the terminal to which ground voltage GND is applied. Therefore, a current I equal to the current I (=Vgs1 / R3) flowing through resistor R3 flows through resistor R4. Therefore, a voltage Vy (=Vgs1×(R4 / R3)) corresponding to the current I is generated across resistor R4.

[0045] Therefore, the constant voltage generating circuit 1 outputs the sum of the gate-source voltage Vgs2 of the transistor EM and the voltage Vy across the resistor R4 as the output voltage VOUT (=Vgs2+Vy).

[0046] The resistors R3 and R4 may be elements having the same temperature coefficient. For example, the resistors R3 and R4 may both be polysilicon resistors having a negative temperature coefficient. Alternatively, the resistors R3 and R4 may both be diffused resistors having a positive temperature coefficient.

[0047] Sixth Embodiment 12 is a diagram showing a sixth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the fifth embodiment (FIG. 11) described above, but the gate of the transistor M1 is connected to the application terminal of the voltage Vy across the resistor R4, rather than the application terminal of the node voltage Vx. In this way, the gate of the transistor M1 does not necessarily have to be connected to the application terminal of the output voltage VOUT, and may be connected to the application terminal of a node voltage (for example, the voltage Vy across the resistor R4) that varies depending on the output voltage VOUT.

[0048] Seventh Embodiment 13 is a diagram showing a seventh embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the first embodiment (FIG. 6) described above, and further includes a transistor M3 (e.g., an NMOSFET) as a component of the output circuit 10. The transistor M3 can be understood as a third output transistor.

[0049] The drain of the transistor M3 is connected to a terminal to which the input voltage VIN is applied. The source and back gate of the transistor M3 are connected to a terminal to which the output voltage VOUT is applied. The gate of the transistor M3 is connected to a terminal to which the node voltage Vx is applied. The transistor M3 is preferably an element having a current capability larger than that of the transistors DM and EM.

[0050] The transistor M3 functions as a voltage follower VF (a source follower in this figure). That is, in the constant voltage generating circuit 1 of this embodiment, the application terminal of the node voltage Vx is connected to the application terminal of the output voltage VOUT via the voltage follower VF. According to this embodiment, the current capability of the constant voltage generating circuit 1 is improved. Even with the introduction of the voltage follower VF, the output voltage VOUT is the gate-source voltage Vgs2 of the transistor EM, as in the first embodiment (FIG. 6) described above.

[0051] The gate of transistor EM is directly connected to the application terminal of output voltage VOUT. Therefore, negative feedback control is applied to transistor EM so that the output voltage VOUT is constant. Furthermore, the gate of transistor M1 is directly connected to the application terminal of output voltage VOUT. Therefore, as in the first embodiment (FIG. 6), the switching circuit 20 switches between enabling and disabling smoothing by capacitor C1 depending on the output voltage VOUT.

[0052] Eighth Embodiment 14 is a diagram showing an eighth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the seventh embodiment (FIG. 13) described above, and further includes resistors R5 and R6 as components of the output circuit 10.

[0053] Resistor R5 is connected between the application terminal of output voltage VOUT and the application terminal of divided voltage Vd1. Resistor R6 is connected between the application terminal of divided voltage Vd1 and the application terminal of ground voltage GND. Resistors R5 and R6 connected in this manner function as a resistive voltage divider circuit DIV that divides the output voltage VOUT to generate divided voltage Vd1 (= VOUT × R6 / (R5 + R6)). The gates of transistors EM and M1 are both connected to the application terminal of divided voltage Vd1. The divided voltage Vd1 can be understood as an example of a node voltage that varies depending on the output voltage VOUT.

[0054] That is, in the constant voltage generating circuit 1 of this embodiment, the gate of the transistor EM is connected to the application terminal of the output voltage VOUT via the resistive voltage divider circuit DIV. With this configuration, the resistance values ​​of the resistors R5 and R6 (and therefore the voltage division ratio of the resistive voltage divider circuit DIV) are appropriately adjusted to generate an arbitrary output voltage VOUT (=Vgs2×(R5+R6) / R6).

[0055] Ninth Embodiment 15 is a diagram showing a ninth embodiment of the constant voltage generating circuit 1. The constant voltage generating circuit 1 of this embodiment is based on the eighth embodiment (FIG. 14) described above, and further includes a resistor R7 as a component of the output circuit 10.

[0056] Resistor R5 is connected between the application terminal of output voltage VOUT and the application terminal of divided voltage Vd1. Resistor R6 is connected between the application terminal of divided voltage Vd1 and the application terminal of divided voltage Vd2. Resistor R7 is connected between the application terminal of divided voltage Vd2 and the application terminal of ground voltage GND. The resistors R5, R6, and R7 connected in this manner function as a resistive voltage divider circuit DIV that divides the output voltage VOUT to generate divided voltage Vd1 (= VOUT × (R6 + R7) / (R5 + R6 + R7)) and divided voltage Vd2 (= VOUT × R7 / (R5 + R6 + R7)), respectively. The gate of transistor M1 is connected to the application terminal of divided voltage Vd1. The gate of transistor EM is connected to the application terminal of divided voltage Vd2. The divided voltages Vd1 and Vd2 can each be understood as examples of node voltages that vary depending on the output voltage VOUT.

[0057] In this embodiment, the threshold voltage Vth (see FIG. 7) of the switching circuit 20, and therefore the time required for the transistor M1 to switch to the ON state after the input voltage VIN is applied, can be adjusted arbitrarily. For example, the threshold voltage Vth may be adjusted so that the transistor M1 switches to the ON state just before the output voltage VOUT reaches a target value.

[0058] <Combination of embodiments> The circuit configurations of the first to ninth embodiments described above may be combined in any manner as long as no contradictions are present. For example, the hysteresis applying circuit HYS of the fourth embodiment (FIG. 10) may be introduced based on the circuit configurations of the fifth to ninth embodiments (FIGS. 11 to 15).

[0059] <Additional Notes> The constant voltage generating circuit according to the present disclosure can achieve both stable output and fast startup.

[0060] [Appendix 1] an output circuit (10) configured to generate a constant output voltage (VOUT) from an input voltage (VIN) using a first depletion mode output transistor (DM) and a second enhancement mode output transistor (EM); a capacitor (C1) configured to smooth the output voltage (VOUT); a switching circuit (20) configured to switch between enabling and disabling the smoothing in accordance with the output voltage (VOUT) or node voltages (Vx, Vy, Vd1) that vary depending on the output voltage (VOUT); A constant voltage generating circuit (1) comprising:

[0061] [Appendix 2] The constant voltage generating circuit (1) according to Appendix 1, wherein the switching circuit (20) disables the smoothing when the output voltage (VOUT) or the node voltages (Vx, Vy, Vd1) are lower than a threshold voltage (Vth), and enables the smoothing when the output voltage (VOUT) or the node voltages (Vx, Vy, Vd1) are higher than the threshold voltage (Vth).

[0062] [Appendix 3] The constant voltage generating circuit (1) according to Appendix 2, wherein the switching circuit (20) includes a first transistor (M1) connected in series with the capacitor (C1), and when the output voltage (VOUT) or the node voltages (Vx, Vy, Vd1) are lower than the threshold voltage (Vth), the first transistor (M1) is turned off, and when the output voltage (VOUT) or the node voltages (Vx, Vy, Vd1) are higher than the threshold voltage (Vth), the first transistor (M1) is turned on.

[0063] [Appendix 4] 4. The constant voltage generating circuit (1) according to claim 2 or 3, wherein the switching circuit (20) further includes a resistor (R1) or a current source (CS1) connected in series with the capacitor (C1).

[0064] [Appendix 5] 5. The constant voltage generating circuit (1) according to any one of appendices 2 to 4, wherein the switching circuit (20) further includes a hysteresis applying circuit (HYS) configured to apply hysteresis to the threshold voltage (Vth).

[0065] [Appendix 6] The constant voltage generating circuit (1) according to Appendix 5, wherein the hysteresis applying circuit (HYS) includes a second transistor (M2) configured to have the output voltage (VOUT) or the node voltages (Vx, Vy, Vd1) applied to a control electrode thereof, a current / voltage conversion circuit (R2) configured to convert a current signal (I2) flowing through the second transistor (M2) into a voltage signal (V1), and a Schmitt buffer (BUF) configured to receive an input of the voltage signal (V1), and the switching circuit (20) switches the on / off state of the first transistor (M1) according to an output signal (S1) of the Schmitt buffer (BUF).

[0066] [Appendix 7] The constant voltage generating circuit (1) according to any one of appendices 1 to 6, wherein the output circuit (10) further includes a third output transistor (M3) having a first main electrode connected to an application terminal of the input voltage (VIN), a second main electrode connected between the application terminal of the output voltage (VOUT), and a control electrode connected to the first main electrode of the second output transistor (EM).

[0067] [Appendix 8] The constant voltage generating circuit (1) according to any one of appendices 1 to 7, wherein a control electrode of the second output transistor (EM) is connected to an application terminal of the output voltage (VOUT) directly or via a resistive voltage dividing circuit (DIV).

[0068] [Appendix 9] The output circuit (VOUT) a first resistor (R3) connected between the control electrode and the second main electrode of the first output transistor (DM); a second resistor (R4) connected to the second output transistor (EM) so that a current (I) having the same value as the current (I) flowing through the first resistor (R3) flows; further comprising The constant voltage generating circuit (1) according to any one of appendices 1 to 8, which outputs, as the output voltage (VOUT), a voltage (Vgs2+Vy) obtained by adding together an inter-electrode voltage (Vgs2) between the control electrode and the second main electrode of the second output transistor (EM) and a voltage (Vy) across the second resistor (R4), or a voltage corresponding thereto.

[0069] [Appendix 10] 10. The constant voltage generating circuit (1) according to any one of appendices 1 to 9, wherein the node voltage (Vd1) is a divided voltage (Vd1) of the output voltage (VOUT).

[0070] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0071] 1 Constant voltage generation circuit 10 Output circuit 20 Switching circuit BUF Schmitt buffer C1 capacitor CS1 current source DIV Resistor voltage divider circuit DM transistor (depletion-type NMOSFET) EM transistor (enhancement type NMOSFET) HYS Hysteresis circuit INV Inverter M1~M3 transistors (NMOSFET) R1~R7 resistance VF Voltage Follower

Claims

1. an output circuit configured to generate a constant output voltage from an input voltage using a first output transistor of a depletion mode and a second output transistor of an enhancement mode; a capacitor configured to smooth the output voltage; a switching circuit configured to switch between enabling and disabling the smoothing in response to the output voltage or a node voltage that varies depending on the output voltage; A constant voltage generating circuit comprising:

2. 2. The constant voltage generating circuit according to claim 1, wherein the switching circuit disables the smoothing when the output voltage or the node voltage is lower than a threshold voltage, and enables the smoothing when the output voltage or the node voltage is higher than the threshold voltage.

3. 3. The constant voltage generating circuit according to claim 2, wherein the switching circuit includes a first transistor connected in series to the capacitor, and the first transistor is turned off when the output voltage or the node voltage is lower than the threshold voltage, and the first transistor is turned on when the output voltage or the node voltage is higher than the threshold voltage.

4. The constant voltage generating circuit according to claim 2 , wherein the switching circuit further includes a resistor or a current source connected in series with the capacitor.

5. 3. The constant voltage generating circuit according to claim 2, wherein the switching circuit further includes a hysteresis applying circuit configured to apply hysteresis to the threshold voltage.

6. 6. The constant voltage generation circuit according to claim 5, wherein the hysteresis applying circuit includes: a second transistor configured to have a control electrode to which the output voltage or the node voltage is applied; a current / voltage conversion circuit configured to convert a current signal flowing through the second transistor into a voltage signal; and a Schmitt buffer configured to receive an input of the voltage signal, and the switching circuit switches the on / off state of the first transistor in response to the output signal of the Schmitt buffer.

7. 2. The constant voltage generating circuit according to claim 1, wherein the output circuit further includes a third output transistor having a first main electrode connected to the input voltage application terminal, a second main electrode connected between the input voltage application terminal and the output voltage application terminal, and a control electrode connected to the first main electrode of the second output transistor.

8. 2. The constant voltage generating circuit according to claim 1, wherein a control electrode of said second output transistor is connected to an application terminal of said output voltage directly or via a resistive voltage dividing circuit.

9. The output circuit a first resistor connected between the control electrode and the second main electrode of the first output transistor; a second resistor connected to the second output transistor so that a current having the same value as the current flowing through the first resistor flows; further comprising 2. The constant voltage generating circuit according to claim 1, wherein the output voltage is a voltage obtained by adding together an inter-electrode voltage between the control electrode and the second main electrode of the second output transistor and a voltage across the second resistor, or a voltage corresponding thereto.

10. 10. The constant voltage generating circuit according to claim 1, wherein the node voltage is a divided voltage of the output voltage.

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