Integrated circuit

Abstract

To provide an integrated circuit making it possible to prevent a ratio of a drive current of a main transistor to a current of a sense transistor from deviating from a desired value.SOLUTION: An integrated circuit includes: a first transistor that includes a high-potential electrode to which a predetermined voltage is applied, a control electrode to which a control voltage is applied, and a low-potential electrode, and that flows a first current to a load; a second transistor that includes a high-potential electrode to which the predetermined voltage is applied, a control electrode to which the control voltage is applied, and a low-potential electrode, and that flows a second current dependent on the first current; a third transistor connected between the low-potential electrode of the second transistor and a predetermined line; an operational amplifier that controls the third transistor so that a voltage at the low-potential electrode of the first transistor agrees with a voltage at the low-potential electrode of the second transistor; and a subtraction circuit that, when a first requirement is satisfied, flows a third current, which is a part of the second current, to the ground.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to integrated circuits. [Background technology]

[0002] As a method for detecting the load current of a transistor that drives a load, a method for detecting the current of a so-called sense transistor that passes a current corresponding to the load current is known (for example, Patent Document 1).

[0003] In general, the size ratio between the sense transistor and the main transistor is determined so that the current flowing through the sense transistor and the current flowing through the transistor that drives the load (hereinafter referred to as the main transistor) has a predetermined ratio. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-037493 Summary of the Invention [Problem to be solved by the invention]

[0005] However, if the size ratio between the sense transistor and the main transistor is affected by manufacturing variations and deviates from the desired size ratio, the ratio between the current from the sense transistor and the drive current of the main transistor may deviate from the desired ratio.

[0006] The present invention has been made in consideration of such problems, and aims to provide an integrated circuit that can suppress deviation of the ratio of the drive current of the main transistor and the current of the sense transistor from a desired value. [Means for solving the problem]

[0007] One invention for achieving the above object is an integrated circuit comprising: a first transistor having a high potential side electrode to which a predetermined voltage is applied, a control electrode to which a control voltage is applied, and a low potential side electrode, and flowing a first current to a load; a second transistor having a high potential side electrode to which the predetermined voltage is applied, a control electrode to which the control voltage is applied, and a low potential side electrode, and flowing a second current corresponding to the first current; a third transistor connected between the low potential side electrode of the second transistor and a predetermined line; an operational amplifier controlling the third transistor so that the voltage of the low potential side electrode of the first transistor and the voltage of the low potential side electrode of the second transistor match; and a subtraction circuit that, when a first condition is satisfied, flows a third current that is a portion of the second current to ground.

[0008] Another invention for achieving the above object is an integrated circuit comprising: a first transistor having a high potential side electrode to which a predetermined voltage is applied, a control electrode to which a control voltage is applied, and a low potential side electrode, and flowing a first current to a load; a second transistor having a high potential side electrode to which the predetermined voltage is applied, a control electrode to which the control voltage is applied, and a low potential side electrode, and flowing a second current corresponding to the first current; a third transistor connected between the low potential side electrode of the second transistor and a predetermined line; an operational amplifier controlling the third transistor so that the voltage of the low potential side electrode of the first transistor and the voltage of the low potential side electrode of the second transistor match; and an adder circuit that adds a fourth current to the current flowing to the predetermined line via the third transistor when a second condition is satisfied.

[0009] Another invention for achieving the above object is an integrated circuit comprising: a first transistor having a high potential side electrode to which a predetermined voltage is applied, a control electrode to which a control voltage is applied, and a low potential side electrode, and flowing a first current to a load; a second transistor having the high potential side electrode to which the predetermined voltage is applied, a control electrode to which the control voltage is applied, and a low potential side electrode, and flowing a second current corresponding to the first current; a third transistor connected between the low potential side electrode of the second transistor and a predetermined line; an operational amplifier that controls the third transistor so that a voltage at the low potential side electrode of the first transistor and a voltage at the low potential side electrode of the second transistor match; a transistor connected to the low potential side electrode of the second transistor and controlled together with the third transistor by the operational amplifier; a bias current source that flows a bias current corresponding to a current flowing through the transistor; and an overcurrent detection circuit that detects whether the first current is an overcurrent based on the current of the bias current source. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an integrated circuit that can prevent the ratio of the drive current of the main transistor and the current of the sense transistor from deviating from a desired value. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating an overview of an integrated circuit 1 according to a first embodiment. [Figure 2] FIG. 2 is a diagram illustrating details of an integrated circuit 1 according to a first embodiment. [Figure 3] 3A to 3C are diagrams illustrating subtraction in the integrated circuit 1 of the first embodiment. [Figure 4] FIG. 2 is a diagram illustrating addition in the integrated circuit 1 of the first embodiment. [Figure 5] FIG. 10 is a diagram illustrating details of an integrated circuit 2 according to a second embodiment. [Figure 6] FIG. 10 is a diagram illustrating the integrated circuit 2 when no correction is performed. [Figure 7]FIG. 10 is a diagram illustrating the integrated circuit 2 when performing addition. [Figure 8] 10 shows the results of a simulation of addition using integrated circuit 2. [Figure 9] FIG. 10 is a diagram illustrating details of an integrated circuit 3 according to a modified example. [Figure 10] FIG. 10 is a diagram illustrating an overview of an integrated circuit 1a according to a third embodiment. [Figure 11] FIG. 2 is a diagram illustrating an example of the configuration of an overcurrent detection circuit 102. [Figure 12] FIG. 10 is a diagram illustrating details of an integrated circuit 1a according to a third embodiment. [Figure 13] FIG. 10 is a diagram illustrating an overview of an integrated circuit 1b according to a fourth embodiment. [Figure 14] FIG. 2 is a diagram illustrating an example of the configuration of a current source 101b. [Figure 15] FIG. 10 is a diagram illustrating an overview of an integrated circuit 1c according to a fifth embodiment. [Figure 16] FIG. 10 is a diagram illustrating an example of the configuration of a current source 101c. DETAILED DESCRIPTION OF THE INVENTION

[0012] At least the following matters will become clear from the description of this specification and the accompanying drawings.

[0013] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The same or equivalent components, members, etc. shown in each drawing are designated by the same reference numerals, and redundant explanations will be omitted where appropriate.

[0014] ==First Embodiment== 1 is a diagram illustrating an overview of an integrated circuit 1 according to this embodiment. The integrated circuit 1 is a circuit that drives a load L based on a drive signal Sin from a microcomputer 4. The load L is, for example, an inductive load such as a motor, but is not limited to this. The integrated circuit 1 according to this embodiment includes terminals TE1 to TE4, a logic circuit 7, a gate driver 10, transistors T1 to T3, an operational amplifier OP, and a correction circuit 11.

[0015] The terminal TE1 is a terminal to which the power supply voltage Vcc of the integrated circuit 1 is applied from a power supply external to the integrated circuit 1, and the terminal TE2 is a terminal to which a logic level signal Sin is input from the microcomputer 4. The terminal TE3 is a terminal to which a load L is connected, and the terminal TE4 is a terminal to which a resistor R is connected.

[0016] In this embodiment, the voltage Vout applied to the load L is applied to the terminal TE3, and the voltage Vsns generated at the resistor R is applied to the terminal TE4. The resistor R corresponds to a so-called sense resistor for detecting a current from the transistor T2 (described later).

[0017] [Logic Circuit 7] The logic circuit 7 receives a control signal Sin transmitted from the microcomputer 4 via the input terminal IN and generates a logic signal that turns on or off the transistors T1 and T2. When the logic circuit 7 receives a high-level (hereinafter referred to as H-level) control signal transmitted from the microcomputer 4 via the control signal Sin, it outputs a logic signal for turning on the transistors T1 and T2.

[0018] [Gate driver 10] The gate driver 10 drives each of the transistors T1 and T2 based on the logic signal output from the logic circuit 7. Specifically, when the signal Sin is at H level, the gate driver 10 turns on the transistors T1 and T2, and when the signal Sin is at low level (hereinafter referred to as L level), the gate driver 10 turns off the transistors T1 and T2.

[0019] [Transistor T1] The transistor T1 (corresponding to a "first transistor") is a so-called main transistor for driving the load L. In this embodiment, the transistor T1 is an n-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0020] A control voltage Vdr from the gate driver 10 is applied to the gate electrode of the transistor T1. A predetermined power supply voltage Vcc (corresponding to a "predetermined voltage") is applied to the drain electrode of the transistor T1 from a terminal TE1. In this embodiment, when the gate driver 10 turns on the transistor T1, the transistor T1 passes a current I1 (corresponding to a "first current") through the load L. Note that the current I1 may hereinafter be referred to as a "load current I1."

[0021] [Transistor T2] The transistor T2 (corresponding to a "second transistor") is a so-called sense transistor that detects the load current I1 by passing a current I2 corresponding to the load current I1 from the transistor T1.

[0022] In this embodiment, the transistor T2 is an n-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0023] A control voltage Vdr is applied to the gate electrode of the transistor T2 from the gate driver 10. A power supply voltage Vcc is applied to the drain electrode of the transistor T2 from the terminal TE1.

[0024] Transistor T2 passes current I2 (corresponding to the "second current") through resistor R in response to load current I1. Current I2 is, for example, a constant multiple of load current I1. In this case, if the channel length L1 of transistor T1 and the channel length L2 of transistor T2 are the same and the ratio of channel width W1 of transistor T1 to channel width W2 of transistor T2 is, for example, 3000:1, then theoretically current I2 will be 1 / 3000 of load current I1.

[0025] When the current I2 flows into the resistor R, a voltage Vsns, which is the product of the known resistance R and the current I2, is output from the terminal TE4. At this time, the microcomputer 4 can detect (actually calculate) the current I2 by detecting the voltage Vsns.

[0026] When the microcomputer 4 detects the current I2, it can detect (actually calculate) the load current I1 based on the relationship between the load current I1 and the current I2 described above.

[0027] [Transistor T3] The transistor T3 (corresponding to the "third transistor") is a transistor for matching the voltages of the source electrodes of the transistors T1 and T2 (details will be described later in the section on operational amplifier OP).

[0028] In this embodiment, the transistor T3 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0029] The transistor T3 is connected between the source electrode of the transistor T2 and a predetermined line L1 (described later). The output voltage of an operational amplifier OP (described later) is applied to the gate electrode of the transistor T3.

[0030] [Transistor T4] The transistor T4 is a transistor for switching whether to detect the load current I1 by the transistor T2 or to stop it.

[0031] In this embodiment, the transistor T4 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0032] The transistor T4 is connected between the transistor T3 and a terminal TE4. For example, a signal S3 from the microcomputer 4 is input to the gate electrode of the transistor T4 via a terminal (not shown).

[0033] When the signal S3 is at a low level, the transistor T2 detects the load current I1, and when the signal S3 is at a high level, the transistor T2 stops detecting the load current I1.

[0034] The back gates of transistors T1 and T2 are supplied with the same voltage as the source electrodes, but may be configured to receive a voltage equal to or lower than the voltage applied to their respective source electrodes. The back gates of transistors T3 and T4 are supplied with power supply voltage Vcc, but may be configured to receive a voltage equal to or higher than the voltage applied to their respective source electrodes.

[0035] [Correction circuit 11] The compensation circuit 11 calculates the load current I1 and the current I flowing through the transistor T2. 2と This is a circuit that corrects the current flowing into resistor R when the ratio deviates from the design value.

[0036] Incidentally, the deviation of the ratio of the load current I1 to the current I2 from the design value can be attributed to, for example, manufacturing variations in the size ratio of the transistors T1 and T2. Here, the "size ratio" of the transistor T1 refers to the ratio of the channel length to the channel width (W1 / L1) of the transistor when the transistor T1 is a MOS transistor as in this embodiment.

[0037] If such manufacturing variations exist, the microcomputer 4 may detect a current value that deviates from the actual value, and may not be able to correctly control the integrated circuit 1 controlled by the microcomputer.

[0038] The correction circuit 11, which will be described in detail later, makes it possible to prevent the ratio of the load current I1 of the transistor T1 to the current I2 of the transistor T2 from deviating from a desired value.

[0039] [Op Amp OP] The operational amplifier OP controls the correction circuit 11 so that the voltage of the source electrode of the transistor T1 and the voltage of the source electrode of the transistor T2 match (details will be described later).

[0040] <Configuration of Integrated Circuit 1> 2 is a diagram illustrating details of the integrated circuit 1 of this embodiment. The integrated circuit of this embodiment includes transistors T1 to T3, an operational amplifier OP, a subtraction circuit 12, an addition circuit 13, and an inverter 14. Note that the transistors T1 to T3 have been described above, so a description thereof will be omitted below.

[0041] In addition, the number "100" assigned to the transistor T3 in FIG. 2 indicates the current flowing through the transistor T3, and is a relative value when the current flowing through the transistor T3 is set to 100.

[0042] [Op Amp OP] The operational amplifier OP controls the transistor T3 so that the voltage at the source electrode of the transistor T1 matches the voltage at the source electrode of the transistor T2.

[0043] The non-inverting input terminal of the operational amplifier OP is connected to the source electrode of the transistor T1, the inverting input terminal of the operational amplifier OP is connected to the source electrode of the transistor T2, and the output terminal of the operational amplifier OP is connected to the gate electrode of the transistor T3.

[0044] The operational amplifier OP controls the transistor T3 so that the voltage of the source electrode of the transistor T2 applied to the inverting input terminal becomes the voltage of the source electrode of the transistor T1 applied to the non-inverting input terminal.

[0045] [[Subtraction circuit 12]] The subtraction circuit 12 is a circuit that subtracts a predetermined value of current from the current flowing into the resistor R in Figure 1 when the ratio of the current I2 flowing through the transistor T2 to the load current I1 becomes larger than the design value due to manufacturing variations in the integrated circuit 1 (hereinafter, this may be simply referred to as "subtraction").

[0046] By performing the subtraction, the difference between the actual load current I1 and the detected load current I1 can be reduced.

[0047] When performing subtraction, the subtraction circuit 12 passes a current I4 (corresponding to a "third current"), which is a part of the current I2, to the ground GND. This will be described in detail below.

[0048] The subtraction circuit 12 includes transistors T10 to T12 and an inverter .

[0049] [Transistor T10] The transistor T10 (corresponding to the "fourth transistor") is a p-channel MOS transistor in this embodiment, and has a source electrode, a gate electrode, and a drain electrode.

[0050] The output voltage of the operational amplifier OP is applied to the gate electrode of the transistor T10, and the source electrode of the transistor T10 is connected to the source electrode of the transistor T2.

[0051] In FIG. 2, the value "2.5" assigned to the transistor T10 indicates the current I3 flowing through the transistor T10, and is a relative value when the current flowing through the transistor T3 is set to 100.

[0052] Similar relative values ​​are assigned to the currents flowing through the other transistors T10, T20, T23, T24, and T25 described later. Note that for transistor T25, the relative value of the current flowing when transistor T26 described later is on is shown.

[0053] For example, by making the channel lengths of the transistors T3 and T10 the same and setting the ratio of their channel widths to 100:2.5, the ratio of the currents flowing through them can also be set to 100:2.5.

[0054] [Transistor T11] The transistor T11 (corresponding to a "first switch") is a p-channel MOS transistor in this embodiment, and has a source electrode, a gate electrode, and a drain electrode.

[0055] The transistor T11 is located between the drain electrode of the transistor T10 and the ground GND. The gate electrode of the transistor T11 is connected to an inverter 14 (described later).

[0056] [Transistor T12] The transistor T12 (corresponding to a "second switch") is a p-channel MOS transistor in this embodiment, and has a source electrode, a gate electrode, and a drain electrode.

[0057] The transistor T12 is turned off when the subtraction circuit 12 performs subtraction, and is turned on when the subtraction circuit 12 does not perform subtraction. That is, the transistors T11 and T12 are turned on and off complementarily (details will be described later).

[0058] [Inverter 14] An inverter 14 (corresponding to a "switch control circuit") turns on and off the transistors T11 and T12 in a complementary manner.

[0059] A signal S1 is input to the inverter 14. When the signal S1 is at H level, the transistor T11 is turned off and the transistor T12 is turned on. When the signal S1 is at L level, the transistor T11 is turned on and the transistor T12 is turned off.

[0060] Although details will be described later, when the subtraction circuit 12 performs subtraction, the signal S1 is set to L level, and when the subtraction circuit 12 does not perform subtraction, the signal S1 is set to H level.

[0061] Addition circuit 13 The adder circuit 13 is a circuit that adds (hereinafter may be simply referred to as "adder") a predetermined value of current to the current flowing into the resistor R in Figure 1 when the ratio of the load current I1 flowing through the transistor T1 to the current I2 flowing through the transistor T2 becomes smaller than the design value due to manufacturing variations in the integrated circuit 1.

[0062] By adding, it is possible to reduce the difference between the actual load current I1 and the detected load current I1.

[0063] When the addition circuit 13 performs addition, it adds the current I6 (corresponding to the "fourth current") to the current I2.

[0064] The adder circuit 13 includes transistors T20 to T26.

[0065] [Transistor T20] The transistor T20 (corresponding to a "fifth transistor") is a p-channel MOS transistor in this embodiment, and has a source electrode, a gate electrode, and a drain electrode.

[0066] The output voltage of the operational amplifier OP is applied to the gate electrode of the transistor T20, and the source electrode of the transistor T20 is connected to the source electrode of the transistor T2.

[0067] [Transistors T21, T22] In this embodiment, the transistors T21 and T22 are both p-channel MOS transistors, and each have a source electrode, a gate electrode, and a drain electrode.

[0068] The transistor T21 is diode-connected between the transistor T20 and the ground GND, and the transistor T22 is connected between a transistor T23 (described later) and the ground GND.

[0069] The transistors T21 and T22 have a size ratio of 1:1. The transistors T21 and T22 form a current mirror circuit. As a result, the current I5 that is the same as the current I5 that flows through the transistor T21 via the transistor T20 flows through the transistor T22 via the transistor T23 (described later).

[0070] [Transistors T23, T24] In this embodiment, the transistors T23 and T24 are both p-channel MOS transistors, and each have a source electrode, a gate electrode, and a drain electrode.

[0071] The transistor T23 is connected between the terminal TE1 and the transistor T22 and is diode-connected. The transistor T24 is connected between the terminal TE1 and the line L1.

[0072] The transistors T23 and T24 have a size ratio of 1:1. The transistors T23 and T24 form a current mirror circuit. As a result, the same current I5 as the current I5 flowing through the transistor T23 flows through the transistor T24.

[0073] [Transistor T25] The transistor T25 (corresponding to the "sixth transistor") is a p-channel MOS transistor in this embodiment, and has a source electrode, a gate electrode, and a drain electrode.

[0074] The transistor T25 is connected between the terminal TE1 and a transistor T26 (described later). The gate electrode of the transistor T25 is connected to the gate electrode of the diode-connected transistor T23.

[0075] Therefore, the transistors T25 and T23 form a current mirror circuit. The transistor T25 generates a current I6 that corresponds to the current flowing through the transistor T23.

[0076] In this embodiment, the transistors T25 and T23 have a size ratio of 1:1.

[0077] [Transistor T26] Transistor T26 (corresponding to a "third switch") is a p-channel MOS transistor in this embodiment, and has a source electrode, a gate electrode, and a drain electrode.

[0078] The transistor T26 is located between the transistor T25 and the line L1. A signal S2 is input to the gate electrode of the transistor T26. The transistor T26 is turned on and off in accordance with the signal S2.

[0079] Although details will be described later, when the adder circuit 13 performs addition, the signal S2 is set to L level, and when the adder circuit 13 does not perform addition, the signal S2 is set to H level.

[0080] The configuration of the integrated circuit 1 of this embodiment has been described above. Subtraction and addition in the integrated circuit 1 will now be described.

[0081] <Subtract> The subtraction in the integrated circuit 1 of this embodiment will be described below. The subtraction is performed when the ratio of the current I2 flowing through the transistor T2 to the load current I1 becomes larger than the design value due to manufacturing variations in the transistors T1 and T2.

[0082] 3 is a diagram illustrating subtraction in the integrated circuit 1 of this embodiment. When subtraction is performed, signals S1 and S2 are set to L level and H level, respectively. Note that when signals S1 and S2 are at L level and H level, respectively, this corresponds to "when the first condition is satisfied."

[0083] The value of the current (current value) flowing into the line L1 at this time will be described below. In the following description, the current values ​​of the above-mentioned currents I1 to I6 will be represented as I1 to I6, respectively.

[0084] As shown in FIG. 3, for subtraction, transistor T11 is on, transistor T12 is off, and transistor T26 is off.

[0085] Therefore, in the case of subtraction, the current value flowing into line L1 is the sum of the current values ​​flowing from transistor T3 and transistor T24.

[0086] The current value I3 flowing from transistor T3 to line L1 is I2-I4-I5, and the current value flowing from transistor T24 to line L is I5.

[0087] Therefore, in the case of subtraction, the current flowing into the line L1 is I2-I4. In other words, the current flowing into the resistor R via the line L1 can be subtracted by the current I4 from the current I2 flowing through the transistor T2.

[0088] In this embodiment, the ratio of the current I2 to the current I4 is 105:2.5. Therefore, a current that is 1 / 42 of the current I2 can be subtracted from the current I2.

[0089] The amount of correction to be subtracted from the current I2 can be set to a desired amount by adjusting the current I4, which can be adjusted, for example, by adjusting the channel width of the transistor T10.

[0090] <Addition> The following describes the addition in the integrated circuit 1 of this embodiment. The addition is performed when the ratio of the current I2 flowing through the transistor T2 to the load current I1 flowing through the transistor T1 becomes smaller than the design value due to manufacturing variations in the transistors T1 and T2.

[0091] 4 is a diagram illustrating addition in the integrated circuit 1 of this embodiment. When addition is performed, signals S1 and S2 are set to H level and L level, respectively. Note that when signals S1 and S2 are H level and L level, respectively, this corresponds to "when the second condition is satisfied."

[0092] The value of the current flowing into the line L1 at this time will be described below. As shown in Fig. 4, in the case of addition, the transistor T11 is off, the transistor T12 is on, and the transistor T26 is on.

[0093] Therefore, in the case of addition, the current value flowing into line L1 is the sum of the current values ​​flowing from transistors T3, T10, T24 and T25.

[0094] The current value flowing from transistor T3 to line L1 is I2-I4-I5. The current value flowing from transistor T10 to line L1 is I4. The current value flowing from transistor T24 to line L1 is I5. The current value flowing from transistor T25 to line L1 is I6.

[0095] Therefore, in the case of addition, the value of the current flowing into the line L1 is I2 + I6. In other words, the current flowing into the resistor R via the line L1 can be added by the current I6 to the current I2 flowing through the transistor T2.

[0096] In this embodiment, the ratio of the current I2 to the current I6 is 105:2.5. Therefore, a current that is 1 / 42 of the current I2 can be added to the current I2.

[0097] The amount of correction to be added to the current I2 can be set to a desired amount by adjusting the current I6, which can be adjusted, for example, by adjusting the channel width of the transistor T25.

[0098] The integrated circuit 1 described above can perform one-stage subtraction and one-stage addition to the current flowing into the resistor R. This makes it possible to prevent the ratio of the load current I1 from the transistor T1 to the current flowing into the resistor R from deviating from a desired value.

[0099] In this embodiment, current I4 and current I6 have the same current value (both 2.5 when current I3 is 100), but this is not limited to this, and current I4 and current I6 may have different current values.

[0100] This allows three stages of subtraction or addition to be performed according to the signals S1 and S2.

[0101] Specifically, when both the subtraction circuit 12 and the addition circuit 13 are operated (signal S1=L, signal S2=L), subtraction or addition can be performed with the correction amount set to I6-I4 (≠0).

[0102] In addition, in this embodiment, the transistors T1 to T3, T10 to T12, and T20 to T26 are MOS transistors, but this is not limitative and other types of transistors such as IGBTs may also be used.

[0103] In addition, the "drain electrodes" in T1, T2, T21 and T22 are an example of "high potential side electrodes", the "gate electrodes" are an example of "control electrodes", and the "source electrodes" are an example of "low potential side electrodes".

[0104] The "source electrodes" of transistors T3, T10 to T12, T20, and T23 to T26 are an example of "high potential side electrodes," the "gate electrodes" are an example of "control electrodes," and the "drain electrodes" are an example of "low potential side electrodes."

[0105] ==Second Embodiment== The integrated circuit 1 of the first embodiment is capable of one-stage subtraction and one-stage addition. In this embodiment, an integrated circuit 2 that is capable of even more stages of subtraction or addition will be described.

[0106] 5 is a diagram illustrating details of the integrated circuit 2 of this embodiment. The integrated circuit 2 is different from the first embodiment in that it has a subtraction circuit 22 and an addition circuit 23. The integrated circuit 2 also includes an inverter 24.

[0107] [[Subtraction circuit 22]] The subtraction circuit 22 differs from the subtraction circuit 12 (FIG. 2) of the first embodiment in that it further includes transistors T13 to T15.

[0108] [Transistor T13] In this embodiment, the transistor T13 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0109] The output voltage of the operational amplifier OP is applied to the gate electrode of the transistor T13. The source electrode of the transistor T13 is connected to the source electrode of the transistor T2. That is, the transistor T13 and the transistor T10 are connected in parallel with each other.

[0110] Also, the relative amount of current flowing through transistor T10 is 2.5, while the relative amount of current flowing through transistor T13 is 5.0.

[0111] [Transistor T14] In this embodiment, the transistor T14 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0112] The transistor T14 is located between the drain electrode of the transistor T13 and the ground GND. The gate electrode of the transistor T14 is connected to an inverter 24 (described later).

[0113] [Transistor T15] In this embodiment, the transistor T15 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0114] The transistor T15 is located between the transistor T13 and the line L1. The gate electrode of the transistor T15 is connected to an inverter 24 (described later).

[0115] [Inverter 24] The inverter 24 turns the transistors T14 and T15 on and off in a complementary manner. A signal S12 is input to the inverter 24. When the signal S12 is at H level, the transistor T14 is off and the transistor T15 is on. When the signal S12 is at L level, the transistor T14 is on and the transistor T15 is off.

[0116] Addition circuit 23 The adder circuit 23 differs from the adder circuit 13 of the first embodiment in that it includes a transistor T30 instead of the transistor T26, and further includes transistors T31 and T32.

[0117] [Transistor T30] The transistor T30 replaces the transistor T26 of the first embodiment, with the only difference being that the relative amount of current flowing through the transistor T26 is 2.5, while the relative amount of current flowing through the transistor T30 is 7.5.

[0118] [Transistor T31] In this embodiment, the transistor T31 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0119] The transistor T31 is connected between the terminal TE1 and a transistor T32 (described later). The gate electrode of the transistor T31 is connected to the gate electrode of the diode-connected transistor T23.

[0120] Therefore, the transistors T31 and T23 form a current mirror circuit. The transistor T31 generates a current corresponding to the current flowing through the transistor T23. As shown in Figure 5, the relative value of the current generated by the transistor T31 is 10.

[0121] In this embodiment, the size ratio between the transistor T30 and the transistor T23 is 3:1, and the size ratio between the transistor T31 and the transistor T23 is 4:1.

[0122] [Transistor T32] In this embodiment, the transistor T32 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0123] The transistor T32 is located between the transistor T31 and the line L1. A signal S22 is input to the gate electrode of the transistor T32. The transistor T32 is turned on and off in accordance with the signal S22.

[0124] The above has described the configuration of the integrated circuit 2 of this embodiment. According to the integrated circuit 2 of this embodiment, it is possible to perform subtraction or addition in 10 stages in response to the signals S11, S12, S21, and S22.

[0125] The 10 stages here exclude the case where the signals S11, S12, S21, and S22 are all at H level. In this case, neither subtraction nor addition is performed.

[0126] Below, one addition among the 10 stages of subtraction or addition in the integrated circuit 2 will be described in comparison with the case where no correction is performed.

[0127] First, regardless of whether correction is performed or not, the current flowing through transistor T2 is the sum of the currents flowing through transistors T3, T10, T13, and T20. Therefore, the relative value of the current flowing through transistor T2 is 110.0 (=100.0+2.5+5.0+2.5).

[0128] <If no correction is performed> 6 is a diagram illustrating the integrated circuit 2 when no correction is performed. When no correction is performed, the signals S11, S12, S21, and S22 are all at H level.

[0129] In this case, as shown in FIG. 6, transistor T11 is off, transistor T12 is on, transistor T14 is off, transistor T15 is on, transistor T26 is off, and transistor T32 is off.

[0130] Therefore, in this case, the current flowing into line L1 is the sum of the currents flowing through transistors T3, T10, T13, and T24. In other words, the relative value of the current flowing into line L1 is 110 (=100+2.5+5.0+2.5).

[0131] That is, the relative value of the current flowing into line L1 is the same as the relative value of the current flowing into transistor T2 and is not corrected.

[0132] <Addition> 7 is a diagram illustrating the integrated circuit 2 when performing addition. In the case of addition in this diagram, signals S11 are H level, S12 are L level, S21 are L level, and S22 are L level.

[0133] In this case, as shown in FIG. 7, transistor T11 is off, transistor T12 is on, transistor T14 is on, transistor T15 is off, transistor T26 is on, and transistor T32 is on.

[0134] Therefore, in this case, the current flowing into line L1 is the sum of the currents flowing through transistors T3, T10, T24, T30, and T31. In other words, the relative value of the current flowing into line L1 is 122.5 (=100.0+2.5+2.5+7.5+10.0).

[0135] In other words, the relative value of the current flowing into line L1 is 11.4% (=(122.5-110.0) / 110.0) added to the relative value (110.0) of the current flowing into transistor T2.

[0136] Below, we will use simulation results to explain to what extent the error in the current flowing into resistor R from the ideal value is reduced by the above-mentioned addition.

[0137] <Simulation results> 8 shows the results of a simulation of addition using the integrated circuit 2. In this simulation, it is assumed that the current I2 flowing through the transistor T2 deviates from the design value due to manufacturing variations.

[0138] Below, we will first explain the results for an ideal case where there are no manufacturing variations (case 1), a case where deviations occur due to manufacturing variations but are not corrected (case 2), and a case where deviations occur due to manufacturing variations and are corrected (case 3).

[0139] Figure 8(a) shows the current flowing through each transistor shown in the first column. In Figure 8(b), the "output current" is the current flowing into line L1 (i.e., the current flowing into resistor R). The "sense ratio" is the value obtained by dividing the load current I1 flowing through transistor T1 by the output current.

[0140] [Ideal case (case 1)] 8(a) and 8(b), the second column shows the results for an ideal case (no deviation). In case 1, the current value I1 flowing through transistor T1 is 3.0 A, and the current value I2 flowing through transistor T2 is 1000 μA.

[0141] In case 1, the current I2 flows directly into resistor R, so the output current is 1000 μA. Therefore, the sense ratio in this case is 3000.

[0142] [When a misalignment occurs but no correction is made (case 2)] 8(a) and 8(b), the third column shows the results when the current value I2 deviates from the ideal value and no correction is performed, i.e., when the signals S11, S12, S21, and S22 in the integrated circuit 2 are all set to the H level.

[0143] In this case, the current I2 flowing through transistor T2 is 889 μA, which is 111 μA less than the current (1000 μA) in case 1. In case 2, current I2 also flows directly into resistor R, so the output current is 889 μA.

[0144] Therefore, the sense ratio in this case is 3375 (=3.0A / 889μA), which is a deviation of +12.5% ​​compared to case 1.

[0145] [When a misalignment occurs and correction is required (case 3)] In (a) and (b) of FIG. 8, the fourth column shows the result when the same deviation as in case 2 occurs in the current value I2 and the above-mentioned addition is performed.

[0146] In this case, the current I2 flowing through the transistor T2 is 889 μA, which is the same as in case 2.

[0147] However, according to the above addition, a current that is +11.4% greater than current I2 flows into resistor R. In this case, the current flowing into resistor R (output current) is 990 μA (≈889 μA × (100% + 11.4%)).

[0148] Therefore, the sense ratio in this case is 3030 (=3.0 A / 990 μA), and the deviation is +1.0% compared to case 1. In other words, it was shown that the above addition can reduce the deviation of the sense ratio compared to case 2.

[0149] == Variations == 9 is a diagram illustrating details of the modified integrated circuit 3. The integrated circuit 3 of this modified example differs from the second embodiment (FIG. 5) in that it further includes cascode-connected transistors T40 and T41 in addition to the transistors T21 and T22.

[0150] With this configuration, when a channel length modulation effect occurs in the transistors T21 and T22 that form the current mirror circuit, it is possible to suppress an error from the ideal value of the current to be copied.

[0151] Although the same voltage as that applied to the source electrode is applied to the back gate of the n-channel MOS transistor constituting the correction circuit 11 in the embodiment described above, a voltage equal to or lower than that applied to each source electrode may be applied. Furthermore, although the power supply voltage Vcc is applied to the back gate of the p-channel MOS transistor constituting the correction circuit 11 in the embodiment described above, a voltage equal to or higher than that applied to each source electrode may be applied.

[0152] ==Third Embodiment== 10 is a diagram illustrating an overview of an integrated circuit 1a according to a third embodiment. The integrated circuit 1a is a circuit that drives a load L based on a drive signal Sin from a microcomputer 4. The integrated circuit 1a according to the third embodiment includes terminals TE1 to TE4, a logic circuit 7, a gate driver 10, transistors T1 to T4 and T20, an operational amplifier OP, a bias current source 50a including a bias voltage source 100 and a current source 101a, and an overcurrent detection circuit 102. The terminals TE1 to TE4, the logic circuit 7, the gate driver 10, and the transistors T1 to T4 have the same configurations and operate as those of the first embodiment shown in FIG. 1, and therefore will not be described here.

[0153] [Transistor T20] The transistor T20 (corresponding to "transistor") is a p-channel MOS transistor in the third embodiment, and has a source electrode, a gate electrode, and a drain electrode.

[0154] The output voltage Vop of the operational amplifier OP is applied to the gate electrode of the transistor T20, similar to the transistor T3. The source electrode of the transistor T20 is connected to the source electrode of the transistor T2.

[0155] [Bias current source 50a] The bias current source 50a includes a bias voltage source 100 and a current source 101a, and generates a bias current I according to the current flowing through the transistor T20. C Flush.

[0156] [Bias voltage source 100] As will be described in detail later, the bias voltage source 100 generates a bias voltage Vo according to the current flowing through the transistor T20.

[0157] [Current source 101a] As will be described in detail later, the current source 101a generates a bias current I C Flush.

[0158] [Overcurrent detection circuit 102] The overcurrent detection circuit 102 detects the bias current I C Whether or not the current I1 is an overcurrent is detected based on the above. The overcurrent detection circuit 102 includes a resistor R1, a reference voltage output circuit 200, and a comparison circuit 201, as shown in FIG.

[0159] Resistor R1 receives bias current I from current source 101a. C flows, and the reference voltage output circuit 200 outputs a reference voltage for detecting whether the current I1 is an overcurrent or not. Then, the comparator circuit 201 compares the voltage generated across the resistor R1 with the reference voltage to detect whether the current I1 is an overcurrent or not.

[0160] When the overcurrent detection circuit 102 detects that the current I1 is an overcurrent, it outputs an H-level signal Sc to the logic circuit 7, and when the current I1 is not an overcurrent, it outputs an L-level signal Sc to the logic circuit 7. Furthermore, when the overcurrent detection circuit 102 outputs an H-level signal Sc, the logic circuit 7 generates a signal to turn off the transistors T1 and T2 and outputs the signal to the gate driver 10.

[0161] In addition, conventionally, whether the current flowing through transistor T1 is an overcurrent or not is detected based on the drain-source voltage of transistor T1. However, due to the positive temperature characteristic of the on-resistance of transistor T1, the current value at which the current I1 flowing through transistor T1 is detected as an overcurrent can decrease as the temperature rises.

[0162] On the other hand, as in this embodiment, the current I C By detecting whether the current I1 is an overcurrent using the above, the influence of the positive temperature characteristic of the on-resistance of the transistor T1 is eliminated, and the current value at which the current I1 flowing through the transistor T1 is detected as an overcurrent becomes constant.

[0163] <Configuration of integrated circuit 1a> 12 is a diagram illustrating an integrated circuit 1a of this embodiment further including a first adder circuit 300. The integrated circuit 1a of this embodiment includes transistors T1 to T4 and T20, an operational amplifier OP, a bias voltage source 100, a current source 101a, and an overcurrent detection circuit 102.

[0164] [Bias voltage source 100] The bias voltage source 100 is configured by a plurality of current mirror circuits, and outputs the gate voltage of the final-stage current mirror circuit as a bias voltage Vo, and outputs the bias voltage Vo according to the current I5 flowing through the transistor T20.

[0165] The bias voltage source 100 includes a first current mirror circuit configured with transistors T21 and T22, and a second current mirror circuit configured with transistors T23 and T24. The gate voltages of the transistors T23 and T24 are output as the bias voltage Vo.

[0166] [Current source 101a] The current source 101a generates a bias current I corresponding to the current I1 based on a bias voltage Vo corresponding to the current I5 flowing from the transistor T20. C The current source 101a includes transistors T400, T410, and T420. In FIG. 12, the value "2.5" assigned to the transistor T400 is a relative value when the current flowing through the transistor T3 is set to 100. In addition, the value "2.5" assigned to the transistor T410 is a relative value when the current flowing through the transistor T400 is set to 100. Therefore, in this embodiment, the current I flowing through the transistor T410 bis a current that is 0.0625% of the current I3 that flows through transistor T3.

[0167] [Transistor T400] In this embodiment, the transistor T400 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0168] The transistor T400 has a source electrode connected to the terminal TE1 and a gate electrode A bias voltage Vo is applied, and a current I having a value corresponding to the current value of the current flowing through the transistor T3 flows from the drain electrode. a In this example, the current I a The current value of this is the same as the current value flowing through the transistor T23.

[0169] [Transistor T410] In this embodiment, the transistor T410 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0170] The transistor T410 has a source electrode connected to the terminal TE1 and a gate electrode When a bias voltage Vo is applied, a current I flows through the transistor T25. b In this embodiment, a current I b The current value of is 1 / 40 of the current value of the current flowing through transistor T25.

[0171] [Transistor T420] In this embodiment, the transistor T420 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0172] The transistor T420 is provided between the transistor T410 and the overcurrent detection circuit 102, and a voltage corresponding to the signal S2 is applied to the gate electrode of the transistor T420. The drain electrode of the transistor T420 is connected to the drain electrode of the transistor T400. The transistor T420 is turned off when the signal S2 is at an H level, and turned on when the signal S2 is at an L level.

[0173] Therefore, when the signal S2 is at the H level, the current source 101a supplies the current I a The bias current I c In this case, the current source 101a generates a bias current I according to the value of the current flowing through the transistor T3. c Flush.

[0174] When the signal S2 is at an L level, the current source 101a supplies a current I a Current I b The current obtained by adding these is the bias current I c In this case, the current source 101a generates a current corresponding to the current flowing through the transistor T3 and a current I6 corresponding to the current I6 flowing through the transistor T25. b The bias current I c Flush.

[0175] That is, the current source 101a generates a bias current I C The current value is changed in two stages, and a bias current Ic of a current value corresponding to the current value flowing through resistor R is passed.

[0176] [First adder circuit 300] The first adder circuit 300 includes transistors T25 and T26. The configuration and operation of the transistors T25 and T26 are the same as those in the first embodiment, and therefore a description thereof will be omitted.

[0177] ==Fourth Embodiment== 13 is a diagram illustrating an overview of an integrated circuit 1b according to the fourth embodiment. The integrated circuit 1b is a circuit that drives a load L based on a drive signal Sin from a microcomputer 4. The integrated circuit 1b according to the fourth embodiment includes terminals TE1 to TE4, a logic circuit 7, a gate driver 10, transistors T1 to T4 and T20, a bias current source 50b including a bias voltage source 100 and a current source 101b, and an overcurrent detection circuit 102. Except for the current source 101b, the configuration and operation are similar to those of the third embodiment shown in FIG. 10, and therefore a description thereof will be omitted.

[0178] 14 is a diagram showing a part of an integrated circuit 1b of the fourth embodiment and a first subtraction circuit 301, and includes T20, a bias voltage source 100, a current source 101b, inverters 14 and 24, and the first subtraction circuit 301. The bias voltage source 100 has the same configuration as that shown in FIG.

[0179] [First subtraction circuit 301] The first subtraction circuit 301 has the same configuration and operation as the subtraction circuit 22 shown in FIG. 5 and the like, and therefore a description thereof will be omitted.

[0180] [Bias current source 50b] The bias current source 50b includes a bias voltage source 100 and a current source 101b, and generates a bias current I according to the current flowing through the transistor T20. C Flush.

[0181] [Current source 101b] The current source 101b generates a bias current I according to the current I1 based on a bias voltage Vo according to the current I5 flowing from the transistor T20. C The current source 101b includes transistors T400, T411, T412, T421, and T422. In FIG. 14, the value "2.5" assigned to transistor T400 is a relative value when the current flowing through transistor T3 is set to 100. Furthermore, the values ​​"2.5" and "5.0" assigned to transistors T411 and T412, respectively, are relative values ​​when the current flowing through transistor T400 is set to 100.

[0182] [Transistor T411] In this embodiment, the transistor T411 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0183] The transistor T411 has a source electrode connected to the terminal TE1 and a gate electrode When a bias voltage Vo is applied, a current I having a value corresponding to the current value of the current flowing through the transistor T10 is generated. b1 In this embodiment, a current I b1 The current value of is 1 / 40 of the current value of the current flowing through transistor T10.

[0184] [Transistor T412] In this embodiment, the transistor T412 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0185] The transistor T412 has a source electrode connected to the terminal TE1 and a gate electrode When a bias voltage Vo is applied, a current I corresponding to the current value of the current flowing through the transistor T13 is generated. b2 In this embodiment, a current I b2 The current value of this is 1 / 40 of the current value of the current flowing through the transistor T13.

[0186] [Transistor T421] In this embodiment, the transistor T421 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0187] The transistor T421 is provided between the transistor T411 and the overcurrent detection circuit 102, and a voltage corresponding to the signal S11b is applied to the gate electrode of the transistor T421. The drain electrode of the transistor T421 is connected to the drain electrode of the transistor T400. The transistor T421 is turned off when the signal S11b is at H level, and turned on when the signal S11b is at L level. The signal S11b is a signal output by the inverter 14.

[0188] [Transistor T422] In this embodiment, the transistor T422 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0189] The transistor T422 is provided between the transistor T412 and the overcurrent detection circuit 102, and a voltage corresponding to the signal S12b is applied to the gate electrode of the transistor T422. The drain electrode of the transistor T422 is connected to the drain electrode of the transistor T400. The transistor T422 is turned off when the signal S12b is at H level, and turned on when the signal S12b is at L level. The signal S12b is a signal output by the inverter 24.

[0190] Therefore, when the signals S11b and S12b are both at the H level, the current source 101b generates a current I a The bias current I c In this case, the bias current I c In other words, the current source 101b generates a bias current I 1 having a value corresponding to the current value of the current flowing through the transistor T10 and the transistor T13 subtracted from the current I2. C Flush.

[0191] Furthermore, when the signal S11b is at an L level and the signal S12b is at an H level, the current source 101b supplies a current I a Current I b1 The current obtained by adding these is the bias current I c In this case, the bias current I c The bias current I1 has a value corresponding to the sum of the current I2 flowing through the transistor T3 and the current I4 flowing through the transistor T10. In other words, the current source 101b generates a bias current I1 having a value corresponding to the sum of the current I2 flowing through the transistor T13 and the current I4 flowing through the transistor T10. C Flush.

[0192] Furthermore, when the signal S11b is at the H level and the signal S12b is at the L level, the current source 101b outputs the current I a Current I b2 The current obtained by adding these is the bias current I c In this case, the bias current I c The bias current I1 has a value corresponding to the sum of the current flowing through the transistor T3 and the current flowing through the transistor T13. In other words, the current source 101b generates a bias current I2 having a value corresponding to the current obtained by subtracting the current flowing through the transistor T10 from the current I2. C Flush.

[0193] When both the signals S11b and S12b are at the L level, the current source 101b supplies the current I a Current I b1 and current I b2 The current obtained by adding these is the bias current I c In this case, the bias current I c The current I1 has a value corresponding to the sum of the current flowing through the transistor T3 and the current flowing through the transistors T10 and T13. In other words, the current source 101b generates a bias current I2 whose value corresponds to the current value of the current I1. C Flush.

[0194] That is, the current source 101b generates a bias current I C The current value of the resistor R is changed in four stages, and the bias current I C Flush.

[0195] == Fifth Embodiment == 15 is a diagram illustrating an overview of an integrated circuit 1c according to a fifth embodiment. The integrated circuit 1c is a circuit that drives a load L based on a drive signal Sin from a microcomputer 4. The integrated circuit 1c according to the fifth embodiment includes terminals TE1 to TE4, a logic circuit 7, a gate driver 10, transistors T1 to T4 and T20, an operational amplifier OP, a bias current source 50c including a bias voltage source 100 and a current source 101c, and an overcurrent detection circuit 102. Since the configuration and operation are the same as those of the third embodiment shown in FIG. 10 except for the current source 101c, a description thereof will be omitted.

[0196] 16 is a diagram illustrating a portion of an integrated circuit 1c according to the fifth embodiment. The diagram illustrates a portion of the integrated circuit 1c according to the fifth embodiment, a first subtraction circuit 301, and a first adder circuit 302, and includes T20, a bias voltage source 100, a current source 101b, inverters 14 and 24, the first subtraction circuit 301, and the first adder circuit 302. The bias voltage source 100 has the same configuration as that shown in FIG. 12. The first subtraction circuit 301 has the same configuration as that shown in FIG. 14.

[0197] [First adder circuit 302] The first adder circuit 302 includes transistors T26, and T30 to 32. The configurations and operations of the transistors T26, and T30 to 32 are the same as those in the second embodiment, and therefore will not be described.

[0198] [Bias current source 50c] The bias current source 50c includes a bias voltage source 100 and a current source 101c, and generates a bias current I according to the current flowing through the transistor T20. C Flush.

[0199] [Current source 101c] As shown in FIG. 16, the current source 101c generates a bias current I1 according to the current I1 based on a bias voltage Vo according to the current I5 flowing from the transistor T20. CThe current source 101c includes transistors T400, T411 to T414, and T421 to T424. In FIG. 16, the value "2.5" assigned to transistor T400 is a relative value when the current flowing through transistor T3 is set to 100. Furthermore, the values ​​"2.5," "5.0," "7.5," and "10" assigned to transistors T411, T412, T413, and T414, respectively, are relative values ​​when the current flowing through transistor T400 is set to 100.

[0200] [Transistor T413] In this embodiment, the transistor T413 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0201] The transistor T413 has a source electrode connected to the terminal TE1 and a gate electrode When the bias voltage Vo is applied, the current I corresponding to the current flowing through the transistor T30 b3 In this embodiment, a current I b3 The current value of is 1 / 40 of the current value of the current flowing through the transistor T30.

[0202] [Transistor T414] In this embodiment, the transistor T414 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0203] The transistor T414 has a source electrode connected to the terminal TE1 and a gate electrode When a bias voltage Vo is applied, a current I corresponding to the current value flowing through the transistor T31 is generated. b4 In this embodiment, a current I b4 The current value of is 1 / 40 of the current value of the current flowing through the transistor T31.

[0204] [Transistor T423] In this embodiment, the transistor T423 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0205] The transistor T423 is provided between the transistor T413 and the overcurrent detection circuit 102, and a voltage corresponding to the signal S21 is applied to the gate electrode of the transistor T423. The drain electrode of the transistor T423 is connected to the drain electrode of the transistor T400. The transistor T423 is turned off when the signal S21 is at H level, and turned on when the signal S21 is at L level.

[0206] [Transistor T424] In this embodiment, the transistor T424 is a p-channel MOS transistor, and has a source electrode, a gate electrode, and a drain electrode.

[0207] The transistor T424 is provided between the transistor T414 and the overcurrent detection circuit 102, and a voltage corresponding to the signal S22 is applied to the gate electrode of the transistor T424. The drain electrode of the transistor T424 is connected to the drain electrode of the transistor T400. The transistor T424 is turned off when the signal S22 is at an H level, and turned on when the signal S22 is at an L level.

[0208] The current source 101c operates in the same manner as the current source 101b based on the signals S11b and S12b, and further operates to generate a bias current I C Therefore, in the following, it is assumed that predetermined signals S11b and S12b are input, and it will be described how the current source 101c controls the bias current I according to the levels of the signals S21 and S22. c This explains how to change the

[0209] When the signals S21 and S22 are both at the H level, the current source 101c generates a current based on the signals S11b and S12b as a current I a The bias current I added to c Dispense as.

[0210] When the signal S21 is at an L level and the signal S22 is at an H level, the current source 101c generates a current based on the signals S11b and S12b and a current I b3current I a The current added to this is the bias current I c In this case, the current source 101c generates a current I based on the signals S11b and S12b and a current having a value corresponding to the value of the current flowing through the transistor T30. a The bias current I c Flush.

[0211] When the signal S21 is at the H level and the signal S22 is at the L level, the current source 101c generates a current based on the signals S11b and S12b and a current I b4 current I a The current added to this is the bias current I c In this case, the current source 101c generates a current I based on the signals S11b and S12b and a current having a value corresponding to the value of the current flowing through the transistor T31. a The bias current I c Flush.

[0212] When the signals S21 and S22 are both at the L level, the current source 101c generates a current based on the signals S11b and S12b and a current I b3 ,I b4 The current obtained by adding this to the current Ia is the bias current I c In this case, the current source 101c generates a bias current I that is equal to the current Ia plus a current based on the signals S11b and S12b and a current that corresponds to the current values ​​of the currents flowing through the transistors T30 and T31. c Flush.

[0213] That is, in the same manner as described with reference to FIG. 5, the current source 101c generates a bias current I C The current value of the resistor R is changed in 10 steps, and the bias current I C Flush.

[0214] ==Summary== The integrated circuits 1, 2, and 3 of the embodiments described above include a transistor T1 having a drain electrode to which a predetermined voltage is applied, a gate electrode to which a control voltage is applied, and a source electrode, and flowing a current I1 to a load; a transistor T2 having a drain electrode to which a predetermined voltage is applied, a gate electrode to which a control voltage is applied, and a source electrode, and flowing a current I2 corresponding to the current I1; a transistor T3 connected between the source electrode of the transistor T2 and a predetermined line L1; an operational amplifier OP that controls the transistor T3 so that the voltage of the source electrode of the transistor T1 and the voltage of the source electrode of the transistor T2 match; and a subtraction circuit 12 or 22 that flows a part of the current I2, a current I4, to ground when a first condition is satisfied.

[0215] This configuration can prevent the ratio of the drive current of the transistor T1 to the current of the transistor T2 from deviating from a desired value.

[0216] In the integrated circuits 1, 2, and 3, the subtraction circuits 12 and 22 include a transistor T10 having a source electrode connected to the source electrode of the transistor T2, a gate electrode to which the output voltage of the operational amplifier OP is applied, and a drain electrode, and a transistor T11 located between the drain electrode of the transistor T10 and ground and turned on when a first condition is satisfied. With this configuration, the subtraction can be performed by turning on the transistor T11 only when subtraction is necessary.

[0217] The integrated circuit 1 further includes an adder circuit 13 that adds a current I6 to the current flowing through the predetermined line L1 via the transistor T3 when the second condition is satisfied. With this configuration, addition can be performed when the current I2 is smaller than the ideal current due to manufacturing variations.

[0218] In the integrated circuits 1, 2, and 3, the subtraction circuits 12 and 22 include a transistor T12 located between the transistor T10 and a predetermined line L1. This configuration makes it easier to adjust the absolute values ​​of the correction amounts in subtraction and addition to the same value.

[0219] In the integrated circuits 1, 2, and 3, the subtraction circuits 12 and 22 include an inverter 14 that complementarily turns on and off the transistors T11 and T12. With this configuration, the amount of correction due to subtraction can be set to zero when no subtraction is performed, and can be set to a desired amount when subtraction is performed.

[0220] In the integrated circuits 1, 2, and 3, the adder circuits 13 and 23 include a transistor T20 having a source electrode connected to the source electrode of the transistor T2, a gate electrode to which the output voltage of the operational amplifier OP is applied, and a drain electrode, a transistor T25 that generates a current corresponding to the current flowing through the transistor T20, and a transistor T26 that is located between the transistor T25 and a predetermined line L1 and turns on when a second condition is satisfied. With this configuration, addition can be performed by turning on the transistor T26 only when addition is necessary.

[0221] In the above integrated circuit, the current I4 may be different from the current I6. With this configuration, it is possible to perform subtraction or addition in even more stages.

[0222] The integrated circuits 1, 2, and 3 of the embodiments include a transistor T1 having a drain electrode to which a predetermined voltage is applied, a gate electrode to which a control voltage is applied, and a source electrode, and flowing a current I1 to a load L; a transistor T2 having a drain electrode to which a predetermined voltage is applied, a gate electrode to which a control voltage is applied, and a source electrode, and flowing a current I2 corresponding to the current I1; a transistor T3 connected between the source electrode of the transistor T2 and a predetermined line L1; an operational amplifier OP that controls the transistor T3 so that the voltage of the source electrode of the transistor T1 and the voltage of the source electrode of the transistor T2 match; and an adder circuit that adds a current I6 to the current flowing to the predetermined line L1 via the transistor T3 when a second condition is satisfied.

[0223] This configuration can prevent the ratio of the drive current of the transistor T1 to the current of the transistor T2 from deviating from a desired value.

[0224] The integrated circuits 1a, 1b, and 1c of the embodiments each include a transistor T1 having a drain electrode to which a predetermined voltage is applied, a gate electrode to which a control voltage is applied, and a source electrode, and flowing a current I1 through a load L; a transistor T2 having a drain electrode to which a predetermined voltage is applied, a gate electrode to which a control voltage is applied, and a source electrode, and flowing a current I2 corresponding to the current I1; a transistor T3 connected between the source electrode of the transistor T2 and a predetermined line L1; an operational amplifier OP that controls the transistors T3 and T20 so that the voltage of the source electrode of the transistor T1 and the voltage of the source electrode of the transistor T2 are the same; a transistor T20 connected to the source electrode of the transistor T2 and controlled together with the transistor T3 by the operational amplifier OP; a bias current source that flows a bias current corresponding to the current flowing through the transistor T20; and an overcurrent detection circuit 102 that detects whether the current I1 is an overcurrent based on the current of the bias current source.

[0225] With this configuration, it is possible to keep the current value for detecting whether the current I1 is an overcurrent constant.

[0226] The integrated circuits 1b and 1c each include a first subtraction circuit 301 that, when the first condition is satisfied, flows a current I4, which is a part of the current I2, to ground in response to the current flowing through the transistor T3. When the first condition is satisfied, the bias current source C Decrease the current value.

[0227] With this configuration, even if the ratio of the current of transistor T2 to the drive current of transistor T1 becomes large, it is possible to detect whether current I1 is an overcurrent or not using bias current Ic according to current I1, thereby improving detection accuracy.

[0228] The integrated circuit 1c includes a first adder circuit 302 that adds a current corresponding to the current flowing through the transistor T20 to the current I2 when the second condition is satisfied, and the bias current source generates a bias current I C Increase the

[0229] With this configuration, even if the ratio of the current of transistor T2 to the drive current of transistor T1 becomes small, it is possible to detect whether current I1 is an overcurrent or not using bias current Ic according to current I1, thereby improving detection accuracy.

[0230] The integrated circuit 1a includes a first adder circuit 300 that adds a current corresponding to the current flowing through the transistor T20 to the current I2 when the second condition is satisfied, and the bias current source generates a bias current I C Increase the

[0231] With this configuration, even if the ratio of the current of transistor T2 to the drive current of transistor T1 becomes small, it is possible to detect whether current I1 is an overcurrent or not using bias current Ic according to current I1, thereby improving detection accuracy.

[0232] In the integrated circuits 1a, 1b, and 1c, the overcurrent detection circuit 102 is provided between a bias current source and the ground, and supplies a bias current I C The circuit includes a resistor R1 through which current I1 flows, a reference voltage output circuit 200 that outputs a reference voltage for detecting whether or not the current I1 is an overcurrent, and a comparison circuit 201 that compares the voltage generated across the resistor R1 with the reference voltage to detect whether or not the current I1 is an overcurrent.

[0233] With this configuration, the bias current I C By detecting whether the current I1 is an overcurrent using the above, the influence of the positive temperature characteristic of the on-resistance of the transistor T1 is eliminated, and the current value at which the current I1 flowing through the transistor T1 is detected as an overcurrent becomes constant. [Explanation of symbols]

[0234] Integrated Circuits: 1, 2, 3 Gate drivers: 10 Correction circuit: 11 Subtraction circuit: 12, 22 Addition circuit: 13, 23 Inverter: 14, 24 Microcontroller: 4 Transistors: T1, T2, T3, T4, T10, T11, T12, T13, T14, T15, T20, T21, T22, T23, T24, T25, T26, T30, T31, T32, T40, T41, T400, T410, T411, T412, T413, T414, T420, T421, T422, T423, T424 Bias current sources: 50a, 50b, 50c Bias voltage source: 100 Current source: 101a, 101b, 101c Overcurrent detection circuit: 102 Resistor: R1 Reference voltage circuit: 200 Comparison circuit: 201 First adder circuit: 300, 302 First subtraction circuit: 301

Claims

1. a first transistor having a high potential side electrode to which a predetermined voltage is applied, a control electrode to which a control voltage is applied, and a low potential side electrode, and causing a first current to flow through a load; a second transistor having a high potential side electrode to which the predetermined voltage is applied, a control electrode to which the control voltage is applied, and a low potential side electrode, and passing a second current corresponding to the first current; a third transistor connected between the low potential side electrode of the second transistor and a predetermined line; an operational amplifier that controls the third transistor so that a voltage of the low potential side electrode of the first transistor and a voltage of the low potential side electrode of the second transistor are equal to each other; a subtraction circuit that causes a third current that is a portion of the second current to flow to ground when a first condition is satisfied; 1. An integrated circuit comprising:

2. 10. The integrated circuit of claim 1, The subtraction circuit a fourth transistor having a high potential side electrode connected to the low potential side electrode of the second transistor, a control electrode to which the output voltage of the operational amplifier is applied, and a low potential side electrode; a first switch located between the low potential side electrode of the fourth transistor and ground, the first switch being turned on when the first condition is satisfied; Integrated circuit.

3. 3. An integrated circuit according to claim 2, The subtraction circuit a second switch located between the fourth transistor and the predetermined line; Integrated circuit.

4. 4. An integrated circuit according to claim 3, The subtraction circuit a switch control circuit that turns on and off the first and second switches in a complementary manner; Integrated circuit.

5. 10. The integrated circuit of claim 1, an adder circuit that adds a fourth current to the second current if a second condition is satisfied; The integrated circuit further comprises:

6. 6. An integrated circuit according to claim 5, The adding circuit a fifth transistor having a high potential side electrode connected to the low potential side electrode of the second transistor, a control electrode to which the output voltage of the operational amplifier is applied, and a low potential side electrode; a sixth transistor that generates a current corresponding to the current flowing through the fifth transistor; a third switch located between the sixth transistor and the predetermined line, the third switch being turned on when the second condition is satisfied; Integrated circuit.

7. 6. An integrated circuit according to claim 5, the third current is different from the fourth current; Integrated circuit.

8. 3. An integrated circuit according to claim 2, an adder circuit that adds a fourth current to the second current if a second condition is satisfied; The integrated circuit further comprises:

9. 9. An integrated circuit according to claim 8, The adding circuit a fifth transistor having a high potential side electrode connected to the low potential side electrode of the second transistor, a control electrode to which the output voltage of the operational amplifier is applied, and a low potential side electrode; a sixth transistor that generates a current corresponding to the current flowing through the fifth transistor; a third switch located between the sixth transistor and the predetermined line, the third switch being turned on when the second condition is satisfied; Integrated circuit.

10. 10. The integrated circuit of claim 9, the third current is different from the fourth current; Integrated circuit.

11. a first transistor having a high potential side electrode to which a predetermined voltage is applied, a control electrode to which a control voltage is applied, and a low potential side electrode, and causing a first current to flow through a load; a second transistor having a high potential side electrode to which the predetermined voltage is applied, a control electrode to which the control voltage is applied, and a low potential side electrode, and passing a second current corresponding to the first current; a third transistor connected between the low potential side electrode of the second transistor and a predetermined line; an operational amplifier that controls the third transistor so that a voltage of the low potential side electrode of the first transistor and a voltage of the low potential side electrode of the second transistor are equal to each other; an adder circuit that adds a fourth current to the second current when a second condition is satisfied; 1. An integrated circuit comprising:

12. 12. The integrated circuit of claim 11, The adding circuit a fifth transistor having a high potential side electrode connected to the low potential side electrode of the second transistor, a control electrode to which the output voltage of the operational amplifier is applied, and a low potential side electrode; a sixth transistor that generates a current corresponding to the current flowing through the fifth transistor; a third switch located between the sixth transistor and the predetermined line, the third switch being turned on when the second condition is satisfied; Integrated circuit.

13. a first transistor having a high potential side electrode to which a predetermined voltage is applied, a control electrode to which a control voltage is applied, and a low potential side electrode, and causing a first current to flow through a load; a second transistor having a high potential side electrode to which the predetermined voltage is applied, a control electrode to which the control voltage is applied, and a low potential side electrode, and passing a second current corresponding to the first current; a third transistor connected between the low potential side electrode of the second transistor and a predetermined line; an operational amplifier that controls the third transistor so that a voltage of the low potential side electrode of the first transistor and a voltage of the low potential side electrode of the second transistor are equal to each other; a transistor connected to the low potential side electrode of the second transistor and controlled together with the third transistor by the operational amplifier; a bias current source that supplies a bias current corresponding to the current flowing through the transistor; an overcurrent detection circuit that detects whether the first current is an overcurrent based on the current of the bias current source; Equipped with Integrated circuit.

14. 14. An integrated circuit according to claim 13, comprising: a first subtraction circuit that, when a first condition is satisfied, flows a third current, which is a part of the second current, to ground in response to a current flowing through the third transistor; Equipped with The bias current source If the first condition is satisfied, the current value of the bias current is decreased. Integrated circuit.

15. 15. An integrated circuit according to claim 14, comprising: a first adder circuit that adds a fourth current corresponding to a current flowing through the transistor to the second current when a second condition is satisfied; Equipped with The bias current source If the second condition is met, increasing the bias current. Integrated circuit.

16. 14. An integrated circuit according to claim 13, comprising: a first adder circuit that adds a fourth current corresponding to a current flowing through the transistor to the second current when a second condition is satisfied; Equipped with The bias current source If the second condition is met, increasing the bias current. Integrated circuit.

17. An integrated circuit according to any one of claims 13 to 16, The overcurrent detection circuit a resistor provided between the bias current source and ground, through which the bias current flows; a reference voltage output circuit that outputs a reference voltage for detecting whether the first current is an overcurrent; a comparison circuit that compares the voltage generated across the resistor with the reference voltage to detect whether the first current is an overcurrent; An integrated circuit comprising:

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