Semiconductor device

Abstract

To provide a transistor which can suppress the occurrence of a geometric defect in a semiconductor device in the case of forming a source electrode layer and a drain electrode layer on an oxide semiconductor film in contact with each other, and to form source and drain electrode layers each having a sectional shape which is unlikely to cause a stage cut even if a gate insulative film formed on the source and drain electrode layers or the oxide semiconductor film is small in film thickness.SOLUTION: In a semiconductor device, an exposed portion of an oxide semiconductor film is reduced in film thickness by the steps of: forming the oxide semiconductor film having a crystal structure on an insulation surface; forming an electrode layer on a part of the oxide semiconductor film; and exposing to dilute hydrofluoric acid of a concentration of over 0.0001% up to 0.25%.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A transistor or the like is manufactured using an oxide semiconductor film in the channel formation region, and the transistor is applied to a display device. For example, zinc oxide (ZnO) is used as the oxide semiconductor film. Transistors and InGaO3 (ZnO) m These transistors include A transistor using the oxide semiconductor film is formed over a light-transmitting substrate, and an image display device is manufactured using the transistor. Patent Documents 1 and 2 disclose techniques used for switching elements in devices.

[0004] Patent Document 3 also describes a method for fabricating a semiconductor device comprising a source electrode and a drain electrode in contact with an oxide semiconductor layer, and an oxide semiconductor layer. a gate electrode overlapping the semiconductor layer, and a gate electrode provided between the oxide semiconductor layer and the gate electrode; an insulating layer, and the source electrode and the drain electrode are formed on the first conductive layer and on the edge of the first conductive layer. A transistor structure having a second conductive layer having a region extending in a channel length direction from the It has been disclosed.

[0005] Furthermore, Patent Document 4 discloses a structure in which gate electrodes are formed above and below an oxide semiconductor layer. It has been done. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-171721 [Patent Document 4] Japanese Patent Application Laid-Open No. 2011-103458 Summary of the Invention [Problem to be solved by the invention]

[0007] Dual gate structures in which gate electrodes are formed above and below the oxide semiconductor film, and bottom gate structures When a transistor having a top-gate structure or a bottom-gate structure is manufactured, In some cases, an electrode layer is formed by using a metal oxide film, and a part of the surface of the oxide semiconductor film is exposed. It is preferable to perform etching treatment that can ensure a sufficient selectivity between the electrode layer and the oxide semiconductor film.

[0008] However, it is difficult to perform an etching process that can achieve a sufficient selectivity between the electrode layer and the oxide semiconductor film. In particular, when the oxide semiconductor film is thin, the oxide semiconductor film is removed during etching of the electrode layer. In addition, depending on the etching conditions, the shape of the electrode layer may change. This may cause defects in the semiconductor film or the formation of holes in the oxide semiconductor film. Poor shape leads to deterioration of electrical characteristics.

[0009] In the case where the source electrode layer and the drain electrode layer are formed on and in contact with the oxide semiconductor film, One of the objectives of the present invention is to provide a method for manufacturing a transistor that suppresses the occurrence of defects in the shape of a semiconductor device. do.

[0010] Further, a source electrode layer and a drain electrode layer are formed over the oxide semiconductor film. A transistor structure that alleviates electric field concentration that may occur at the edge of the drain electrode layer One of our goals is to provide

[0011] In addition, in a semiconductor device including a transistor in which an oxide semiconductor film is used for a channel formation region, One of the objectives is to provide stable electrical characteristics and improve reliability.

[0012] In addition, the thickness of the gate insulating film formed on the source electrode layer and the drain electrode layer and the oxide semiconductor The source electrode layer and the drain electrode layer have a cross-sectional shape that is unlikely to cause step discontinuities even when the film thickness is small. One of the objectives is to form a pole layer. [Means for solving the problem]

[0013] The base film is an oxide semiconductor film having a crystalline structure, and after forming a single-layer metal film on the base film, A resist mask is formed and etching is performed multiple times to form an electrode with a cross-sectional structure having a protruding portion. Forms poles.

[0014] Specifically, a resist mask is formed on the metal film, and about half of the thickness of the metal film is removed to expose the portion. The first etching is carried out to thin the resist film, and the resist mask is then ashed. After the area of ​​the resist mask is reduced, the second resist mask is formed using the reduced area. Etching is performed to form a single layer metal film having protrusions.

[0015] In addition, when the base film is an oxide semiconductor film having a crystalline structure, When processing a single layer metal film that contacts a conductive film, or after that, wafer processing using the metal film as a mask Hot etching is performed to form a thin region (i.e., a region overlapping with the metal film) in the oxide semiconductor film. A region (thinner than the metal film and not overlapping with the metal film) may be formed, and the thin region may be used as a channel. A transistor can be fabricated in the formation region.

[0016] The thin region of the oxide semiconductor film that will become the channel formation region is etched by wet etching using diluted hydrofluoric acid. The diluted hydrofluoric acid is preferably at a concentration of 0.25% or less, and even more preferably at a concentration of 0.25% or less. It is recommended to use a very low concentration solution, such as 0.0025%, diluted with water. By using diluted hydrofluoric acid, it is possible to obtain an oxide semiconductor film having a crystalline structure compared to an oxide semiconductor film having an amorphous structure. The etching rate of the semiconductor film can be slowed down by about three times, and the etching progress The situation can also be different. By using diluted hydrofluoric acid, anisotropic etching can be performed, and the electrode layer and the oxide semiconductor The cross-sectional shape of the conductive film can be improved. In contrast, when such diluted hydrofluoric acid is used, isotropic etching occurs.

[0017] One embodiment of the invention disclosed in this specification is an oxide semiconductor having a crystalline structure on an insulating surface. A film is formed, an electrode layer is formed on a part of the oxide semiconductor film in contact with the film, and a concentration of 0.0001% or less is formed. The thickness of the exposed part of the oxide semiconductor film is reduced by exposing it to diluted hydrofluoric acid with a concentration of 0.25% or less. The present invention relates to a method for manufacturing a semiconductor device.

[0018] In addition, when a source electrode layer and a drain electrode layer are formed over an oxide semiconductor film, the above procedure is Thus, a source electrode layer and a drain electrode layer having protrusions extending in the channel length direction are formed. A gate electrode can be formed on the source electrode layer and the drain electrode layer having such a cross-sectional shape. When a gate insulating film is formed, a step-cut is not formed even if the thickness of the gate insulating film or the oxide semiconductor film is small. Furthermore, a single layer of metal film is used to form a protrusion extending in the channel length direction. By forming the source electrode layer and the drain electrode layer, it is possible to improve the This simplifies the manufacturing process.

[0019] In addition, the protrusion of the source electrode layer (or the protrusion of the drain electrode layer) is formed on the oxide semiconductor film. This has the effect of alleviating the electric field concentration that may occur at the overlapping edges, improving the electrical characteristics of the transistor. This also contributes to improved performance and reliability.

[0020] Gate electrode layers are disposed above and below the oxide semiconductor film, and one of the gate electrodes is By setting the potential of the electrode layer to GND, the threshold voltage of the transistor becomes more positive, and the The transistor may be a mary-off transistor.

[0021] In addition, the gate electrode layer, which has a potential of GND, shields the external electric field. It also has the function of preventing the transistor from being affected (especially the electrostatic shielding function against static electricity). The shielding function of the gate electrode layer, which has a ground potential, prevents the device from being affected by external electric fields such as static electricity. This can prevent the electrical characteristics of the transistor from fluctuating.

[0022] After the source electrode layer and the drain electrode layer are formed by the above-mentioned manufacturing method, Then, wet etching is performed to form a thin region in the oxide semiconductor film, and a channel formation region is formed. By doing so, the performance of the transistor can be improved. This can reduce the electric field concentration that may occur between the insulating layer and the insulating electrode layer.

[0023] The oxide semiconductor film is wet-etched using diluted hydrofluoric acid, thereby forming a channel formation region. The film thickness of the thin region can be controlled more accurately, and the channel formation region (thin region) ) can reduce pollutants in the vicinity.

[0024] The semiconductor device further includes a source electrode layer and a drain electrode layer having protrusions extending in the channel length direction. Therefore, when a gate insulating film is formed on the source electrode layer and the drain electrode layer, the gate insulating film Even if the thickness of the insulating film or oxide semiconductor film is small, step breaks are unlikely to occur. The source electrode layer and the drain electrode layer have protrusions extending in the channel length direction using a film. By forming the above, the process can be simplified.

[0025] In addition, in a dual gate structure in which gate electrodes are formed above and below an oxide semiconductor film, The conductive layer functioning as a gate electrode located under the oxide semiconductor film is buried in the oxide insulating film. The oxide insulating film is provided so as to be submerged, and the vicinity of the lower surface of the oxide insulating film and the conductive layer In the area where the oxide insulating film is present, the amount of oxygen in the vicinity of the conductive layer exceeds the stoichiometric composition of the oxide insulating film. There is an oxygen excess region present.

[0026] The oxygen-excess region is formed by forming a conductive layer and an oxide insulating film on the conductive layer, and then the shape of the conductive layer is reversed. Formed by performing oxygen introduction treatment (oxygen doping treatment) on an oxide insulating film having a convex portion on the upper surface. After forming the oxygen-excess region, the oxide insulating film is subjected to a planarization process to remove the protrusions on the top surface. The planarization process uses chemical mechanical polishing.

[0027] By the planarization treatment, the oxide insulating film on the conductive layer is selectively removed and thinned. The distance between the oxygen-excess region and the top surface of the oxide insulating film is also shortened. In the region where the conductive layer does not exist, the oxide insulating film is hardly removed, and in the region where the oxygen is excessive, Therefore, the oxygen-excess region in the oxide insulating film is The insulating film is formed at a shallower position in the region where the conductive layer exists, and at a shallower position in the other region (conductive layer). In the region where no conductive layer is present, the electrode is provided at a deep position.

[0028] Therefore, the oxide semiconductor film (at least the channel formation region) is provided. In the oxide insulating film, an oxygen-excess region can be provided in the vicinity of the oxide semiconductor film. Therefore, oxygen can be efficiently supplied from the oxygen-excess region to the oxide semiconductor film. The supply of elements can also be promoted by carrying out a heat treatment.

[0029] Therefore, in the semiconductor device, oxygen vacancies in the oxide semiconductor film and at the interface can be efficiently compensated for. This makes it possible to do so.

[0030] The oxide semiconductor film can be a stack of oxide semiconductor films having different compositions.

[0031] For example, when two oxide semiconductor films are stacked, the ratio is In:Ga:Zn=3:1:2 (=1 / In-Ga-Zn system oxide film formed using a target with an atomic ratio of 2:1 / 6:1 / 3 The atomic ratio of In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) was The laminated film is made of In-Ga-Zn oxide films deposited using a target. can be done.

[0032] In this case, the oxide semiconductor film having a thin region has a composition of In:Ga:Zn=1:1:1 It is preferable to use a target having the atomic ratio of In—Ga—Zn based oxide film.

[0033] For example, when a three-layer oxide semiconductor film is stacked, the ratio of In:Ga:Zn=1:3:2 ( In-Ga-Z films are formed using a target with an atomic ratio of 1 / 6:1 / 2:1 / 3. Deposition on an n-type oxide film using a target with an atomic ratio of In:Ga:Zn=3:1:2 In-Ga-Zn oxide films are stacked, with an atomic ratio of In:Ga:Zn=3:1:2. On the In-Ga-Zn oxide film formed using the target of In:Ga:Zn= The In-Ga-Zn oxide film is deposited using a target with an atomic ratio of 1:1:1. A laminated film in which the layers are stacked can be used.

[0034] In this case, the oxide semiconductor film having a thin region has a composition of In:Ga:Zn=1:1:1 It is preferable that the In-Ga-Zn oxide film is formed using a target having the following atomic ratio: Desirable.

[0035] For example, when a three-layer oxide semiconductor film is stacked, the composition is In:Ga:Zn=1:1:1. On the In-Ga-Zn oxide film formed using a target with the atomic ratio of In:Ga In-Ga-Zn oxide film formed using a target with an atomic ratio of Zn=3:1:2 The film was deposited using a target with an atomic ratio of In:Ga:Zn=3:1:2. On the In-Ga-Zn oxide film, a target with an atomic ratio of In:Ga:Zn=1:3:2 was deposited. It is possible to use a laminated film in which In-Ga-Zn oxide films are deposited using a Cut.

[0036] In this case, the oxide semiconductor film having a thin region has a composition of In:Ga:Zn=1:3:2 It is preferable that the In-Ga-Zn oxide film is formed using a target having the following atomic ratio: It's nice.

[0037] In the case where a single-layer oxide semiconductor film is used, an oxide semiconductor film having a thin region and a thin region are used. The oxide semiconductor film is left on the surface of the base film so that the surface of the base film in contact with the oxide semiconductor film is not exposed. It is preferable to do so.

[0038] When stacked oxide semiconductor films having different compositions are used, an oxide semiconductor film having a thin film thickness is formed on the stacked oxide semiconductor films. The oxide semiconductor film is left so that the surface of the oxide semiconductor film in contact with the oxide semiconductor film is not exposed. It is preferable to do so.

[0039] In the above structure, an insulating layer may be provided to overlap the source electrode layer and the drain electrode layer. The insulating layer may have a gate insulating film on it. The parasitic capacitance formed between the gate electrode layer and the source electrode layer and the parasitic capacitance formed between the gate electrode layer and the drain electrode layer This insulating layer reduces the parasitic capacitance formed between the silicon oxide film and the silicon nitride film. It is formed using a silicon nitride film, etc., and is used when etching the gate insulating film or the gate electrode layer. The source electrode layer and the drain electrode layer are protected during switching.

[0040] In addition, a gallium oxide film (GaO X Also, X is a natural number. (Not limited to, including non-natural numbers.) Ga2O3 (Gd2O3) film, high gallium content and gallium oxide films such as insulating In-Ga-Zn oxide films with a low indium content. It is preferable to use an insulating film containing gallium. In addition, an insulating film containing gallium does not contain oxygen in the film. It is preferable to include a large amount of gallium in the insulating film. The film formation conditions are set, or oxygen doping treatment is performed after the formation of the insulating film containing gallium.

[0041] "Oxygen doping" means the doping of oxygen (at least oxygen radicals, oxygen atoms, oxygen molecules, and oxygen atoms). ions, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions The term "bulk" refers to the addition of oxygen to the surface of the thin film. The term "oxygen doping" is used to clarify that the doping is not limited to the thin film but is done inside the thin film. This includes "oxygen plasma doping," which adds plasma-formed oxygen to the bulk.

[0042] The oxygen doping treatment can be performed using a gas containing oxygen. Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen doping treatment, a rare gas may be contained in the oxygen-containing gas.

[0043] Depending on the treatment conditions, oxygen doping treatment can damage not only the film directly exposed to the oxygen doping treatment but also the The underlying film can also be doped with oxygen. When a gate insulating film made of a lithium film is formed and oxygen doped, In addition, oxygen can be contained in the oxide semiconductor film.

[0044] The oxide semiconductor film preferably has a crystalline structure. The conductive film can be a single crystal film, a microcrystalline film, a polycrystalline film (also called polycrystal), or a CAAC film. -OS(C Axis Aligned Crystalline Oxide Sem The film is an ion conducting film.

[0045] In addition, there are areas with a small film thickness (areas that do not overlap with the metal film) and areas with a large film thickness (areas that overlap with the metal film). a boundary region between the oxide semiconductor film and the oxide semiconductor film has a cross-sectional shape rising in the film thickness direction; The present invention also provides a semiconductor device having the same, and the semiconductor device has a structure including a conductive layer and an oxide insulating layer on the conductive layer. a first insulating film on the oxide insulating film, and a channel forming region in contact with the first insulating film. a source electrode on the oxide semiconductor film and electrically connected to the oxide semiconductor film; a first electrode layer and a second electrode layer on the oxide semiconductor film, the source electrode layer, and the drain electrode layer; The oxide semiconductor film has an insulating film of 2, and the oxide semiconductor film has a thickness between a thin region and a thick region. The semiconductor device has a cross-sectional shape in which the boundary region rises in the film thickness direction. The oxide semiconductor film is particularly preferably a CAAC-OS film. By using this, the thin region of the oxide semiconductor film (the region that does not overlap with the metal film, i.e., the channel The thick region (the region overlapping with the metal film, i.e., the source electrode layer or the drain electrode The boundary area between the layer and the substrate (the area in contact with the substrate) has a cross-sectional shape that rises in the film thickness direction, and Specifically, the cross-sectional shape formed by the surface of the boundary region and the surface of the oxide insulating film is inclined in the direction of the surface of the oxide insulating film. The angle can be greater than 0° and less than 90°, preferably greater than 20° and less than 70°. In the boundary region, the film thickness increases continuously from the boundary with the thin region to form a thick region. Therefore, the cross section of the oxide semiconductor film formed on the oxide semiconductor film is The coverage of the gate insulating film and the gate electrode layer can be improved. Even if the film thickness is small, step disconnection can be prevented.

[0046] By thinning the channel formation region of the CAAC-OS film, the switching It is possible to prevent deterioration of characteristics and improve electrical characteristics.

[0047] The crystals in the CAAC-OS film are sized to fit within a cube with sides of less than 100 nm. In addition, transmission electron microscope (TEM) The image observed under a microscope shows that the CAAC-OS film contains The boundary between the crystalline regions is not clear. Therefore, the CAAC-OS film has a grain boundary. Therefore, the decrease in electron mobility caused by the grain boundaries is suppressed.

[0048] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The direction is parallel to the normal vector of the hole or surface, and perpendicular to the ab plane. When viewed from the side, the metal atoms are arranged in a triangular or hexagonal shape, and when viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in a triangular or hexagonal shape. The metal atoms and oxygen atoms are arranged in layers, or in layers. The directions of the a-axis and the b-axis may be different for each of the above. In this case, the angle may be in the range of 80° to 100°, preferably 85° to 95°. In addition, when simply describing it as parallel, it means that it is between -10° and 10°, preferably between -5 This also includes the range of 10° to 5°.

[0049] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystals of the crystal part in the impurity-doped region are Sexuality may also decrease.

[0050] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film is oriented parallel to the normal vector of the film or surface. Depending on the shape (cross-sectional shape of the surface to be formed or cross-sectional shape of the surface), they may face in different directions. In addition, the crystalline portion is formed by a crystallization process such as heat treatment during or after film formation. Therefore, the c-axis direction of the crystalline part is the same as that of the CAAC-OS film. The direction of the normal vector of the surface to be formed or the direction parallel to the normal vector of the surface Sea urchins line up.

[0051] In addition, in oxide semiconductors with crystalline parts such as CAAC-OS, defects in the bulk can be further reduced. By improving the surface flatness, the movement can be reduced more than that of an amorphous oxide semiconductor. To improve the flatness of the surface, it is necessary to deposit an oxide semiconductor on a flat surface. Specifically, it is preferable to form a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0 It is preferable to form it on the surface with a thickness of 0.3 nm or less, more preferably 0.1 nm or less.

[0052] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible light or ultraviolet light. Therefore, by using the oxide semiconductor film as a CAAC-OS film, This suppresses changes in the electrical characteristics of transistors caused by irradiation with visible light or ultraviolet light, resulting in highly reliable The semiconductor device may be a semiconductor device.

[0053] In addition, when the oxide semiconductor film is a CAAC-OS film, the first The insulating film and the second insulating film preferably have an amorphous structure. The first insulating film and the second insulating film are formed at a substrate temperature lower than the film formation temperature of the -OS film. Alternatively, a rare gas such as argon may be used as the sputtering gas to form the first insulating film and the second insulating film. The insulating film is then deposited.

[0054] The first insulating film containing gallium oxide is subjected to oxygen doping treatment to form an amorphous structure; and an oxygen-excess region in which oxygen exists in excess of the stoichiometric composition of the first insulating film containing gallium oxide; For example, in the case of a gallium oxide film, which can be represented by Ga2O3, the oxide The electron-rich region is GaO X (X>1.5). The first insulating film including the oxygen-excess region is The present invention provides an effective oxygen supply that prevents oxygen from being desorbed from an oxide semiconductor film and supplies oxygen to an oxide semiconductor film. It also functions as a supply layer.

[0055] The second insulating film containing gallium oxide is subjected to oxygen doping treatment to form an amorphous structure, and an oxygen-excess region in which oxygen exists in excess of the stoichiometric composition of the second insulating film containing gallium oxide; The second insulating film including the oxygen excess region may be formed from the oxide semiconductor film. It also functions as an effective oxygen supply layer that prevents oxygen desorption and supplies oxygen to the oxide semiconductor film. do.

[0056] A semiconductor film containing gallium as an oxide semiconductor film (for example, an In-Ga-Zn oxide film) The oxide semiconductor film is sandwiched between insulating films containing gallium (e.g., oxide When a gallium nitride film is used, the insulating films arranged above and below contain the same material as the oxide semiconductor film. Since the oxide semiconductor film contains the oxide material, the interface state of the oxide semiconductor film can be improved, and the oxide semiconductor film can be stabilized. In addition, the oxide semiconductor film can be sandwiched between two oxide films. By providing an insulating film made of gallium nitride, there is a risk of the oxide semiconductor film being affected from the outside. It acts to block the penetration of impurities such as nitrogen and metal elements by diffusion. Therefore, the oxide semiconductor film can be sandwiched between the oxide semiconductor layers or can be surrounded by the oxide semiconductor layers. By providing an insulating film made of gallium, the composition and It is possible to maintain a constant purity and realize a semiconductor device with stable electrical characteristics.

[0057] Note that in this specification, a region with a small thickness in an oxide semiconductor film is referred to as a channel formation region. The lower end of the source electrode layer extending in the channel length direction and the channel The distance between the lower end of the drain electrode layer extending in the channel length direction and the lower end of the drain electrode layer is defined as the channel length.

[0058] In this specification, the term "etching rate" (also referred to as "etching speed") means This refers to the amount of etching per minute in the direction of film thickness. The unit of " shall be indicated in nm / min.

[0059] In this specification, the term "contamination" refers to the deterioration of electrical characteristics of a transistor. This term is used to mean that variations in electrical characteristics and reliability may occur. . [Effects of the Invention]

[0060] After forming a source electrode layer and a drain electrode layer on and in contact with the oxide semiconductor film, Wet etching using acid reduces the occurrence of shape defects in semiconductor devices. Furthermore, by performing wet etching using diluted hydrofluoric acid, Cl, Al, A part of the surface of the oxide semiconductor film on which impurities such as C and B are attached is removed, and a thin film is formed. The region can be made to function as a channel forming region, thereby reducing variations in electrical characteristics. do.

[0061] In addition, even if the thickness of the thin region is 20 nm or less, the oxide semiconductor film can be prevented from disappearing. By thinning the oxide semiconductor film in the channel formation region, the transistor can be highly Performance can be improved.

[0062] The thickness of the gate insulating film is 20 nm or less, or the thickness of the oxide semiconductor film (thick region) is A source electrode layer and a drain electrode layer having a cross-sectional shape that is unlikely to cause a step discontinuity even when the cross-sectional shape is 30 nm or less An electrode layer can be formed.

[0063] In addition, insulating films containing gallium oxide are used above and below the oxide semiconductor film so as to sandwich the oxide semiconductor film. This provides stable electrical characteristics and improves reliability. [Brief explanation of the drawings]

[0064] [Figure 1] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating steps in one embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 6] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Figure 7] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 8] 1A and 1B are a cross-sectional view and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a perspective view illustrating one embodiment of a semiconductor device. [Figure 11] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 12] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 15] FIG. 10 is a cross-sectional view showing a comparison with one embodiment of the present invention. [Figure 16] FIG. 1 is a diagram showing a SIMS measurement result according to one embodiment of the present invention. [Figure 17] FIG. 1 is a diagram showing a SIMS measurement result according to one embodiment of the present invention. [Figure 18] FIG. 1 is a diagram showing a SIMS measurement result according to one embodiment of the present invention. [Figure 19] FIG. 1 is a diagram showing a SIMS measurement result according to one embodiment of the present invention. [Figure 20] FIG. 1 is a diagram showing a SIMS measurement result according to one embodiment of the present invention. [Figure 21] 1A and 1B are diagrams showing a sample according to one embodiment of the present invention and a comparative sample. [Figure 22] 1A to 1C illustrate electronic devices. [Figure 23] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0065] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0066] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, an example of a method for manufacturing a transistor including an oxide semiconductor film will be described. .

[0067] First, a conductive film is formed on a substrate 400 having an insulating surface by using a sputtering method, a vapor deposition method, or the like. The conductive film is then etched to form a conductive layer 491.

[0068] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as aluminoborosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. Also, silicon or silicon carbide substrates can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A substrate, an SOI substrate, or the like can also be used, and a semiconductor element is provided on such a substrate. may be used as the substrate 400.

[0069] The material of the conductive layer 491 is molybdenum, titanium, tantalum, tungsten, aluminum, Metallic materials such as copper, chromium, neodymium, scandium, etc., or alloy materials containing these as the main components The conductive layer 491 can be formed using an impurity element such as phosphorus. Semiconductor films, such as polycrystalline silicon films, and silicides, such as nickel silicide. The conductive layer 491 may have a single-layer structure or a stacked-layer structure.

[0070] The conductive layer 491 is made of indium tin oxide or indium oxide containing tungsten. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium oxide zinc oxide, silicon oxide Conductive materials such as indium tin oxide can also be used. It is also possible to use a laminated structure of the above-mentioned material and the above-mentioned metal material.

[0071] In addition, to realize a normally-off switching element, a voltage of 5 eV (electron volts) or more is required. Preferably, the conductive layer 491 is made of a material having a work function of 5.5 eV (electron volts) or more. It is preferable to use I to make the threshold voltage of the transistor positive. It has nN bonds and a specific resistance of 1×10 -4 ~1×10 -1 Ω·cm, preferably Resistivity is 1×10 -4 ~5×10 -2 A material having a resistivity of Ω·cm is used as the conductive layer 491. Examples of such materials include In-Ga-Zn oxide films containing nitrogen and I-type n-Sn-O film, In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Examples include In-O films containing elements and metal nitride films (InN, etc.).

[0072] Next, an oxide insulating film 480 is formed over the substrate 400 and the conductive layer 491 (see FIG. 1A). The oxide insulating film 480 has protrusions on its surface that reflect the shape of the conductive layer 491. .

[0073] The oxide insulating film 480 is formed by a plasma CVD method, a sputtering method, or the like. Silicon, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide The oxide can be formed using gallium oxide, zinc oxide, or a mixture of these materials. The insulating film 480 may be a single layer or a multilayer.

[0074] In this embodiment, the oxide insulating film 480 is formed by a silicon oxide film formed by a sputtering method. A silicon oxide nitride film is used. Good too.

[0075] Next, a process of introducing oxygen 431 into the oxide insulating film 480 having a projection on its surface ( The oxide insulating film 480 and the conductive layer 491 are doped with oxygen. As a result, the oxide insulating film 48 having the oxygen excess region 481 is formed. 4 is formed (see FIG. 1(B)). In the figure, the oxygen excess region 48 shown by the dotted line 1 shows a schematic representation of the distribution center of the introduced oxygen.

[0076] Oxygen 431 contains at least oxygen radicals, oxygen atoms, oxygen molecules, ozone, and oxygen ions. (oxygen molecular ions), and / or oxygen cluster ions.

[0077] The oxygen 431 can be introduced into the oxide insulating film 480 by, for example, ion implantation or ion doping. method, plasma immersion ion implantation method, plasma treatment, etc. It is also possible to use a gas cluster ion beam as the ion implantation method. The oxygen 431 may be introduced to the entire surface of the substrate 400 at once, or may be introduced to a linear inlet. When a linear ion beam is used, the substrate or the ion beam By moving (scanning) the film relatively, oxygen 431 is introduced to the entire surface of the oxide insulating film 480. You can enter.

[0078] As the supply gas of oxygen 431, a gas containing O may be used, for example, O2 gas, N2O gas, CO2 gas, CO gas, NO2 gas, etc. can be used. The supply gas may contain a rare gas (for example, Ar).

[0079] Also, for example, when oxygen is introduced by ion implantation, the dose of oxygen 431 is set to 0.5× 10 16 cm -2 5x10 or more 16 cm -2 Less than (e.g., 1×10 16 cm -2 ), Canada The initial energy is preferably 50 eV or more and 70 eV or less (for example, 50 eV). The oxygen content in the oxide insulating film including the oxygen excess region 481 after the oxygen doping treatment is It is preferable that the composition of the coating exceeds the stoichiometric composition of the coating. The region containing more oxygen than the composition may be present in the oxygen excess region 481. The implantation depth of the element 431 may be appropriately controlled by the implantation conditions.

[0080] Next, a planarization treatment is performed to remove protrusions on the top surface of the oxide insulating film 484 including the oxygen excess region 481. The oxide insulating film 484 over the conductive layer 491 is selectively removed to planarize the surface. A planarized oxide insulating film 436 is formed (see FIG. 1C).

[0081] The oxide insulating film over the conductive layer 491 is selectively removed and thinned by the planarization treatment. Therefore, the distance between the oxygen-excess region 481 over the conductive layer 491 and the top surface of the oxide insulating film becomes shorter. In the oxide insulating film, the oxide insulating film is hardly removed in a region where the conductive layer 491 is not present. The oxidation hardly occurs, and the oxygen excess region 481 exists near the bottom surface of the oxide insulating film. In the oxide insulating film 436, the oxygen excess region 481 is formed by In the region where the conductive layer 491 is present, the conductive layer 491 is provided at a shallower position, and in the other region (the region where the conductive layer 491 is not present), the conductive layer 491 is provided at a shallower position. ) is placed at a deep position.

[0082] Therefore, the oxide insulating film 4 overlapping the conductive layer 491 on which an oxide semiconductor film will be provided in a later step is removed. In 36, an oxygen excess region 481 can be provided in the vicinity of the oxide semiconductor film. Therefore, oxygen can be efficiently supplied from the oxygen excess region 481 to the oxide semiconductor film. The supply of oxygen can be further promoted by carrying out a heat treatment.

[0083] Furthermore, in the oxide insulating film 436, the oxygen excess region 481 is formed by an oxide film that requires oxygen supply. In the region other than under the semiconductor film, the oxide insulating film 436 is separated from the top surface of the oxide insulating film 436. Therefore, even when heat treatment is performed, the oxide insulating film 436 Unnecessary oxygen release from the top surface can be suppressed, and the oxide insulating film 436 is maintained in an oxygen-excess state. It is possible.

[0084] Note that although the example in which oxygen 431 is introduced into the oxide insulating film 480 is described in this embodiment, If the oxide insulating film 480 containing sufficient oxygen can be formed immediately after deposition, the oxide insulating film The introduction of oxygen 431 into membrane 480 can be omitted.

[0085] The planarization treatment is not particularly limited, but may be a polishing treatment (for example, a chemical mechanical polishing method). (Chemical Mechanical Polishing: CMP), dry Etching treatment and plasma treatment can be used.

[0086] Next, the oxide semiconductor film 403 is formed over the oxide insulating film 436. 3 is a binary metal oxide, such as In-Zn oxide, In-Mg oxide, and In-Ga In-Ga-Zn oxide (also written as IGZO), which is an oxide of a ternary metal ), In-Sn-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Sn-Hf-Zn oxide, etc. can be used. Cut.

[0087] Here, for example, In-Ga-Zn oxide refers to an oxide containing In, Ga, and Zn. The ratio of In, Ga and Zn does not matter. Other metal elements may also be included.

[0088] In this embodiment, the oxide semiconductor film 403 is formed by a sputtering method. The target used was an oxide target with an atomic ratio of In:Ga:Zn=3:1:2. In-Ga-Zn oxide film (IGZO film) is formed with a thickness of 5 nm to 30 nm. do.

[0089] Note that the oxide semiconductor film 403 is particularly preferably a CAAC-OS film. When an -OS film is used, the oxide semiconductor film 40 Even if a part of the conductive layer 491 (a part that overlaps with the conductive layer 491 and becomes a channel forming region) is thinned, the oxide The boundary region between the thin region of the compound semiconductor film 403 and the thick region (the region overlapping with the metal film) is The cross-sectional shape rises in the film thickness direction and then slopes smoothly in the forward tapered direction. The thin region of the oxide semiconductor film 403 is thinner than at least the thick region. It is assumed to be thicker than half the thickness of the thick region.

[0090] The relative density (filling rate) of the metal oxide target is preferably 90% or more and 100% or less. The relative density is 95% or more and 99.9% or less. Use a metal oxide target with a high relative density. As a result, the formed oxide semiconductor film can be a dense film.

[0091] The oxide semiconductor film 403 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0092] The substrate is held in a film-forming chamber that is kept in a reduced pressure state, and the remaining moisture in the film-forming chamber is removed. The sputtering gas from which hydrogen and moisture have been removed is introduced, and the oxide insulating film is formed using the target. The oxide semiconductor film 403 is formed on the insulating film 436. Adsorption type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps, It is preferable to use a turbo molecular pump as the exhaust means. The deposition chamber is evacuated using a cryopump. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably compounds containing carbon atoms) Since the oxide semiconductor film 403 formed in the deposition chamber is exhausted, the oxide semiconductor film 403 is not included in the oxide semiconductor film 403. This reduces the concentration of impurities.

[0093] The oxide semiconductor film 403 is formed by forming an oxide semiconductor film into island-like regions by a photolithography process. The insulating film can be formed by processing an oxide semiconductor film.

[0094] In addition, a resist mask for forming the island-shaped oxide semiconductor film 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0095] In order to promote supply of oxygen from the oxide insulating film 436 to the oxide semiconductor film 403, A heat treatment may be carried out.

[0096] Next, a source electrode layer 405a and a drain electrode layer 405b electrically connected to the oxide semiconductor film 403 are formed. The source electrode layer 405a and the drain electrode layer 405b are used to form another transistor. By electrically connecting it to transistors and elements, various circuits can be configured.

[0097] The source electrode layer 405a and the drain electrode layer 405b are formed by, for example, sputtering or vapor deposition. The conductive film can be formed by forming a conductive film using a metal such as fluorine or the like and processing it by etching.

[0098] Examples of conductive films used for the source electrode layer 405a and the drain electrode layer 405b include: A metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements membrane) can be used.

[0099] In this embodiment mode, a single layer tungsten film is used, and a resist mask is formed on the tungsten film. The first etching removes about half of the thickness of the tungsten film to make it partially thin. Then, ashing (O2 ashing, etc.) is performed on the resist mask to remove the surface of the resist mask. After the process to reduce the area, a second etching is performed using the reduced resist mask. 1D, that is, the source electrode layer 405a having the protruding portion and the protruding portion A drain electrode layer 405b having a projection is formed on each of the electrodes.

[0100] Next, the reduced resist mask is removed. The cross section at this stage corresponds to FIG. 1(D). do.

[0101] Next, the oxide semiconductor film 403 was treated with diluted hydrofluoric acid (concentration: 0.0025%). When wet etching is performed, the concentration of diluted hydrofluoric acid and the wet etching temperature are The etching treatment time, the crystallinity of the oxide semiconductor film 403, and the like are appropriately controlled. By using diluted hydrofluoric acid, a thin region can be formed in the oxide semiconductor film 403. By performing wet etching, the thickness of the oxide semiconductor film in the channel formation region can be further reduced. This allows for more precise control and reduces contaminants near the channel formation region. Therefore, the performance of the transistor can be improved.

[0102] In addition, by forming a thin region in the oxide semiconductor film 403, the source electrode layer 405a This can alleviate the electric field concentration that may occur between the drain electrode layer 405b and the drain electrode layer 405c. .

[0103] In this embodiment, as an example, after processing the tungsten film, diluted hydrofluoric acid is used to remove the tungsten. A step of forming a thin region in the oxide semiconductor film 403 by wet etching is described below. The etching conditions for processing the tungsten film are as follows: By appropriately adjusting the thickness, a thin region may be formed in the oxide semiconductor film 403.

[0104] The wet etching removes the source electrode layer 405a having the protrusion and the drain electrode layer 405b having the protrusion. The oxide semiconductor film 403 is exposed using the oxide electrode layer 405b as a mask. do.

[0105] In this embodiment, the exposed oxide semiconductor film 403 is Etching is performed (thinning the film by about 5 nm). In this case, wet etching is performed. The optimum time can be calculated appropriately based on the etching rate.

[0106] Wet etching is performed using the source electrode layer 405a and the drain electrode layer 405b as a mask. When the oxide semiconductor film 403 is subjected to the etching, the source electrode layer 405a and the drain electrode layer 405b are The thickness of the oxide semiconductor film 403 in a region that does not overlap with the source electrode layer 405a and The thickness of the oxide semiconductor film 403 in a region overlapping with the drain electrode layer 405b is smaller than that of the oxide semiconductor film 403 in a region overlapping with the drain electrode layer 405b ( (See Figure 1(E)). This thin region can be used as the channel formation region of a transistor. Therefore, the source electrode layer 440 overlaps the conductive layer 491 and extends in the channel length direction. between the bottom end of the drain electrode layer 405a and the bottom end of the drain electrode layer 405b extending in the channel length direction. The distance can be the channel length.

[0107] Note that when the thin region is formed in the oxide semiconductor film 403, the oxide semiconductor film 403 is not excessively etched. By etching, the oxide insulating film 436 formed in contact with the oxide semiconductor film 403 It is necessary to take sufficient care so that the surface of the The etching time, the crystallinity of the oxide semiconductor film 403, and the like can be appropriately controlled. preferable.

[0108] Next, pure water megasonic cleaning is performed. The cross section at this stage corresponds to Figure 1(E).

[0109] As for the oxide semiconductor film to be wet-etched using diluted hydrofluoric acid as described above, When an oxide semiconductor film having a crystalline structure, specifically a CAAC-OS film, is used, -Improved coverage of the gate insulating film and gate electrode layer formed on the OS film, The effect of improving the performance of the transistor and preventing the deterioration of the electrical characteristics of the transistor are remarkable. Therefore, it is preferable to use a CAAC-OS film.

[0110] The CAAC-OS film is, for example, an oxide semiconductor film in which the entire film or most of the film is amorphous. Compared with the film (also called amorphous-OS film), etching is more likely to proceed anisotropically. The crystalline structure of the CAAC-OS film causes differences in the etching rate for each crystal plane. By utilizing this difference, it is possible to make the etching proceed anisotropically. do.

[0111] Therefore, by using the CAAC-OS film, the thin region of the CAAC-OS film (the source electrode layer 4 405a and the drain electrode layer 405b) and the thick CAAC-OS film region ( The boundary region between the source electrode layer 405a and the drain electrode layer 405b is a film. The cross-sectional shape rises in the thickness direction and then slopes smoothly in the forward tapered direction. is possible.

[0112] In addition, the coverage can be improved even if the gate insulating film is thin. This reduces the concentration of electric fields at the boundary between the thin and thick regions, improving the reliability of the transistor. It is possible to do this.

[0113] On the other hand, the amorphous-OS film is easily etched isotropically. When etching progresses, etching proceeds at the same rate not only downward but also laterally. The source electrode layer 405a having a protrusion, which is used as a mask, and the drain electrode layer 405b having a protrusion Therefore, the amorphous-OS film formed on the amorphous-OS film is removed to just below the drain electrode layer 405b. The coverage of the gate insulating film and gate electrode layer decreases.

[0114] Next, the oxide semiconductor film 403, the source electrode layer 405a, and the drain electrode layer 405b were A covering gate insulating film 402 is formed (see FIG. 1(F)).

[0115] The thickness of the gate insulating film 402 is, for example, 1 nm or more and 20 nm or less, and is formed by a sputtering method. The MBE method, CVD method, pulsed laser deposition method, ALD method, etc. can be used as appropriate. The gate insulating film 402 is formed by depositing a plurality of substrates approximately perpendicular to the surface of the sputtering target. The film may be formed using a sputtering device that performs film formation while the surface is set.

[0116] The gate insulating film 402 may be a silicon oxide film, a gallium oxide film, Ga2O3 (Gd2O 3) Film, zinc oxide film, aluminum oxide film, silicon nitride film, silicon oxynitride film, oxide An aluminum nitride film or a silicon nitride oxide film can be used. An In-Ga-Zn oxide film having an insulating layer can also be used as the gate insulating film 402. The In-Ga-Zn oxide film with the insulating properties has an atomic ratio of In:Ga:Zn=1:3:2. The substrate temperature was set to room temperature, and the sputtering gas was argon or Alternatively, it may be formed using a mixed gas of argon and oxygen.

[0117] In this embodiment, a gallium oxide film formed by sputtering is used as the gate insulating film 402. When a gallium oxide film is used as the gate insulating film 402, the same Since the oxide semiconductor film contains one component material, the interface state of the oxide semiconductor film can be made favorable. , and stable electrical properties can be imparted.

[0118] Next, a conductive film is formed on the gate insulating film 402 by using a sputtering method, a vapor deposition method, or the like. The conductive film is then etched to form gate electrode layers 401a and 401b.

[0119] The gate electrode layers 401a and 401b are made of molybdenum, titanium, tantalum, tungsten, or the like. Metallic materials such as nickel, aluminum, copper, chromium, neodymium, scandium, etc., or materials mainly containing these The gate electrode layers 401a and 401b can be formed using an alloy material containing the same component. 1b is a semiconductor film, typically a polycrystalline silicon film, doped with impurity elements such as phosphorus. Alternatively, a silicide film such as nickel silicide may be used. 1b may have a single layer structure or a laminated structure.

[0120] In this embodiment, the gate electrode layer 401a in contact with the gate insulating film 402 is formed by using a gate electrode layer containing nitrogen. A metal oxide film containing nitrogen (In-Ga-Zn oxide film containing nitrogen) is used, and a gate electrode is formed on it. A tungsten film is used as the electrode layer 401b. A nitrogen-containing metal oxide film is used as the gate electrode layer 4 By using O1a, the threshold voltage of the transistor can be made positive.

[0121] Through the above steps, the transistor 440a of this embodiment can be manufactured (FIG. 2(A)). )). The transistor 440a is an example of a top-gate transistor, and is shown in FIG. 2(A) is a cross-sectional view of the transistor 440a in the channel length direction.

[0122] The conductive layer 491 provided in the oxide insulating film 436 including the oxygen excess region 481 is The gate electrode layers 401a and 401b overlap with the channel forming region, and the transistor 440 Control the electrical characteristics of a.

[0123] The conductive layer 491 is a second gate electrode layer (so-called For example, the potential of the conductive layer 491 can be controlled by By setting the potential to GND (or a fixed potential), the threshold voltage of the transistor 440a can be made higher. The transistor may be a normally-off transistor.

[0124] The gate electrode layers 401a and 401b are connected to the source electrode layer 405a and the drain electrode layer 405b. The protrusion of the source electrode layer 405a (or the drain electrode The protruding portion of the layer 405b is shaped to improve the coverage of the gate insulating film 402. This has the effect of mitigating electric field concentration, improving the electrical characteristics and reliability of transistors. contribute to.

[0125] Next, an insulating film 407 is formed to cover the gate electrode layers 401a and 401b (see FIG. 2(B)). The insulating film 407 prevents oxygen from the oxide semiconductor film 403 or the gate insulating film 402. It functions as a highly effective barrier film (protective film) that prevents the release of

[0126] The insulating film 407 serving as a barrier film prevents insufficient heat such as hydrogen and moisture from entering the oxide semiconductor film 403. A dense film that can prevent the intrusion of impurities is preferred.

[0127] The insulating film 407 that functions as a barrier film is, for example, a gallium oxide film, Ga2O3( Gd2O3) film, silicon oxide film, silicon oxynitride film, aluminum oxide film, oxynitride film Aluminum film, silicon nitride film, aluminum nitride film, silicon nitride oxide film, nitride oxide An inorganic insulating film such as an aluminum film or a zinc oxide film can be used, and it may be a single layer or a laminated layer. The insulating film 407 functioning as a barrier film is formed by a plasma CVD method or a sputtering method. Alternatively, a CVD method using a film-forming gas or an MBE method can be used.

[0128] Next, an interlayer insulating film 485 is formed on the insulating film 407. The interlayer insulating film 485 is made of silicon oxide. Silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, silicon nitride film Silicon nitride film, aluminum nitride film, silicon oxide nitride film, aluminum oxide nitride film, gallium oxide film An inorganic insulating film such as an inorganic film can be used, and may be a single layer or a multilayer.

[0129] The cross section at the stage where buried wiring is formed in the interlayer insulating film 485 corresponds to FIG. 2(C). A contact hole reaching the source electrode layer 405a is formed in the interlayer insulating film 485. A barrier metal film 486 is formed, and a copper or A copper alloy film is formed, and then polished to be flat, and the exposed low-resistance conductive layer 48 To protect the buried wiring, a second barrier metal film 488 is formed. a first barrier metal film 486, a second barrier metal film 488, and a first barrier metal film 486 and a second barrier metal film 488. It is composed of a low resistance conductive layer 487 surrounded by a rear metal film 488.

[0130] The first barrier metal film 486 and the second barrier metal film 488 are included in the low resistance conductive layer 487. A conductive material that suppresses the diffusion of copper contained in the film may be used, such as a tantalum nitride film or a molybdenum nitride film. A tungsten film, a tungsten nitride film, etc. are used.

[0131] By going through the above steps, other semiconductor elements and wiring can be formed on the transistor 440a. By forming the above, a semiconductor device having a multi-layer structure can be formed. Other semiconductor elements and wirings provided on the substrate 440a are electrically connected to the embedded wirings. It is possible.

[0132] The cross-sectional structure of the transistor 440a in this embodiment is just an example. Cross section of the conductive film 403 (preferably the source electrode layer 405a and the drain electrode layer 405b) There are no particular limitations as long as the shape is the same. Although an IGBT (Insulated GaAs Transistor) is shown as an example, the transistor 440a is te Bipolar Transistor), MESFET(Metal Semi Conductor Field Effect Transistor) However, when an IGBT is used as the transistor 440a, the source electrode The layer corresponds to the emitter terminal, and the drain electrode layer corresponds to the collector terminal. Examples of the cross-sectional structure of a transistor are listed below.

[0133] The transistor 440b illustrated in FIG. 3A includes a first oxide semiconductor film 403a over the first oxide semiconductor film 403b. A second oxide semiconductor film 403b having a different composition from the oxide semiconductor film 403a is formed. The second oxide semiconductor film 403b has a stacked-layer structure and includes a small-thickness region. Since the structure is the same as that of FIG. 2(B) except for the two-layer stack, detailed explanation is omitted here. It will be decided.

[0134] The first oxide semiconductor film 403a is a tantalum oxide semiconductor film having an atomic ratio of In:Ga:Zn=3:1:2. The first oxide film is an In-Ga-Zn oxide film formed using a target. The semiconductor film 403a may be a semiconductor film in which the atomic ratio of In is greater than that of Ga and Zn. The second oxide semiconductor film 403b has an atomic ratio of In:Ga:Zn=1:1:1. An In-Ga-Zn oxide film is used, which is formed using a target with the same ratio.

[0135] When stacked oxide semiconductor films having different compositions are used, the first oxide semiconductor film 403a is exposed. To prevent this, a thin region is formed in the second oxide semiconductor film 403b.

[0136] The transistor 440b shown in FIG. 3A has a channel formation region formed of In:Ga:Zn=3: An In-Ga-Zn oxide film is formed using a target with an atomic ratio of 1:2. Therefore, the field effect mobility can be improved.

[0137] In addition, the transistor 440c illustrated in FIG. 3B includes a third oxide semiconductor film 403c over which: a first oxide semiconductor film 403a having a different composition from a third oxide semiconductor film 403c is formed; A second oxide semiconductor film having a composition different from that of the first oxide semiconductor film is formed over the first oxide semiconductor film. The oxide semiconductor film 403b is formed to have a three-layer structure, and the first oxide semiconductor film 403b has a thin region. 2B and 2C, except for the three-layer structure. Since they are identical, detailed description will be omitted here.

[0138] The first oxide semiconductor film 403a is a tantalum oxide semiconductor film having an atomic ratio of In:Ga:Zn=3:1:2. The first oxide film is an In-Ga-Zn oxide film formed using a target. The semiconductor film 403a may be a semiconductor film in which the atomic ratio of In is greater than that of Ga and Zn. The second oxide semiconductor film 403b has an atomic ratio of In:Ga:Zn=1:1:1. An In-Ga-Zn oxide film formed using a target having a ratio of In may be used. In-Ga-Zn film formed using a target with an atomic ratio of Ga:Zn=1:3:2 Alternatively, the third oxide semiconductor film 403c may be an In:Ga-based oxide film. In-Ga-Zn oxide film formed using a target with an atomic ratio of Zn=1:3:2 A target with an atomic ratio of In:Ga:Zn=1:1:1 may be used. Alternatively, a deposited In-Ga-Zn oxide film may be used.

[0139] When stacked oxide semiconductor films having different compositions are used, the first oxide semiconductor film 403a is exposed. To prevent this, a thin region is formed in the second oxide semiconductor film 403b.

[0140] The transistor 440c shown in FIG. 3B has a channel formation region formed of In:Ga:Zn=3: An In-Ga-Zn oxide film is formed using a target with an atomic ratio of 1:2. Therefore, the field effect mobility can be improved.

[0141] In addition, in a transistor 440d illustrated in FIG. 3C, the conductive layer 492 overlaps with the channel formation region. In this example, the conductive layer 492 is disposed at a position where it does not overlap with the channel formation region. Since the configuration is the same as that of FIG. 3(B) except for the configuration arranged in the position, detailed description is omitted here. This will be omitted.

[0142] Immediately after fabricating transistor 440d, the threshold voltage of the transistor is increased. If a normally-off transistor is realized, as shown in Figure 3(C), In addition, the conductive layer 492 does not need to overlap with the channel formation region. If it is not necessary for the transistor to be normally-off, then only that transistor should be normally-on. It can also be used as a transistor.

[0143] The transistors shown in FIGS. 2B, 3A, 3B, and 3C are Although each of them has a partially different configuration, there is no particular limitation, and various combinations are possible.

[0144] (Embodiment 2) In this embodiment, a gate electrode layer, a gate insulating film, and a gate electrode layer formed by way of the gate insulating film are provided. The parasitic capacitance formed between the gate electrode layer and the source electrode layer overlapping the gate insulating layer is The gate insulating film is formed between the drain electrode layer and the gate electrode layer. An example of a method for manufacturing a transistor with reduced parasitic capacitance will be described below. Since the steps are the same up to the middle, detailed explanation of those steps will be omitted.

[0145] First, the same steps as those shown in FIG. 1(C) in the first embodiment are carried out. A conductive layer 491 is formed thereover, and an oxide insulating film 436 including an oxygen excess region 481 is formed thereover. The cross section at this stage is shown in Figure 4(A). Note that Figure 1(C) and Figure 4(A) are the same.

[0146] Next, the first oxide semiconductor film 403a and the first oxide semiconductor film 403b were formed over the oxide insulating film 436. A second oxide semiconductor film 403b is formed over the first oxide semiconductor film 403a. After the formation of the oxide semiconductor film 403a, the second oxide semiconductor film 403b is successively formed without exposure to the air. do.

[0147] The first oxide semiconductor film 403a is a tantalum oxide semiconductor film having an atomic ratio of In:Ga:Zn=3:1:2. The first oxide film is an In-Ga-Zn oxide film formed using a target. The semiconductor film 403a may be a semiconductor film in which the atomic ratio of In is greater than that of Ga and Zn. The second oxide semiconductor film 403b has an atomic ratio of In:Ga:Zn=1:1:1. The In-Ga-Zn oxide film is formed using a target having the same ratio. The oxide semiconductor film 403a and the second oxide semiconductor film 403b are made of an oxide having a crystalline structure. The membrane is preferably a CAAC-OS membrane.

[0148] Next, the oxide semiconductor film is processed into an island shape by a photolithography process. A conductive film is formed by using a tartering method, a vapor deposition method, or the like.

[0149] Next, resist masks 408a and 408b are formed over the conductive film, and the resist masks are formed to cover about half the thickness of the conductive film. Then, etching is performed to remove the impurities and thin the conductive film 40. 6 is formed. The cross section at this stage is shown in FIG. 4(B).

[0150] Next, the resist masks 408a and 408b are removed, and then the partially thinned conductive film 406 A protective layer 409 is formed on the gate insulating layer 409 (see FIG. 4(C)). This is a film provided to protect a part of the conductive film when etching the film 402. Silicon film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, nitride Silicon film, aluminum nitride film, silicon nitride oxide film, aluminum nitride oxide film, etc. The protective layer 409 is made of a material different from that of the gate insulating film 402. In this embodiment, a material having a large selection ratio of oxide film obtained by sputtering is used. A silicon membrane is used.

[0151] Next, a resist mask is formed on the protective layer 409, and the cross-sectional shape shown in FIG. The source electrode layer 405a having a protrusion and the drain electrode layer 405b having a protrusion are formed on the The source electrode layer 405a and the drain electrode layer 405b are formed. The protective layer 409 is also etched to expose the first protective layer 409 that contacts and overlaps the source electrode layer 405a. 10a and a second protective layer 410b that contacts and overlaps the drain electrode layer 405b are formed. The cross-sectional view at the stage when the resist mask is removed is shown in FIG.

[0152] Next, diluted hydrofluoric acid (concentration 0.0025%) was used to remove the oxide semiconductor, which was a CAAC-OS film. The conductive film is subjected to wet etching to form an oxide semiconductor film (here, the second oxide semiconductor film) A thin film region can be formed on the wet film 403b. By performing the etching, the thickness of the oxide semiconductor film to be the channel formation region can be determined more accurately. It is possible to control the amount of contaminants in the vicinity of the channel forming region. Therefore, the performance of the transistor can be improved.

[0153] Next, pure water megasonic cleaning is performed. The cross section at this stage corresponds to Figure 4(E).

[0154] Next, the second oxide semiconductor film 403b, the first protective layer 410a, and the second protective layer 41 A gate insulating film 402 is formed to cover the gate insulating film 402b. In this embodiment, the material of the gate insulating film 402 is As the insulating film, a film containing gallium oxide, typically a gallium oxide film, is used. Even if the film is thin, less than 20 nm, it is possible to form a nitrogen-containing metal oxide film in a later process. Even if the film is formed by sputtering or other methods, impurities such as nitrogen may accumulate in the underlying oxide semiconductor during or after film formation. It also has the effect of preventing penetration into the conductive film.

[0155] Next, a conductive film is formed on the gate insulating film 402 by using a sputtering method, a vapor deposition method, or the like. The conductive film is then etched to form gate electrode layers 401a and 401b. Using the gate electrode layers 401a and 401b as a mask, a part of the gate insulating film 402 is removed. When removing a part of the gate insulating film 402, the first protective layer 410a and the second protective layer 410b are removed. The layer 410b functions as an etching stopper, and the source electrode layer 405a and the drain electrode layer 405b are The pole layer 405b is protected from the etching process.

[0156] In this embodiment, the gate electrode layer 401a in contact with the gate insulating film 402 is formed by using a gate electrode layer containing nitrogen. A metal oxide film containing nitrogen (In-Ga-Zn oxide film containing nitrogen) is used, and a gate electrode is formed on it. A tungsten film is used as the pole layer 401b.

[0157] Through the above steps, the transistor 441a of this embodiment can be manufactured. The gate electrode layers 401a and 401b are covered with a first protective layer 410a and a second protective layer 410b. An insulating film 407 is formed in contact with the first insulating film 407 (see FIG. 4F). The oxide semiconductor film 403a, the second oxide semiconductor film 403b, or the gate insulating film 402 The transistor 441a functions as a barrier film that has a high function of preventing oxygen from being released from the semiconductor substrate. , an example of a top-gate transistor, and FIG. 4F shows a transistor 441a 1 is a cross-sectional view in the channel length direction.

[0158] In the transistor 441a illustrated in FIG. 4F, the gate electrode layers 401a and 401b are Although the source electrode layer 405a and the drain electrode layer 405b overlap with each other, A first protective layer 410a is disposed on the drain electrode layer 405a and in contact with the drain electrode layer 405b. Since the second protective layer 410b is provided, the parasitic capacitance in this portion is the same as that shown in the first embodiment. This is a reduced configuration compared to the transistor 440a.

[0159] The cross-sectional structure of the transistor 441a described in this embodiment is just an example. Cross section of the conductive film 403 (preferably the source electrode layer 405a and the drain electrode layer 405b) There is no particular limitation as long as the shape is the same. Below is an example of the cross-sectional structure of another transistor. List them.

[0160] The transistor 441b illustrated in FIG. 5A includes an oxide insulating film 436 and a first oxide semiconductor film In this example, an insulating film 438 containing gallium oxide is provided between the layers 403a.

[0161] The transistor 441b illustrated in FIG. 5A includes a source electrode layer 405a and a drain electrode layer 405b. The insulating film 438 containing gallium oxide is also in contact with the lower surface of the insulating film 438. The insulating film 438 protects the oxide insulating film 436 when the gate insulating film 402 is etched. It also functions as an etching stopper. The insulating film 407 and the insulating film 438 containing gallium oxide are in contact with each other.

[0162] An insulating film containing gallium oxide is provided between the oxide insulating film 436 and the first oxide semiconductor film 403a. Since the configuration other than that having 438 is the same as that of FIG. 4(F), detailed description will be omitted here. It will be decided.

[0163] The transistor 441c illustrated in FIG. 5B includes the oxide insulating film 436 and the first oxide semiconductor layer. An insulating film 438 containing gallium oxide is provided between the conductive films 403a, and a part of the insulating film 438 and This is an example in which the gate insulating film 402 is in contact with the other gate insulating film 402. Other than this, it is the same as FIG. 5(A), so detailed description will be omitted here.

[0164] The transistor 441c has a gate insulating film 402 containing gallium oxide. A first oxide semiconductor film 403a, a second oxide semiconductor film 403b, and a source electrode layer 405a and the drain electrode layer 405b is covered with an insulating film containing gallium oxide. Therefore, the structure prevents oxygen from being released from the stack of oxide semiconductor films from all sides. .

[0165] In addition, a transistor 441d illustrated in FIG. 5C has an oxide semiconductor film having a three-layer stack structure. A layer having a composition different from that of the third oxide semiconductor film 403c is formed over the third oxide semiconductor film 403c. A first oxide semiconductor film 403a is formed, and a first oxide semiconductor film 403b is formed on the first oxide semiconductor film 403a. The second oxide semiconductor film 403a and the third oxide semiconductor film 403c have different compositions. The second oxide semiconductor film 403b has a thin region. It has a range.

[0166] The insulating film 434 is formed to cover the conductive layer 491, and the oxide insulating film 435 is polished. As a result, a part of the insulating film 434 is exposed.

[0167] The insulating film 434 is a barrier film, and may be an aluminum oxide film, an aluminum oxynitride film, a nitride film, or the like. Silicon film, aluminum nitride film, silicon nitride oxide film, aluminum nitride oxide film, oxide An inorganic insulating film such as a gallium film is used.

[0168] The insulating film 434 is a silicon oxide film or a silicon oxynitride film obtained by the plasma CVD method. do.

[0169] The transistor 441d illustrated in FIG. 5C has a three-layer oxide semiconductor film. 5A except that the insulating film 434 is provided and oxygen doping treatment is not performed. Since they are identical, detailed description will be omitted here.

[0170] The transistor 441e illustrated in FIG. 6A has a three-layer oxide semiconductor film. Other than this, the configuration is the same as FIG. 5(A), and therefore detailed description thereof will be omitted here.

[0171] 6B shows an example of a top view of the transistor 441e. The cross section taken along line B corresponds to FIG. 6(A). As shown in FIG. 6(B), the second oxide semiconductor The periphery of the body membrane 403b is covered with the source electrode layer 405a or the drain electrode layer 405b. The gate electrode layer 401b is provided to cover the uncovered region of the second oxide semiconductor film 403b. Therefore, the second oxide semiconductor film 403 is not etched when the gate electrode layer 401b is etched. 6(A), there is no exposed portion of the source electrode layer 405a. The upper surface of the drain electrode layer 405b is covered with a first protective layer 410a, or the upper surface of the drain electrode layer 405b is covered with a second protective layer 410b. Since the gate electrode layer 401b is covered with the protective layer 410b, the source voltage is not applied when the gate electrode layer 401b is etched. Neither the pole layer 405a nor the drain electrode layer 405b is removed.

[0172] In addition, the transformers shown in Figs. 4(F), 5(A), 5(B), 5(C), and 6(A) Although each register has a different configuration, there are no particular limitations and various combinations are possible. It is Noh.

[0173] This embodiment mode can be freely combined with Embodiment Mode 1.

[0174] In this embodiment, the same parts as those in the first embodiment are designated by the same reference numerals, and the same materials are used. It goes without saying that it is possible to use

[0175] (Embodiment 3) In this embodiment, a semiconductor device using the transistor described in Embodiment 1 or 2 is An example of the body device will be described with reference to FIG.

[0176] The semiconductor device shown in FIG. 7 includes transistors 740 and 750 using a first semiconductor material in the lower portion. The transistor 610 is made of a second semiconductor material. The transistor 610 has a structure similar to that of the transistor 441d described in Embodiment 2. 5. The same parts as in FIG. 5 will be described using the same reference numerals. 1 is a circuit diagram of a semiconductor device corresponding to

[0177] Here, the first and second semiconductor materials have different bandgaps. For example, it is desirable to use a semiconductor material other than an oxide semiconductor (silicon The second semiconductor material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can easily operate at high speed. The characteristics of a resistor allow it to retain charge for a long period of time.

[0178] Substrates used in semiconductor devices include single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, and Conductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon on Insulator) n insulator substrate, etc., can be used, and the channel formation region of the transistor The region can be formed in or on a semiconductor substrate. The semiconductor device is an example in which a channel forming region is formed in a semiconductor substrate to form a lower transistor. is.

[0179] In the semiconductor device shown in FIG. 7A, a single crystal silicon substrate is used as the substrate 700. The transistor 740 and the transistor 750 are formed on a single crystal silicon substrate. Single crystal silicon is used as the semiconductor material. The transistor 740 is an n-channel transistor. The transistor 750 is a p-channel transistor, and the transistor 740 and transistor 750 is electrically connected to a CMOS (complementary metal oxide semiconductor: plementary Metal Oxide Semiconductor) circuit It forms 760.

[0180] In this embodiment, the substrate 700 is a single crystal silicon substrate having a p-type conductivity. Therefore, the n-type transistor 750 is formed in a region where the p-channel transistor is formed. An impurity element that imparts a type is added to form an n-well. The formation region 753 is formed in an n-well. The impurity element that imparts n-type conductivity is phosphorus (P ) or arsenic (As), etc. can be used.

[0181] Here, a p-type conductive layer is formed in the region where the transistor 740, which is an n-channel transistor, is formed. Although no impurity element that gives the electrode type is added, an impurity element that gives the p-type is added. The impurity element that gives the p-type conductivity is boron ( B), aluminum (Al), gallium (Ga), etc. can be used.

[0182] On the other hand, when using a single crystal silicon substrate with n-type conductivity, impurities that give p-type conductivity are added. A p-well may be formed by adding a metal element.

[0183] The transistor 740 includes a channel forming region 743, an LDD (Lightly Doped The n-type impurity region 744 functions as a drain region and an extension region. An n-type impurity region 745 which functions as a drain region or a gate insulating film 742, a gate insulating film 743, a gate insulating film 744, a gate insulating film 745, a gate insulating film 742, a gate insulating film 74 ...4, The n-type impurity region 745 has a gate electrode layer 741. The impurity concentration of the n-type impurity region 745 is The gate electrode layer 741 is provided with a sidewall insulating layer 746 on its side. The gate electrode layer 741 and the sidewall insulating layer 746 are used as masks to form a gate insulating film having different impurity concentrations. The n-type impurity regions 744 and 745 can be formed in a self-aligned manner. .

[0184] The transistor 750 includes a channel forming region 753, an LDD region, an extension region, and a p-type impurity region 754 functioning as a source region or a drain region; It has a pure region 755, a gate insulating film 752, and a gate electrode layer 751. The impurity concentration of the pure region 755 is higher than that of the p-type impurity region 754. A sidewall insulating layer 756 is provided on the side surface of the gate electrode layer 751 and the sidewall insulating layer 75 6 as a mask, p-type impurity region 754 and p-type impurity region 7 55 can be formed in a self-aligned manner.

[0185] In the substrate 700, the transistor 740 and the transistor 750 are formed by an element isolation region 789. The transistors 740 and 750 are separated by an insulating film 788. and an insulating film 687 are stacked on the insulating film 687. An insulating film 788 and an insulating film 68 a wiring layer 647 electrically connected to the n-type impurity region 745 through an opening formed in the semiconductor substrate 7; The insulating film 788 and the insulating film 687 are electrically connected to the p-type impurity region 755 through openings formed therein. The insulating film 687 has a wiring layer 657 connected to the transistor 740 and the A wiring layer 748 is formed to electrically connect the transistor 750 to the wiring layer 748. is an opening formed in the insulating film 788 and the insulating film 687 and reaching the n-type impurity region 745. The p-type impurity region 745 is electrically connected to the insulating film 788 and the insulating film 687. The p-type impurity region 755 is electrically connected to the p-type impurity region 755 through an opening that reaches the p-type impurity region 755 .

[0186] An insulating film 686 is provided on the insulating film 687, the wiring layer 647, the wiring layer 748, and the wiring layer 657. The wiring layer 658 is formed on the insulating film 686. The wiring layer 658 is formed by an insulating film 788, an insulating film The insulating film 687 is electrically connected to the gate wiring through an opening formed in the insulating film 686. The gate wiring is formed on the gate insulating film 742 and the channel forming region 753. The gate wirings are branched into gate electrode layers 741 and 751. do.

[0187] The semiconductor device of this embodiment is not limited to the configuration shown in FIG. 40, 750, transistors with silicide (salicide) and transistors with sidewall insulating layers A transistor that does not have a silicide (salicide) structure may be used. The resistance of the source and drain regions can be reduced, and the speed of the semiconductor device can be increased. In addition, since the semiconductor device can operate at a low voltage, the power consumption of the semiconductor device can be reduced.

[0188] Next, the configuration of the upper element provided on the lower transistor in the semiconductor device of FIG. 7 will be described. Reveal.

[0189] An insulating film 684 is laminated on the insulating film 686 and the wiring layer 658, and a conductive layer The conductive layer 491 and the wiring layer 692 are formed on the insulating film 43. 4 is provided over the oxide insulating film 435. a third oxide semiconductor film 403c, and a third oxide semiconductor film 403b formed on the third oxide semiconductor film 403c. The first oxide semiconductor film 403a has a different composition from the oxide semiconductor film 403c. A first oxide semiconductor film 403a and a third oxide semiconductor film 403c are formed on the oxide semiconductor film 403a. The second oxide semiconductor film 403b has a different composition. The second oxide semiconductor film 4 has a configuration including a region with a small film thickness. On the substrate 03b, a source electrode layer 405a having a protrusion and a drain electrode layer 405b having a protrusion are formed. a first protective layer 410a that is in contact with and overlaps the source electrode layer 405a; and a second protective layer 410b that is in contact with and overlaps the second oxide semiconductor layer 405b. The conductive film 403b overlaps with the source electrode layer 405a and the drain electrode layer 405b. The gate insulating film 402 is in contact with the thinned region (channel forming region) that is not covered by the gate insulating film 402. Gate electrode layers 401a and 401b are provided thereon.

[0190] The capacitor 690 is also formed over the oxide insulating film 435 in a process similar to that for the transistor 610. The capacitor element 690 has the source electrode layer 405a as one electrode and the capacitor electrode layer 69 3a, 693b are the other electrodes, and the first protective layer 410a and , the capacitance has an insulating film 682 formed in the same process as the gate insulating film 402 as a dielectric. The capacitor electrode layers 693a and 693b are formed in the same process as the gate electrode layers 401a and 401b. It is done.

[0191] The conductive layer 491 is set to a potential of GND (or a fixed potential) to control the voltage of the transistor 610. The conductive layer 491 functions as a back gate that controls the electrostatic properties. However, the conductive layer 491 is used to When it is not necessary to control the resistance of the transistor to be a normally-off transistor, the conductive layer 491 is provided. In addition, when the transistor 610 is used as part of a specific circuit, If providing layer 491 is likely to cause problems, it may not be provided in that circuit.

[0192] The wiring layer 692 is electrically connected to the wiring layer 658 through an opening formed in the insulating film 684. In this embodiment, the insulating film 684 is subjected to planarization processing by the CMP method. be.

[0193] The insulating film 434 is provided between the lower and upper parts of the semiconductor device, and the upper transistor Impurities such as hydrogen, which cause deterioration or fluctuation of the electrical characteristics of the capacitor 610, do not penetrate from the bottom to the top. Therefore, it functions as a dense inorganic insulating film with high blocking properties against impurities. It is preferable to use a film (for example, an aluminum oxide film, a silicon nitride film, etc.).

[0194] The transistor 610 can be manufactured by the manufacturing method described in Embodiment 2. The method for manufacturing the transistor 610 will be briefly described below. do.

[0195] The conductive layer 491 is formed over the insulating film 684 provided over the transistor 740 and the transistor 750. And a wiring layer 692 is formed.

[0196] Next, the insulating film 434 is formed to cover the conductive layer 491 and the wiring layer 692 .

[0197] Next, a convex portion reflecting the shapes of the conductive layer 491 and the wiring layer 692 is formed on the surface of the insulating film 434. Then, the oxide insulating film is subjected to CMP treatment to form a conductive layer 4. The oxide insulating film on the wiring layer 692 is selectively removed to flatten the surface. Then, a fluorinated oxide insulating film 435 is formed.

[0198] Next, the insulating film 434 formed on the upper surface of the wiring layer 692 is selectively removed to form the wiring layer 6 An opening is formed to expose the top surface of 92.

[0199] Next, the third oxide semiconductor film 403c, the first oxide semiconductor film 403a, and the second oxide semiconductor film 403b were mixed. The nitride semiconductor film 403b is successively formed by sputtering without being exposed to the atmosphere. A photomask is used to selectively etch the film.

[0200] Then, a conductive film is formed over the second oxide semiconductor film 403b by a sputtering method or the like. A resist mask is then formed on the silicon oxide film. The first etching is performed to remove about half of the thickness of the silicon oxide film to make it partially thin. Ashing is performed on the resist mask to reduce its area. After the etching, a second etching is performed using a smaller resist mask to form the protrusion. a source electrode layer 405a having a protruding portion and a drain electrode layer 405b having a protruding portion, Furthermore, the first protective layer 410a remains on the thick region of the source electrode layer 405a. The second protective layer 410b remains on the thick region of the drain electrode layer 405b. The source electrode layer 405a is electrically connected to the wiring layer 692 through an opening in the insulating film 434. is connected to.

[0201] Next, the second oxide semiconductor film 403b, the first protective layer 410a, and the second protective layer 41 A gate insulating film 402 is formed on the gate insulating film 402b. In this embodiment, the material of the gate insulating film 402 is A gallium oxide film is used.

[0202] Next, a conductive film is formed on the gate insulating film 402 by using a sputtering method, a vapor deposition method, or the like. The conductive film is then etched to form gate electrode layers 401a and 401b and a capacitor electrode layer 693. Next, the gate electrode layers 401a and 401b are used as a mask to form the gate electrodes. A part of the insulating film 402 is removed. In the same process, the capacitor electrode layers 693a and 693b are also removed. As a mask, a part of the gate insulating film 402 is removed to form an insulating film 682. When removing a part of the gate insulating film 402 which is a gallium nitride film, the first silicon oxide film The first protective layer 410a and the second protective layer 410b function as an etching stopper. The source electrode layer 405a and the drain electrode layer 405b are protected from etching.

[0203] Through the above steps, the transistor 610 and the capacitor 690 are formed. Even if the gate insulating film 402 is thin, ie, 20 nm or less, it is possible to form a nitrogen-containing film in a subsequent process. Even if a metal oxide film containing nitrogen is formed by sputtering or other methods, impurities such as nitrogen may be present during or after film formation. This also has the effect of preventing the oxygen from penetrating into the second oxide semiconductor film 403b below.

[0204] Next, the insulating film 407 and the interlayer insulating film 485 are formed over the transistor 610 and the capacitor 690. The cross-sectional view at this stage corresponds to FIG. 7(A). In this way, buried wiring is formed in the interlayer insulating film 485, and other semiconductor elements or Wiring and the like may be formed to manufacture a semiconductor device having a multilayer structure.

[0205] This embodiment mode can be freely combined with Embodiment Mode 1 or 2. Cut.

[0206] (Fourth embodiment) As another example of a semiconductor device including the transistor described in Embodiment 1 or 2, FIG. 8(A) shows an example of a cross-sectional view of a NOR type circuit, which is a logic circuit. (A) is a circuit diagram of a NOR type circuit, and Fig. 8(C) is a circuit diagram of a NAND type circuit. be.

[0207] In the NOR type circuits shown in FIGS. 8A and 8B, the p-channel transistors The transistors 801 and 802 have a structure similar to that of the transistor 750 shown in FIG. A transistor using a single crystal silicon substrate in the channel formation region is an n-channel transistor. The transistors 803 and 804 are the same as the transistor 610 shown in FIG. As in the transistor 441d described in Embodiment 2, a region in which the oxide semiconductor film is thin is A transistor is used as a channel formation region.

[0208] The transistor 803 is an example in which an oxide semiconductor film has a stacked structure of three layers. a first oxide semiconductor film having a composition different from that of the third oxide semiconductor film; A conductive film 403a is formed, and a third oxide semiconductor film 4 is formed on the first oxide semiconductor film 403a. 403c and a second oxide semiconductor film 403b having a composition different from that of the first oxide semiconductor film 403a. In the second oxide semiconductor film 403b, a region with a small thickness is formed as a channel-type oxide semiconductor film. It can be a composite area.

[0209] Note that an insulating film containing gallium oxide is formed between the oxide insulating film 435 and the first oxide semiconductor film 403a. An insulating film is provided on the first oxide semiconductor film 403a, and a film having a composition with the first oxide semiconductor film 403a is formed on the first oxide semiconductor film 403a. A second oxide semiconductor film 403b having a different thickness is formed to have a stacked structure, and a region having a small thickness is formed. Alternatively, a second oxide semiconductor film 403b may be formed. In this case, oxygen is supplied to the stack of oxide semiconductor films at a concentration exceeding the stoichiometric composition. Since the insulating film containing gallium oxide has an excess region, the oxide insulating film 435 is doped with oxygen. In this structure, the insulating film 434 covering the conductive layer 491 is not required. The oxide insulating film 435 is polished to expose part of the insulating film 434. An insulating film comprising gallium oxide is provided overlying the exposed portion.

[0210] In the NOR circuits shown in FIGS. 8A and 8B, the transistor 803 The electrical characteristics of a transistor can be controlled through an oxide semiconductor film that overlaps with a gate electrode layer. The potential of the conductive layer is controlled to, for example, GND, thereby The threshold voltage of the transistor 803 is set to a more positive value, and the transistor is made normally off. In this embodiment, in the NOR circuit, the transistor 803 The conductive layers provided in the transistor 804 and capable of functioning as a back gate are electrically connected to each other. However, the present invention is not limited to this example, and any other conductive material that can function as the back gate may be used. The electrical layers may be structured so that they are electrically controlled independently of one another.

[0211] The semiconductor device shown in FIG. 8(A) uses a single crystal silicon substrate as a substrate 800. A transistor 802 is formed on a silicon substrate, and an oxide semiconductor film This is an example of stacking a transistor 803 using a stacked layer for a channel formation region.

[0212] The gate electrode layers 401a and 401b of the transistor 803 are electrically connected to the wiring layer 832. The wiring layer 832 is electrically connected to the wiring layer 835. The gate electrode layers 401a and 401b of the gate electrode 803 are electrically connected to the buried wiring. The buried wiring is electrically connected to the conductive layer 842. a first barrier metal film 486, a second barrier metal film 488, and a first barrier metal film 486 and a second barrier metal film 488. The low-resistance conductive layer 487 is surrounded by a rear metal film 488. The manufacturing method is described in Embodiment Mode 1, and therefore detailed description thereof will be omitted here.

[0213] The wiring layer 832 is provided on the insulating film 830, and the wiring layer 835 is provided on the opening formed in the insulating film 833. The conductive layer 842 is provided in an opening formed in the insulating film 434 .

[0214] The electrode layer 825 of the transistor 802 is connected to the transistor 802 via the wiring layer 831 and the wiring layer 834. The wiring layer 831 is formed on the insulating film 830. The wiring layer 834 is provided in an opening formed in the insulating film 833, and the electrode layer The electrode layer 845a is provided in an opening formed in the insulating film 434. The electrode layer 845 b is a source or drain electrode layer of the transistor 803 .

[0215] When an insulating film containing gallium oxide is used, the insulating film containing gallium oxide has an amorphous structure. The first oxide semiconductor film 403a is formed in an oxygen atmosphere. In an atmosphere of 100% oxygen, an oxide film of In:Ga:Zn=3:1:2 [atomic ratio] was formed. The film is formed using a target, and the c-axis is the normal vector of the film formation surface or the normal vector of the surface. Aligned in a direction parallel to the vector and triangular or hexagonal when viewed from a direction perpendicular to the ab plane When viewed from the direction perpendicular to the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are arranged in a The second acid is added to the crystal part arranged in layers, which is called CAAC-OS film. The compound semiconductor film 403b is formed by growing In:Ga:Zn= The CAAC-OS film was formed using an oxide target with an atomic ratio of 1:1:1. Furthermore, when a transistor is finally completed, the first oxide semiconductor film 403a and the second oxide semiconductor film 403b are The total thickness of the compound semiconductor film 403b is set to 5 nm or more and 10 nm or less. In the above embodiment, an example in which an oxide semiconductor film having a crystal part is formed immediately after the film formation is shown. The crystal portion may be formed by heat treatment.

[0216] A first oxide semiconductor film 403a is formed on and in contact with an insulating film made of a gallium oxide film. A gate insulating film 402 made of a gallium oxide film is formed on and in contact with the oxide semiconductor film 403b of the second electrode. In the case where the first oxide semiconductor film 403a and the second oxide semiconductor film 4 Oxygen can be efficiently supplied to the gallium oxide film. The gate insulating film 402 made of a gallium oxide film can suppress unnecessary release of oxygen. Therefore, the first oxide semiconductor film 403a can be kept in an oxygen-excess state. In the transistor 803, oxygen vacancies in the first oxide semiconductor film 403a and at the interface are efficiently eliminated. It will be possible to compensate for the loss.

[0217] In the NAND circuit shown in FIG. 8C, transistor 8, which is a p-channel transistor, 11 and 814 have a structure similar to that of the transistor 750 shown in FIG. 7 and are n-channel transistors. The transistors 812 and 813 are the same as the transistor 610 shown in FIG. A transistor using an oxide semiconductor film having a thin region in a channel formation region is used. There are.

[0218] In the NAND circuit shown in FIG. 8C, the transistors 812 and 813 are The electrical characteristics of the transistor are controlled by a layer that overlaps the gate electrode layer through a semiconductor film. A conductive layer is provided. The potential of the conductive layer is controlled to, for example, GND, thereby 2,813 threshold voltage is made more positive, and furthermore, it is made a normally-off transistor. In this embodiment, in the NAND circuit, the transistor 812 The conductive layers provided in the transistor 813 and functioning as back gates are electrically connected to each other. However, the present invention is not limited to this example, and a conductive material that can function as the back gate may be used. The layers may each be electrically controlled independently.

[0219] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using transistors with extremely small capacitance, power consumption can be significantly reduced. .

[0220] In addition, stacking semiconductor elements using different semiconductor materials allows for miniaturization and high integration. A semiconductor device that realizes the above and is provided with stable and high electrical characteristics, and manufacturing method of the semiconductor device A method can be provided.

[0221] In this embodiment, the transistor described in Embodiment 1 or 2 is used. Although the examples of the NOR type circuit and the NAND type circuit are shown, the present invention is not particularly limited to the above. An AND circuit, an OR circuit, or the like can be formed using the transistor described in Embodiment 2. For example, the transistor described in Embodiment 1 or 2 can be used to It is possible to retain memory contents even when power is not supplied, and there is no limit to the number of times it can be written. It is also possible to fabricate semiconductor devices (memory devices).

[0222] FIG. 9 shows a circuit diagram of the semiconductor device.

[0223] In FIG. 9, the first wiring (1st Line) and the source electrode layer of the transistor 160 are electrically connected to the second line (2nd Line) and the drain of the transistor 160. The transistor 160 is electrically connected to the gate electrode layer of the transistor 160 shown in Embodiment 3. The transistors 740 and 750, the transistor 802 shown in this embodiment, and the like can be used.

[0224] In addition, the third wiring (3rd Line) and the source electrode layer or the drain electrode layer of the transistor 162 The fourth line and the transistor electrode layer are electrically connected to each other. The gate electrode layer of the transistor 160 is electrically connected to the gate electrode layer of the transistor 162. The gate electrode layer of the transistor 162 and the other of the source electrode layer and the drain electrode layer of the transistor 162 are The fifth wiring (5th Line) is electrically connected to one of the electrodes of the capacitor element 164. The other electrode of the capacitor 164 is electrically connected.

[0225] The transistor 162 is the same as the transistor 440a described in Embodiment 1 or 2. 440b, 440c, 440d, 441a, 441b, 441c, 441d, 441e, Either the transistor 610 described in Embodiment 3 or the transistor 803 described in this embodiment Either structure can be used.

[0226] In the semiconductor device having the circuit configuration shown in FIG. 9, the potential of the gate electrode layer of the transistor 160 By taking advantage of the feature that information can be stored, it is possible to write, store, and read information as follows: It is possible.

[0227] The writing and retention of data will be explained. First, the potential of the fourth wiring is applied to the transistor The potential is set to a level at which the transistor 162 is turned on, thereby turning on the transistor 162. The potential of the third wiring is applied to the gate electrode layer of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode layer of the transistor 160. (Write). Here, charges that give two different potential levels (hereinafter referred to as Low-level charges) , High level charge) is given. Then, the fourth wiring The potential of the transistor 162 is set to a potential at which the transistor 162 is turned off. By setting the transistor 160 in this state, the charge applied to the gate electrode layer of the transistor 160 is held. (hold).

[0228] Since the off-state current of the transistor 162 is extremely small, the gate electrode layer of the transistor 160 The charge is retained for a long time.

[0229] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 The second wiring has a different potential depending on the amount of charge held in the electrode layer. If the transistor 160 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 160. The apparent threshold voltage V for a given charge th_H The gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 160 is turned on. This refers to the potential of the fifth wiring required to achieve the "state." The potential of V th_H and V th_LBy setting the potential V0 between For example, in writing, the charge given to the gate electrode layer can be determined. If a Bell charge is applied, the potential of the fifth wire is V0 (>V th_H ) then When a low level charge is applied, the transistor 160 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 160 remains "off" Therefore, by observing the potential of the second wiring, the stored information It can be read out.

[0230] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 160 is in the "off state" regardless of V th_H Alternatively, a smaller potential may be applied to the fifth wiring. The potential at which transistor 160 is in the "on" state, i.e., V th_L Larger potential is given to the fifth wire.

[0231] FIG. 10 shows an example of a different storage device structure.

[0232] FIG. 10 is a perspective view of a storage device. The storage device shown in FIG. A memory cell array (memory cell array 3400(1) to memory cell array 3400(2)) including a plurality of memory cells. The memory cell array 3400(n) has a plurality of layers, and the memory cell array 340 Logic circuits 300 required to operate memory cell arrays 3400(1) to 3400(n) It has 4.

[0233] In FIG. 10, the logic circuit 3004, the memory cell array 3400(1), and the memory cell array 3400(2) is shown, and the memory cell array 3400(1) or the memory cell array Among the multiple memory cells included in 3400(2), memory cell 3170a and memory cell The memory cell 3170a and the memory cell 3170b are shown as representatives. For example, the same circuit configuration as that of FIG. 9 described in this embodiment may be used. .

[0234] The transistors included in the memory cell 3170a and the memory cell 3170b are oxidized. A transistor is used in which the thin region of the oxide semiconductor film is used as the channel formation region. Regarding the structure of a transistor in which a region with a small thickness of a semiconductor film is used as a channel formation region, The configuration is the same as that described in the first or second embodiment, so the description is omitted. do.

[0235] In addition, the logic circuit 3004 uses a semiconductor material other than an oxide semiconductor for a channel formation region. For example, a transistor is formed on a substrate containing a semiconductor material (e.g., silicon). An element isolation insulating layer is provided, and a region to be a channel forming region is formed in the region surrounded by the element isolation insulating layer. The transistor can be obtained by forming the , semiconductor films such as polycrystalline silicon films formed on insulating surfaces, and silicon films of SOI substrates. It may be a transistor in which a channel formation region is formed.

[0236] Memory cell arrays 3400(1) to 3400(n) and logic circuit 30 04 is stacked with an interlayer insulating layer in between, and is appropriately connected by electrodes and wiring that penetrate the interlayer insulating layer. Electrical connections and the like can be made.

[0237] In the semiconductor device described in this embodiment, a region of the oxide semiconductor film having a small thickness is used as a channel forming region. By using a transistor with extremely low off-state current, It is possible to retain the stored contents for a long time. In other words, refresh operations are not required. Or, the frequency of refresh operations can be reduced significantly, so power consumption can be reduced sufficiently. Furthermore, when there is no power supply (however, the potential is fixed), Even if the storage device is in a non-volatile memory (preferably a hard disk drive), it is possible to retain the stored contents for a long period of time.

[0238] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0239] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0240] This embodiment mode can be freely combined with embodiment mode 1, embodiment mode 2, or embodiment mode 3. It can be adjusted.

[0241] (Embodiment 5) In this embodiment, the semiconductor device shown in Embodiment 1 or 2 will be described as an example of a semiconductor device. Transistors 440a, 440b, 440c, 440d, 441a, 441b, 441c, 441d, 441e at least in part using either one of the CPU (Central P This section explains the Processing Unit.

[0242] FIG. 11(A) is a block diagram showing a specific configuration of the CPU. The PU is provided on a substrate 1190 with an ALU 1191 (ALU: Arithmetic logic c unit, arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189(R The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 are provided on a separate chip. Of course, the CPU shown in FIG. 11(A) is an example in which the configuration is simplified. However, actual CPUs have a wide variety of configurations depending on their use.

[0243] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0244] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0245] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by an internal clock generator. Supply to the seed circuit.

[0246] In the CPU shown in FIG. 11A, a memory cell is provided in the register 1196. The memory cells of the register 1196 are the same as those disclosed in the fourth embodiment. can be done.

[0247] In the CPU shown in FIG. 11A, the register controller 1197 controls the ALU 1191 The holding operation in register 1196 is selected according to the instruction from register 1196. In the memory cell of the data buffer 1196, data is held by a flip-flop. The flip-flop is used to select whether to hold data using a capacitor. When retention is selected, the power supply voltage is supplied to the memory cells in the register 1196. If data retention in the capacitive element is selected, the data is written to the capacitive element. The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. can.

[0248] Regarding power supply shutdown, as shown in FIG. 11(B) or FIG. 11(C), A switching element is connected between nodes to which the power supply potential VDD or VSS is applied. The circuits shown in FIGS. 11(B) and 11(C) are explained below. Do the following.

[0249] In FIG. 11B and FIG. 11C, a switch for controlling the supply of a power supply potential to a memory cell is shown. The switching element includes the transistors 440a and 440b shown in Embodiment 1 or 2. Any one of 440c, 440d, 441a, 441b, 441c, 441d, or 441e 1 shows an example of the configuration of a memory circuit including:

[0250] The memory device shown in FIG. 11B includes a switching element 1141 and a memory cell 1142. Specifically, each memory cell 1142 has: The memory cells described in the third embodiment can be used. Each memory cell 1142 has a high level through a switching element 1141. The power supply potential VDD is supplied to the memory cells 1143. The potential of the signal IN and the potential of the low-level power supply potential VSS are applied to 1142. .

[0251] In FIG. 11B, the switching element 1141 is the one described in the first embodiment or the second embodiment. The transistors 440a, 440b, 440c, 440d, 441a, 441b, 4 41c, 441d, or 441e, and the transistor has a gate The switching is controlled by a signal SigA applied to the electrode layer.

[0252] In FIG. 11B, the switching element 1141 has only one transistor. However, there is no particular limitation to the configuration, and a plurality of transistors may be included. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the series and parallel connections may be combined.

[0253] In FIG. 11B, a memory cell group 1143 is enabled by a switching element 1141. The supply of a high-level power supply potential VDD to each memory cell 1142 is controlled. The supply of the low-level power supply potential VSS is controlled by the switching element 1141. That's fine.

[0254] In addition, in FIG. 11C, each memory cell 1142 included in the memory cell group 1143 is A low-level power supply potential VSS is supplied to the memory device through the switching element 1141. The switching element 1141 switches each memory cell in the memory cell group 1143. The supply of a low-level power supply potential VSS to the memory cell 1142 can be controlled.

[0255] A switch is provided between the memory cell group and a node to which the power supply potential VDD or VSS is applied. When a switching element is installed to temporarily stop CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, and power consumption can be reduced. Specifically, for example, a user of a personal computer inputs information into an input device such as a keyboard. You can stop the CPU from operating while you are no longer entering information, which will save you money. Power consumption can be reduced.

[0256] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0257] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0258] (Embodiment 6) In this embodiment mode, an example of manufacturing a display device using a bottom-gate transistor will be described. The bottom gate type transistor can be manufactured by the same method as in the first embodiment or the second embodiment. For example, after forming the gate electrode layer, the oxide insulating layer is formed. An insulating film is formed, and then an oxide semiconductor film is laminated without CMP processing, and a source electrode is formed on top of that. The source electrode layer and the drain electrode layer can be formed. After forming the drain electrode layer, wet etching is performed with diluted hydrofluoric acid to remove part of the oxide semiconductor film. By thinning the portion, a channel-etched transistor can be manufactured.

[0259] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element can change its brightness depending on the current or voltage. This category includes elements that are controlled by the Also included are electronic ink displays (e-page displays), organic EL displays, etc. It can also be used for display media in which the contrast changes due to electrical effects, such as LCD. .

[0260] One mode of a display device will be described with reference to Fig. 12. In Fig. 12, a liquid crystal element is used as a display element. An example of a liquid crystal display device using a device will be shown.

[0261] The liquid crystal display device can be a vertical electric field type or a horizontal electric field type. 12(B) shows an example of a vertical electric field type, and F An example of using FS (Fringe Field Switching) mode is shown below.

[0262] However, in the display panel, the transistor 4010 provided in the pixel portion 4002 is connected to the display element. The display element is not particularly limited as long as it can display. A variety of display elements can be used.

[0263] As shown in FIG. 12, the display device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrodes 4015 and the terminal electrodes 4016 are anisotropically connected to the terminals of the FPC 4018. They are electrically connected via a conductive layer 4019 .

[0264] The connection terminal electrode 4015 is formed from the same conductive layer as the first electrode layer 4034, and the terminal electrode 4 016 is the same conductor as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. The insulating layer is formed of a conductive layer.

[0265] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a substrate 4001. In FIG. 12, the pixel portion 4002 includes a transistor 4010. and a transistor 4011 included in the scan line driver circuit 4004. In this example, an insulating layer 4032 is provided over the transistors 4010 and 4011 .

[0266] In FIG. 12B, a planarization insulating layer 4040 is provided over the insulating layer 4032. An insulating layer 4042 is provided between the electrode layer 4034 and the second electrode layer 4031 .

[0267] The transistors 4010 and 4011 are the transistors described in Embodiment 1 or 2. The transistors 4010 and 4011 are bottom gate transistors. It's Jista.

[0268] The transistors 4010 and 4011 have a second oxide layer that functions as a current path (channel). a first oxide semiconductor film having a lower carrier density than a second oxide semiconductor film, and a second oxide semiconductor film sandwiched between the first oxide semiconductor film and the second oxide semiconductor film; Therefore, the transistors 4010 and 4011 have a current path. It is a buried channel transistor in which the gate is kept away from the insulating layer interface, and has a high field efficiency. In addition, the influence of the interface state that may be formed on the back channel side is reduced. At the same time, the light degradation of the transistor (for example, negative bias light degradation) is reduced, resulting in high reliability. It is a small transistor.

[0269] In addition, the oxide semiconductor film overlaps with the channel formation region of the transistor 4011 for the driver circuit. A conductive layer may be further provided at a position overlapping with the channel formation region of the oxide semiconductor film. By providing the transistor 4011 at a position where the threshold voltage of the transistor 4011 is higher than the threshold voltage of the transistor 4011, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. In addition, the conductive layer has a potential equal to that of the gate electrode layer of the transistor 4011. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer may be GND, 0V, or may be in a floating state.

[0270] The conductive layer also shields external electric fields, i.e., prevents external electric fields from reaching the internal It also has a function (particularly an electrostatic shielding function against static electricity) to prevent it from acting on the circuitry (including the circuit section). The shielding function of the conductive layer prevents the transistor from being electrically damaged by external electric fields such as static electricity. Fluctuations in characteristics can be prevented.

[0271] In FIG. 12, the liquid crystal element 4013 includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer 4008. Note that the liquid crystal layer 4008 is sandwiched between two layers that function as alignment films. Insulating layers 4038 and 4033 are provided.

[0272] In FIG. 12A, the second electrode layer 4031 is provided on the substrate 4006 side, and the first electrode layer 4 The liquid crystal layer 4008 is disposed between the first electrode layer 4034 and the second electrode layer 4031 . In FIG. 12B, the second electrode layer 4008 has an opening pattern below the liquid crystal layer 4008. 4031, and a flat plate-shaped The first electrode layer 4034 is a second electrode layer having an opening pattern in FIG. The layer 4031 has a shape including bent portions and branched comb-like shapes. The first electrode layer 4031 and the second electrode layer 4032 are arranged in the same shape and do not overlap each other in order to generate an electric field between the electrodes. A flat second electrode layer 4031 is formed on and in contact with the planarization insulating layer 4040. A pixel electrode having an opening pattern is formed on the second electrode layer 4031 via an insulating layer 4042. The first electrode layer 4034 may have a line.

[0273] The first electrode layer 4034 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide , silicon oxide-doped indium tin oxide, graphene, and other transparent conductive materials Fees can be used.

[0274] The first electrode layer 4034 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the metals, alloys thereof, or metal nitrides thereof. Cut.

[0275] The first electrode layer 4034 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or Copolymers consisting of two or more of aniline, pyrrole and thiophene, or derivatives thereof Examples include:

[0276] The spacers 4035 are columnar spacers obtained by selectively etching the insulating layer. and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Spherical spacers may also be used.

[0277] When liquid crystal elements are used as display elements, thermotropic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, These liquid crystal materials can be low molecular weight compounds or high molecular weight compounds. These liquid crystal materials (liquid crystal compositions) may exhibit a cholesteric phase, a smectic phase, or the like depending on the conditions. These phases include nematic, cubic, chiral, and isotropic phases.

[0278] In addition, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008, the first electrode layer 4034, and the second electrode layer 4031 The blue phase is one of the liquid crystal phases, and when the temperature of the cholesteric liquid crystal is increased, The blue phase is the phase that appears just before the transition from the cholesteric phase to the isotropic phase. It can be expressed by using a liquid crystal composition in which a chiral agent and a blue colorant are mixed. In order to widen the temperature range in which the blue phase appears, a polymerizable monomer is added to the liquid crystal composition that appears the blue phase. A polymerization initiator may also be added to form a liquid crystal layer by carrying out a polymer stabilization process. The liquid crystal composition exhibiting the blue phase has a short response time and is optically isotropic, so Since alignment treatment is not required, the viewing angle dependency is small. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This makes it possible to reduce defects and damage to the liquid crystal display device during the manufacturing process. This makes it possible to improve the productivity of the display device.

[0279] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in this document are those measured at 20°C.

[0280] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size of the oxide film may be set in consideration of the off-state current of the transistor. By using a transistor with a semiconductor film, the liquid crystal capacitance in each pixel It is sufficient to provide a storage volume having a size of 1 / 3 or less, preferably 1 / 5 or less, of the capacity of the do.

[0281] The transistor including the oxide semiconductor film disclosed in this specification has a current value ( Therefore, the retention time of electrical signals such as image signals can be controlled to be low. The refresh interval can be set to a longer value. This reduces the power consumption.

[0282] In addition, a transistor including an oxide semiconductor film disclosed in this specification has high field-effect mobility. For example, such a transistor can be used in a liquid crystal display device. By using this in a device, the switching transistor in the pixel section and the driver used in the drive circuit section can be The bar transistor can be formed on the same substrate. By using such a transistor, high-quality images can be provided.

[0283] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Comp Ensulated Birefringence mode, FLC (Ferrerolect ric Liquid Crystal) mode, AFLC (AntiFerroele You can use modes such as electrolytic Liquid Crystal.

[0284] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used. It can also be applied to VA type liquid crystal display devices. VA type liquid crystal display devices are: It is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. VA type liquid crystal display devices are When no voltage is applied, the liquid crystal molecules are oriented perpendicular to the panel surface. Also, a pixel is divided into several regions (subpixels), each of which is oriented in a different direction. This is called multi-domain or multi-domain design, which is designed to knock down molecules. The following method can be used.

[0285] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0286] The display method in the pixel section uses a progressive method, an interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each dot of the color element. is not limited to color display devices, but also applies to monochrome display devices. It is also possible.

[0287] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0288] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element. An example using an organic EL element is shown below.

[0289] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes needs to be light-transmitting. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite to the substrate. There are various types of light sources, including top emission, bottom emission, and light emission from the substrate side and the opposite side of the substrate. There are light emitting elements with a double-sided emission structure that emits light from both sides, and light emitting elements of any emission structure can be applied. It is possible.

[0290] 13A and 13B show examples of a light-emitting device using a light-emitting element as a display element.

[0291] FIG. 13A is a plan view of the light emitting device, and dashed lines S1-T1 and S2- The cross sections cut at T2 and S3-T3 correspond to FIG. 13(B). In the plan view, the electroluminescent layer 542 and the second electrode layer 543 are omitted and not shown. do not have.

[0292] The light-emitting device shown in FIG. 13 includes a transistor 510, a capacitor 520, and wirings on a substrate 500. The transistor 510 has a layer intersection 530, and is electrically connected to the light emitting element 540. 13 shows a bottom emission light source that passes through the substrate 500 and extracts light from the light emitting element 540. This is a light emitting device with a molded structure.

[0293] The transistor 510 is a bottom-gate transistor.

[0294] The transistor 510 includes gate electrode layers 511a and 511b, gate insulating films 501 and 502, The first oxide semiconductor film 512a, the n-type second oxide semiconductor film 512b, and the third oxide semiconductor film 512c are The oxide semiconductor stack 512 including the semiconductor film 512c is used as a source electrode layer or a drain electrode layer. The transistor 510 includes conductive layers 513a and 513b that function as a gate insulating layer. 25 has been formed.

[0295] The capacitor element 520 includes conductive layers 521a and 521b, gate insulating films 501 and 502, a first oxide film, and a a second oxide semiconductor film 522a containing an impurity imparting n-type conductivity; an oxide semiconductor stack 522 including a third oxide semiconductor film 522c and a conductive layer 523; The conductive layers 521a and 521b and the conductive layer 523 form the gate insulating films 501 and 502 and the oxide film. A capacitance is formed by sandwiching the semiconductor laminate 522.

[0296] The wiring layer intersection 530 is an intersection between the gate electrode layers 511a and 511b and the conductive layer 533. The gate electrode layers 511a and 511b and the conductive layer 533 are provided with a gate insulating film 501 therebetween. , 502.

[0297] In this embodiment, the gate electrode layer 511a and the conductive layer 521a are formed to a thickness of 30 nm. A titanium film of 200 nm thick was used as the gate electrode layer 511b and the conductive layer 521b. Therefore, the gate electrode layer has a stacked structure of a titanium film and a copper film.

[0298] The transistor 510 has a second oxide semiconductor film sandwiched therebetween, the second oxide semiconductor film serving as a current path (channel). The first oxide semiconductor film and the third oxide semiconductor film have a lower carrier density than the second oxide semiconductor film. Therefore, the current path of the transistor 510 is kept away from the insulating layer interface. It is a buried channel transistor with high field effect mobility. The influence of the interface state that may be formed on the back channel side is reduced, and the This is a highly reliable transistor with reduced light degradation (for example, negative bias light degradation).

[0299] The transistor 510 also has a gate insulating film 502 with a reduced ammonia content. A first nitrogen-containing silicon film, a thick film (for example, a thickness of 300 The second silicon film containing nitrogen has reduced defects in the film (nm), and the third silicon film has reduced hydrogen concentration. The gate insulating film 501 includes a stacked structure of a silicon film containing nitrogen and an oxide insulating layer. With this structure, the electrical characteristics of the transistor 510 are The transistor 510 can be prevented from being damaged by electrostatic discharge. Therefore, it becomes possible to provide highly reliable semiconductor devices with a high yield.

[0300] An interlayer insulating layer 504 is formed on the transistor 510, the capacitor element 520, and the wiring layer intersection 530. A color filter is formed on the interlayer insulating layer 504 in an area overlapping the light emitting element 540. A flat insulating layer 504 is provided on the interlayer insulating layer 504 and the color filter layer 505. An insulating layer 506 is provided which functions as a protective insulating layer.

[0301] A first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked in this order on an insulating layer 506. The light emitting element 540 includes a stacked structure. 510 is an opening formed in the insulating layer 506 and the interlayer insulating layer 504 that reaches the conductive layer 513a. At this point, the first electrode layer 541 and the conductive layer 513a are in contact with each other, thereby forming an electrical connection. A partition wall 507 is provided to cover a part of the first electrode layer 541 and the opening. It is being done.

[0302] The insulating layer 506 is a photosensitive acrylic film with a thickness of 1500 nm, and the partition wall 507 is a nm photosensitive polyimide film can be used.

[0303] The color filter layer 505 may be made of, for example, a transparent resin of a chromatic color. As the colored light-transmitting resin, photosensitive or non-photosensitive organic resins can be used. The use of a functional organic resin layer reduces the number of resist masks, simplifying the process. And preferable.

[0304] Chromatic colors are colors other than achromatic colors such as black, gray, and white. It is made of materials that transmit only colored light. Chromatic colors include red, green, and blue. Also, cyan, magenta, yellow, etc. may be used. The color filter layer transmits only light of the selected chromatic color. The color filter layer has a peak at the wavelength of light of It is advisable to appropriately control the optimum film thickness taking into consideration the relationship between the concentration of the color and the light transmittance. The thickness of the filter layer 505 may be set to 1500 nm or more and 2000 nm or less.

[0305] The partition wall 507 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin material. An opening is formed on the first electrode layer 541 using a material, and the sidewall of the opening has a continuous curvature. It is preferable to form the inclined surface so that the inclined surface is formed with a curved surface.

[0306] The electroluminescent layer 542 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's

[0307] The second electrode layer 5 is formed so as to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 540. A protective film may be formed on the insulating film 43 and the partition wall 507. The protective film may be a silicon nitride film, a nitride film, or the like. Silicon oxide films, DLC films, etc. can be formed.

[0308] In addition, in order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 540, A layer containing an organic compound covering 540 may be formed by evaporation.

[0309] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0310] The insulating layer 506, which functions as a planarizing insulating layer, is made of acrylic resin, polyimide, benzo Uses heat-resistant organic materials such as cyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, siloxane resin, PSG (phosphor glass), B Low-k materials such as PSG (Phosphorus-Boron Glass) can be used. The insulating layer 506 is formed by stacking a plurality of insulating layers made of these materials. You may do so.

[0311] The method for forming the insulating layer 506 is not particularly limited, and may be a sputtering method, a spin-on method, or the like, depending on the material. Coating, dipping, spray coating, droplet ejection method (inkjet method), screen printing , offset printing, etc. can be used.

[0312] The first electrode layer 541 and the second electrode layer 543 are the same as those of the first electrode layer of the display device shown in FIG. The layer 4034 can be made of the same material as the second electrode layer 4031 .

[0313] In this embodiment, the light emitting device shown in FIG. 13 is a bottom emission type, so the first electrode layer 54 The first electrode layer 541 has a light-transmitting property, and the second electrode layer 543 has a reflective property. When a film is used, the film thickness is set to be small enough to maintain light-transmitting properties, and the second electrode layer 543 is set to have light-transmitting properties. When a conductive layer having reflectivity is used, it is preferable to laminate a conductive layer having reflectivity.

[0314] A protection circuit for protecting the drive circuit may be provided. The protection circuit is configured using a nonlinear element. It is preferable to do so.

[0315] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0316] (Embodiment 7) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic devices include televisions, monitors, and other display devices, lighting devices, and desktop Or a laptop computer, word processor, DVD (Digital Playing still images or videos stored on recording media such as a Versatile Disc image playback devices, portable CD players, radios, tape recorders, headphone stereos Audio, stereos, cordless telephone handsets, transceivers, portable radios, mobile phones, car phones , portable game consoles, calculators, personal digital assistants, electronic organizers, e-books, electronic translators, voice input devices High-frequency heating equipment such as electric appliances, video cameras, digital still cameras, electric shavers, and microwave ovens Electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioning equipment such as air conditioners, tableware Washing machines, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerated freezers These include refrigerators, freezers for storing DNA, smoke detectors, radiation detectors, dialysis machines and other medical equipment. In addition, it is used in emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial Examples include industrial equipment such as robots and power storage systems. Also, vehicles propelled by electric motors using power from non-aqueous secondary batteries are included in the category of electrical equipment. The above-mentioned mobile units include, for example, electric vehicles (EVs), internal combustion engines, and Hybrid electric vehicles (HEV) and plug-in hybrid electric vehicles (PHEV) , tracked vehicles in which these tires and wheels are converted into tracks, and motorized vehicles including electrically assisted bicycles. Bicycles, motorcycles, electric wheelchairs, golf carts, small or large boats, submarines, helicopters Examples include robots, aircraft, rockets, satellites, space probes, planetary rovers, and spacecraft. Specific examples of these electronic devices are shown in FIGS. 22 and 23.

[0317] Figures 22(A) and 22(B) show a foldable tablet terminal. 9631a is in an open state, and the tablet terminal includes a housing 9630, a display unit 9631a, and a display unit 9631b, display mode switch 9034, power switch 9035, power saving mode It has a mode changeover switch 9036, a fastener 9033, and an operation switch 9038.

[0318] In the portable devices shown in FIGS. 22(A) and 22(B), image data is temporarily stored. For example, in the fourth embodiment, SRAM or DRAM is used as a memory. The semiconductor device described above can be used as a memory. By using semiconductor devices in memory, writing and reading of information can be performed at high speed and for a long time. It is possible to store and hold data for a certain period of time, and power consumption can be reduced sufficiently. In the portable devices shown in Fig. 22(A) and Fig. 22(B), a CP that performs image processing and calculations is used. The CPU used can be the CPU shown in the fifth embodiment. When used, it is possible to reduce the power consumption of portable devices.

[0319] In addition, a part of the display portion 9631a can be used as a touch panel area 9632a. Data can be input by touching the operation keys 9638 shown on the display unit 963. The display device described in Embodiment 6 can be used for the display portion 9631a. In this case, for example, half of the area has a display function, and the other half has a touch function. Although the display unit 9631a has a configuration having a touch panel function, the present invention is not limited to this configuration. The entire display area may have a touch panel function. The entire surface of the display is used as a touch panel by displaying keyboard buttons, and the display part 9631b is used as a display screen. It can be used as follows.

[0320] In addition, in the display unit 9631b, as in the display unit 9631a, a part of the display unit 9631b The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard can be displayed on the display portion 9631b.

[0321] In addition, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input characters using the touchpad.

[0322] A display mode changeover switch 9034 is used to change the display orientation between portrait and landscape. You can select between black and white and color display. The 9036 is a tablet device that detects external light during use using a built-in light sensor. The display brightness can be optimized according to the amount of light. In addition, other detection devices such as gyro, acceleration sensor, etc. that detect tilt are also included. It may be stored.

[0323] FIG. 22A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other, and the display For example, one display panel may be capable of displaying images with higher resolution than the other. It may also be possible to use the following.

[0324] FIG. 22(B) shows the tablet terminal in a closed state, and the tablet terminal includes a housing 9630, a solar cell 96 33, a charge / discharge control circuit 9634, a battery 9635, and a DC / DC converter 9636 22B, a battery 9635 is used as an example of the charge / discharge control circuit 9634. , a configuration having a DC-DC converter 9636 is shown.

[0325] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the display portions 9631a and 9631b can be withstood. This makes it possible to provide a tablet terminal that is highly durable and reliable even from the perspective of long-term use.

[0326] In addition, the tablet terminals shown in Figs. 22(A) and 22(B) can store various information. Functions that display information (still images, videos, text images, etc.), calendars, dates, or times, etc. The function to display the information on the display unit, and the function to operate or edit the information displayed on the display unit by touch input. It has the function of controlling the processing by various software (programs), etc. This can be done.

[0327] The solar cell 9633 attached to the surface of the tablet terminal supplies power to the touch panel, The solar cell 9633 can be supplied to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by the battery 9630. The battery 9635 may be a lithium-ion battery. This has the advantage of enabling miniaturization.

[0328] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 22(B) will be described with reference to FIG. ) shows a block diagram and explains. In FIG. 22(C), a solar cell 9633, a battery 96 35, DC-DC converter 9636, converter 9637, switches SW1 to SW3, The display unit 9631 is shown, along with the battery 9635 and the DC-DC converter 9636. The converter 9637 and the switches SW1 to SW3 constitute a charge / discharge control circuit shown in FIG. This corresponds to road 9634.

[0329] First, an example of operation when power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is converted to a voltage to charge the Battery 9635. The voltage is increased or decreased by a C converter 9636. When power is being used from the battery 9633, the switch SW1 is turned on and the converter 96 37 increases or decreases the voltage to the voltage required for the display unit 9631. When not displaying in 31, turn SW1 off and SW2 on to charge the battery. 35 charging configuration.

[0330] The solar cell 9633 is shown as an example of a power generating means, but is not particularly limited thereto. Other power generation methods such as piezoelectric elements (piezoelectric elements) and thermoelectric elements (Peltier elements) For example, it may be configured to transmit and receive power wirelessly (contactlessly). A wireless power transmission module that charges by transmitting power, or a configuration that combines other charging methods It may also be possible to use the following.

[0331] In FIG. 23A, a television device 8000 includes a housing 8001 and a display unit 8002. It displays images on a display unit 8002 and outputs audio from a speaker unit 8003. It is possible to output it.

[0332] The display unit 8002 may be a liquid crystal display device as shown in the sixth embodiment, an organic EL display device as shown in the sixth embodiment, or the like. Light-emitting devices having light-emitting elements such as elements in each pixel, electrophoretic displays, DMDs (Digit al Micromirror Device), PDP(Plasma Displa A semiconductor display device such as a LCD panel can be used.

[0333] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via Recipient) or two-way (between sender and recipient, or between recipients) information communication It is also possible.

[0334] The television device 8000 also includes a CPU and memory for performing information communication. The television device 8000 may include the memory shown in the fourth embodiment and the memory shown in the fifth embodiment. The CPU shown can be used.

[0335] In FIG. 23(A), an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is shown. This is an example of an electrical device using the CPU of the fifth embodiment. The device includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. Although the CPU 8203 is provided in the indoor unit 8200, 203 may be provided in the outdoor unit 8204. Alternatively, the indoor unit 8200 and the outdoor unit 82 The CPU 8203 may be provided in both the CPU 04 and the CPU 8203 shown in the fifth embodiment. Using it in the CPU of an air conditioner can help save energy.

[0336] In FIG. 23A, an electric refrigerator-freezer 8300 includes a CPU using an oxide semiconductor. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator compartment, 23A, the C The PU 8304 is provided inside the housing 8301. By using it in the CPU 8304 of the electric refrigerator-freezer 8300, power saving can be achieved.

[0337] FIG. 23(B) shows an example of an electric vehicle, which is an example of an electric device. The power of the secondary battery 9701 is supplied to the control circuit 97 The output is adjusted by the control circuit 9702 and supplied to the driving device 9703. It is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. (not shown). By using the CPU shown in form 5 as the CPU of the electric vehicle 9700, power saving can be achieved. It can be planned.

[0338] The driving device 9703 is a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 is configured in combination with the electric vehicle 9700. (acceleration, deceleration, stopping, etc.) and driving information (uphill and downhill slopes, etc., load on the drive wheels) Based on input information (such as cargo information), the control circuit 9702 outputs a control signal. 702 is supplied with electric energy from a secondary battery 9701 in response to a control signal from a processing unit 9704. It adjusts the energy and controls the output of the drive unit 9703. When an AC motor is installed Although not shown, the inverter for converting direct current to alternating current is also built in.

[0339] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Example]

[0340] In this example, a part of a cross section of a transistor using a CAAC-IGZO film is shown in FIG. A partial cross-sectional view of a transistor using an amorphous-IGZO film is shown in Figure 15. 14(A) and 15(A) show cross-sectional TEM images, and FIG. 14(B) and FIG. 15(B) show cross-sectional TEM images. A schematic diagram of the surface is shown.

[0341] In the transistor of this embodiment, after the source electrode layer and the drain electrode layer are formed, Using the layer as a mask, wet etching is performed on the IGZO film, and a thin area is formed on the IGZO film. The CAAC-IGZO film and the amorphous-IGZO film have different crystal structures. The crystal structure is different (amorphous-IGZO film is more crystalline than CAAC-IGZO film). is low).

[0342] Specifically, the wet etching was performed using 0.0025% hydrofluoric acid. 5% hydrofluoric acid can be prepared by mixing 1990 ml of water (H2O) with 10 ml of 0.5% HF. It was produced by.

[0343] The transistor in the above-described embodiment is made of a CAAC-IGZO film shown in FIG. The transistor using the amorphous-IGZO film shown in Figure 15 The star was prepared for comparison.

[0344] The samples used in this example will be described in detail below.

[0345] Sample A shown in Figure 14 was grown using a target with an atomic ratio of In:Ga:Zn=3:1:2. The first layer was formed using a target with an atomic ratio of In:Ga:Zn=1:1:1. The sample B shown in Figure 15 was a CAAC-IGZO film with a second layer stacked using I A single layer amorphous film formed using a target with an atomic ratio of n:Ga:Zn=1:1:1 A GaN-IGZO film was used.

[0346] <Sample A> A silicon oxide film (SiOx film) was deposited on a silicon substrate by sputtering for 30 minutes as a base film. After that, a CAAC-IGZO film was deposited on the underlayer to a thickness of 150 nm by sputtering. The CAAC-IGZO film was deposited with a target atomic ratio of In:Ga:Zn=3:1:2. The first layer of CAAC-IGZO was deposited at 5 nm using a target, and then the first layer of CAAC -Two layers were deposited on the IGZO film using a target with an atomic ratio of In:Ga:Zn=1:1:1 The first CAAC-IGZO film was deposited to a thickness of 10 nm. Then, a W film was deposited to a thickness of 100 nm as a metal film. The film is formed and then ICP (Inductively Coupled Plasma) The metal film was etched using an ICP etching system using the plasma etching method. .

[0347] The deposition conditions for the SiOx film were as follows: a single crystal silicon target was used, and the deposition pressure was 0.4 Pa. The Ar flow rate was set to 25 sccm, the O2 flow rate was set to 25 sccm, and the film formation temperature was set to 100°C (based The target temperature was 100°C, and the input power using a DC power supply was 5 kW. The distance was set to 60 mm.

[0348] The deposition conditions for the CAAC-IGZO film (3:1:2) were In:Ga:Zn=3:1:2. The deposition pressure was 0.4 Pa and the Ar flow rate was 30 sccm. The O2 flow rate was set to 45 sccm, the film formation temperature was set to 308°C (substrate temperature 250°C), and the DC power The input power was set to 0.5 kW, and the distance between the target and the substrate was set to 60 mm.

[0349] The deposition conditions for the CAAC-IGZO film (1:1:1) were In:Ga:Zn=1:1:1. The deposition pressure was 0.4 Pa and the Ar flow rate was 30 sccm. The O2 flow rate was set to 45 sccm, the film formation temperature was set to 416°C (substrate temperature 350°C), and the DC power The input power was set to 0.5 kW, and the distance between the target and the substrate was set to 60 mm.

[0350] The first etching conditions for the W film were a pressure of 0.67 Pa and a CF4 flow rate of 55 sccm. The Cl2 flow rate was set to 45 sccm, the O2 flow rate to 55 sccm, and the substrate temperature to 40°C. The ICP power was 3000 W (0.76 W / cm 2 ) and the bias power is 11 0W (0.07W / cm 2 ) and the etching time was 10 seconds. The W film was etched to provide areas with a thinner film thickness.

[0351] The second etching conditions for the W film were a pressure of 3.0 Pa and an O 2 flow rate of 55 sccm. The substrate temperature was set to 40°C. The ICP power was set to 2000 W (0.51 W / cm 2 )year, The bias power was set to 0 W, and the etching time was set to 15 seconds. The area of ​​the mask was reduced.

[0352] The third etching condition for the W film was a pressure of 0.67 Pa and a CF4 flow rate of 55 sccm. The Cl2 flow rate was set to 45 sccm, the O2 flow rate to 55 sccm, and the substrate temperature to 40°C. The ICP power was 3000 W (0.76 W / cm 2 ) and the bias power is 11 0W (0.07W / cm 2 ) and the etching time was 15 seconds. Then, the W film was further etched.

[0353] <Sample B> A 300 nm SiOx film was formed as an underlayer on a silicon substrate by sputtering. After that, an amorphous IGZO film was deposited to a thickness of 15 nm on the underlayer by sputtering. Amorphous IGZO films are grown using a target with an atomic ratio of In:Ga:Zn=1:1:1. After that, a 100 nm W film was formed as a metal film, and then the film was placed in an ICP etching device. The metal film was etched further.

[0354] The deposition conditions for the SiOx film were as follows: a single crystal silicon target was used, and the deposition pressure was 0.4 Pa. The Ar flow rate was set to 25 sccm, the O2 flow rate was set to 25 sccm, and the film formation temperature was set to 100°C (based The input power using a DC power supply was set to 5 kW, and the target and substrate The distance between the plates was 60 mm.

[0355] The deposition conditions for the amorphous IGZO film were In:Ga:Zn=1:1:1 atomic ratio. The deposition pressure was set to 0.4 Pa, the Ar flow rate was set to 30 sccm, and the O2 flow rate was set to 1 The deposition temperature was room temperature (substrate temperature 23 to 25°C). The input power used was 0.5 kW, and the distance between the target and the substrate was 60 mm.

[0356] The first etching conditions for the W film were a pressure of 0.67 Pa and a CF4 flow rate of 55 sccm. The Cl2 flow rate was set to 45 sccm, the O2 flow rate to 55 sccm, and the substrate temperature to 40°C. The ICP power was set to 3000 W (0.76 W / cm 2 ) and the bias power is set to 11 0W (0.07W / cm 2 ) and the etching time was set to 13 seconds.

[0357] The second etching conditions for the W film were a pressure of 3.0 Pa and an O2 flow rate of 55 sccm. The substrate temperature was set to 40°C. The ICP power was set to 2000 W (0.51 W / cm 2 )year, The bias power was set to 0 W, and the etching time was set to 15 seconds.

[0358] The third etching condition for the W film was a pressure of 0.67 Pa and a CF4 flow rate of 55 sccm. The Cl2 flow rate was set to 45 sccm, the O2 flow rate to 55 sccm, and the substrate temperature to 40°C. The ICP power was set to 3000 W (0.76 W / cm 2 ) and the bias power is set to 11 0W (0.07W / cm 2 ) and the etching time was set to 12 seconds.

[0359] The above-mentioned samples A and B were subjected to wet etching using 0.0025% hydrofluoric acid. We conducted a survey.

[0360] The wet etching conditions were as follows: etching time for sample A was 86 seconds, and for sample B The etching time for sample A was 23 seconds. The etching temperature for Plue B was also set to 25°C.

[0361] In this embodiment, the temperature of the diluted hydrofluoric acid is preferably 25°C or higher and 40°C or lower.

[0362] In this embodiment, the concentration of the diluted hydrofluoric acid is preferably 0.25% or less. The concentration of diluted hydrofluoric acid is preferably 0.0025% (i.e., 25 ppm) or less. The lower limit is 0.0001% (i.e. 1 ppm), and any higher concentration is acceptable. When the concentration is higher than 0.0025%, the etching rate of the IGZO film becomes faster, and the above-mentioned This may deteriorate the electrical characteristics of the transistor in the embodiment and reduce its reliability. Therefore, in order to achieve a thin IGZO film in the channel formation region, 0. It is preferable to set it to 0.025% or less.

[0363] Figures 14 and 15 show the CAAC-IGZO film and the IGZO film after wet etching with diluted hydrofluoric acid. The cross-sectional shapes of the amorphous-IGZO film and amorphous-IGZO film are shown.

[0364] As shown in Figure 14(A), the CAAC-IGZO film has a thin film thickness (due to wet etching). The cross-sectional shape of the boundary area between the thicker region and the thinner region rises in the direction of the film thickness. It was found that the cross-sectional shape was smoothly tapered in the forward taper direction. By providing this area, the distance between the lower end of the metal film and the thin area can be increased, and CA The cross section of the AC-IGZO film can be formed into a concave shape. The boundary region is shown in the schematic diagram of FIG. 14(B), and a continuous film is formed from the boundary with the thin region. The thickness of the oxide insulating film is increased to form a thick region. The taper angle θ1 between the surface is greater than 0° and less than 90°, preferably greater than or equal to 20° and less than or equal to 70°. The taper angle θ2 is the angle between the side surface of the metal film and the surface of the oxide insulating film. The difference from the taper angle θ1 is within 20°, preferably within 10°, More preferably, they are the same angle. If the difference between the taper angle θ1 and the taper angle θ2 is small, the metal The side surface of the film and the surface of the boundary region can be said to be smooth. It was confirmed that the taper angle θ2 was less than 90°. In the cross-sectional shape of the oxide semiconductor film, the oxide insulating film surface and the boundary region (thick region and thin region) In Figure 14(B), the oxide insulating film The taper angles θ1 and θ2 are shown as angles formed with the base film (SiOx film). Since the surface is almost parallel to the plate surface, the taper angle θ1 and the taper angle θ 2 is calculated in the same way. When a layer is provided, the surface of the oxide insulating film may not be flat, making it difficult to use it as a reference surface. In order to do this, the taper angles θ1 and θ2 should be determined based on the angles formed with the substrate surface. Etching does not progress directly below the metal film (W) used as a barrier. It was confirmed that etching proceeded anisotropically in the CAAC-IGZO film.

[0365] As shown in Figure 15(A), the amorphous-IGZO film has a wet-etched area. The metal film (W) used as a mask is hollowed out and overlaps the lower part of the mask. Therefore, it was found that the amorphous-IGZO film had a fin-hanging shape. It was confirmed that etching proceeded isotropically.

[0366] From the results of Fig. 14(A) and Fig. 15(A), it is clear that the difference in crystal structure affects wet etching. After that, the cross-sectional shape of the CAAC-IGZO film was different from that of the amorphous-IGZO film. It can be considered that the difference between the CAAC-IGZO film and the amorphous-IGZO film It is suggested that the difference in the crystal structure of the will be done.

[0367] In addition, the surface of the boundary region of the CAAC-IGZO film and the side surface at the edge of the metal film are smooth. Since the film is almost flush with the surface, it is easier to The coverage of the gate insulating film and gate electrode layer formed on the GZO film can be improved. Furthermore, it was found that even if the thickness of the gate insulating film is small, step discontinuities are unlikely to occur. This suggests that it is possible.

[0368] In addition, the CAAC-IGZO film was wet-etched using diluted hydrofluoric acid. This suggests that the film thickness in the panel-forming region can be controlled more accurately. [Example]

[0369] In this example, the CAAC-IGZO film was wet etched using diluted hydrofluoric acid. The metal film (W) adheres to the CAAC-IGZO film during etching. Contaminants Cl2, C, F caused by process gases (CF4 gas, Cl2 gas) in , HEPA filter (High Efficiency Particulate Air) in the device Contaminants caused by scattering from glass fibers used in the Air Filter B, and contaminants such as Al, which are caused by components contained in the etching chamber materials, have been significantly reduced. The reduction is shown in FIGS. 16 to 20.

[0370] The measurement is performed using secondary ion mass spectrometry (SIMS). The primary ions were incident on the sample surface. When the sample is heated, various particles such as electrons, neutral particles, and ions are emitted from the sample surface. Quantitative analysis involves separating the ions (secondary ions) from these particles by mass, and then This is a method for qualitatively and quantitatively determining the components contained in a sample by measuring the amount of detected ions.

[0371] The samples used in the measurements in this example will be described in detail below.

[0372] As shown in Figure 21, samples C and D were used for the measurement. The difference between sample C and sample D shown in FIG. 21(B) is 0.0 for sample C. The only difference was that wet etching was performed using 0.25% hydrofluoric acid; other conditions were In addition, samples C and D have the same composition of In:Ga:Zn=1:1:1. A single layer CAAC-IGZO film was used, which was deposited using a target with a molecular ratio of 1.0.

[0373] <Sample C and Sample D> A 300 nm SiOx film was formed as an underlayer on a silicon substrate by sputtering. After that, a CAAC-IGZO film was formed on the underlayer by sputtering to a thickness of 50 nm. A 100 nm W film was formed as a metal film, and the metal film was etched using an ICP etching device. After that, a gate insulating film was formed on the CAAC-IGZO film and the metal film by PCVD. A silicon oxynitride film (also called an SiON film) was formed to a thickness of 100 nm by the method.

[0374] The deposition conditions for the SiOx film were as follows: a single crystal silicon target was used, and the deposition pressure was 0.4 Pa. The Ar flow rate was set to 25 sccm, the O2 flow rate was set to 25 sccm, and the film formation temperature was set to 100°C (based The target temperature was 100°C. The input power using a DC power supply was 5 kW. The distance between the substrates was set to 60 mm.

[0375] The deposition conditions for the CAAC-IGZO film were as follows: In:Ga:Zn=1:1:1 atomic ratio target The deposition pressure was set to 0.4 Pa, the Ar flow rate was set to 30 sccm, and the O2 flow rate was set to 45 The deposition temperature was 416°C (substrate temperature 350°C). The input power was set to 0.5 kW, and the distance between the target and the substrate was set to 60 mm.

[0376] The first etching conditions for the W film were a pressure of 0.67 Pa and a CF4 flow rate of 55 sccm. The Cl2 flow rate was set to 45 sccm, the O2 flow rate to 55 sccm, and the substrate temperature to 40°C. The ICP power was set to 3000 W (0.76 W / cm 2 ) and the bias power is set to 11 0W (0.07W / cm 2 ) and the etching time was set to 13 seconds.

[0377] The second etching conditions for the W film were a pressure of 3.0 Pa, an O2 flow rate of 55 sccm, and a substrate The plate temperature was set to 40°C. The ICP power was set to 2000W (0.51W / cm 2 ) and The bias power was set to 0 W, and the etching time was set to 15 seconds.

[0378] The third etching condition for the W film was a pressure of 0.67 Pa and a CF4 flow rate of 55 sccm. The Cl2 flow rate was set to 45 sccm, the O2 flow rate to 55 sccm, and the substrate temperature to 40°C. The ICP power was set to 3000 W (0.76 W / cm 2 ) and the bias power is set to 11 0W (0.07W / cm 2 ) and the etching time was set to 12 seconds.

[0379] The conditions for forming the SiON film were a film forming pressure of 40 Pa, a SiH4 flow rate of 1 sccm, and N The 2O flow rate was set to 800 sccm, and the film formation temperature was set to 400°C (substrate temperature 400°C).

[0380] Only the prepared sample C was subjected to wet etching using 0.0025% hydrofluoric acid. Ta.

[0381] The wet etching conditions for sample C were an etching time of 72 seconds, The temperature was set to 25°C or higher and 40°C or lower.

[0382] The measurement results are shown in Figures 16 to 20.

[0383] Figure 16 shows the Cl concentration near the CAAC-IGZO film in samples C and D. (unit: atoms / cm 3 ) is compared. It can be seen that a large amount of Cl remains near the CAAC-IGZO film compared to pull C. Ta.

[0384] Figure 17 shows the Al concentration near the CAAC-IGZO film in samples C and D. (unit: atoms / cm 3 ) is compared. It can be seen that more Al remains near the CAAC-IGZO film than in pull C. Ta.

[0385] Figure 18 shows the C concentration ( Unit: atoms / cm 3 ) is a graph comparing the sample D. It was confirmed that more C remained near the CAAC-IGZO film than in the ZnO film.

[0386] Figure 19 shows the F concentration ( Unit: atoms / cm 3 ) is a graph comparing the results of sample D and sample C. In all cases, it was confirmed that a large amount of F remained near the CAAC-IGZO film.

[0387] Figure 20 shows the B concentration ( Unit: atoms / cm 3 ) is a graph comparing the results of sample D and sample C. In all cases, it was confirmed that a large amount of B remained near the CAAC-IGZO film.

[0388] Considering the measurement results shown in Figures 16 to 20, it is possible to obtain CAAC-IGZO using diluted hydrofluoric acid. By wet etching the film, contaminants remaining near the CAAC-IGZO film are removed. The adhesion of contaminants to the transistors can significantly reduce the quality of the switches. Therefore, the transistor performance is likely to deteriorate and the electrical characteristics are likely to fluctuate. By significantly reducing contaminants that have adverse effects on the A transistor using a wet-etched CAAC-IGZO film in the channel formation region In semiconductor devices with stators, stable electrical characteristics can be imparted, improving reliability. It suggests that it is possible. [Example]

[0389] In this example, diluted hydrofluoric acid was used to form CAAC-IGZO films and amorphous-IGZO films. Wet etching is performed on the film, and the etching rate ( The IGZO film with the thinned channel formation region was used as a transistor. When applying it to a transistor, the CAAC-IGZO film was used rather than the amorphous-IGZO film. Measurement results show that this method can improve the performance of transistors.

[0390] The samples used had the same sample structure as Sample A and Sample B in Example 1. Therefore, the description of the first embodiment can be referred to for details.

[0391] Sample A with CAAC-IGZO film, sample B with amorphous-IGZO film Each of B was wet etched using 0.0025% hydrofluoric acid. The wet etching conditions were also the same as those in Example 1.

[0392] The etching rate was measured using a spectroscopic ellipsometer UT300. 2.7cm x 12.7cm) surface was measured at 25 points and the 25 measured values ​​were averaged did.

[0393] As a result of the measurement, the average etching rate of the CAAC-IGZO film was approximately 4.3 nm / min. The average etching rate of the amorphous-IGZO film is approximately 12.9 nm / min. Therefore, the etching rate of the amorphous-IGZO film was The etching rate of CAAC-IGZ is about three times faster than that of The thickness of the O film is easier to control than that of the amorphous-IGZO film.

[0394] Because the etching rate of the CAAC-IGZO film is slow, wet etching is performed using diluted hydrofluoric acid. By thinning the CAAC-IGZO film by etching, the CAA This suggests that the thickness of the CAAC-IGZO film can be controlled more precisely. The thickness of the gate insulating film formed on the ZO film is smaller than that of the oxide semiconductor film. It is suggested that it is possible to improve the coverage of the gate insulating film even in cases where the That is, wet etching is performed using diluted hydrofluoric acid to remove the etched CAAC-IGZO film. This suggests that the performance of transistors can be improved by thinning the channel formation region. . [Explanation of symbols]

[0395] 400: Substrate 401: gate electrode layer 401a: gate electrode layer 401b: gate electrode layer 402: Gate insulating film 403: Oxide semiconductor film 403a: Oxide semiconductor film 403b: Oxide semiconductor film 403c: Oxide semiconductor film 405a: Source electrode layer 405b: Drain electrode layer 406: Conductive film 407: Insulating film 408a: Resist mask 408b: Resist mask 409: Protective layer 410a: Protective layer 410b: Protective layer 431: Oxygen 434: Insulating film 435: Oxide insulating film 436: Oxide insulating film 438: Insulating film 440a:Transistor 440b:Transistor 440c:Transistor 440d:Transistor 441a:Transistor 441b:Transistor 441c:Transistor 441d:Transistor 441e:Transistor 480: oxide insulating film 481:Oxygen excess region 482: Insulating film 484: Oxide insulating film 485: Interlayer insulating film 486: Barrier metal film 487: Low resistance conductive layer 488: Barrier metal film 491: Conductive layer 492: Conductive layer 493: Oxide insulating film 610:Transistor 647: Wiring layer 657: Wiring layer 658: Wiring layer 682: Insulating film 684: Insulating film 686: Insulating film 687: Insulating film 690: Capacitor element 692: Wiring layer 693a: Capacitive electrode layer 693b: Capacitive electrode layer 700: Circuit board 740:Transistor 741: Gate electrode layer 742: Gate insulating film 743: Channel formation region 744:n-type impurity region 745:N-type impurity region 746: Sidewall insulating layer 748: Wiring layer 750:Transistor 751: Gate electrode layer 752: Gate insulating film 753: Channel formation region 754:p-type impurity region 755:p-type impurity region 756: Sidewall insulating layer 760: Circuit 788: Insulating film 789: Element isolation region 800: Substrate 801:Transistor 802:Transistor 803:Transistor 811:Transistor 812:Transistor 813:Transistor 814:Transistor 825: Electrode layer 826: Insulating film 830: insulating film 831: Wiring layer 832: Wiring layer 833: insulating film 834: Wiring layer 835: Wiring layer 842: Conductive layer 845a: Electrode layer 845b: Electrode layer

Claims

1. an oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer; a second conductive layer having a region located above the oxide semiconductor layer; a first insulating layer having a region located above the first conductive layer; a second insulating layer having a region located above the second conductive layer; a third insulating layer having a region located above the first insulating layer, a region located above the oxide semiconductor layer, and a region located above the second insulating layer; the first conductive layer functions as one of a source electrode and a drain electrode of a transistor, the second conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor layer has a channel formation region of the transistor, the oxide semiconductor layer has a first region, a second region, and a third region located between the first region and the second region; the first region overlaps the first conductive layer; the second region overlaps the second conductive layer; the third region does not overlap the first conductive layer; the third region does not overlap the second conductive layer; a film thickness of the third region is smaller than a film thickness of the first region and smaller than a film thickness of the second region; the third insulating layer has a region in contact with the third region, the first conductive layer has a fourth region and a fifth region; the fifth region has a smaller film thickness than the fourth region; the fifth region is disposed at an end of the first conductive layer; the second conductive layer has a sixth region and a seventh region; the seventh region has a smaller film thickness than the sixth region; the seventh region is disposed at an end of the second conductive layer; the first insulating layer has a region in contact with the fourth region and a region in contact with the fifth region, and does not have a region in contact with the oxide semiconductor layer; the second insulating layer has a region in contact with the sixth region and a region in contact with the seventh region, and does not have a region in contact with the oxide semiconductor layer.

2. an oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer; a second conductive layer having a region located above the oxide semiconductor layer; a first insulating layer having a region located above the first conductive layer; a second insulating layer having a region located above the second conductive layer; a third insulating layer having a region located above the first insulating layer, a region located above the oxide semiconductor layer, and a region located above the second insulating layer; the first conductive layer functions as one of a source electrode and a drain electrode of a transistor, the second conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor layer has a channel formation region of the transistor, the oxide semiconductor layer has a first region, a second region, and a third region located between the first region and the second region; the first region overlaps the first conductive layer; the second region overlaps the second conductive layer; the third region does not overlap the first conductive layer; the third region does not overlap the second conductive layer; a film thickness of the third region is smaller than a film thickness of the first region and smaller than a film thickness of the second region; the third insulating layer has a region in contact with the third region, the first conductive layer has a fourth region and a fifth region; the fifth region has a smaller film thickness than the fourth region; the fifth region is disposed at an end of the first conductive layer; the second conductive layer has a sixth region and a seventh region; the seventh region has a smaller film thickness than the sixth region; the seventh region is disposed at an end of the second conductive layer; the first insulating layer has a different material than the third insulating layer; the second insulating layer has a different material than the third insulating layer; the first insulating layer has a region in contact with the fourth region and a region in contact with the fifth region, and does not have a region in contact with the oxide semiconductor layer; the second insulating layer has a region in contact with the sixth region and a region in contact with the seventh region, and does not have a region in contact with the oxide semiconductor layer.

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