Power conversion device

Abstract

To provide a power conversion device that achieves the suppression of current unbalance and the improvement of the reliability of a signal input part.SOLUTION: A power conversion device includes a plurality of semiconductor packages including a semiconductor element and a source conductor bonded to a source electrode of the semiconductor element, and a printed wiring board where the semiconductor packages are mounted. The printed wiring board includes a source wiring pattern to which each source conductor is electrically connected in parallel, a gate signal wiring pattern that transmits a gate driving signal to the semiconductor element, and a source signal wiring pattern that transmits a control source signal to the semiconductor element. The source signal wiring pattern is connected to the source wiring pattern in an inner layer of the printed wiring board.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] A power conversion device converts DC power into AC power by switching an inverter circuit having switching elements configured in upper and lower arms. When multiple switching elements are connected in parallel in each arm of the inverter circuit, differences in wiring inductance occur in the wiring to each switching element when the switching elements are connected in parallel along the wiring. This causes differences in switching speed and causes an imbalance in the current flowing through each switching element.

[0003] As an example of a solution to the problem of inductance, for example, Patent Document 1 listed below discloses a configuration in which, in a power conversion circuit configured by connecting a multilayer wiring board to the upper surfaces of switching elements that make up upper and lower arms, the device in the lower arm is inverted to eliminate the intermediate electrode conductor, thereby shortening the current path and reducing inductance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2020-161680 Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the technology described in Patent Document 1, an object of the present invention is to provide a power conversion device that suppresses current imbalance and improves the reliability of a signal input section. [Means for solving the problem]

[0006] The power conversion device comprises a plurality of semiconductor packages each having a semiconductor element and a source conductor to which a source electrode of the semiconductor element is joined, and a printed wiring board on which the plurality of semiconductor packages are mounted, the printed wiring board having a source wiring pattern to which the source conductors are electrically connected in parallel, a gate signal wiring pattern for transmitting a gate drive signal to the semiconductor element, and a source signal wiring pattern for transmitting a control source signal to the semiconductor element, the source signal wiring pattern being connected to the source wiring pattern on an inner layer of the printed wiring board. [Effects of the Invention]

[0007] It is possible to provide a power conversion device that suppresses current imbalance and improves the reliability of the signal input section. [Brief explanation of the drawings]

[0008] [Figure 1] 1A and 1B are a plan view and a cross-sectional view of a semiconductor package according to an embodiment of the present invention; [Figure 2] FIG. 2 is a plan view of the semiconductor package as viewed from direction B in FIG. 1. [Figure 3] 1 is a plan view of a semiconductor package mounted on a printed wiring board according to an embodiment of the present invention; [Figure 4] 1 is a plan view of a printed wiring board according to an embodiment of the present invention; [Figure 5] 4 is a cross-sectional view taken along line CC of the power converter of FIG. 3 according to one embodiment of the present invention. [Figure 6] 1 is an electrical circuit diagram of a power conversion device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0010] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0011] (One embodiment and overall configuration) (Fig. 1, Fig. 2) Fig. 1(a) is a plan view of a semiconductor package 10 of the present invention, Fig. 1(b) is a cross-sectional view taken along line AA in Fig. 1(a), Fig. 2(a) is a plan view of the semiconductor package 10 as viewed from direction B in Fig. 1(b), Fig. 2(b) is a plan view in which the molding resin 6 has been removed from Fig. 2(a), and Fig. 2(c) is a plan view in which the source conductor 4 has been removed from Fig. 2(b).

[0012] The semiconductor package 10 has a drain conductor 3, a source conductor 4, a drain terminal 11, a gate terminal 12, a temperature detection terminal 13, and a semiconductor element 20. Each component in the semiconductor package 10 is molded with a molding resin 6.

[0013] The semiconductor element 20 has a source electrode 21, a drain electrode, a gate signal electrode 23, and a source signal electrode 24. The drain electrode is not shown in the figure because it is provided on the surface of the semiconductor element 20 opposite to the source electrode 21. The gate terminal 12 and the gate signal electrode 23 are connected by a bonding wire 5.

[0014] On one surface of the semiconductor element 20, a drain electrode of the semiconductor element 20 is joined to a drain conductor 3 via solder 2. On the other surface of the semiconductor element 20, a source electrode 21 of the semiconductor element 20 is joined to a source conductor 4 via solder 2. A drain terminal 11 is connected to the drain conductor 3.

[0015] In the present invention, a bonding wire 5 is connected to the gate signal electrode 23, but a bonding wire 5 is not connected to the source signal electrode 24. The source conductor 4 of the semiconductor package 10 is bonded to a source wiring pattern on a printed wiring board 30 (described later) on the side opposite to the side bonded to the semiconductor element 20, thereby eliminating the need to connect a bonding wire 5 to the source signal electrode 24 of the semiconductor element 20. Therefore, there is no need to worry about the effects of heat generation at the wire bonding portion used for signal input, and reliability in the signal input portion can be ensured.

[0016] (Figure 3) Fig. 3(a) is a plan view of a printed wiring board 30 mounted with multiple semiconductor packages 10, and Fig. 3(b) is a plan view of Fig. 3(a) with the semiconductor packages 10 removed. The printed wiring board 30 is formed in four layers, and Fig. 3 shows only the first layer.

[0017] A plurality of semiconductor packages 10 are mounted on a printed wiring board 30. In a power conversion device 50, an upper arm drain wiring pattern 31, which is a high-potential side wiring pattern, an output wiring pattern 32, and a lower arm source wiring pattern 33, which is a low-potential side wiring pattern, are formed on the first layer of the printed wiring board 30. The output wiring pattern 32 includes an upper arm source wiring pattern and a lower arm drain wiring pattern. The upper arm source wiring pattern 32 and the lower arm source wiring pattern 33 are electrically connected in parallel to the source conductors of the plurality of semiconductor packages 10, respectively.

[0018] The printed wiring board 30 and the upper arm drain wiring pattern 31 have a capacitor connecting through-hole via 35. The output wiring pattern 32 has an output through-hole via 39.

[0019] Additionally, an upper arm gate signal wiring pattern 36H and a lower arm gate signal wiring pattern 36L are formed on the first layer of the printed wiring board 30. The upper arm gate signal wiring pattern 36H has a through-hole via 41H for connecting gate signals to an upper arm gate drive circuit. The lower arm gate signal wiring pattern 36L has a through-hole via 41L for connecting gate signals to a lower arm gate drive circuit. The upper arm gate signal wiring pattern 36H and the lower arm gate signal wiring pattern 36L transmit gate drive signals to the semiconductor element 20 of the semiconductor package 10 via the gate terminal 12 (FIG. 1).

[0020] Furthermore, the printed wiring board 30 is formed with a through-hole via 42H for connecting source signals of the upper arm gate drive circuit and a through-hole via 42L for connecting source signals of the lower arm gate drive circuit.

[0021] The upper arm semiconductor packages 10H are connected to the upper arm drain wiring pattern 31, the output wiring pattern 32, and the signal wiring pattern 36H. The lower arm semiconductor packages 10L are connected to the output wiring pattern 32, the lower arm source wiring pattern 33, and the signal wiring pattern 36L. The output wiring pattern 32 and the lower arm source wiring pattern 33 have a plurality of through-hole vias 38.

[0022] The multiple upper arm semiconductor packages 10H and the multiple lower arm semiconductor packages 10L are arranged on the printed wiring board 30 along the first direction 15. Furthermore, the current flowing through the source wiring patterns 32, 33 flows along the first direction 15. As a result, each semiconductor package 10 is connected to the source wiring patterns 32, 33, and a parasitic inductance 62 of the source wiring pattern is generated between each semiconductor package 10. This causes a problem of current imbalance.

[0023] (Figure 4) 4(a) is a plan view of the second layer of the printed wiring board 30, and FIG. 4(b) is a plan view of the third and fourth layers of the printed wiring board 30. The printed wiring board 30 has multiple layers, and an upper arm source signal wiring pattern 37H is provided on the second layer, which is the lower layer of the multiple layers of the printed wiring board 30, and the upper arm source signal wiring pattern 37H is connected to the upper arm source wiring pattern 32. Similarly, a lower arm source signal wiring pattern 37L is provided on the second layer, which is the lower layer of the printed wiring board 30, and the lower arm source signal wiring pattern 37L is connected to the lower arm source wiring pattern 33. The lower arm source wiring pattern 33 and the output wiring pattern 32 are formed on the third and fourth layers of the printed wiring board 30.

[0024] As described above, the source conductors of each semiconductor package 10 are connected to the upper arm source wiring pattern 32 and the lower arm source wiring pattern 33, and therefore the upper arm side source signal wiring pattern 37H and the lower arm side source signal wiring pattern 37L transmit control source signals to the semiconductor elements 20 of each semiconductor package 10 via the upper arm source wiring pattern 32 and the lower arm source wiring pattern 33 which are connected on the inner layer of the printed wiring board 30.

[0025] The upper arm source signal wiring pattern 37H is connected to a source signal connecting through-hole via 42H (FIG. 3) of the upper arm gate drive circuit, and the lower arm source signal wiring pattern 37L is connected to a source signal connecting through-hole via 42L (FIG. 3) of the lower arm gate drive circuit.

[0026] (Fig. 5, Fig. 6) 6, DC power output from a battery (not shown) is smoothed by a smoothing capacitor 80 and input to the power conversion device 50. The smoothed DC power is input to each upper arm semiconductor package 10H via a positive-side capacitor connecting through-hole via 35 and an upper arm drain wiring pattern 31, and is also input to each lower arm semiconductor package 10L via a negative-side capacitor connecting through-hole via 35 and a lower arm source wiring pattern 33.

[0027] The upper arm gate signal wiring pattern 36H is connected to the gates of each upper arm semiconductor package 10H and is connected to the gate drive circuit 70 via a gate signal connecting through-hole via 41H. Similarly, the upper arm source signal wiring pattern 37H is connected to the source side of each upper arm semiconductor package 10H and is connected to the gate drive circuit 70 via a gate signal connecting through-hole via 41L.

[0028] The lower arm gate signal wiring pattern 36L is connected to the gate of each lower arm semiconductor package 10L and is connected to the gate drive circuit 70 via a source signal connecting through-hole via 42H. Similarly, the lower arm source signal wiring pattern 37L is connected to the source side of each lower arm semiconductor package 10L and is connected to the gate drive circuit 70 via a source signal connecting through-hole via 42L.

[0029] 5, in the printed wiring board 30, source wiring patterns 32 and 33 are formed on each of multiple layers arranged in the stacking direction. The source conductor 4 of the semiconductor package 10 is joined to the source wiring patterns 32 and 33 formed on the first layer of the printed wiring board 30 on the surface opposite to the surface connected to the semiconductor element 20 (FIG. 1). As a result, a source signal is input via the parasitic inductance 60 of the source conductor 4, eliminating the need for a bonding wire 5 for inputting the source signal to the semiconductor element, thereby simplifying the terminals of the semiconductor package 10 and the wiring pattern of the printed wiring board 30.

[0030] Furthermore, in the second layer of the printed wiring board 30, the source signal wiring patterns 37H and 37L are connected to the upper arm source wiring pattern 32 and the lower arm source wiring pattern 33, which are the main current paths of the printed wiring board 30. As a result, a source signal is input to the semiconductor element from the lower layer of the printed wiring board 30 via the parasitic inductance 61 of the through-hole via 38 and the parasitic inductance 60 of the source conductor 4.

[0031] In this way, the voltage generated in the parasitic inductance 60 of the source conductor 4 reduces the gate voltage of the semiconductor package 10 where the current is concentrated, thereby suppressing the current imbalance. Furthermore, since the total inductance of the parasitic inductances 61 and 60 is large, the source signal is input to the semiconductor element via these two inductances, thereby further improving the effect of suppressing the current imbalance.

[0032] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0033] (1) A power conversion device 10 is provided, which includes a plurality of semiconductor packages 10, each having a semiconductor element 20 and a source conductor 4 to which a source electrode 21 of the semiconductor element 20 is joined, and a printed wiring board 30 on which the plurality of semiconductor packages 10 are mounted, the printed wiring board 30 having source wiring patterns 32, 33 to which the source conductors 4 are electrically connected in parallel, a gate signal wiring pattern 36 that transmits a gate drive signal to the semiconductor element 20, and a source signal wiring pattern 37 that transmits a control source signal to the semiconductor element 20, the source signal wiring pattern 37 being connected to the source wiring patterns 32, 33 on an inner layer of the printed wiring board 30. In this way, a power conversion device 100 can be provided that suppresses current imbalance and improves the reliability of the signal input section.

[0034] (2) The multiple semiconductor packages 10 are arranged along the first direction 15, and the current flowing through the source wiring patterns 32, 33 flows along the first direction 15. By applying the present invention to such a structure, it is possible to suppress current imbalance.

[0035] (3) The source conductor 4 is bonded to the source wiring patterns 32, 33 on the surface opposite to the surface bonded to the semiconductor element 20. This simplifies the terminals of the semiconductor package 10 and the wiring pattern of the printed wiring board 30.

[0036] (4) The printed wiring board 30 has multiple layers, the source wiring patterns 32 and 33 are formed on each of the multiple layers, and the source signal wiring pattern 37 is provided on a lower layer of the multiple layers. This configuration can improve the effect of suppressing current imbalance.

[0037] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted. [Explanation of symbols]

[0038] 2 Solder 3 Drain conductor 4 Source conductor 5 Bonding Wire 6 Molding resin 10 Semiconductor Package 10H Upper arm semiconductor package 10L Lower arm semiconductor package 11 Drain terminal 12 Gate terminal 13 Temperature detection terminal 15 1st direction 20 Semiconductor elements 21 Source electrode 23 Gate signal electrode 24 source signal electrodes 30 Printed wiring board 31 Upper arm drain wiring pattern 32 Output wiring pattern (upper arm source wiring pattern, lower arm drain wiring pattern) 33 Lower arm source wiring pattern 35 Capacitor connection through-hole via 36H Upper arm gate signal wiring pattern 36L Lower arm gate signal wiring pattern 37H Upper arm source signal wiring pattern 37L Lower arm source signal wiring pattern 38 through-hole vias 39 Output through-hole via 41H Gate signal connection through-hole via (upper arm gate drive circuit) 41L Gate signal connection through-hole via (lower arm gate drive circuit) 42H Source signal connection through-hole via (upper arm gate drive circuit) 42L Source signal connection through-hole via (lower arm gate drive circuit) 50 Power conversion device 60 Parasitic inductance of the source conductor 61 Parasitic inductance of through-hole vias 62 Parasitic inductance of source wiring pattern 70 Gate drive circuit 80 Smoothing capacitor 100 Power conversion device

Claims

1. a plurality of semiconductor packages each having a semiconductor element and a source conductor to which a source electrode of the semiconductor element is joined; a printed wiring board on which the plurality of semiconductor packages are mounted, the printed wiring board has a source wiring pattern to which the source conductors are electrically connected in parallel, a gate signal wiring pattern for transmitting gate drive signals to the semiconductor elements, and a source signal wiring pattern for transmitting control source signals to the semiconductor elements; The source signal wiring pattern is connected to the source wiring pattern on an inner layer of the printed wiring board. Power conversion device.

2. The power conversion device according to claim 1, The plurality of semiconductor packages are arranged along a first direction, The current flowing through the source wiring pattern flows in the first direction. Power conversion device.

3. The power conversion device according to claim 2, The source conductor is bonded to the source wiring pattern on the surface opposite to the surface bonded to the semiconductor element. Power conversion device.

4. The power conversion device according to claim 1, the printed wiring board has multiple layers; the source wiring patterns are formed in the plurality of layers, The source signal wiring pattern is provided in a lower layer of the plurality of layers. Power conversion device.

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