Semiconductor package and manufacturing method for the same

Abstract

To provide a semiconductor package that can embody a small form factor to maximize the heat dissipation characteristic, and can improve the reliability, and a manufacturing method for the same.SOLUTION: A semiconductor package includes: a first rewiring board; a first semiconductor chip disposed on the right side in a first direction on the first rewiring board; a first penetration post disposed on the left side of the first semiconductor chip in the first direction on the first rewiring board; a second rewiring board disposed on the first semiconductor chip and the first penetration post; a second semiconductor chip disposed on the left side in the first direction on the second rewiring board; a second penetration post disposed on the right side of the second semiconductor chip in the first direction on the second rewiring board; a third rewiring board disposed on the second rewiring board and the second penetration post; a heat dissipation block disposed on the left side in the first direction on the third rewiring board; and a semiconductor element disposed on the right side of the heat dissipation block in the first direction on the third rewiring board.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including two logic chips and a method for manufacturing the same. [Background technology]

[0002] Due to the rapid development of the electronics industry and the needs of users, electronic devices are becoming smaller and lighter. As electronic devices become smaller and lighter, the semiconductor packages used in them are also becoming smaller and lighter. Furthermore, semiconductor packages are required to have high reliability as well as high performance and large capacity. As the performance and capacity of semiconductor packages increase, their power consumption is also increasing. This has led to a growing need for smaller semiconductor packages, improved performance, and improved heat dissipation characteristics. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package that can realize a small form factor, maximize heat dissipation characteristics, and improve reliability, and a manufacturing method thereof.

[0004] Furthermore, the problems to be solved by the present invention are not limited to those mentioned above, and other problems will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] In order to solve the above problem, the present invention provides a semiconductor package including a first rewiring substrate, a first semiconductor chip arranged on the right side in a first direction on the first rewiring substrate, a first through post arranged on the first rewiring substrate to the left of the first semiconductor chip in the first direction, a second rewiring substrate arranged on the first semiconductor chip and the first through post, a second semiconductor chip arranged on the left side in the first direction on the second rewiring substrate, a second through post arranged on the right side of the second semiconductor chip in the first direction on the second rewiring substrate, a third rewiring substrate arranged on the second rewiring substrate and the second through post, a heat dissipation block arranged on the left side in the first direction on the third rewiring substrate, and a semiconductor element arranged on the third rewiring substrate to the right of the heat dissipation block in the first direction.

[0006] In order to solve the above problem, the present invention provides a semiconductor package including: a first redistribution substrate; a first semiconductor chip disposed on the first redistribution substrate on the right side in a first direction; a first through-post disposed on the first redistribution substrate on the left side of the first semiconductor chip in the first direction; a second through-post disposed on the first semiconductor chip; a second semiconductor chip disposed on the first through-post; a second redistribution substrate disposed on the second semiconductor chip and the second through-post; a heat dissipation block disposed on the left side in the first direction on the second redistribution substrate; a semiconductor element disposed on the third redistribution substrate to the right of the heat dissipation block in the first direction; a sealant disposed between the first redistribution substrate and the second redistribution substrate, the sealant covering side surfaces of the first through-post and the second through-post, side surfaces and an upper surface of the first semiconductor element, and side surfaces and a lower surface of the second semiconductor element; and an external connection terminal disposed on the lower surface of the first redistribution substrate.

[0007] Furthermore, in order to solve the above problem, the present invention provides a semiconductor package including a first rewiring substrate, a first semiconductor chip arranged on the right side in a first direction on the first rewiring substrate, a first through post arranged on the first rewiring substrate to the left side of the first semiconductor chip in the first direction, a second through post arranged on the first semiconductor chip, a second semiconductor chip arranged on the first through post, a second rewiring substrate arranged on the second semiconductor chip and the second through post, a heat dissipation block arranged on the left side in the first direction on the second rewiring substrate, and a semiconductor element arranged on the right side of the heat dissipation block in the first direction on the third rewiring substrate.

[0008] Meanwhile, to solve the above problem, the present invention provides a method for manufacturing a semiconductor package, including the steps of forming a first rewiring substrate, forming a first through post on the first rewiring substrate on the left side in a first direction, arranging a first semiconductor chip on the first rewiring substrate to the right of the first through post in the first direction, forming a second rewiring substrate on the first through post and the first semiconductor chip, forming a second through post on the second rewiring substrate on the right side in the first direction, arranging a second semiconductor chip on the second rewiring substrate to the left of the second through post in the first direction, forming a third rewiring substrate on the second semiconductor chip and the second through post, and arranging a heat dissipation block on the third rewiring substrate on the left side in the first direction and arranging a semiconductor element on the right side of the heat dissipation block in the first direction.

[0009] Meanwhile, to solve the above problem, the present invention provides a method for manufacturing a semiconductor package, including the steps of forming a first redistribution substrate, forming a first through-post on the first redistribution substrate on a left side in a first direction, disposing a first semiconductor chip on the first redistribution substrate to the right of the first through-post in the first direction, forming a first sealant covering a side surface of the first through-post and a side surface and a top surface of the first semiconductor chip, forming a second through-post on the first semiconductor chip, disposing a second semiconductor chip on the lower sealant to the left of the second through-post in the first direction, forming an upper sealant covering a side surface of the second through-post and a side surface and a bottom surface of the second semiconductor chip, forming a second redistribution substrate on the second semiconductor chip and the second upper sealant, and disposing a heat dissipation block on the second redistribution substrate on the left side in the first direction and disposing a semiconductor element on the right side of the heat dissipation block. [Effects of the Invention]

[0010] The semiconductor package according to the present invention has a FOWLP structure, which improves heat dissipation characteristics and allows for a small form factor. It is possible to simultaneously realize a small form factor and improve reliability. For example, by arranging the heat dissipation block on the third redistribution substrate in a structure in which it substantially overlaps the second semiconductor chip, which is the upper AP chip, the heat dissipation effect of the second semiconductor chip is improved. Also, by arranging the first semiconductor chip, which is the lower AP chip, and the second semiconductor chip, which is the upper AP chip, in a structure in which they overlap in the z direction, it is possible to realize a small form factor for the semiconductor package. Furthermore, by shortening the connection path between the first semiconductor chip and the second semiconductor chip, it is possible to improve SI (Signal Interconnect). This makes it possible to realize semiconductor packages with improved integrity and reliability. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 2A] 2 is a cross-sectional view showing the structure of a semiconductor element in more detail in the semiconductor package of FIG. 1. FIG. [Figure 2B] 2 is a cross-sectional view showing the structure of a semiconductor element in more detail in the semiconductor package of FIG. 1. FIG. [Figure 2C] 2 is a cross-sectional view showing the structure of a semiconductor element in more detail in the semiconductor package of FIG. 1. FIG. [Figure 3A] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 3B] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 3C] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 4A] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 4B] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 5A] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 5B] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. [Figure 6A] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6B] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6C] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6D] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6E] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6F] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6G]1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6H] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6I] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6J] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6K] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6L] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6M] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6N] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 7A] FIG. 6D is a cross-sectional view showing the stage of FIG. 6C more specifically. [Figure 7B] FIG. 6D is a cross-sectional view showing the stage of FIG. 6C more specifically. [Figure 7C] FIG. 6D is a cross-sectional view showing the stage of FIG. 6C more specifically. [Figure 7D] FIG. 6D is a cross-sectional view showing the stage of FIG. 6C more specifically. [Figure 7E] FIG. 6D is a cross-sectional view showing the stage of FIG. 6C more specifically. [Figure 8A] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 8B] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 8C] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 8D]1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used to designate the same components in the drawings, and redundant description thereof will be omitted.

[0013] FIG. 1 is a cross-sectional view of a semiconductor package according to one embodiment of the present invention.

[0014] Referring to FIG. 1, the semiconductor package 1000 of this embodiment includes first to third redistribution substrates 100-1 to 100-3, a first semiconductor chip 200, a second semiconductor chip 300, a semiconductor device 400, a heat dissipation block 600, first and second through posts 600-1 and 600-2, first and second sealing materials 700-1 and 700-2, and an external connection terminal 800.

[0015] The first redistribution substrate 100-1 is disposed under the first semiconductor chip 200, the first through posts 600-1, and the first sealing material 700-1. The first redistribution substrate 100-1 may serve to redistribute chip pads of the first semiconductor chip 200 to an external region of the first semiconductor chip 200. The first redistribution substrate 100-1 includes a body insulating layer 101, redistribution lines 103, and vertical vias 105.

[0016] The body insulating layer 101 is made of an insulating material, for example, PID (Photo Insulator Layer). The body insulating layer 101 may be formed of a photoimageable dielectric (PIP) or photoimageable polyimide (PIP) resin and may further contain an inorganic filler. However, the material of the body insulating layer 101 is not limited to the above-mentioned materials. For example, the body insulating layer 101 may contain polyimide isoindroquirazorindione (PIQ), polyimide (PI), polybenzoxazole (PBO), etc.

[0017] The body insulating layer 101 has a multi-layer structure due to the multi-layer structure of the redistribution lines 103. However, for convenience, the body insulating layer 101 is shown as a single layer in FIG. 1. However, when the body insulating layer 101 has a multi-layer structure, all layers of the body insulating layer 101 may contain the same material, or at least one layer may contain a different material.

[0018] The redistribution lines 103 are arranged in multiple layers within the body insulating layer 101. Redistribution lines 103 arranged in different layers may be connected to each other by vertical vias 105. Meanwhile, redistribution lines 103 that are located at two or more different levels may be connected to each other by stacking multiple vertical vias 105. Stacked vertical vias 105 are called stacked vias. The redistribution lines 103 and the vertical vias 105 may include, for example, copper (Cu). However, the material of the redistribution lines 103 and the vertical vias 105 is not limited to Cu.

[0019] An external connection terminal 800 is disposed on the lower surface of the body insulating layer 101. The external connection terminal 800 is disposed on an external connection pad disposed on the lower surface of the body insulating layer 101. The external connection pad is included as a part of the redistribution line 103. However, in some embodiments, the external connection pad may be treated as a component separate from the redistribution line 103.

[0020] The first semiconductor chip 200 is disposed on the first redistribution substrate 100-1 via an adhesive layer 230. The first semiconductor chip 200 is disposed offset to one side in the x-direction on the first redistribution substrate 100-1. For example, as shown in FIG. 1, the first semiconductor chip 200 is disposed offset to the right side in the x-direction on the first redistribution substrate 100-1.

[0021] The first semiconductor chip 200 may be a logic chip. Accordingly, the first semiconductor chip 200 may include a plurality of logic elements therein. Here, the logic elements are elements that perform various signal processing, and include, for example, AND, OR, NOT, flip-flops, etc. For example, the first semiconductor chip 200 may include an NPU (Neural Processing Unit). In some embodiments, the first semiconductor chip 200 is a NPU (Numerical Processing Unit) chip that supports communication with the second semiconductor chip 300. However, the type of the first semiconductor chip 200 is not limited to an NPU chip or a modem chip. For example, the first semiconductor chip 200 may include various types of integrated devices for performing individual calculations or supporting the operation of the second semiconductor chip 300. The first semiconductor chip 200 includes a multi-channel I / O interface for exchanging memory signals with the semiconductor device 400. The first semiconductor chip 200 also includes an SRAM for temporarily storing data.

[0022] As shown in FIG. 1 , the first semiconductor chip 200 includes a substrate 201, an active layer 210, and a first connecting terminal 220. The substrate 201 forms the body of the first semiconductor chip 200 and is based on a silicon wafer. The active layer 210 is disposed on an upper portion of the substrate 201. Strictly speaking, the active layer 210 includes an integrated circuit layer in which active elements such as transistors are disposed, and a multiple wiring layer disposed on the integrated circuit layer. Generally, the multiple wiring layer occupies most of the active layer 210, and the integrated circuit layer occupies only a portion of the active layer 210. Meanwhile, the multiple wiring layer includes multiple wiring lines, and the wiring lines of different layers may be connected to each other through vias. Chip pads connected to the wiring lines of the multiple wiring layer are disposed on the upper surface of the active layer 210, and the first connecting terminal 220 is disposed on the chip pads.

[0023] The top surface of the first semiconductor chip 200 is the front side, which is an active surface, and the bottom surface is the back side, which is an inactive surface. In other words, the top surface of the active layer 210 corresponds to the front side of the first semiconductor chip 200, and the bottom surface of the substrate 201 corresponds to the back side of the first semiconductor chip 200. Chip pads are formed on the front side, which is the active side, and first connecting terminals 220 are disposed on the chip pads. The first connecting terminals 220 include metal pillars or solder. In some embodiments, the first connecting terminals 220 include metal pillars and solder. Here, the metal pillars include, for example, Cu. However, the material of the metal pillars is not limited to Cu. The first semiconductor chip 200 is connected to the second redistribution substrate 100-2 via the first connecting terminals 220.

[0024] The first through post 600-1 is disposed between the first redistribution substrate 100-1 and the second redistribution substrate 100-2. A first sealant 700-1 is disposed between the first redistribution substrate 100-1 and the second redistribution substrate 100-2, so that the first through post 600-1 extends in the z-direction through the first sealant 700-1. The first through post 600-1 electrically connects the first redistribution substrate 100-1 and the second redistribution substrate 100-2. For example, the first through post 600-1 is connected to the redistribution line 103 of the lower first redistribution substrate 100-1 and also to the redistribution line of the upper second redistribution substrate 100-2.

[0025] In the semiconductor package 1000 of this embodiment, the first through-posts 600-1 are arranged in a two-dimensional array structure on the first redistribution substrate 100-1 on the left side of the first semiconductor chip 200 in the x-direction. The first through-posts 600-1 are connected to the second semiconductor chip 300 via the second redistribution substrate 100-2. The first through-posts 600-1 are also connected to the semiconductor element 400 via the second redistribution substrate 100-2 and the second through-posts 600-2.

[0026] The first through post 600-1 may include, for example, Cu. Therefore, the first through post 600-1 may be referred to as a Cu-post. However, the material of the first through post 600-1 is not limited to Cu. The first through post 600-1 may be formed by electroplating using a seed metal. The seed metal may include various metal materials such as Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). In the semiconductor package 1000 of this embodiment, the lower pad 610-1 of the first redistribution substrate 100-1 may function as the seed metal. However, depending on the embodiment, the seed metal may be formed separately from the lower pad 610-1.

[0027] The second redistribution substrate 100-2 is disposed on the first semiconductor chip 200, the first through-posts 600-1, and the first sealing material 700-1. The second redistribution substrate 100-2 also includes a body insulating layer, redistribution lines, and vertical vias. The second redistribution substrate 100-2 has a similar structure to the first redistribution substrate 100-1, but differs in thickness. For example, the number of layers of the redistribution lines of the second redistribution substrate 100-2 is smaller than the number of layers of the redistribution lines 103 of the first redistribution substrate 100-1. However, in some embodiments, the number of layers of the redistribution lines of the second redistribution substrate 100-2 may be substantially the same as the number of layers of the redistribution lines 103 of the first redistribution substrate 100-1. Meanwhile, the redistribution lines of the second redistribution substrate 100-2 are connected to the external connection terminals 800 via the first through-posts 600-1 and the first redistribution substrate 100-1.

[0028] The second semiconductor chip 300 is mounted on the second redistribution substrate 100-2 via the second connecting terminals 320. The second semiconductor chip 300 is disposed on the left side of the second redistribution substrate 100-2 in the x-direction, corresponding to the first through-posts 600-1. The second semiconductor chip 300 and the first semiconductor chip 200 at least partially overlap each other in the z-direction. For example, the overlapping area OLA where the second semiconductor chip 300 and the first semiconductor chip 200 overlap each other has an area less than 50% of the area of ​​each of the second semiconductor chip 300 and the first semiconductor chip 200. However, the area of ​​the overlapping area OLA is not limited to the above numerical range. The second semiconductor chip 300 and the first semiconductor chip 200 are connected to each other using the portion of the second redistribution substrate 100-2 corresponding to the overlapping area OLA, thereby minimizing the signal path between the first semiconductor chip 200 and the second semiconductor chip 300.

[0029] In some embodiments, the second semiconductor chip 300 is bonded using pad-to-pad bonding, hybrid bonding, or the like. The second redistribution substrate 100-2 may be mounted on the second redistribution substrate 100-2 by bonding using anisotropic conductive film (HB) or anisotropic conductive film (ACF). For reference, pad-to-pad bonding may also be called Cu-to-Cu bonding because the pads are usually made of Cu. HB refers to a combination of pad-to-pad bonding and insulator-to-insulator bonding. ACF is an anisotropic conductive film that conducts electricity in only one direction, and refers to a conductive film formed into a film by mixing minute conductive particles into an adhesive resin.

[0030] The second semiconductor chip 300 may be a logic chip. As a result, the second semiconductor chip 300 may include a plurality of logic elements therein. In the semiconductor package 1000 of this embodiment, the second semiconductor chip 300 may be, for example, an AP (Application The second semiconductor chip 300 is a control chip, a process chip, a CPU (Central Processing Unit), etc. On the other hand, in terms of integrated functions, the second semiconductor chip 300 may be referred to as a System on a Chip (SoC) together with the first semiconductor chip 200 or independently. It may also be referred to as "on chip."

[0031] The second semiconductor chip 300 includes a substrate 301, an active layer 310, and a second connecting terminal 320. The active layer 310 includes an integrated circuit layer and a multi-wiring layer. The integrated circuit layer includes a plurality of integrated devices. The multi-wiring layer is disposed below the integrated circuit layer and includes multi-layer wiring lines. The lower surface of the second semiconductor chip 300 is the front surface, which is an active surface, and the upper surface is the back surface, which is an inactive surface. In other words, the lower surface of the active layer 310 corresponds to the front surface of the second semiconductor chip 300, and the upper surface of the substrate 301 corresponds to the back surface of the second semiconductor chip 300.

[0032] The second through post 600-2 is disposed between the second redistribution substrate 100-2 and the third redistribution substrate 100-3. A second sealant 700-2 is disposed between the second redistribution substrate 100-2 and the third redistribution substrate 100-3, so that the second through post 600-2 extends in the z-direction through the second sealant 700-2. The second through post 600-2 connects the second redistribution substrate 100-2 and the third redistribution substrate 100-3. For example, the second through post 600-2 is connected to the redistribution line of the lower second redistribution substrate 100-2 and also to the redistribution line of the upper third redistribution substrate 100-3.

[0033] In the semiconductor package 1000 of this embodiment, the second through posts 600-2 are arranged in a two-dimensional array structure on the second redistribution substrate 100-2 on the right side of the second semiconductor chip 300 in the x-direction. The second through posts 600-2 are connected to the semiconductor element 400 via the third redistribution substrate 100-3. The second through posts 600-2 may also be connected to the first semiconductor chip 200 and the second semiconductor chip 300 via the second redistribution substrate 100-2.

[0034] Meanwhile, in the semiconductor package 1000 of this embodiment, the left and right sides in the x direction are relative concepts. Therefore, the positions of the first semiconductor chip 200 and the first through-post 600-1 may be reversed. For example, the first semiconductor chip 200 is disposed offset to the left in the x direction, and the first through-post 600-1 is disposed to the right of the first semiconductor chip 200 in the x direction. Furthermore, the second semiconductor chip 300 is disposed to the right in the x direction corresponding to the first through-post 600-1, and the second through-post 600-2 and the semiconductor element 400 are disposed to the left in the x direction.

[0035] The material and forming method of the second through posts 600-2 are substantially the same as those of the first through posts 600-1. However, the number of the first through posts 600-1 is greater than that of the second through posts 600-2. For example, the number of the first through posts 600-1 is greater than that of the second through posts 600-2 by 30% or more. However, the difference in number between the first through posts 600-1 and the second through posts 600-2 is not limited to the above-mentioned numerical range.

[0036] The third redistribution substrate 100-3 is disposed on the second semiconductor chip 300, the second through-posts 600-2, and the second sealant 700-2. The third redistribution substrate 100-3 also includes a body insulating layer, redistribution lines, and vertical vias. The third redistribution substrate 100-3 has a structure similar to that of the first redistribution substrate 100-1 or the second redistribution substrate 100-2, but differs in thickness. For example, the number of layers of the redistribution lines in the third redistribution substrate 100-3 is fewer than the number of layers of the redistribution lines 100 in the first redistribution substrate 100-1. Specifically, the number of layers of the redistribution lines in the third redistribution substrate 100-3 is fewer than the number of layers of the redistribution lines 103 in the first redistribution substrate 100-1, but more than the number of layers of the redistribution lines in the second redistribution substrate 100-2. However, the number of layers of the redistribution lines in the third redistribution substrate 100-3 is not limited to the above. Meanwhile, the rewiring lines of the third rewiring substrate 100-3 are connected to the first semiconductor chip 200 and the second semiconductor chip 300 via the second through posts 600-2 and the second rewiring substrate 100-2.

[0037] The semiconductor device 400 is mounted on the third redistribution substrate 100-3 via the third connecting terminal 450. The semiconductor device 400 is disposed on the right side of the third redistribution substrate 300-3 in the x direction, corresponding to the second through post 600-2. The semiconductor device 400 may be a single chip or a package including multiple chips. For example, if the semiconductor device 400 is a single chip, the semiconductor device 400 includes one memory chip. If the semiconductor device 400 is a package, the semiconductor device 400 includes, for example, multiple memory chips. The memory chip of the semiconductor device 400 may be, for example, a DRAM (Dynamic Random Access Memory). The semiconductor device 400 may include a volatile memory device such as a DRAM (Dynamic Random Access Memory) or a static random access memory (SRAM), or a non-volatile memory device such as a flash memory. In the semiconductor package 1000 of this embodiment, the memory chip of the semiconductor device 400 is, for example, a DRAM chip. However, the type of memory chip of the semiconductor device 400 is not limited to a DRAM chip. The single-chip structure or package structure of the semiconductor device 400 will be described in more detail in the description of FIGS. 2A to 2C.

[0038] On the other hand, when the semiconductor element 400 is a package, the semiconductor package 1000 of this embodiment is a POP (Package For example, in the semiconductor package 1000 of this embodiment, the first to third redistribution substrates 100-1 to 100-3, the first and second semiconductor chips 200 and 300, and the first and second through-posts 600-1 and 600-2 constitute a lower package, and the semiconductor element 400 of the package structure constitutes an upper package. As a result, the semiconductor package 1000 of this embodiment has a POP structure in which the upper package is stacked on the lower package.

[0039] The heat dissipation block 500 is mounted on the third redistribution substrate 100-3 via an adhesive layer 530. The heat dissipation block 500 is disposed on the left side of the third redistribution substrate 300-3 in the x direction, corresponding to the second semiconductor chip 300. That is, the heat dissipation block 500 is disposed on the left side of the semiconductor element 400 in the x direction on the third redistribution substrate 300-3. The heat dissipation block 500 includes, for example, a heat sink or a heat slug. Depending on the embodiment, the heat dissipation block 500 may be a heat sink (HPB). The adhesive layer 530 may be referred to as a thermal path block (TIM). On the other hand, the adhesive layer 530 includes a material with high thermal conductivity. For example, the adhesive layer 530 is formed of a thermal interface material (TIM) or a thermally conductive resin. The TIM includes a material with high thermal conductivity, i.e., low thermal resistance, such as grease, tape, an elastomer-filled pad, or a phase change material.

[0040] The first sealant 700-1 is disposed between the first redistribution substrate 100-1 and the second redistribution substrate 100-2. The first sealant 700-1 covers and seals the side surfaces of the first through posts 600-1 and the side surfaces and top surface of the first semiconductor chip 200. In some embodiments, the first semiconductor chip 200 is connected to the second redistribution substrate 100-2 by pad-to-pad bonding, HB bonding, ACF bonding, or the like, and the first sealant 700-1 covers the side surfaces of the first semiconductor chip 200.

[0041] The second sealant 700-2 is disposed between the second redistribution substrate 100-2 and the third redistribution substrate 100-3. The second sealant 700-2 covers and seals the side surfaces of the second through posts 600-2 and the side surfaces and bottom surface of the second semiconductor chip 300. In some embodiments, the second sealant 700-2 covers the side surfaces of the second through posts 600-2 and the second semiconductor chip 300.

[0042] The first sealant 700-1 and the second sealant 700-2 include an insulating material, for example, a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as a polyimide, or a resin containing a reinforcing material such as an inorganic filler. For example, the first sealant 700-1 and the second sealant 700-2 include ABF, FR-4, BT resin, etc. Also, the first sealant 700-1 and the second sealant 700-2 may include a molding material such as EMC, or PIE (Photo Insulator Etched Extruder). However, the materials of the first sealant 700-1 and the second sealant 700-2 are not limited to the above-mentioned materials.

[0043] The external connection terminals 800 are disposed on the lower surface of the first redistribution substrate 100-1. For example, external connection pads are disposed on the lower surface of the first redistribution substrate 100-1, and the external connection terminals 800 are disposed on the external connection pads. The external connection terminals 800 connect the semiconductor package 1000 to a package substrate of an external system or a main board of an electronic device such as a mobile phone. The external connection terminals 800 are electrically connected to the redistribution lines 103 of the first redistribution substrate 100-1 via the external connection pads. The external connection terminals 800 may also be electrically connected to the first through posts 600-1 via the redistribution lines 103 of the first redistribution substrate 100-1.

[0044] The external connection terminal 800 includes a metal pillar 810 and a solder 820. The metal pillar 810 includes, for example, Cu. However, the material of the metal pillar 810 is not limited to Cu. In some embodiments, the external connection terminal 800 may include only solder.

[0045] Meanwhile, as the external connection terminals 800 are arranged on the lower surface of the first redistribution substrate 100-1, the external connection terminals 800 may be arranged over an area larger than the area of ​​the first semiconductor chip 200 or the second semiconductor chip 300. A package structure in which the external connection terminals 800 are arranged over an area larger than the area of ​​the first semiconductor chip 200 or the second semiconductor chip 300 is called a fan-out (FO) package.

[0046] In the semiconductor package 1000 of this embodiment, for example, the first semiconductor chip 200 has a size of 8.0×12.0 mm 2 The second semiconductor chip 300 has an area of ​​5.0×11.0 mm 2 The semiconductor element 400 has an area of ​​7.0×13.0 mm 2 The overall package area is 17.0 x 14.0 mm. 2The pitch / width of the first connecting terminals 220 of the first semiconductor chip 200 and the second connecting terminals 320 of the second semiconductor chip 300 are, for example, 90 / 50 μm or less, respectively. However, in the semiconductor package 1000 of this embodiment, the areas of the components and the pitch / width of the connecting terminals are not limited to the above numerical ranges.

[0047] 1, the areas and positional relationships of the first through third redistribution substrates 100-1 through 100-3, the first and second semiconductor chips 200 and 300, the first and second through-posts 600-1 and 600-2, and the semiconductor device 400 are examined. The first through third redistribution substrates 100-1 through 100-3 each have substantially the same planar area as the first and second sealants 700-1 and 700-2, respectively. Therefore, the first semiconductor chip 200 and the first through-posts 600-1 are located within the first redistribution substrate 100-1. The second semiconductor chip 300 and the second through-posts 600-2 are located within the second redistribution substrate 100-2. The semiconductor device 400 and the heat dissipation block 500 are located within the third redistribution substrate 100-3.

[0048] The first semiconductor chip 200 and the second semiconductor chip 300 at least partially overlap each other in the z direction. For example, the first semiconductor chip 200 and the second semiconductor chip 300 overlap each other by 50% or less of their respective areas in the z direction. In addition, the heat dissipation block 500 overlaps the second semiconductor chip 300 in the z direction. For example, the heat dissipation block 500 overlaps the second semiconductor chip 300 so as to cover 70% or more of the area of ​​the second semiconductor chip 300. However, the area over which the heat dissipation block 500 covers the second semiconductor chip 300 is not limited to the above numerical range. Meanwhile, the semiconductor element 400 overlaps the first semiconductor chip 200. However, in the case of the semiconductor element 400, the area over which it overlaps the first semiconductor chip 200 is not particularly important.

[0049] The semiconductor package 1000 of this embodiment is a FOWLP (FO The semiconductor device has a Wafer Level Package (Wafer Level Package) structure, which can simultaneously achieve improved heat dissipation characteristics, a small form factor, and improved reliability. Specifically, the heat dissipation block 500 is disposed on the third redistribution substrate 100-3 in a structure that substantially overlaps the second semiconductor chip 300, and the second semiconductor chip 300 is connected to the first redistribution substrate 100-1 through the first through posts 600-1 while abutting the second redistribution substrate 100-2, thereby improving the heat dissipation effect of the second semiconductor chip 300. Furthermore, the first semiconductor chip 200 is connected to the second redistribution substrate 100-2 through the first connecting terminals 220 while abutting the first redistribution substrate 100-1, thereby improving the heat dissipation effect of the first semiconductor chip 200.

[0050] The semiconductor package 1000 of this embodiment can realize a small form factor by arranging the first semiconductor chip 200 and the second semiconductor chip 300 in a structure overlapping in the z direction. For example, the semiconductor package 1000 of this embodiment has the first semiconductor chip 200 and the second semiconductor chip 300 arranged side by side in the horizontal direction (side by side). Compared to a package structure with a side-by-side layout, the area can be reduced by more than 30%.

[0051] In the semiconductor package 1000 of this embodiment, the connection path between the first semiconductor chip 200 and the second semiconductor chip 300 is shortened, thereby improving SI (Signal Interference). This enables the realization of a semiconductor package with improved integrity and reliability. Specifically, the first semiconductor chip 200 and the second semiconductor chip 300 are connected by a portion of the second redistribution substrate 100-2 corresponding to the overlapping area OLA, thereby shortening the connection path and improving the SI characteristics. For example, if the connection between the first semiconductor chip 200 and the second semiconductor chip 300 is realized by the first redistribution substrate 100-1, the number of layers of the redistribution lines 103 in the first redistribution substrate 100-1 increases, thereby lengthening the connection path and degrading the SI characteristics. Also, stacked vias are sometimes used to minimize the resistance of multiple redistribution layers, but stacked vias have reliability issues due to damage such as cracks. On the other hand, it is possible to consider connecting the first semiconductor chip 200 and the second semiconductor chip 300 using a bridge chip, but using a bridge chip is disadvantageous in terms of process and cost, and if the bridge chip is placed on the underside of the first redistribution substrate 100-1, the area without external connection terminals 800 will increase accordingly, which may degrade the reliability of the entire semiconductor package.

[0052] 2A to 2C are cross-sectional views showing in more detail the structure of a semiconductor element in the semiconductor package of Fig. 1. Contents already explained in the explanation of Fig. 1 will be briefly explained or omitted.

[0053] 2A, the semiconductor device 400 includes one memory chip. The memory chip may be a volatile memory device such as a DRAM or an SRAM, or a non-volatile memory device such as a flash memory. In the semiconductor package 1000 of this embodiment, the memory chip of the semiconductor device 400 is, for example, a DRAM chip. The semiconductor device 400 has a flip-chip bonding structure using third connecting terminals 450 and is mounted on a third redistribution substrate 100-3. The third connecting terminals 450 may include a metal pillar and solder, or may include only solder.

[0054] Referring to FIG. 2B, the semiconductor device 400a includes a semiconductor package having a wire bonding structure. Specifically, the semiconductor device 400a includes a package substrate 410 and a plurality of memory chips 420 stacked on the package substrate 410. The memory chips 420 are mounted on the package substrate 410 using a wire bonding structure using an adhesive layer 425 and wires 430. The memory chips 420 of the semiconductor device 400a include, for example, volatile memory devices such as DRAM or SRAM, or non-volatile memory devices such as flash memory. In the semiconductor package 1000 of this embodiment, the memory chips 420 of the semiconductor device 400a include, for example, DRAM chips. Meanwhile, the semiconductor device 400a includes an internal sealant that seals the memory chips 420 and wires 430 on the package substrate 410. However, the internal sealant is omitted from FIG. 2B for convenience.

[0055] 2B, four memory chips 420 are stacked on the package substrate 410, but the number of memory chips 420 is not limited to four. For example, three or fewer, or five or more, memory chips 420 may be stacked on the package substrate 410. Furthermore, the memory chips 420 are not limited to being stacked in a staircase structure, and may be stacked on the package substrate 410 in a zigzag structure or a structure that combines a staircase structure and a zigzag structure. A third connecting terminal 450 is disposed on the lower surface of the package substrate 410. Therefore, the semiconductor element 400a having a package structure may also be mounted on the third redistribution substrate 100-3 via the third connecting terminal 450.

[0056] Referring to FIG. 2C, the semiconductor device 400b is an HBM (High The semiconductor device 400b includes a semiconductor memory (SRAM) package. Specifically, the semiconductor device 400b includes a base chip 410a, a plurality of core chips 420a stacked on the base chip 410a, and an internal sealant 440. The base chip 410a and the core chips 420a each include a through electrode 430a therein. However, the uppermost core chip 420a may not include the through electrode 430a.

[0057] The base chip 410a includes logic elements. Therefore, the base chip 410a is also a logic chip. The base chip 410a is disposed below the core chip 420a to integrate signals from the core chip 420a and transmit them to the outside, and also transmit external signals and power to the core chip 420a. Therefore, the base chip 410a may be called a buffer chip or a control chip. Meanwhile, each of the core chips 420a is a memory chip. For example, each of the core chips 420a is a DRAM chip. Meanwhile, the core chips 420a may be stacked on the base chip 410a or the underlying core chip 420a by pad-to-pad bonding, HB bonding, bonding using a connecting terminal, or bonding using ACF. In FIG. 2C , four core chips 420a are stacked on the base chip 410a, but the number of core chips 420a is not limited to four. For example, three or fewer core chips 420a may be stacked on the base chip 410a, or five or more core chips 420a may be stacked on the base chip 410a.

[0058] A third connecting terminal 450 is disposed on the lower surface of the base chip 410a. Therefore, the semiconductor device 400b in the HBM package can also be mounted on the third redistribution substrate 100-3 via the third connecting terminal 450. The core chips 420a on the base chip 410a are sealed by an internal sealant 440. However, the upper surface of the uppermost core chip 420a among the core chips 420a may not be covered by the internal sealant 440. However, in other embodiments, the upper surface of the uppermost core chip 420a may be covered by the internal sealant 440.

[0059] 3A to 3C are cross-sectional views of a semiconductor package according to an embodiment of the present invention, and the contents already described in the description of FIGS. 1 to 2C will be briefly described or omitted.

[0060] 3A, the semiconductor package 1000a of the present embodiment differs from the semiconductor package 1000 of FIG. 1 in that it further includes a third through-post 600-3. Specifically, the semiconductor package 1000a of the present embodiment includes first through third redistribution substrates 100-1 through 100-3, a first semiconductor chip 200, a second semiconductor chip 300, a semiconductor device 400, a heat dissipation block 600, first through third through-posts 600-1 through 600-3, first and second sealants 700-1 and 700-2, and an external connection terminal 800.

[0061] The first to third redistribution substrates 100-1 to 100-3, the first semiconductor chip 200, the second semiconductor chip 300, the semiconductor element 400, the heat dissipation block 600, the first and second through posts 600-1 and 600-2a, the first and second sealing materials 700-1 and 700-2, and the external connection terminals 800 are as described in the description of the semiconductor package 1000 in FIG. 1.

[0062] The third through posts 600-3 are arranged on the first redistribution substrate 100-1 to the right of the first semiconductor chip 200 in the x direction. The third through posts 600-3 are arranged, for example, in a single row along the y direction on the first redistribution substrate 100-1 to the right of the first semiconductor chip 200 in the x direction. However, in some embodiments, the third through posts 600-3 may be arranged in multiple rows along the y direction. Also, in some embodiments, the third through posts 600-3 are arranged on the first redistribution substrate 100-1 on both sides of the first semiconductor chip 200 in the y direction.

[0063] The third through post 600-3 is connected to the semiconductor element 400 via the second redistribution substrate 100-2, the second through post 600-2, and the third redistribution substrate 100-3. As such, the third through post 600-3 is disposed on the first redistribution substrate 100-1 at the lower portion of the semiconductor element 400, so that power can be effectively transmitted to the semiconductor element 400 via the third through post 600-3. For example, the third through post 600-3, the second redistribution substrate 100-2, the second through post 600-2, and the third redistribution substrate 100-3 can be used to form a power transmission path to the semiconductor element 400 in the shortest distance.

[0064] 3B, the semiconductor package 1000b of the present embodiment differs from the semiconductor package 1000 of FIG 1 in the structure and coupling structure of the first semiconductor chip 200a. Specifically, the semiconductor package 1000b of the present embodiment includes first through third redistribution substrates 100-1 through 100-3, the first semiconductor chip 200a, the second semiconductor chip 300, the semiconductor device 400, the heat dissipation block 600, the first and second through posts 600-1 and 600-2, the first and second sealants 700-1 and 700-2, and the external connection terminal 800.

[0065] The first to third redistribution substrates 100-1 to 100-3, the second semiconductor chip 300, the semiconductor element 400, the heat dissipation block 600, the first and second through posts 600-1 and 600-2a, the first and second sealing materials 700-1 and 700-2, and the external connection terminals 800 are as described in the description of the semiconductor package 1000 in FIG. 1.

[0066] In the semiconductor package 1000b of this embodiment, the first semiconductor chip 200a is substantially identical to the first semiconductor chip 200 of the semiconductor package 1000 of FIG. 1 except for the structure and the coupling structure to the first and second redistribution substrates 100-1 and 100-2. Therefore, the first semiconductor chip 200a may be a logic chip and may include multiple logic elements therein. For example, the first semiconductor chip 200a may be an NPU chip or a modem chip.

[0067] The first semiconductor chip 200a includes a substrate 201, an active layer 210, first connecting terminals 220, fourth connecting terminals 240, and through electrodes 250. The substrate 201, active layer 210, and first connecting terminals 220 are the same as those described for the first semiconductor chip 200 of the semiconductor package 1000 of FIG. 1 . However, in the semiconductor package 1000b of this embodiment, the active layer 210 of the first semiconductor chip 200a is disposed below the substrate 201, and therefore the lower surface of the first semiconductor chip 200a may be a front surface, which is an active surface, and the upper surface of the first semiconductor chip 200a may be a rear surface, which is an inactive surface. In other words, the lower surface of the active layer 210 corresponds to the front surface of the first semiconductor chip 200a, and the upper surface of the substrate 201 corresponds to the rear surface of the first semiconductor chip 200a. Chip pads are formed on the front surface, which is the active surface, and the first connecting terminals 220 are disposed on the chip pads. As a result, the first connecting terminals 220 are disposed on the lower surface of the first semiconductor chip 200a, and therefore the first semiconductor chip 200a can be mounted on the redistribution substrate 100-1 via the first connecting terminals 220.

[0068] Meanwhile, the position of the first semiconductor chip 200a on the first redistribution substrate 100-1 is substantially the same as the position of the first semiconductor chip 200 in the semiconductor package 1000 of Fig. 1. For example, as shown in Fig. 3B, the first semiconductor chip 200a is positioned to the right in the x-direction on the first redistribution substrate 100-1.

[0069] The through electrodes 250 extend vertically, i.e., in the z-direction, and penetrate the substrate 201. The lower surfaces of the through electrodes 250 are connected to wiring lines of the multiple wiring layer of the active layer 210, and the upper surfaces of the through electrodes 250 are connected to the fourth connecting terminals 240. For example, upper pads are disposed on the upper surfaces of the through electrodes 250, and the fourth connecting terminals 240 are connected to the through electrodes 250 via the upper pads. Thus, the first semiconductor chip 200a may be connected to the second redistribution substrate 100-2 via the through electrodes 250 and the fourth connecting terminals 240. The first semiconductor chip 200a may also be connected to the second semiconductor chip 300 via the through electrodes 250 and the second redistribution substrate 100-2. Furthermore, the first semiconductor chip 200a may be connected to the semiconductor device 400 via the through electrode 250, the second redistribution substrate 100-2, the second through post 600-2, and the third redistribution substrate 100-3. Meanwhile, in some embodiments, the fourth connecting terminal 240 may be omitted, and the through electrode 250 may be directly connected to the second redistribution substrate 100-2 via an upper pad on the through electrode 250.

[0070] The through electrode 250 has a structure that penetrates the silicon that constitutes the substrate 201, and therefore is a TSV (Through Silicon Vess) For reference, the through electrode 250 can be classified into a via-first structure formed before the formation of an integrated circuit layer of the active layer 210, a via-middle structure formed after the formation of the integrated circuit layer and before the formation of multiple wiring layers of the active layer 210, and a via-last structure formed after the formation of multiple wiring layers. In FIG. 3B , the through electrode 250 corresponds to, for example, a via-middle structure. However, the present invention is not limited thereto, and the through electrode 250 in the semiconductor package 1000b of this embodiment may have a via-first or via-last structure.

[0071] 3C, the semiconductor package 1000c of this embodiment has a structure that combines the semiconductor package 1000a of FIG. 3A and the semiconductor package 1000b of FIG. 3B. Specifically, the semiconductor package 1000c of this embodiment further includes third through-posts 600-3 compared to the semiconductor package 1000 of FIG. 1, and differs in the structure of the first semiconductor chip 200a and the bonding structure to the first and second redistribution substrates 100-1 and 100-2. The third through-posts 600-3 are as described in the description of the semiconductor package 1000a of FIG. 3A, and the structure of the first semiconductor chip 200a and the bonding structure to the first and second redistribution substrates 100-1 and 100-2 are as described in the description of the semiconductor package 1000b of FIG. 3B.

[0072] 4A and 4B are cross-sectional views of a semiconductor package according to an embodiment of the present invention, and the contents already described in the description of FIGS. 1 to 3C will be briefly described or omitted.

[0073] 4A, the semiconductor package 1000d of this embodiment differs from the semiconductor package 1000 of FIG. 1 in that the second redistribution substrate is omitted, thereby changing the coupling structure of the first and second semiconductor chips 200 and 300. Specifically, the semiconductor package 1000d of this embodiment includes first and third redistribution substrates 100-1 and 100-3, a first semiconductor chip 200, a second semiconductor chip 300, a semiconductor device 400, a heat dissipation block 600, first and second through posts 600-1 and 600-2a, first and second sealants 700-1 and 700-2, and an external connection terminal 800. The first and third rewiring substrates 100-1 and 100-3, the first semiconductor chip 200, the second semiconductor chip 300, the semiconductor element 400, the heat dissipation block 600, the first and second through posts 600-1 and 600-2a, the first and second sealing materials 700-1 and 700-2, and the external connection terminals 800 are as described in the description of the semiconductor package 1000 in FIG. 1.

[0074] However, as the second redistribution substrate 100-2 is omitted, the coupling structure between the first and second semiconductor chips 200 and 300 and the first and second through-posts 600-1 and 600-2a may change. Specifically, the second through-post 600-2a is coupled to the first connecting terminal 220 of the first semiconductor chip 200. In addition, in an overlapping area (OLA) where the first semiconductor chip 200 overlaps the second semiconductor chip 300, the first connecting terminal 220 of the first semiconductor chip 200 is directly coupled to the second connecting terminal 320 of the second semiconductor chip 300. Furthermore, the first through-post 600-1 is directly coupled to the second connecting terminal 320 of the second semiconductor chip 300. Meanwhile, the coupling between the first semiconductor chip 200 and the second semiconductor chip 300 in the overlapping area (OLA) may be performed by pad-to-pad bonding, hybrid bonding, or bonding using an ACF.

[0075] Meanwhile, because the second through post 600-2a is directly connected to the first semiconductor chip 200, the length of the second through post 600-2a is longer than the second through post 600-2 of the semiconductor package 1000 of FIG. 1 by the thickness of the second redistribution substrate 100-2. Also, if the first sealant 700-1 and the second sealant 700-2 are made of the same material, the first sealant 700-1 and the second sealant 700-2 are integrated into one to form the overall sealant 700T. As a result, the first sealant 700-1 and the second sealant 700-2 are indistinguishable from each other in the overall sealant 700T.

[0076] In the semiconductor package 1000d of this embodiment, the second rewiring substrate 1000-2 is omitted, thereby reducing the thickness of the entire semiconductor package by the thickness of the second rewiring substrate 1000-2. Furthermore, the process of forming the second rewiring substrate 1000-2 is omitted, which reduces the number of steps in the semiconductor package manufacturing process and saves materials. Therefore, the manufacturing cost of the semiconductor package can be significantly reduced.

[0077] 4B, the semiconductor package 1000e of the present embodiment differs from the semiconductor package 1000d of FIG. 4A in the structure and coupling structure of the first semiconductor chip 200a. Specifically, the semiconductor package 1000e of the present embodiment includes first and third redistribution substrates 100-1 and 100-3, a first semiconductor chip 200a, a second semiconductor chip 300, a semiconductor device 400, a heat dissipation block 600, first and second through posts 600-1 and 600-2a, first and second sealants 700-1 and 700-2, and an external connection terminal 800.

[0078] The first and third rewiring substrates 100-1 and 100-3, the second semiconductor chip 300, the semiconductor element 400, the heat dissipation block 600, the first and second through posts 600-1 and 600-2a, the first and second sealing materials 700-1 and 700-2, and the external connection terminals 800 are as described in the description of the semiconductor package 1000 in Figure 1.

[0079] Meanwhile, the first semiconductor chip 200a is as described in the description of the semiconductor package 1000b in FIG. 3B. However, as the second redistribution substrate 100-2 is omitted, the coupling structure between the first and second semiconductor chips 200a and 300 and the first and second through-posts 600-1 and 600-2a may change. Specifically, the second through-post 600-2a is connected to the fourth connecting terminal 240 of the first semiconductor chip 200a. Furthermore, in the overlapping area (OLA) where the first semiconductor chip 200a overlaps the second semiconductor chip 300, the fourth connecting terminal 240 of the first semiconductor chip 200a is directly connected to the second connecting terminal 320 of the second semiconductor chip 300. Furthermore, the first through-post 600-1 is directly connected to the second connecting terminal 320 of the second semiconductor chip 300. Meanwhile, the connection between the first semiconductor chip 200a and the second semiconductor chip 300 in the overlapping area OLA may be performed by pad-to-pad bonding, hybrid bonding, or bonding using ACF.

[0080] Meanwhile, because the second through post 600-2a is directly connected to the first semiconductor chip 200a, the length of the second through post 600-2a is longer than the second through post 600-2 of the semiconductor package 1000 of FIG. 1 by the thickness of the second redistribution substrate 100-2. Also, if the first sealant 700-1 and the second sealant 700-2 are made of the same material, the first sealant 700-1 and the second sealant 700-2 are integrated into one to form the overall sealant 700T. As a result, the first sealant 700-1 and the second sealant 700-2 are indistinguishable from each other in the overall sealant 700T.

[0081] 5A and 5B are cross-sectional views of a semiconductor package according to an embodiment of the present invention. Contents already described in the description of FIGS. 1 to 4B will be briefly described or omitted.

[0082] 5A, the semiconductor package 1000f of this embodiment is similar to the semiconductor package 1000 of FIG. 1, but includes a passive component 900 disposed on the bottom surface of the first redistribution substrate 100-1. In some embodiments, the passive component 900 is disposed on the top surface of or inside the first redistribution substrate 100-1. Alternatively, the passive component 900 may be disposed on the bottom surface, top surface, or inside the second redistribution substrate 100-2 or the third redistribution substrate 100-3. For example, in the case of the semiconductor packages 1000 and 1000a to 1000e of FIGS. 1 and 3A to 4B, the passive component is disposed inside at least one of the first to third redistribution substrates 100-1 to 100-3. The passive component 900 includes a two-terminal component such as a resistor, inductor, or capacitor. In the semiconductor package 1000f of this embodiment, the passive component 900 may be, for example, a multi-layer capacitor (MLCC). Ceramic Capacitor 910 and Si-Capacitor 920.

[0083] 5B, the semiconductor package 1000g of this embodiment is similar to the semiconductor package 1000d of FIG. 4A, but includes a passive component 900 disposed on the lower surface of the first redistribution substrate 100-1. In some embodiments, the passive component 900 is disposed on the upper surface or inside the first redistribution substrate 100-1. Furthermore, the external connection terminal 900 may be disposed on the lower surface, upper surface, or inside the third redistribution substrate 100-3. In the semiconductor package 1000g of this embodiment, the passive component 900 includes, for example, an MLCC 910 and a Si-capacitor 920.

[0084] 6A to 6N are cross-sectional views schematically illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. The description will be made with reference to FIG. 1, and the contents already described in the description of FIGS. 1 to 5B will be briefly described or omitted.

[0085] 6A , in the method for manufacturing a semiconductor package according to this embodiment, first, a lower redistribution substrate 100S-1 is formed. The lower redistribution substrate 100S-1 includes a body insulating layer 101, redistribution lines 103, and vertical vias 105. The lower redistribution substrate 100S-1 is formed on a first carrier substrate 2000. The first carrier substrate 2000 is a large-sized substrate such as a wafer. Alternatively, the lower redistribution substrate 100S-1 formed on the first carrier substrate 2000 may be a large-sized redistribution substrate including a plurality of first redistribution substrates 100-1. Meanwhile, although not shown, an adhesive layer may be disposed between the lower redistribution substrate 100S-1 and the first carrier substrate 2000. The adhesive layer adheres and fixes the lower redistribution substrate 100S-1 to the first carrier substrate 2000.

[0086] For reference, as will be described later, several components are formed on a large-sized rewiring substrate, and then the components are separated by a sawing process or a singulation process to manufacture a semiconductor package. The semiconductor package manufactured in this manner is called a wafer-level package (WLP). For convenience of explanation, only components corresponding to one first rewiring substrate 100-1 are shown in FIG. 6A and subsequent drawings.

[0087] 6B, a first through post 600-1 is then formed on the lower redistribution substrate 100S-1. The first through post 600-1 may be formed on the left side of the lower redistribution substrate 100S-1 in the x direction, taking into account the area where the first semiconductor chip 200 will be disposed in the future. A method for forming the first through post 600-1 will be described in more detail in the description of FIGS. 7A to 7E.

[0088] 3A, the third through-post 600-3 may be formed together with the first through-post 600-1. The third through-post 600-3 may be disposed to the right of the portion where the first semiconductor chip 200 is disposed in the x-direction.

[0089] 6C, after the first through posts 600-1 are formed, the first semiconductor chip 200 is mounted on a portion of the lower redistribution substrate 100S-1 where the first through posts 600-1 are not disposed, i.e., on the right side of the lower redistribution substrate 100S-1 in the x-direction. Specifically, the first semiconductor chip 200 is mounted on the lower redistribution substrate 100S-1 via an adhesive layer 230. Meanwhile, the first connecting terminals 220 are disposed on the upper surface of the first semiconductor chip 200. The first semiconductor chip 200 is as described in the description of the semiconductor package 1000 of FIG.

[0090] 3B, the first semiconductor chip 200a having the through electrodes 250 may be mounted on the lower redistribution substrate 100S-1. The first semiconductor chip 200a may be mounted on the lower redistribution substrate 100S-1 via the first connecting terminals 220, and the fourth connecting terminals 240 connected to the through electrodes 250 may be disposed on the upper surface of the first semiconductor chip 200a.

[0091] 6D, after the first semiconductor chip 200 is mounted, the first semiconductor chip 200 and the first through posts 600-1 are sealed with a lower sealant 700S-1a. The lower sealant 700S-1a covers the side and top surfaces of the first semiconductor chip 200 and the first through posts 600-1. The lower sealant 700S-1a also fills the spaces between the first connecting terminals 220. The material of the lower sealant 700S-1a is the same as that described in the description of the semiconductor package 1000 in FIG.

[0092] Referring to FIG. 6E, thereafter, mold grinding is performed. An upper portion of the lower sealant 700S-1a is removed by a grinding (MG) process. After the MG process, the upper surfaces of the first connecting terminals 220 and the first through posts 600-1 of the first semiconductor chip 200 are exposed from the lower sealant 700S-1. Furthermore, as the upper surfaces of the first connecting terminals 220 and the first through posts 600-1 are exposed through the MG process, the upper surfaces of the first connecting terminals 220, the first through posts 600-1, and the lower sealant 700S-1 become substantially flush.

[0093] 6F, an intermediate redistribution substrate 100S-2 is then formed on the first semiconductor chip 200, the first through-posts 600-1, and the lower sealing material 700S-1. The intermediate redistribution substrate 100S-2 includes a body insulating layer, redistribution lines, and vertical vias. The redistribution lines of the intermediate redistribution substrate 100S-2 are connected to the first through-posts 600-1 and also to the first connecting terminals 220 of the first semiconductor chip 200. Meanwhile, the intermediate redistribution substrate 100S-2 is a large-sized redistribution substrate and includes a plurality of second redistribution substrates 100-2.

[0094] 6G, after the intermediate redistribution substrate 100S-2 is formed, a second through post 600-2 is formed on the intermediate redistribution substrate 100S-2. The second through post 600-2 may be formed on the right side of the intermediate redistribution substrate 100S-2 in the x direction, taking into account the area where the second semiconductor chip 300 will be disposed in the future. The method of forming the second through post 600-2 is substantially the same as the method of forming the first through post 600-1.

[0095] 6H, after the second through-post 600-2 is formed, the second semiconductor chip 300 is mounted on the intermediate redistribution substrate 100S-2. Specifically, the second semiconductor chip 300 is mounted on the intermediate redistribution substrate 100S-2 via the second connecting terminal 320 and is disposed in a portion corresponding to the first through-post 600-1. For example, the second semiconductor chip 300 is disposed on the left side of the second through-post 600-2 in the x-direction.

[0096] The second connecting terminal 320 includes a metal pillar 322 and a solder 324. In some embodiments, the second connecting terminal 320 may include only the solder 324. When mounting the second semiconductor chip 300 using the second connecting terminal 320, reflow, TCB (Thermal Bonding) and the like may be used. Various bonding processes such as compression bonding (CMB) and laser-assisted bonding (LAB) can be used. The second semiconductor chip 300 is the same as that described in the description of the semiconductor package 1000 of FIG.

[0097] 6I, after the second semiconductor chip 300 is mounted, the second semiconductor chip 300 and the second through posts 600-2 are sealed with an upper sealant 700S-2. The upper sealant 700S-2 covers the side surfaces of the second semiconductor chip 300 and the second through posts 600-2 and the side surfaces and bottom surface of the second semiconductor chip 300. The upper sealant 700S-2 also fills the spaces between the second connecting terminals 320. The material of the upper sealant 700S-2 is substantially the same as that of the lower sealant 700S-1. The process of forming the upper sealant 700S-2 is substantially the same as that of the lower sealant 700S-1. For example, an initial upper sealant is first formed to cover the side surfaces and top surfaces of the second semiconductor chip 300 and the second through posts 600-2. Next, an upper portion of the upper sealing material is initially removed using the MG process to expose the upper surfaces of the second semiconductor chip 300 and the second through posts 600-2. As a result, the upper surfaces of the second semiconductor chip 300 and the second through posts 600-2 are exposed from the upper sealing material 700S-2. In addition, the upper surfaces of the second semiconductor chip 300, the second through posts 600-2, and the upper sealing material 700S-2 are flush with each other.

[0098] 6J, after forming the upper sealant 700S-2, an upper redistribution substrate 100S-3 is formed on the second semiconductor chip 300, the second through-posts 600-2, and the upper sealant 700S-2. The upper redistribution substrate 100S-3 includes a body insulating layer, redistribution lines, and vertical vias. The redistribution lines of the upper redistribution substrate 100S-3 are connected to the second through-posts 600-2. Meanwhile, the upper redistribution substrate 100S-3 is a large-sized redistribution substrate and includes a plurality of third redistribution substrates 100-3.

[0099] 6K, after the upper redistribution substrate 100S-3 is formed, the lower redistribution substrate 100S-1 and its upper structure are separated from the first carrier substrate 2000 and then inverted and attached to the second carrier substrate 3000. In other words, as shown in FIG. 6K, the upper redistribution substrate 100S-3 is attached to the second carrier substrate 3000, and the second semiconductor chip 300, the intermediate redistribution substrate 100S-2, the first semiconductor chip 200, and the lower redistribution substrate 100S-1 are arranged on the upper redistribution substrate 100S-3 in this order. Meanwhile, although not shown, an adhesive layer may be arranged between the upper redistribution substrate 100S-3 and the second carrier substrate 3000.

[0100] 6l, thereafter, the external connection terminal 800 is attached to the upper surface of the lower rewiring substrate 100S-1. In FIG. 6l, the upper surface of the lower rewiring substrate 100S-1 corresponds to the lower surface of the first rewiring substrate 100-1 in the semiconductor package 1000 of FIG. 1. Meanwhile, the external connection terminal 800 is as described in the description of the semiconductor package 1000 of FIG. 1. When manufacturing the semiconductor package 1000f of FIG. 5A, the passive element 900 is attached to the upper surface of the lower rewiring substrate 100S-1.

[0101] 6M, after the external connection terminals 800 are attached, the entire structure is separated from the second carrier substrate 3000, and the entire structure is subjected to a sawing process S. For example, the sawing process S is performed using a ring mount device. Through the sawing process S, multiple structures included in the entire structure can be separated into individual pieces.

[0102] 6N, the heat dissipation block 500 may then be disposed on the third redistribution substrate 100-3. Specifically, the heat dissipation block 500 is disposed on the third redistribution substrate 100-3 via an adhesive layer 550, and is disposed in a portion corresponding to the second semiconductor chip 300. For example, the heat dissipation block 500 may be disposed on the left side of the third redistribution substrate 100-3 in the x direction.

[0103] Next, the semiconductor element 400 is mounted on the third redistribution substrate 100-3. Specifically, the semiconductor element 400 is disposed on the third redistribution substrate 100-3 via the third connecting terminal 450, and is disposed in a portion corresponding to the second through post 600-2. For example, the semiconductor element 400 is disposed on the right side of the heat dissipation block 500 in the x direction. However, depending on the embodiment, the order in which the heat dissipation block 500 and the semiconductor element 400 are mounted may be changed. By mounting the heat dissipation block 500 and the semiconductor element 400 on the third redistribution substrate 100-3, the semiconductor package 1000 of FIG. 1 is completed.

[0104] 7A to 7E are cross-sectional views showing the step of FIG. 6C in more detail.

[0105] 7A, in the method for manufacturing a semiconductor package according to this embodiment, the first through post 600-1 is formed on the lower redistribution substrate 100S-1 through the following process. First, a lower pad 610-1 is formed on the lower redistribution substrate 100S-1. The lower pad 610-1 may include various metal materials, such as Cu, Ti, Ta, TiN, or TaN. In the method for manufacturing a semiconductor package according to this embodiment, the lower pad 610-1 may include Cu, for example.

[0106] 7B, a photoresist (PR) 1500 is then applied onto the lower rewiring substrate 100S-1. The PR 1500 is applied by, for example, a spin coater. The PR 1500 is applied by a spin coating method using a coater. The PR 1500 is formed to a thickness corresponding to the length of the first through post 600-1.

[0107] Referring to FIG. 7C, after the application of the PR 1500, an exposure process is performed. The exposure process is performed using a mask having a specific pattern. For example, light is transmitted through a transparent portion of a transmission mask, and the light is irradiated onto a predetermined portion of the PR 1500. The portion of the PR 1500 irradiated with light may have a different chemical property. For example, after the exposure process, the PR 1500a is divided into an unexposed portion 1510 and an exposed portion 1520. As can be seen from FIG. 7C, the exposed portion 1520 is located on the left side of the lower redistribution substrate 100S-1 in the x direction.

[0108] 7D, after the exposure process, a development process of the PR 1500a is performed. In the development process, for example, the exposed portion 1520 is removed. For example, the PR 1500a is a positive PR. Meanwhile, in some embodiments, a negative PR may be used. When a negative PR is used, the unexposed portion is removed in the development process.

[0109] The exposed portion 1520 is removed through a development process, thereby forming a PR pattern 1500b. The PR pattern 1500b includes a plurality of through holes H. The lower pads 610-1 are exposed at the bottom of the through holes H. Meanwhile, after the development process, by-products such as PR scum remain inside the through holes H. Therefore, the by-products are removed through a cleaning process.

[0110] 7E, after a cleaning process, a first through post 600-1 is formed inside the through hole H by electroplating. The first through post 600-1 includes, for example, Cu. Although not shown, the first through post 600-1 is also formed on a portion of the top surface of the PR pattern 1500b adjacent to the through hole H, away from the through hole H.

[0111] After the first through post 600-1 is formed, the PR pattern 1500b is removed by an ashing / strip process. By removing the PR pattern 1500b, the first through post 600-1 of FIG. 6C can be formed.

[0112] 8A to 8D are cross-sectional views schematically illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. Please refer to FIG. 4, and the contents already described in the description of FIGS. 6A to 7E will be briefly described or omitted.

[0113] 8A, the method for manufacturing a semiconductor package according to this embodiment sequentially performs the processes of FIGS. 6A to 6E. Next, second through posts 600-2a are formed on the first semiconductor chip 200. The second through posts 600-2a are formed to be connected to the first connecting terminals 220 of the first semiconductor chip 200. The second through posts 600-2a may be formed using substantially the same method as the method for forming the first through posts 600-1. However, instead of the upper pads 610-1, the first connecting terminals 220 are used as seed metal, and the second through posts 600-2a are formed only on some of the first connecting terminals 220.

[0114] 8B, after the second through posts 600-2a are formed, the second semiconductor chip 300 is mounted on the first through posts 600-1 and the first semiconductor chip 200. Specifically, the second semiconductor chip 300 is mounted on the portion where the first through posts 600-1 are arranged via the second connecting terminals 320 and on the portion where some of the first connecting terminals 220 of the second semiconductor chip 300 are arranged. For example, the second connecting terminals 320 are coupled to all of the first through posts 600-1 and to some of the first connecting terminals 220 of the second semiconductor chip 300. Therefore, at least a portion of the second semiconductor chip 300 and the first semiconductor chip 200 overlap each other in the z direction.

[0115] 8C, after the second semiconductor chip 300 is mounted, the second semiconductor chip 300 and the second through posts 600-2a are sealed with an upper sealant 700S-2. The upper sealant 700S-2 covers the side surfaces of the second semiconductor chip 300 and the second through posts 600-2a, as well as the side surfaces and bottom surface of the second semiconductor chip 300. The upper sealant 700S-2 also fills the spaces between the second connecting terminals 320. The material of the upper sealant 700S-2 is substantially the same as that of the lower sealant 700S-1. The process of forming the upper sealant 700S-2 is substantially the same as that of the lower sealant 700S-1. For example, an initial upper sealant is first formed to cover the side surfaces and top surfaces of the second semiconductor chip 300 and the second through posts 600-2a. Next, an upper portion of the upper sealant is initially removed using the MG process to expose the upper surfaces of the second semiconductor chip 300 and the second through posts 600-2a. As a result, the upper surfaces of the second semiconductor chip 300 and the second through posts 600-2a are exposed through the upper sealant 700S-2. Meanwhile, because the first sealant 700-1 and the second sealant 700-2 are made of the same material and there is no intermediate redistribution substrate 100S-2 between the first sealant 700-1 and the second sealant 700-2, the first sealant 700-1 and the second sealant 700-2 are integrated into one to form the overall sealant 700T.

[0116] Referring to FIG. 8D, after forming the upper sealant 700S-2, an upper redistribution substrate 100S-3 is formed on the second semiconductor chip 300, the second through-posts 600-2a, and the upper sealant 700S-2. The upper redistribution substrate 100S-3 includes a body insulating layer, redistribution lines, and vertical vias. The redistribution lines of the upper redistribution substrate 100S-3 are connected to the second through-posts 600-2a. Subsequently, the processes of FIGS. 6K through 6N are performed to complete the semiconductor package 1000d of FIG. 4A.

[0117] While the present invention has been described above with reference to the embodiments shown in the drawings, these are merely illustrative, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of the present invention should be determined by the technical spirit of the claims. [Explanation of symbols]

[0118] 100-1 to 100-3: First to third rewiring substrates 101: Body insulation layer 103: Rewiring line 105: Vertical via 200, 200a: first semiconductor chip, 201 301: Substrate 210, 310: Active layer 220, 240, 320, 450: 1st, 4th, 2nd, 3rd connection terminal 230, 425, 530: Adhesive layer 250: Through electrode 300: Second semiconductor chip 400, 400a, 400b: semiconductor elements 410: Package substrate 420: Memory chip 430: Wire 410a: Buffer chip 420a: Core chip 430a: Through electrode 440: Internal sealant 500: Heat dissipation block 600-1, 600-2, 600-2a, 600-3: 1st, 2nd, 3rd penetration posts 700-1 and 700-2: First and second sealants 700T: Overall sealant 800: External connection terminal 810: Metal pillar 820: Handa 900: Passive elements 910:MLCC 920:Si-capacitor 1000 and 1000a to 1000g: Semiconductor packages 1500 and 1500a:PR 1500b:PR pattern 2000 and 3000: First and second carrier substrates

Claims

1. a first rewiring substrate; a first semiconductor chip disposed on the first rewiring substrate on the right side in a first direction; a first through post disposed on the first rewiring substrate to the left of the first semiconductor chip in the first direction; a second rewiring substrate disposed on the first semiconductor chip and the first through-post; a second semiconductor chip disposed on the second rewiring substrate on the left side in the first direction; a second through post disposed on the second rewiring substrate to the right of the second semiconductor chip in the first direction; a third rewiring substrate disposed on the second rewiring substrate and the second through-post; a heat dissipation block disposed on the third rewiring substrate on the left side in the first direction; a semiconductor element disposed on the third rewiring substrate to the right of the heat dissipation block in the first direction.

2. 2. The semiconductor package of claim 1, wherein the first semiconductor chip and the second semiconductor chip are at least partially overlapped with each other in a direction perpendicular to the top surface of the first rewiring substrate.

3. 2. The semiconductor package according to claim 1, wherein the heat dissipation block overlaps the second semiconductor chip in a direction perpendicular to an upper surface of the first rewiring substrate.

4. The semiconductor package of claim 1 , wherein the number of the first through posts is greater than the number of the second through posts.

5. an upper surface of the first semiconductor chip is an active surface, and the upper surface of the first semiconductor chip is coupled to a lower surface of the second redistribution substrate; a bottom surface of the second semiconductor chip being an active surface, the bottom surface of the second semiconductor chip being coupled to an upper surface of the second redistribution substrate; 2. The semiconductor package of claim 1, wherein the active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip via the second redistribution substrate.

6. the first semiconductor chip includes a through electrode therein; a lower surface of the first semiconductor chip being an active surface, and an upper surface of the first semiconductor chip being coupled to a lower surface of the second redistribution substrate; a bottom surface of the second semiconductor chip being an active surface, the bottom surface of the second semiconductor chip being coupled to an upper surface of the second redistribution substrate; The semiconductor package of claim 1 , wherein the active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip via the through-electrodes and the second redistribution substrate.

7. The semiconductor package of claim 1 , further comprising a third through post disposed on the first redistribution substrate to the right of the first semiconductor chip in the first direction.

8. a first sealing material disposed between the first redistribution substrate and the second redistribution substrate, the first sealing material covering a side surface of the first through post and a side surface and an upper surface of the first semiconductor chip; 2. The semiconductor package of claim 1, further comprising: a second sealing material disposed between the second redistribution substrate and the third redistribution substrate, the second sealing material covering the side surfaces of the second through posts and the side surfaces and bottom surface of the second semiconductor chip.

9. a first rewiring substrate; a first semiconductor chip disposed on the first rewiring substrate on the right side in a first direction; a first through post disposed on the first rewiring substrate to the left of the first semiconductor chip in the first direction; a second through post disposed on the first semiconductor chip; a second semiconductor chip disposed on the first through post; a second rewiring substrate disposed on the second semiconductor chip and the second through-posts; a heat dissipation block disposed on the second rewiring substrate on the left side in the first direction; a semiconductor element disposed on the third rewiring substrate to the right of the heat dissipation block in the first direction; a sealing material disposed between the first redistribution substrate and the second redistribution substrate, the sealing material covering side surfaces of the first through-posts and the second through-posts, the side surfaces and upper surface of the first semiconductor chip, and the side surfaces and lower surface of the second semiconductor chip; an external connection terminal disposed on the lower surface of the first redistribution substrate.

10. the first semiconductor chip and the second semiconductor chip are at least partially overlapped with each other in a vertical direction perpendicular to an upper surface of the first rewiring substrate; The semiconductor package according to claim 9 , wherein the heat dissipation block overlaps the second semiconductor chip in the vertical direction.

11. the first semiconductor chip and the second semiconductor chip each include an overlapping region in which portions of the first semiconductor chip and the second semiconductor chip overlap each other in a vertical direction perpendicular to an upper surface of the first rewiring substrate; the first semiconductor chip has an upper surface as an active surface, and the second semiconductor chip has a lower surface as an active surface; The semiconductor package of claim 9 , wherein the first and second semiconductor chips are bonded together such that their active surfaces face each other in the overlapping region.

12. the first semiconductor chip and the second semiconductor chip each include an overlapping region in which portions of the first semiconductor chip and the second semiconductor chip overlap each other in a vertical direction perpendicular to an upper surface of the first rewiring substrate; the first semiconductor chip includes a through electrode therein; the first semiconductor chip has an active surface on its bottom surface, and the second semiconductor chip has an active surface on its bottom surface; the first semiconductor chip and the second semiconductor chip are bonded to each other in the overlapping region such that an inactive surface of the first semiconductor chip and an active surface of the second semiconductor chip face each other; 10. The semiconductor package of claim 9, wherein the active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip through the through-electrode.

13. a first rewiring substrate; a first semiconductor chip disposed on the first rewiring substrate on the right side in a first direction; a first through post disposed on the first rewiring substrate to the left of the first semiconductor chip in the first direction; a second through post disposed on the first semiconductor chip; a second semiconductor chip disposed on the first through post; a second rewiring substrate disposed on the second semiconductor chip and the second through-posts; a heat dissipation block disposed on the second rewiring substrate on the left side in the first direction; a semiconductor element disposed on the third rewiring substrate to the right of the heat dissipation block in the first direction.

14. the first semiconductor chip and the second semiconductor chip each include an overlapping region in which portions of the first semiconductor chip and the second semiconductor chip overlap each other in a vertical direction perpendicular to an upper surface of the first rewiring substrate; the first semiconductor chip has an upper surface as an active surface, and the second semiconductor chip has a lower surface as an active surface; The semiconductor package of claim 13 , wherein the first and second semiconductor chips are bonded together such that their active surfaces face each other in the overlapping region.

15. further including an intermediate rewiring substrate disposed on the first semiconductor chip and the first through posts; the second semiconductor chip is disposed on the intermediate rewiring substrate on the left side in the first direction; the second through post is disposed on the intermediate rewiring substrate to the right of the second semiconductor chip in the first direction; The sealant is divided into a lower sealant disposed at a lower portion and an upper sealant disposed at an upper portion based on the intermediate rewiring substrate, The semiconductor package of claim 14 , wherein active surfaces of the first semiconductor chip and the second semiconductor chip face each other in the overlapping region via the intermediate redistribution substrate.

16. the first semiconductor chip and the second semiconductor chip each include an overlapping region in which portions of the first semiconductor chip and the second semiconductor chip overlap each other in a vertical direction perpendicular to an upper surface of the first rewiring substrate; the first semiconductor chip includes a through electrode therein; the first semiconductor chip has an active surface on its bottom surface, and the second semiconductor chip has an active surface on its bottom surface; the first semiconductor chip and the second semiconductor chip are bonded to each other in the overlapping region such that an inactive surface of the first semiconductor chip and an active surface of the second semiconductor chip face each other; The semiconductor package of claim 13 , wherein the active layer of the first semiconductor chip is connected to the active layer of the second semiconductor chip through the through-electrode.

17. forming a first redistribution substrate; forming a first through post on the first redistribution substrate on a left side in a first direction; disposing a first semiconductor chip on the first redistribution substrate to the right of the first through post in the first direction; forming a second redistribution substrate on the first through posts and the first semiconductor chip; forming a second through post on the second redistribution substrate on a right side in the first direction; disposing a second semiconductor chip on the second redistribution substrate to the left of the second through post in the first direction; forming a third redistribution substrate on the second semiconductor chip and the second through posts; disposing a heat dissipation block on the third rewiring substrate on the left side in the first direction, and disposing a semiconductor element on the right side of the heat dissipation block in the first direction.

18. the first semiconductor chip and the second semiconductor chip are at least partially overlapped with each other in a vertical direction perpendicular to the top surface of the first rewiring substrate; 18. The method of claim 17, wherein the heat dissipation block overlaps the second semiconductor chip in a direction perpendicular to an upper surface of the first rewiring substrate.

19. Before forming the second redistribution substrate, forming a first sealant covering a side surface of the first through post and a side surface and an upper surface of the first semiconductor chip; Before forming the third redistribution substrate, The method of claim 17 , further comprising: a second sealant covering the side surfaces of the second through posts and the side surfaces and bottom surface of the second semiconductor chip.

20. forming a first redistribution substrate; forming a first through post on the first redistribution substrate on a left side in a first direction; disposing a first semiconductor chip on the first redistribution substrate to the right of the first through post in the first direction; forming a first sealant covering a side surface of the first through post and a side surface and an upper surface of the first semiconductor chip; forming a second through post on the first semiconductor chip; placing a second semiconductor chip on the lower sealant to the left of the second through post in the first direction; forming an upper sealant covering a side surface of the second through post and a side surface and a bottom surface of the second semiconductor chip; forming a second redistribution substrate on the second semiconductor chip and the second upper sealing material; and disposing a heat dissipation block on the second rewiring substrate on the left side in the first direction, and disposing a semiconductor element on the right side of the heat dissipation block.

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