Semiconductor device

Abstract

To prevent a component space while reducing a ringing peak of a semiconductor device.SOLUTION: A semiconductor device of an embodiment comprises a first switching element, a second switching element, and a capacitor. The second switching element is electrically connected to the first switching element. The capacitor has a first end, a second end, and a capacitor part electrically connected to the first end at one end and electrically connected to the second end at the other end. The first end is electrically connected to the first switching element. The second end is electrically connected to the second switching element. The capacitor part is located above the first switching element and the second switching element along a first direction. The width of the capacitor part in a second direction that is a direction connecting one end and the other end of the capacitor part is larger than the width of a pair of the first switching element and the second switching element in the second direction. The first switching element and the second switching element are arranged side by side in the second direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices including a semiconductor chip and a resin that seals the semiconductor chip are known, and high-speed response and miniaturization are required for the semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5447453 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of reducing ringing peaks while minimizing component space is provided. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a first switching element, a second switching element, and a capacitor. The second switching element is electrically connected to the first switching element. The capacitor has a first terminal, a second terminal, and a capacitor unit having one end electrically connected to the first terminal and the other end electrically connected to the second terminal. The first terminal is electrically connected to the first switching element. The second terminal is electrically connected to the second switching element. The capacitor unit is located above the first switching element and the second switching element in a first direction. The width of the capacitor unit in a second direction, which is a direction connecting one end of the capacitor unit to the other end, is greater than the width of the pair of the first switching element and the second switching element in the second direction. The first switching element and the second switching element are aligned in the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view showing an example of the structure of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a perspective view showing an example of the structure of a semiconductor device according to a first embodiment, viewed from below. [Figure 3] 3 is a cross-sectional view taken along line III-III in FIG. 1, showing an example of a cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of the cross-sectional structure of the semiconductor device according to the first embodiment. [Figure 5] FIG. 2 is a circuit diagram showing an example of an electric circuit of the semiconductor device according to the first embodiment. [Figure 6] FIG. 3 is a conceptual diagram showing an example in which a high-frequency signal is input to the semiconductor device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, the drawings may include portions in which the relationship and ratio of dimensions differ from one another.

[0009] Hereinafter, embodiments will be described using an XYZ Cartesian coordinate system. The positive direction of the vertical axis of a drawing may be referred to as the upper side, and the negative direction as the lower side. The positive direction of the horizontal axis of a drawing may be referred to as the right side, and the negative direction as the left side. That is, in a plan view showing the XY plane (XY plane view (hereinafter the same)), the upper side indicates the +Y direction, the lower side indicates the -Y direction, the right side indicates the +X direction, and the left side indicates the -X direction.

[0010] Hatching has been added to the plan views as appropriate for clarity. The hatching added to the plan views does not necessarily relate to the materials or properties of the components to which the hatching has been added. In cross-sectional views, components such as insulating layers, substrates, wiring, and terminals have been omitted as appropriate for clarity.

[0011] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via an element that is always or selectively conductive.

[0012] 1. First embodiment A semiconductor device according to a first embodiment will be described.

[0013] The semiconductor device according to the first embodiment is a device including a semiconductor chip, a resin for sealing the semiconductor chip, and an external connection terminal. Examples of applications of the semiconductor device according to the first embodiment include switching devices for automobiles. The semiconductor device includes, for example, a GaN module.

[0014] FIG. 1 is a perspective view showing an example of the structure of a semiconductor device according to the first embodiment.

[0015] The semiconductor device 1 includes a package substrate 10, a case 11, a first lead frame 12, a second lead frame 13, a third lead frame 14, a capacitor 15, a first control driver 16, a second control driver 17, and external connection terminals 41 to 49. In Fig. 1, for the sake of visibility, the case 11 is indicated by a dashed line frame.

[0016] The package substrate 10 is a support for the semiconductor device 1. The package substrate 10 has a flat plate shape, for example, a quadrilateral shape. The package substrate 10 forms the lower part of the container for the semiconductor device 1. The package substrate 10 includes, for example, ceramics.

[0017] The case 11 is an insulating material having a rectangular cylindrical shape. The case 11 is located on the upper surface of the package substrate 10. The case 11 forms the sides and the top of the container for the semiconductor device 1. The case 11 is fixed to the package substrate 10. The case 11 is also called insulating resin, sealing resin, or molding resin.

[0018] In the following description, the plane on which the package substrate 10 extends is referred to as the XY plane. The longitudinal direction of the package substrate 10 is referred to as the Y direction, and the direction perpendicular to the Y direction is referred to as the X direction. The direction from the package substrate 10 toward the case 11 is referred to as the Z direction. The Z direction is also the upward direction.

[0019] The first lead frame 12 is provided on the package substrate 10. The first lead frame 12 has a flat plate shape, for example, a quadrilateral shape. The first lead frame 12 includes, for example, copper (Cu).

[0020] The second lead frame 13 is provided on the package substrate 10. The second lead frame 13 has a flat plate shape, for example, a quadrilateral shape, and includes, for example, copper.

[0021] The third lead frame 14 is provided on the package substrate 10. The third lead frame 14 has a flat plate shape, for example, a quadrilateral shape, and includes, for example, copper.

[0022] The first control driver 16 is provided on the package substrate 10. The first control driver 16 has a flat plate shape. The first control driver 16 has, for example, a quadrilateral structure with multiple protrusions added. FIG. 1 and the following description are based on an example in which there are three protrusions. The protrusions are, for example, aligned in the Y direction on the side closer to the side of the case 11. The first control driver 16 may not have protrusions depending on the design. The first control driver 16 includes, for example, copper.

[0023] The second control driver 17 is provided on the package substrate 10. The second control driver 17 has a flat plate shape. The second control driver 17 has, for example, a quadrilateral structure with multiple protrusions added. FIG. 1 and the following description are based on an example in which there are three protrusions. The protrusions are, for example, aligned in the Y direction on the side closer to the side of the case 11. The second control driver 17 may not have any protrusions depending on the design. The second control driver 17 includes, for example, copper. Here, the control driver is also referred to as a control device.

[0024] The first lead frame 12, the second lead frame 13, and the third lead frame 14 are arranged, for example, in this order along the -Y direction. The first control driver 16 is arranged near the first lead frame 12 and the second lead frame 13. The second control driver 17 is arranged near the third lead frame 14. Details will be described later.

[0025] The capacitor 15 functions as a decoupling capacitor (bypass capacitor) in the semiconductor device 1. The capacitor 15 is, for example, an MLCC (Multi-Layer Ceramic Capacitor). The capacitor 15 is provided above the first lead frame 12, the second lead frame 13, and the third lead frame 14. One end of the capacitor 15 is electrically connected to the first lead frame 12. The other end of the capacitor 15 is electrically connected to the third lead frame 14. The capacitor 15 may be, for example, a silicon capacitor or a film capacitor, as long as it functions as a decoupling capacitor. The capacitor 15 will be described in detail later.

[0026] Each of the external connection terminals 41 to 49 is a terminal that electrically connects between an external device and the inside of the semiconductor device 1. FIG. 1 and the following description are based on an example in which the semiconductor device 1 has external connection terminals on the bottom surface of the semiconductor device 1.

[0027] The external connection terminals 41 to 49 will be described with reference to Fig. 2. Fig. 2 is a perspective view showing an example of the structure of the semiconductor device 1 according to the first embodiment as viewed from below (in the -Z direction).

[0028] The external connection terminals 41 are provided on the lower surface of the first lead frame 12, and the lower surfaces of the external connection terminals 41 are exposed at the lower surface of the package substrate 10. The external connection terminals 41 are electrically connected to the first lead frame 12. The external connection terminals 41 have a flat plate shape, for example, a quadrilateral shape.

[0029] The external connection terminals 42 are provided on the lower surface of the second lead frame 13, and the lower surfaces of the external connection terminals 42 are exposed at the lower surface of the package substrate 10. The external connection terminals 42 are electrically connected to the second lead frame 13. The external connection terminals 42 have a flat plate shape, for example, a quadrilateral shape.

[0030] The external connection terminals 43 are provided on the lower surface of the third lead frame 14, and the lower surfaces of the external connection terminals 43 are exposed at the lower surface of the package substrate 10. The external connection terminals 43 are electrically connected to the third lead frame 14. The external connection terminals 43 have a flat plate shape, for example, a quadrilateral shape.

[0031] The external connection terminals 41 to 43 are arranged in this order along the −Y direction, for example.

[0032] The external connection terminals 44 to 46 are provided on the lower surface of the first control driver 16, and the lower surfaces of the external connection terminals 44 to 46 are exposed at the lower surface of the package substrate 10. Each of the external connection terminals 44 to 46 is electrically connected to the first control driver 16. Each of the external connection terminals 44 to 46 has a flat plate shape, for example, a quadrilateral shape. The external connection terminals 44 to 46 are provided, for example, on the lower surfaces of three protrusions of the first control driver 16. The external connection terminals 44 to 46 are lined up in this order, for example, along the -Y direction.

[0033] The external connection terminals 47 to 49 are provided on the lower surface of the second control driver 17, and the lower surfaces of the external connection terminals 47 to 49 are exposed at the lower surface of the package substrate 10. Each of the external connection terminals 47 to 49 is electrically connected to the second control driver 17. Each of the external connection terminals 47 to 49 has a flat plate shape, for example, a quadrilateral shape. The external connection terminals 47 to 49 are provided, for example, on the lower surfaces of three protrusions of the second control driver 17. The external connection terminals 47 to 49 are lined up in this order, for example, along the -Y direction.

[0034] The positions of the external connection terminals of the semiconductor device 1 are not limited to the bottom surface of the semiconductor device 1, and the external connection terminals may be located, for example, on the side surface of the semiconductor device 1. Furthermore, the number of external connection terminals that each of the first lead frame 12, the second lead frame 13, the third lead frame 14, the first control driver 16, and the second control driver 17 has may be designed to be any number and is not limited to the descriptions in FIGS.

[0035] FIG. 3 is an example of a cross-sectional structure of the semiconductor device according to the first embodiment, and shows a cross-sectional view taken along line III-III in FIG.

[0036] As shown in FIG. 3, the semiconductor device 1 further includes a first GaN transistor 21, a second GaN transistor 22, a first P-type MOSFET 23, a second P-type MOSFET 24, and a plurality of bonding wires 25-28.

[0037] The first GaN transistor 21 and the second GaN transistor 22 include, for example, normally-on GaN-HEMTs (High Electron Mobility Transistors).

[0038] The first P-type MOSFET 23 and the second P-type MOSFET 24 are p-type MOS (Metal-Oxide-Semiconductor) transistors.

[0039] As described above, the first lead frame 12 is provided on the external connection terminal 41. The second lead frame 13 is provided on the external connection terminal 42. The third lead frame 14 is provided on the external connection terminal 43.

[0040] The first GaN transistor 21 is provided on the first lead frame 12.

[0041] The first P-type MOSFET 23 is provided on the second lead frame 13. The first P-type MOSFET 23 controls the first GaN transistor 21 so that the first GaN transistor 21 exhibits a normally-off behavior.

[0042] The second GaN transistor 22 and the second P-type MOSFET 24 are provided on the third lead frame 14. The second P-type MOSFET 24 controls the second GaN transistor 22 so that the second GaN transistor 22 exhibits normally-off behavior.

[0043] The bonding wires 25 to 28 will be described later with reference to FIG.

[0044] The capacitor 15 has, for example, a first terminal 151, a second terminal 152, and a capacitor portion 153. The first terminal 151 is provided on and electrically connected to the first lead frame 12. The second terminal 152 is provided on and electrically connected to the second lead frame 13.

[0045] One end of the capacitor section 153 is electrically connected to the first terminal 151, and the other end is electrically connected to the second terminal 152. The capacitor section 153 is provided above the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24. The capacitor section 153 extends in the Y direction and is sandwiched between the first terminal 151 and the second terminal 152. A set of the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24 may be referred to as a GaN transistor group TR hereinafter.

[0046] The width of the capacitor section 153 in the Y direction is larger than the width of the GaN transistor group TR in the Y direction. That is, in the XY plan view (top view), the capacitor section 153 covers the GaN transistor group TR in the Y direction. In other words, with respect to the Y direction, the end of the capacitor section 153 on the first terminal 151 side is located on the +Y side of the end of the first GaN transistor 21 on the first terminal 151 side, and is located closer to the +Y side surface of the case 11. Similarly, the end of the capacitor section 153 on the second terminal 152 side is located on the -Y side of the end of the second P-type MOSFET 24 on the second terminal 152 side, and is located closer to the -Y side surface of the case 11.

[0047] The width of the GaN transistor group TR in the Y direction can also be said to be the distance in the Y direction between the +Y-direction end of the element located at the farthest end on the +Y-direction side among the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24 arranged in the Y direction, and the -Y-direction end of the element located at the farthest end on the -Y-direction side opposite the +Y direction.

[0048] In addition, the width of the GaN transistor group TR in the Y direction can also be said to be the total length in the Y direction of the width of the first GaN transistor 21, the width of the second GaN transistor 22, the width of the first P-type MOSFET 23, the width of the second P-type MOSFET 24, and the distance between adjacent elements in the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24 arranged in the Y direction.

[0049] In addition, the width of the GaN transistor group TR in the Y direction can also be said to be the total length in the Y direction of the width of the first GaN transistor 21, the width of the second GaN transistor 22, the width of the first P-type MOSFET 23, the width of the second P-type MOSFET 24, the distance between the first GaN transistor 21 and the first P-type MOSFET 23, the distance between the first P-type MOSFET 23 and the second GaN transistor 22, and the distance between the second GaN transistor 22 and the second P-type MOSFET 24.

[0050] For example, the width of the capacitor section 153 in the X direction may be equal to or greater than the width of the GaN transistor group TR in the X direction. That is, in the XY plane view (top view), the capacitor section 153 may cover the GaN transistor group TR.

[0051] The width in the X direction of the GaN transistor group TR can also be said to be the distance in the X direction between the end on the +X direction side of the element located at the end furthest on the +X direction side among the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24, and the end on the −X direction side of the element located at the end furthest on the −X direction side opposite the +X direction.

[0052] An example in which the width of the capacitor section 153 in the X direction is smaller than the width of the GaN transistor group TR in the X direction will be described later.

[0053] The configuration of the transistors included in the semiconductor device 1 is not limited to the above-described configuration. For example, the first GaN transistor 21 may be a normally-off GaN transistor. In that case, the semiconductor device 1 does not include the first P-type MOSFET 23. Similarly, the second GaN transistor 22 may be a normally-off GaN transistor. In that case, the semiconductor device 1 does not include the second P-type MOSFET 24. Even in such a configuration, the width of the capacitor section 153 in the Y direction is larger than the width of the pair of the first GaN transistor 21 and the second GaN transistor 22 in the Y direction.

[0054] Furthermore, the pair of the first GaN transistor 21 and the first P-type MOSFET 23 may be replaced with transistors other than GaN transistors, for example, by a single switching element. Similarly, the pair of the second GaN transistor 22 and the second P-type MOSFET 24 may be replaced with transistors other than GaN transistors, for example, by a single switching element. The first P-type MOSFET 23 and the second P-type MOSFET 24 may be replaced with transistors other than P-type MOSFETs.

[0055] Fig. 4 shows an example of a cross-sectional structure of the semiconductor device according to the first embodiment, and is a cross-sectional view taken along line IV-IV in Fig. 3. As shown in Fig. 4, the semiconductor device 1 further includes bonding wires 31 to 38.

[0056] In the XY plane view (top view), for example, the first terminal 151, the first GaN transistor 21, the first P-type MOSFET 23, the second GaN transistor 22, the second P-type MOSFET 24, and the second terminal 152 are arranged in this order along the −Y direction.

[0057] The first control driver 16 controls the first GaN transistor 21 and the first P-type MOSFET 23. By arranging the first control driver 16 close to the first GaN transistor 21 and the first P-type MOSFET 23, it is possible to reduce parasitic inductance, which depends on the length of the current path. For this reason, the first control driver 16 is arranged close to the first lead frame 12 and the second lead frame 13 to the extent that the current flowing through the capacitor 15 does not adversely affect the first control driver 16. In other words, for example, the distance in the XY plane between the first control driver 16 and the capacitor 15 is the minimum distance at which the current flowing through the capacitor 15 does not adversely affect the first control driver 16.

[0058] The second control driver 17 controls the second GaN transistor 22 and the second P-type MOSFET 24. By arranging the second control driver 17 close to the second GaN transistor 22 and the second P-type MOSFET 24, it is possible to reduce parasitic inductance, which depends on the length of the current path. For this reason, the second control driver 17 is arranged close to the third lead frame 14 to the extent that the current flowing through the capacitor 15 does not adversely affect the second control driver 17. In other words, for example, the distance in the XY plane between the second control driver 17 and the capacitor 15 is the minimum distance at which the current flowing through the capacitor 15 does not adversely affect the second control driver 17.

[0059] One end of the first GaN transistor 21 is electrically connected to the first lead frame 12 via a plurality of bonding wires 25. The plurality of bonding wires 25 are connected in parallel between one end of the first GaN transistor 21 and the first lead frame 12. The other end of the first GaN transistor 21 is electrically connected to one end of the first P-type MOSFET 23 via a plurality of bonding wires 26. The plurality of bonding wires 26 are connected in parallel between the other end of the first GaN transistor 21 and one end of the first P-type MOSFET 23.

[0060] The other end of the first GaN transistor 21 is connected to the first control driver 16 via a bonding wire 31. There may be multiple bonding wires 31, in which case they are connected in parallel between the other end of the first GaN transistor 21 and the first control driver 16. The gate end of the first GaN transistor 21 is connected to the first control driver 16 via a bonding wire 32. There may be multiple bonding wires 32, in which case they are connected in parallel between the gate end of the first GaN transistor 21 and the first control driver 16.

[0061] The other end of the first P-type MOSFET 23 is electrically connected to the second lead frame 13 via the back surface of the first P-type MOSFET 23, for example.

[0062] The other end of the first P-type MOSFET 23 is connected to the first control driver 16 via a bonding wire 33. There may be multiple bonding wires 33, in which case they are connected in parallel between the other end of the first P-type MOSFET 23 and the first control driver 16. The gate end of the first P-type MOSFET 23 is connected to the first control driver 16 via a bonding wire 34. There may be multiple bonding wires 34, in which case they are connected in parallel between the gate end of the first P-type MOSFET 23 and the first control driver 16.

[0063] One end of the second GaN transistor 22 is electrically connected to the second lead frame 13 via a plurality of bonding wires 27. The plurality of bonding wires 27 are connected in parallel between one end of the second GaN transistor 22 and the second lead frame 13. The other end of the second GaN transistor 22 is electrically connected to one end of the second P-type MOSFET 24 via a plurality of bonding wires 28. The plurality of bonding wires 28 are connected in parallel between the other end of the second GaN transistor 22 and one end of the second P-type MOSFET 24.

[0064] The other end of the second GaN transistor 22 is connected to the second control driver 17 via a bonding wire 35. There may be multiple bonding wires 35, in which case they are connected in parallel between the other end of the second GaN transistor 22 and the second control driver 17. The gate end of the second GaN transistor 22 is connected to the second control driver 17 via a bonding wire 36. There may be multiple bonding wires 36, in which case they are connected in parallel between the gate end of the second GaN transistor 22 and the second control driver 17.

[0065] The other end of the second P-type MOSFET 24 is electrically connected to the third lead frame 14 via the back surface of the second P-type MOSFET 24, for example.

[0066] The other end of the second P-type MOSFET 24 is connected to the second control driver 17 via, for example, a bonding wire 37. There may be multiple bonding wires 37, in which case they are connected in parallel between the other end of the second P-type MOSFET 24 and the second control driver 17. The gate end of the second P-type MOSFET 24 is connected to the second control driver 17 via, for example, a bonding wire 38. There may be multiple bonding wires 38, in which case they are connected in parallel between the gate end of the second P-type MOSFET 24 and the second control driver 17.

[0067] The capacitor 15 may or may not be connected to the second control driver 17 via, for example, a bonding wire.

[0068] The external connection terminal 41 is an input terminal. The first lead frame 12 receives, via the external connection terminal 41, for example, an input signal VDC+ from the outside.

[0069] The external connection terminal 42 is an output terminal. The second lead frame 13 outputs an output signal VSW to the outside via the external connection terminal 42, for example.

[0070] The external connection terminal 43 is an input terminal. The third lead frame 14 receives, for example, an input signal VDC− from the outside via the external connection terminal 43. The input signal VDC− is smaller than the input signal VDC+ and includes a voltage of, for example, 0 V.

[0071] The first control driver 16 is connected to a node of an external voltage VDD1, for example, via an external connection terminal 44. A voltage of a constant magnitude VDD1 is applied to the node of the voltage VDD1, for example.

[0072] The first control driver 16 receives a control signal Vx from the outside via, for example, the external connection terminal 45. The control signal Vx is a signal that controls the first control driver 16, for example.

[0073] The first control driver 16 is connected to a node of an external voltage VSS1 via, for example, an external connection terminal 46. A voltage of a constant magnitude VSS1 is applied to the node of the voltage VSS1. The voltage VSS1 is smaller than the voltage VDD1, for example, 0 V.

[0074] The second control driver 17 is connected to, for example, a node of an external voltage VDD2 via an external connection terminal 47. A voltage of a constant magnitude VDD2 is applied to the node of the voltage VDD2, for example.

[0075] The second control driver 17 receives a control signal Vy from the outside via, for example, the external connection terminal 48. The control signal Vy is a signal that controls the second control driver 17, for example.

[0076] The second control driver 17 is connected to a node of an external voltage VSS2 via, for example, an external connection terminal 49. A voltage of a constant magnitude VSS2 is applied to the node of the voltage VSS2. The voltage VSS2 is smaller than the voltage VDD2, for example, 0 V.

[0077] The shapes (sometimes referred to as planar shapes) along the XY plane of the first lead frame 12, the second lead frame 13, the third lead frame 14, the first control driver 16, and the second control driver 17 shown in FIG. 4 are examples, and they may have any planar shape as long as the electrical circuit shown in FIG. 5 is realized.

[0078] The connections of the bonding wires 31 to 38 shown in FIG. 4 are examples, and other connection structures may be used as long as the electric circuit shown in FIG. 5 is realized.

[0079] The number of external connection terminals and signals received by each of the first control driver 16 and the second control driver 17 are examples, and other configurations are possible as long as they can control the first GaN transistor 21, the second GaN transistor 22, the first P-type MOSFET 23, and the second P-type MOSFET 24.

[0080] FIG. 5 is a circuit diagram showing an example of an electric circuit of the semiconductor device according to the first embodiment.

[0081] The drain terminal of the first GaN transistor 21 is connected to a node N1. The node N1 corresponds to an external connection terminal 41, and receives, for example, an input signal VDC+.

[0082] The source terminal of the first GaN transistor 21 is connected to the drain terminal of the first P-type MOSFET 23.

[0083] The gate terminal of the first GaN transistor 21 is connected to, for example, a node corresponding to the external connection terminal 45 of the first control driver 16, and receives, for example, a control signal Vx.

[0084] The source terminal of the first P-type MOSFET 23 is connected to a node N2. The node N2 corresponds to an external connection terminal 42, and outputs, for example, an output signal VSW.

[0085] The gate terminal of the first P-type MOSFET 23 is connected to a node of a voltage VDD1 corresponding to the external connection terminal 44, for example.

[0086] The drain terminal of the second GaN transistor 22 is connected to a node N2.

[0087] The source terminal of the second GaN transistor 22 is connected to the drain terminal of the second P-type MOSFET 24 .

[0088] The gate terminal of the second GaN transistor 22 is connected to, for example, a node corresponding to the external connection terminal 48 of the second control driver 17, and receives, for example, a control signal Vy.

[0089] The source terminal of the second P-type MOSFET 24 is connected to a node N3. The node N3 corresponds to an external connection terminal 43 and receives, for example, an input signal VDC−.

[0090] The gate terminal of the second P-type MOSFET 24 is connected to a node of a voltage VDD2 corresponding to the external connection terminal 47, for example.

[0091] One end of the capacitor 15 is connected to the node N1, and the other end is connected to a node N3.

[0092] The first GaN transistor 21 and the first P-type MOSFET 23 are, for example, cascode-connected. The second GaN transistor 22 and the second P-type MOSFET 24 are, for example, cascode-connected.

[0093] In this way, the on and off operations of the semiconductor device 1 are controlled by the control signals Vx and Vy. That is, the on and off operations of the semiconductor device 1 are controlled by the first GaN transistor 21 and the second GaN transistor 22. The first P-type MOSFET 23 is turned on when the first GaN transistor 21 starts up, and continues to be on thereafter. Similarly, the second P-type MOSFET 24 is turned on when the second GaN transistor 22 starts up, and continues to be on thereafter.

[0094] 5 shows an example in which the first GaN transistor 21 and the second GaN transistor 22 are normally-on GaN-HEMTs, and the semiconductor device 1 includes a first P-type MOSFET 23 and a second P-type MOSFET 24. The electric circuit realized by the semiconductor device 1 is not limited to the example of FIG. 5. For example, the set of the first GaN transistor 21 and the first P-type MOSFET 23 may be one GaN transistor. Similarly, the set of the second GaN transistor 22 and the second P-type MOSFET 24 may be one GaN transistor.

[0095] According to the semiconductor device 1 of the first embodiment, as will be described below, it is possible to provide a semiconductor device that can reduce the component space.

[0096] As described above, the semiconductor device 1 according to the first embodiment has the capacitor 15 above the GaN transistor group TR (in the +Z direction). When the decoupling capacitor of the semiconductor device is arranged in the XY plane direction (e.g., the +X direction) of the GaN transistor group TR, it may be necessary to expand the package substrate 10, case 11, first lead frame 12, second lead frame 13, and third lead frame 14 of the semiconductor device in the +X direction, for example. That is, the component space in the XY plane view (top view) increases by the area of ​​the decoupling capacitor, which may increase the area of ​​the entire semiconductor device.

[0097] In contrast to this, the semiconductor device 1 has the capacitor 15, which functions as a decoupling capacitor, above the GaN transistor group TR, thereby reducing the component space and the area of ​​the device when viewed from above.

[0098] Furthermore, the semiconductor device 1 has the capacitor 15 above the GaN transistor group TR, and thus can utilize the canceling effect of the magnetic field to reduce ringing peaks during switching.

[0099] 6 is a conceptual diagram showing an example in which a high-frequency signal is input to the semiconductor device according to the first embodiment, and shows a cross section of the same region as in FIG.

[0100] The current path DI is an example of a path of a high-frequency current IAC that flows through the semiconductor device 1 when a high-frequency signal is input to the device. The current path DI is, for example, a circular path that includes paths that pass through the GaN transistor group TR and the capacitor 15. The high-frequency current IAC, for example, loops through the current path DI. Specifically, the high-frequency current IAC passes through, in this order, the first GaN transistor 21, the first P-type MOSFET 23, the second GaN transistor 22, the second P-type MOSFET 24, the second terminal 152, the capacitor unit 153, and the first terminal 151, and then loops. That is, the high-frequency current IAC that has passed through the first terminal 151 flows back into the first GaN transistor 21.

[0101] For example, such high-frequency current IAC flows in the +Y direction when passing through capacitor section 153, and in the -Y direction when passing through GaN transistor group TR. The magnetic fields generated by high-frequency current IAC flowing in the +Y direction and the magnetic fields generated by high-frequency current IAC flowing in the -Y direction cancel each other out. Because the magnetic fields generated when high-frequency current IAC flows cancel each other out, semiconductor device 1 can reduce ringing peaks that occur during switching. The loop direction of high-frequency current IAC, etc., can change depending on the voltage applied to the external connection terminal.

[0102] Furthermore, by arranging the decoupling capacitor near the GaN transistor group TR, parasitic inductance can be reduced and ringing peaks can be further reduced. The semiconductor device 1 has the capacitor 15 above the GaN transistor group TR, and therefore, due to its structure, the decoupling capacitor can be arranged near the GaN transistor group TR, thereby reducing ringing peaks. By adjusting the heights of the first terminal 151 and the second terminal 152 in the Z direction, the capacitor section 153 of the capacitor 15 can be arranged near the GaN transistor group TR. For example, the distance in the Z direction between the capacitor section 153 and the GaN transistor group TR is the minimum distance at which the capacitor section 153 does not interfere with the GaN transistor group TR.

[0103] In the semiconductor device 1, the capacitor 15 is provided above the GaN transistor group TR, so the first terminal 151, the second terminal 152, and the capacitor portion 153 have an integrated structure as the capacitor 15. This allows the capacitor 15 to be easily and electrically stably connected to the lead frame. Furthermore, the semiconductor device 1 has the first terminal 151 and the second terminal 152, and the capacitor portion 153 does not contact the lead frame, so it has high resistance to vibration and can suppress capacitor noise. The capacitor 15 can be arranged in the semiconductor device 1 at low cost.

[0104] In this way, by having the capacitor 15 above the GaN transistor group TR, the semiconductor device 1 can reduce the ringing peak while suppressing the component space and reducing the device area. With this design, the semiconductor device 1 can improve the design freedom and the applicability of the device.

[0105] In the above-described first embodiment, an example has been described in which the width of the capacitor section 153 in the X direction is equal to or larger than the width of the GaN transistor group TR in the X direction, but this is not limited thereto. For example, the width of the capacitor section 153 in the X direction may be smaller than the width of the GaN transistor group TR in the X direction as long as it does not hinder the reduction of the ringing peak of the semiconductor device 1. In other words, for example, in the XY plan view (top view), the capacitor section 153 does not have to cover the GaN transistor group TR in the X direction.

[0106] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0107] 1. Semiconductor devices 10...Package substrate 11...Case 12~14...Lead frame 15...Capacitor 16,17...Control driver 21, 22...Transistor 23,24...MOSFET 25~28, 31~38...Bonding wire 41~49...External connection terminals

Claims

1. a first switching element; a second switching element electrically connected to the first switching element; a capacitor having a first terminal, a second terminal, and a capacitor portion electrically connected to the first terminal at one end and electrically connected to the second terminal at the other end; Equipped with the first terminal is electrically connected to the first switching element; the second terminal is electrically connected to the second switching element; the capacitor unit is located above the first switching element and the second switching element in a first direction, a width of the capacitor unit in a second direction that is a direction connecting the one end and the other end of the capacitor unit is larger than a width of the pair of the first switching element and the second switching element in the second direction; The first switching element and the second switching element are aligned in the second direction. Semiconductor devices.

2. The width of the pair of the first switching element and the second switching element in the second direction is the total length of the width of the first switching element, the width of the second switching element, and the distance between the first switching element and the second switching element, The semiconductor device of claim 1 .

3. The width of the pair of the first switching element and the second switching element in the second direction is is a distance in the second direction between an end of an element located on a side in the second direction, in the second direction, of the first switching element and the second switching element arranged side by side in the second direction, and an end of an element located on a side in the third direction opposite to the second direction, in the third direction; The semiconductor device of claim 1 .

4. a first lead frame having the first switching element and the first terminal provided on an upper surface thereof; a second lead frame having the second switching element and the second terminal provided on an upper surface thereof; a first external connection terminal electrically connected to the first lead frame; a second external connection terminal electrically connected to the second lead frame; a third external connection terminal; Further provided with one end of the first switching element is electrically connected to the first external connection terminal, and the other end is electrically connected to one end of the second switching element and the third external connection terminal; the other end of the second switching element is electrically connected to the second external connection terminal; the first terminal is electrically connected to the one end of the first switching element, the second terminal is electrically connected to the other end of the second switching element; The semiconductor device of claim 1 .

5. a first lead frame having the first switching element and the first terminal provided on an upper surface thereof; a second lead frame having the second switching element and the second terminal provided on an upper surface thereof; a third lead frame; a first external connection terminal electrically connected to the first lead frame; a second external connection terminal electrically connected to the second lead frame; a third external connection terminal electrically connected to the third lead frame; a first MOSFET provided on the third lead frame; a second MOSFET provided on the second lead frame; Further provided with one end of the first switching element is electrically connected to the first external connection terminal, and the other end is electrically connected to one end of the first MOSFET; the other end of the first MOSFET is electrically connected to a control terminal of the first switching element, one end of the second switching element, and the third external connection terminal; the other end of the second switching element is electrically connected to one end of the second MOSFET; the other end of the second MOSFET is electrically connected to a control terminal of the second switching element and the second external connection terminal; the first terminal is electrically connected to the one end of the first switching element, the second terminal is electrically connected to the other end of the second MOSFET; a width of the capacitor section in the second direction is larger than a width of a set of the first switching element, the first MOSFET, the second switching element, and the second MOSFET in the second direction; the first switching element, the first MOSFET, the second switching element, and the second MOSFET are aligned in the second direction, the first switching element and the second switching element are GaN transistors; The semiconductor device of claim 1 .

6. The width in the second direction of the set of the first switching element, the first MOSFET, the second switching element, and the second MOSFET is is a distance in the second direction between an end of an element located at an end closest to the second direction among the first switching element, the first MOSFET, the second switching element, and the second MOSFET that are arranged in the second direction, in the second direction, and an end of an element located at an end closest to the second direction in a third direction opposite to the second direction, in the third direction; The semiconductor device of claim 5 .

7. The width in the second direction of the set of the first switching element, the first MOSFET, the second switching element, and the second MOSFET is a total length in the second direction of the width of the first switching element, the width of the first MOSFET, the width of the second switching element, the width of the second MOSFET, and the distance between adjacent elements of the first switching element, the first MOSFET, the second switching element, and the second MOSFET which are arranged in the second direction, The semiconductor device of claim 5 .

8. The width in the second direction of the set of the first switching element, the first MOSFET, the second switching element, and the second MOSFET is a total length in the second direction of the width of the first switching element, the width of the first MOSFET, the width of the second switching element, the width of the second MOSFET, the distance between the first switching element and the first MOSFET, the distance between the first MOSFET and the second switching element, and the distance between the second switching element and the second MOSFET, The semiconductor device of claim 5 .

9. the first switching element and the second switching element are GaN transistors; The semiconductor device of claim 1 .

10. The capacitor is a multilayer ceramic capacitor (MLCC). The semiconductor device of claim 1 .

11. a width of the capacitor portion in a fourth direction intersecting the first direction and the second direction is equal to or larger than a width of the pair of the first switching element and the second switching element in the fourth direction; The semiconductor device of claim 1 .

12. The width of the pair of the first switching element and the second switching element in the fourth direction is a distance in the fourth direction between an end of the first switching element or the second switching element that is located on the fourth direction side and an end of the fifth direction of an element that is located on a fifth direction side opposite to the fourth direction, The semiconductor device of claim 11.

13. a first control device that controls the first switching element; a second control device that controls the second switching element; Further comprising: The semiconductor device of claim 1 .

14. a first control device that controls the first switching element; a second control device that controls the second switching element; a resin covering the first switching element, the second switching element, the capacitor, the first lead frame, the second lead frame, the first control device, and the second control device; Further comprising: The semiconductor device of claim 4 .

15. When viewed from above, the capacitor portion covers the first switching element and the second switching element. The semiconductor device of claim 11.

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