Active matrix substrate, display device, and manufacturing method for active matrix substrate

Abstract

To provide an active matrix substrate including a scanning signal line driving circuit including an oxide semiconductor TFT, in which both high mobility and high source-drain withstanding voltage of the oxide semiconductor TFT can be achieved.SOLUTION: An active matrix substrate includes a scanning signal line driving circuit including an oxide semiconductor TFT. The oxide semiconductor TFT includes an oxide semiconductor layer including a channel region, a first contact region, and a second contact region, a gate electrode disposed over the channel region through a gate insulating layer, a source electrode, and a drain electrode. The oxide semiconductor layer includes a multilayer structure including a first layer, and a second layer existing between the first layer and the gate insulating layer, corresponding to the uppermost layer of the oxide semiconductor layer, and having the lower mobility than the first layer. The thickness of the second layer in the channel region is 3.4% or more of the thickness of the gate insulating layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an active matrix substrate, and more particularly to an active matrix substrate including an oxide semiconductor TFT. The present invention also relates to a display device including such an active matrix substrate and a method for manufacturing such an active matrix substrate. [Background technology]

[0002] Active matrix substrates used in liquid crystal display devices, organic electroluminescence (EL) display devices, and the like have a display area with a plurality of pixels and a non-display area (sometimes called a "frame area") located around the display area. In the display area, a thin film transistor (hereinafter referred to as "TFT") is provided for each pixel. Conventionally, TFTs with an amorphous silicon film as the active layer (hereinafter referred to as "amorphous silicon TFTs") and TFTs with a polycrystalline silicon film as the active layer (hereinafter referred to as "polycrystalline silicon TFTs") have been widely used as the TFTs provided for each pixel.

[0003] It has been proposed to use oxide semiconductors as the active layer material of TFTs instead of amorphous silicon or polycrystalline silicon. Such TFTs are called "oxide semiconductor TFTs." Oxide semiconductors have higher mobility than amorphous silicon. Therefore, oxide semiconductor TFTs can operate at higher speeds than amorphous silicon TFTs.

[0004] TFT structures are broadly divided into bottom-gate and top-gate structures. Currently, the bottom-gate structure is often adopted for oxide semiconductor TFTs, but the use of a top-gate structure has also been proposed (see, for example, Patent Document 1). With the top-gate structure, the gate insulating layer can be made thin, resulting in high current supply performance.

[0005] Furthermore, peripheral circuits including TFTs may be monolithically (integrally) formed in the non-display area of ​​an active matrix substrate. Monolithically forming peripheral circuits can narrow the non-display area (narrow the frame) and reduce costs by simplifying the mounting process. For example, in the non-display area, a gate driver circuit (scanning signal line driving circuit) may be monolithically formed, and a source driver circuit (video signal line driving circuit) may be mounted using a COG (Chip on Glass) method. A monolithically formed gate driver circuit is called a GDM (Gate Driver Monolithic) circuit. Patent Document 2 discloses a liquid crystal display device in which a GDM circuit is formed on an active matrix substrate.

[0006] In this specification, a TFT arranged in each pixel of the display area is referred to as a "pixel TFT." Also, a TFT constituting a peripheral circuit provided in the non-display area is referred to as a "circuit TFT." When the pixel TFT is an oxide semiconductor TFT, it is preferable from the viewpoint of the manufacturing process that the circuit TFT is also an oxide semiconductor TFT. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-21312 [Patent Document 2] International Publication No. 2011 / 055584 Summary of the Invention [Problem to be solved by the invention]

[0008] The circuit TFTs in a GDM circuit are applied with a voltage equivalent to or higher than the peak-to-peak voltage Vpp of the clock signal that drives the GDM circuit. Therefore, when oxide semiconductor TFTs are used as circuit TFTs in a GDM circuit, they are required to have a high source-drain breakdown voltage. On the other hand, to reduce the circuit size of the GDM circuit, oxide semiconductor TFTs are also required to have high mobility.

[0009] However, the higher the mobility of an oxide semiconductor TFT, the more difficult it becomes to ensure a high source-drain breakdown voltage. In other words, it is difficult to achieve both a high source-drain breakdown voltage and high mobility in an oxide semiconductor TFT.

[0010] The embodiments of the present invention have been made in view of the above-mentioned problems, and an object of the present invention is to provide an active matrix substrate that includes a scanning signal line drive circuit including an oxide semiconductor TFT, and that can achieve both a high source-drain breakdown voltage and high mobility in the oxide semiconductor TFT. [Means for solving the problem]

[0011] This specification discloses an active matrix substrate, a display device, and a method for manufacturing an active matrix substrate, as described in the following items.

[0012] [Item 1] A substrate; a plurality of scanning signal lines supported by the substrate; a scanning signal line driving circuit for driving the plurality of scanning signal lines, the scanning signal line driving circuit having a plurality of oxide semiconductor TFTs; An active matrix substrate comprising: the plurality of oxide semiconductor TFTs include a plurality of first oxide semiconductor TFTs, Each of the first oxide semiconductor TFTs is a first oxide semiconductor layer including a channel region and a first contact region and a second contact region located on both sides of the channel region, respectively; a first gate electrode disposed on the channel region of the first oxide semiconductor layer via a first gate insulating layer; a first source electrode electrically connected to the first contact region; a first drain electrode electrically connected to the second contact region; the first oxide semiconductor layer has a stacked structure including a first layer and a second layer that is located between the first layer and the first gate insulating layer, is an uppermost layer of the first oxide semiconductor layer, and has a mobility lower than that of the first layer; an active matrix substrate, wherein the thickness of the second layer in the channel region is 3.4% or more of the thickness of the first gate insulating layer;

[0013] [Item 2] Item 2. The active matrix substrate according to item 1, wherein the thickness of the second layer in the channel region is 5 nm or more.

[0014] [Item 3] 3. The active matrix substrate according to item 1 or 2, wherein the first oxide semiconductor layer further includes a third layer located on the opposite side of the first layer from the second layer, the third layer having a lower mobility than the first layer.

[0015] [Item 4] 4. The active matrix substrate according to any one of items 1 to 3, wherein the plurality of first oxide semiconductor TFTs include at least a pair of first oxide semiconductor TFTs connected in series.

[0016] [Item 5] the plurality of oxide semiconductor TFTs include an oxide semiconductor TFT having a first channel length CL1; 5. The active matrix substrate according to any one of items 1 to 4, wherein the plurality of first oxide semiconductor TFTs include a first oxide semiconductor TFT having a second channel length CL2 that is greater than the first channel length CL1.

[0017] [Item 6] the plurality of oxide semiconductor TFTs further include a plurality of second oxide semiconductor TFTs; Each second oxide semiconductor TFT is a second oxide semiconductor layer that is a layer different from the first oxide semiconductor layer and has a lower mobility than the first layer of the first oxide semiconductor layer; 6. The active matrix substrate according to any one of items 1 to 5, further comprising: a second gate electrode disposed on a portion of the second oxide semiconductor layer via a second gate insulating layer.

[0018] [Item 7] 7. The active matrix substrate according to item 6, wherein the plurality of second oxide semiconductor TFTs include at least a pair of second oxide semiconductor TFTs connected in series.

[0019] [Item 8] the plurality of oxide semiconductor TFTs include an oxide semiconductor TFT having a first channel length CL1; 8. The active matrix substrate according to item 6 or 7, wherein the plurality of second oxide semiconductor TFTs include a second oxide semiconductor TFT having a second channel length CL2 greater than the first channel length CL1.

[0020] [Item 9] 9. The active matrix substrate according to any one of items 1 to 8, wherein the first gate insulating layer does not overlap the first contact region and the second contact region of the first oxide semiconductor layer in a plan view.

[0021] [Item 10] an upper insulating layer covering the first oxide semiconductor layer and the first gate electrode; the upper insulating layer has a source contact hole for electrically connecting the first source electrode to the first contact region and a drain contact hole for electrically connecting the first drain electrode to the second contact region; 10. The active matrix substrate according to any one of items 1 to 9, wherein the second layer of the first oxide semiconductor layer is present at least in a region of the first contact region that does not overlap with the source contact hole, and is present at least in a region of the second contact region that does not overlap with the drain contact hole.

[0022] [Item 11] the second layer of the first oxide semiconductor layer is removed in a portion of the first contact region and a portion of the second contact region; 11. The active matrix substrate according to any one of items 1 to 10, wherein the first source electrode and the first drain electrode are in direct contact with the first layer of the first oxide semiconductor layer.

[0023] [Item 12] 12. The active matrix substrate according to any one of items 1 to 11, wherein the scanning signal line driving circuit is monolithically formed on the active matrix substrate.

[0024] [Item 13] 13. The active matrix substrate according to any one of items 1 to 12, wherein the first oxide semiconductor layer includes an In—Ga—Zn—O-based semiconductor.

[0025] [Item 14] 14. A display device comprising the active matrix substrate according to any one of items 1 to 13.

[0026] [Item 15] A method for manufacturing an active matrix substrate according to any one of items 1 to 13, Step (A) of forming the first oxide semiconductor layer; After the step (A), a step (B) of depositing an insulating film on the first oxide semiconductor layer; After the step (B), a step (C) of etching the insulating film to form the first gate insulating layer; Including, a thickness of the second layer of the first oxide semiconductor layer formed in the step (A) is set so that the second layer remains over the entire region that will become the first contact region and the entire region that will become the second contact region when the step (C) is completed. [Effects of the Invention]

[0027] According to an embodiment of the present invention, there is provided an active matrix substrate that includes a scanning signal line drive circuit including an oxide semiconductor TFT, and that can achieve both a high source-drain breakdown voltage and high mobility in the oxide semiconductor TFT. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a schematic cross-sectional view showing a liquid crystal display device 100 according to an embodiment of the present invention. [Figure 2] FIG. 1 is a schematic plan view showing a liquid crystal display device 100. [Figure 3] 1 is an equivalent circuit diagram of one pixel P of the liquid crystal display device 100. FIG. [Figure 4] 1 is a cross-sectional view schematically illustrating a TFT substrate 10 included in a liquid crystal display device 100, showing a region corresponding to a certain circuit TFT 3. FIG. [Figure 5A] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 5B] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 5C] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 5D] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 5E] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 5F] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 5G] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 5H] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10. FIG. [Figure 6] 1 is a cross-sectional view schematically illustrating another TFT substrate 10A used in the liquid crystal display device 100, showing areas corresponding to two circuit TFTs 3A and 3B among the circuit TFTs included in the gate driver 40. FIG. [Figure 7A] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7B] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7C] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7D] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7E] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7F] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7G] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7H] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7I] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 7J] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing the TFT substrate 10A. [Figure 8] 10 is a cross-sectional view schematically illustrating a further TFT substrate 10B used in the liquid crystal display device 100, showing a region corresponding to a certain circuit TFT 3 among the circuit TFTs included in the gate driver 40. FIG. [Figure 9] 1 is a schematic plan view showing a liquid crystal display device 100A including a first gate driver 40A and a second gate driver 40B. [Figure 10] 2 is a diagram showing the overall configuration of a first gate driver 40A and a second gate driver 40B. FIG. [Figure 11] 1 is a schematic circuit diagram showing the configuration of a first gate driver 40A. FIG. [Figure 12] FIG. 2 is a circuit diagram showing the basic configuration of a unit circuit including a bistable circuit SR(n). [Figure 13] FIG. 10 is a circuit diagram showing an example of a detailed configuration of a unit circuit including a bistable circuit SR(n). [Figure 14] FIG. 10 is a circuit diagram showing an example of a detailed configuration of a unit circuit including a bistable circuit SR(n). DETAILED DESCRIPTION OF THE INVENTION

[0029] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, although a liquid crystal display device will be exemplified as a display device according to an embodiment of the present invention, the display device according to an embodiment of the present invention is not limited to a liquid crystal display device. For example, a display device according to an embodiment of the present invention may be an organic EL display device. Furthermore, the thin film transistors in the following description are n-type TFTs, and the electrical connection relationship when an n-type TFT is used will be described. Note that the electrical connection between the source and drain of a p-type TFT is opposite to the electrical connection between the source and drain of an n-type TFT.

[0030] [General configuration of liquid crystal display device] First, the schematic configuration of a liquid crystal display device 100 according to an embodiment of the present invention will be described with reference to Figures 1, 2, and 3. Figures 1 and 2 are a schematic cross-sectional view and a schematic plan view, respectively, that show the liquid crystal display device 100. Figure 3 is an equivalent circuit diagram of one pixel P of the liquid crystal display device 100.

[0031] 1, the liquid crystal display device 100 includes a display panel 1. The display panel 1 includes an active matrix substrate (hereinafter referred to as a "TFT substrate") 10, a counter substrate (sometimes referred to as a "color filter substrate") 20 disposed opposite the TFT substrate 10, and a liquid crystal layer 30 provided between the TFT substrate 10 and the counter substrate 20.

[0032] As shown in FIG. 2, the liquid crystal display device 100 has a display region DR and a non-display region (also called a "peripheral region" or "frame region") FR. The display region DR is defined by a plurality of pixels P. The plurality of pixels P are arranged in a matrix including a plurality of rows and a plurality of columns. The non-display region FR is located on the periphery of the display region DR and does not contribute to display.

[0033] The display panel 1 (more specifically, the TFT substrate 10) of the liquid crystal display device 100 has a plurality (i) of gate bus lines (scanning signal lines) GL(1) to GL(i) and a plurality (j) of source bus lines (video signal lines) SL(1) to SL(j). The gate bus lines GL(1) to GL(i) (sometimes collectively referred to as "gate bus lines GL") extend in the row direction, whereas the source bus lines SL(1) to SL(j) (sometimes collectively referred to as "source bus lines SL") extend in the column direction (a direction substantially perpendicular to the row direction). The gate bus lines GL and the source bus lines SL are supported by a substrate 11, which will be described later.

[0034] As shown in Fig. 3, each pixel P is provided with a thin film transistor (pixel TFT) 2 and a pixel electrode PE. The pixel TFT 2 is supplied with a scanning signal (gate signal) from the corresponding gate bus line GL and with a video signal (source signal) from the corresponding source bus line SL. The pixel TFT 2 is an oxide semiconductor TFT having an oxide semiconductor layer as an active layer. The pixel electrode PE is electrically connected to the pixel TFT 2. A common electrode CE is arranged opposite the pixel electrode PE.

[0035] The liquid crystal display device 100 further includes a gate driver (scanning signal line drive circuit) 40 that drives the gate bus lines GL(1) to GL(i), and a source driver (video signal line drive circuit) 50 that drives the source bus lines SL(1) to SL(j). The gate driver 40 and the source driver 50 are arranged in the non-display region FR.

[0036] The gate driver 40 sequentially selects the plurality of gate bus lines GL(1) to GL(i) (a state in which a high-level potential of a scanning signal is applied). Here, the gate driver 40 is monolithically formed on the active matrix substrate 10. In other words, the gate driver 40 is a GDM circuit.

[0037] The gate driver 40 has a plurality of circuit TFTs. Like the pixel TFT 2, each circuit TFT is an oxide semiconductor TFT.

[0038] [Circuit TFT structure] The structure of the circuit TFT included in the gate driver 40 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view showing a schematic view of the TFT substrate 10, illustrating a region corresponding to a certain circuit TFT 3.

[0039] 4, the TFT substrate 10 has a substrate 11, a light-shielding layer 12, and a circuit TFT 3. Although one circuit TFT 3 is shown here, the TFT substrate 10 has a plurality of circuit TFTs 3 having the structure shown in FIG.

[0040] The substrate 11 is transparent and insulating. The substrate 11 is, for example, a glass substrate or a plastic substrate. The substrate 11 supports the circuit TFT 3 and the like.

[0041] The light-shielding layer 12 is provided on the substrate 11. The light-shielding layer 12 is made of a material (e.g., a metal material) that has light-shielding and electrical conductivity. A lower insulating layer 13 is provided to cover the light-shielding layer 12.

[0042] The circuit TFT 3 has an oxide semiconductor layer 14 provided on the lower insulating layer 13, a gate insulating layer 15 provided on the oxide semiconductor layer 14, and a gate electrode 16 arranged to face the oxide semiconductor layer 14 with the gate insulating layer 15 interposed therebetween. The circuit TFT 3 further has a source electrode 17 and a drain electrode 18 electrically connected to the oxide semiconductor layer 14.

[0043] The oxide semiconductor layer 14 includes a channel region 14a, and a source contact region (first contact region) 14b and a drain contact region (second contact region) 14c located on either side of the channel region 14a. The channel region 14a overlaps with the gate insulating layer 15 and the gate electrode 16 in a planar view. The source contact region 14b and the drain contact region 14c do not overlap with the gate insulating layer 15 and the gate electrode 16 in a planar view, and have a lower resistivity than the channel region 14a. The source contact region 14b and the drain contact region 14c can be formed, for example, by performing a resistance reduction process on the oxide semiconductor layer 14 using the gate electrode 16 and the gate insulating layer 15 as a mask.

[0044] The gate insulating layer 15 is formed on the oxide semiconductor layer 14 and overlaps the channel region 14a in plan view. That is, the gate insulating layer 15 is removed from above the source contact region 14b and the drain contact region 14c.

[0045] The gate electrode 16 is disposed on the channel region 14a of the oxide semiconductor layer 14 via a gate insulating layer 15. An upper insulating layer 19 is provided to cover the oxide semiconductor layer 14, the gate insulating layer 15, and the gate electrode 16.

[0046] The source electrode 17 and the drain electrode 18 are formed on the upper insulating layer 19. The source electrode 17 is electrically connected to the source contact region 14b, and the drain electrode 18 is electrically connected to the drain contact region 14c. The source electrode 17 is connected to the source contact region 14b through a source contact hole CHs formed in the upper insulating layer 19 or the like, and the drain electrode 18 is connected to the drain contact region 14c through a drain contact hole CHd formed in the upper insulating layer 19 or the like.

[0047] The light-shielding layer 12 is disposed below the oxide semiconductor layer 14 and faces the channel region 14a of the oxide semiconductor layer 14 via the lower insulating layer 13. The light-shielding layer 12 may be in an electrically floating state, or may be given a predetermined potential and function as a lower gate electrode. When the light-shielding layer 12 functions as a lower gate electrode, the same potential as that of the gate electrode 16 may be given to the light-shielding layer 12, for example.

[0048] In this embodiment, the oxide semiconductor layer 14 has a stacked structure. In the illustrated example, the oxide semiconductor layer 14 includes a first layer L1, a second layer L2 located between the first layer L1 and the gate insulating layer 15, and a third layer L3 located on the opposite side of the first layer L1 from the second layer L2. That is, the oxide semiconductor layer 14 has a three-layer structure. The first layer L1, the second layer L2, and the third layer L3 are arranged on the lower insulating layer 13 in this order: the third layer L3, the first layer L1, and the second layer L2. Therefore, the first layer L1, the second layer L2, and the third layer L3 can be considered to be the "middle layer," the "upper layer," and the "lower layer," respectively.

[0049] As is apparent from the above description, the second layer L2 is the uppermost layer of the oxide semiconductor layer 14. The second layer L2 has a lower mobility than the first layer L1.

[0050] As can be seen from the above description, the third layer L3 is the bottom layer of the oxide semiconductor layer 14. The third layer L3 also has a lower mobility than the first layer L1.

[0051] Thus, the second layer L2 and the third layer L3 each have a lower mobility than the first layer L1. In other words, the first layer L1 has a higher mobility than the second layer L2 and the third layer L3. That is, the first layer L1 has a lower band gap than the second layer L2 and the third layer L3. Note that the first layer L1 only needs to have a relatively high mobility, and its mobility is not particularly limited. The mobility of the first layer L1 is, for example, 10 cm 2 / Vs or more.

[0052] 4, the thickness t2b of the second layer L2 in the source contact region 14b and the drain contact region 14c is smaller than the thickness t2a of the second layer L2 in the channel region 14a. This is because, when the insulating film that will become the gate insulating layer 15 is patterned by etching, the second layer L2 in the regions that will become the source contact region 14b and the drain contact region 14c is also etched.

[0053] In this embodiment, the thickness t2a of the second layer L2 in the channel region 14a is set to satisfy a predetermined relationship with the thickness tgi of the gate insulating layer 15. Specifically, the thickness t2a of the second layer L2 in the channel region 14a is 3.4% or more of the thickness tgi of the gate insulating layer 15.

[0054] Although not shown here, the circuit TFT3 and pixel TFT2 are covered with an interlayer insulating layer. In the display region DR, pixel electrodes PE and the like are provided on the interlayer insulating layer. The pixel electrodes PE are made of a transparent conductive material (e.g., ITO or IZO). When the display mode of the liquid crystal display device 100 is FFS mode (a type of horizontal field mode), the TFT substrate 10 further includes a common electrode CE that faces the pixel electrodes PE with a dielectric layer interposed therebetween. The common electrode CE is made of a transparent conductive material (e.g., ITO or IZO).

[0055] As described above, in the TFT substrate 10 of the liquid crystal display device 100 according to the embodiment of the present invention, the thickness t2a of the second layer L2 in the channel region 14a is 3.4% or more of the thickness tgi of the gate insulating layer 15. The inventors' investigations revealed that if, when etching the insulating film that will become the gate insulating layer 15, the second layer L2 in the regions that will become the source contact region 14b and the drain contact region 14c is completely removed by etching (i.e., the first layer L1 is exposed and the etching reaches the first layer L1), the source-drain breakdown voltage of the circuit TFT 3 decreases. By making the thickness t2a of the second layer L2 in the channel region 14a 3.4% or more of the thickness tgi of the gate insulating layer 15 as in the embodiment of the present invention, the second layer L2 in the regions that will become the source contact region 14b and the drain contact region 14c can be more reliably left intact when patterning the insulating film that will become the gate insulating layer 15, thereby ensuring a sufficient source-drain breakdown voltage of the circuit TFT 3.

[0056] The thickness t2a of the second layer L2 in the channel region 14a is not particularly limited as long as it is 3.4% or more of the thickness tgi of the gate insulating layer 15 (i.e., approximately 1 / 30 or more of the thickness tgi of the gate insulating layer 15), but is more preferably 6.7% or more of the thickness tgi of the gate insulating layer 15 (i.e., approximately 1 / 15 or more of the thickness tgi of the gate insulating layer 15). Specifically, the thickness t2a of the second layer L2 in the channel region 14a is, for example, 5 nm or more.

[0057] It is not necessary that all of the multiple circuit TFTs included in the gate driver 40 have the same structure as the illustrated circuit TFT 3. Of the multiple circuit TFTs in the gate driver 40, the circuit TFT that is desired to have a high source-drain breakdown voltage may have the same structure as the illustrated circuit TFT 3.

[0058] [Effects of the third layer] In cases where a light-shielding layer is disposed between the oxide semiconductor layer and the substrate of a TFT with a top-gate structure, or where the light-shielding layer also functions as the lower gate electrode (i.e., in the case of a double-gate structure), discontinuities in the oxide semiconductor layer due to the presence of the light-shielding layer may occur. Forming a relatively thick oxide semiconductor layer is thought to be able to suppress such discontinuities. However, simply increasing the thickness of the oxide semiconductor layer may result in failure to obtain desired TFT characteristics or reduced reliability due to reasons other than discontinuities. For example, in a TFT with a single oxide semiconductor layer with relatively high mobility as its active layer, simply increasing the thickness of the oxide semiconductor layer may cause a negative shift in the threshold voltage of the TFT due to degradation caused by backlight light (photodegradation).

[0059] In contrast, as illustrated, by including the third layer L3 in addition to the first layer L1 and the second layer L2, the total thickness T of the oxide semiconductor layer 14 can be increased without increasing the thickness t1 of the first layer L1. Here, the total thickness T is the sum of the thickness t1 of the first layer L1, the thickness t3 of the third layer L3, and the thickness L2a of the second layer L2 in the channel region 14a. Increasing the total thickness T of the oxide semiconductor layer 14 can suppress discontinuities in the oxide semiconductor layer 14. Furthermore, since there is no need to significantly increase the thickness t1 of the first layer L1, negative shifts in the threshold voltage due to photodegradation of the first layer L1 can be suppressed. Furthermore, since the first layer L1 is located closer to the gate insulating layer 15 than the third layer L3, a decrease in mobility caused by the provision of the third layer L3 can be suppressed.

[0060] [Thickness of oxide semiconductor layer] The total thickness T of the oxide semiconductor layer 14 is preferably 30 nm or more, and more preferably 40 nm or more, from the viewpoint of suppressing discontinuities in the oxide semiconductor layer 14 caused by the light-shielding layer 12. Furthermore, from the viewpoint of reducing steps occurring in the upper insulating layer 19, the total thickness T of the oxide semiconductor layer 14 is preferably 80 nm or less.

[0061] The thickness t1 of the first layer L1 is, for example, 4 nm or more and 12 nm or less. When the thickness t1 of the first layer L1 is 4 nm or more, a current path can be more reliably secured within the first layer L1, thereby more effectively increasing the on-current. Furthermore, when the thickness t1 of the first layer L1 is 12 nm or less, a negative shift in the threshold voltage due to photodegradation can be more effectively suppressed.

[0062] As illustrated, when the oxide semiconductor layer 14 includes the third layer L3, the thickness t1 of the first layer L1 is preferably ½ or less, and more preferably ⅓ or less, of the thickness t3 of the third layer L3, from the viewpoint of more effectively suppressing a negative shift in threshold voltage due to photodegradation of the first layer L1 while ensuring the total thickness T of the oxide semiconductor layer 14. Furthermore, from the viewpoint of ensuring a current path within the first layer L1, the thickness t1 of the first layer L1 is preferably ⅙ or more of the thickness t3 of the third layer L3.

[0063] As already explained, the thickness t2a of the second layer L2 in the channel region 14a is 3.4% or more, and more preferably 6.7% or more, of the thickness tgi of the gate insulating layer 15. Furthermore, from the viewpoint of suppressing a decrease in on-current caused by placing the second layer L2 on the gate insulating layer 15 side of the first layer L1, the thickness t2a of the second layer L2 in the channel region 14a is preferably 3 / 2 or less of the thickness t1 of the first layer L1, and preferably 1 / 3 or less of the thickness t3 of the third layer L3.

[0064] From the viewpoint of suppressing discontinuity of the oxide semiconductor layer 14 due to the light-shielding layer 12, the thickness t3 of the third layer L3 is preferably greater than the thickness t1 of the first layer L1 and the thickness t2a of the second layer L2 in the channel region 14a. The thickness t3 of the third layer L3 can be set so that the total thickness T of the oxide semiconductor layer 14 has a desired value. The thickness t3 of the third layer L3 is, for example, 6 nm or more and 50 nm or less. From the viewpoint of suppressing discontinuity of the oxide semiconductor layer 14, the thickness t3 of the third layer L3 is preferably 6 nm or more. From the viewpoint of increasing the on-current when the light-shielding layer 12 functions as a lower gate electrode, the thickness t3 of the third layer L3 is preferably 50 nm or less.

[0065] [Source contact hole and drain contact hole structure] 4, the first layer L1 and the second layer L2 of the oxide semiconductor layer 14 are removed in the source contact hole CHs and the drain contact hole CHd. That is, the source contact hole CHs and the drain contact hole CHd are each formed across the upper insulating layer 19 and the second layer L2 and the first layer L1 of the oxide semiconductor layer 14. This structure is obtained, for example, by removing the second layer L2 and the first layer L1 of the oxide semiconductor layer 14 when etching the upper insulating layer 19.

[0066] The source electrode 17 is in contact with the portions of the first layer L1 and the second layer L2 of the oxide semiconductor layer 14 that are exposed on the side surfaces of the source contact holes CHs and the portions of the third layer L3 that are exposed on the bottom surfaces of the source contact holes CHs. The drain electrode 18 is in contact with the portions of the first layer L1 and the second layer L2 of the oxide semiconductor layer 14 that are exposed on the side surfaces of the drain contact holes CHd and the portions of the third layer L3 that are exposed on the bottom surfaces of the drain contact holes CHd. This structure increases the contact area between the source electrode 17 and / or the drain electrode 18 and the oxide semiconductor layer 14, and by directly contacting the source electrode 17 and / or the drain electrode 18 with the first layer L1, the contact resistance can be more effectively reduced.

[0067] The structures of the source contact hole CHs and the drain contact hole CHd are not limited to the structure exemplified in Fig. 4. The second layer L2 of the oxide semiconductor layer 14 is removed in part of the source contact region 14b and part of the drain contact region 14c, and the source electrode 17 and the drain electrode 18 are in direct contact with the first layer L1 of the oxide semiconductor layer 14, respectively, thereby achieving the above-mentioned effects. For example, the first layer L1 of the oxide semiconductor layer 14 may be exposed at the bottom of each of the source contact hole CHs and the drain contact hole CHd.

[0068] The second layer L2 of the oxide semiconductor layer 14 is required to be present at least in the region of the source contact region 14b that does not overlap with the source contact hole CHs, and to be present at least in the region of the drain contact region 14c that does not overlap with the drain contact hole CHd.

[0069] [Composition of each layer of the oxide semiconductor layer] In the TFT substrate 10 of the liquid crystal display device 100 according to the embodiment of the present invention, the compositions of the first layer L1, the second layer L2, and the third layer L3 of the oxide semiconductor layer 14 are set so that the first layer L1 has a higher mobility than the second layer L2 and the third layer L3.

[0070] The second layer L2 and the third layer L3 may contain In, Ga, and Zn. The second layer L2 and the third layer L3 may mainly contain, for example, an In—Ga—Zn—O-based semiconductor. The second layer L2 and the third layer L3 may have the same composition or different compositions.

[0071] The first layer L1 may mainly include an In-Zn-O based semiconductor layer. Alternatively, the first layer L1 may mainly include an oxide semiconductor containing Sn. Examples of oxide semiconductors containing Sn include In-Ga-Zn-Sn-O based semiconductors, In-Ga-Sn-O based semiconductors, and In-Sn-Zn-O based semiconductors.

[0072] When the second layer L2 and the third layer L3 mainly contain an In—Ga—Zn—O-based semiconductor and the first layer L1 mainly contains an In—Zn—O-based semiconductor, the ratio of In in the In—Ga—Zn—O-based semiconductor of each of the second layer L2 and the third layer L3 may be, for example, 1 / 3 or more. The ratio (atomic ratio) of In, Ga, and Zn in the In—Ga—Zn—O-based semiconductor of each of the second layer L2 and the third layer L3 may be, for example, 1:1:1, 4:2:4, etc.

[0073] When the second layer L2 and the third layer L3 mainly contain an In-Ga-Zn-O-based semiconductor and the first layer L1 mainly contains an oxide semiconductor containing Sn, the composition of the In-Ga-Zn-O-based semiconductor in the second layer L2 and the third layer L3 is not particularly limited. The ratio of In, Ga, and Zn in the second layer L2 and the third layer L1 may be, for example, 1:1:1, 4:2:4, 1:3:2, 1:3:6, etc.

[0074] Here, In is referred to as the "first metal element," and Ga and Zn are referred to as the "second metal elements." It is known that the higher the ratio of the first metal element in an oxide semiconductor, the higher the mobility, and the higher the ratio of the second metal element, the lower the mobility but the higher the crystallinity. Therefore, when an oxide semiconductor contains the first metal element and at least one of the second metal elements (Ga or Zn), an oxide semiconductor layer having a desired mobility can be formed by adjusting the ratio of these metal elements.

[0075] The atomic ratio of In to all metal elements contained in the first layer L1 may be greater than the atomic ratio of In to all metal elements contained in the second layer L2 and the third layer L3. As an example, the atomic ratio of the first metal element to all metal elements contained in the first layer L1 may be equal to or greater than the atomic ratio of the second metal element. Preferably, the atomic ratio of the first metal element may be greater than the atomic ratio of the second metal element. On the other hand, the atomic ratio of the first metal element to all metal elements contained in the second layer L2 and the third layer L3 may be equal to or less than the atomic ratio of the second metal element.

[0076] By having the above-described compositions for the first layer L1, the second layer L2, and the third layer L3, the first layer L1 has higher mobility than the second layer L2 and the third layer L3 and can function as a channel layer. On the other hand, the second layer L2 and the third layer L3 are highly crystallized layers with higher crystallinity than the first layer L1 and have excellent etching resistance and barrier properties. Therefore, for example, in the patterning process of the gate insulating layer 15 and the gate electrode 16, the second layer L2 can function as a protective layer and a sacrificial layer for the first layer L1.

[0077] The first layer L1, the second layer L2, and the third layer L3 may have the same composition. Even in this case, for example, by varying the formation conditions or crystal structure of each oxide semiconductor layer, it is possible to make the mobility of the first layer L1 higher than that of the second layer L2 and the third layer L3.

[0078] [TFT substrate manufacturing method] 5A to 5H, the method for manufacturing the TFT substrate 10 will be described. FIGS. 5A to 5H are cross-sectional views illustrating the steps of the method for manufacturing the TFT substrate 10.

[0079] 5A, a light-shielding layer 12 is formed on a substrate 11. Specifically, a conductive film for the light-shielding layer (thickness: for example, 50 nm or more and 500 nm or less) is formed on an insulating substrate 11 by a sputtering method or the like, and then the conductive film for the light-shielding layer is patterned, thereby forming the light-shielding layer 12.

[0080] The substrate 11 may be, for example, a glass substrate or a heat-resistant plastic substrate (resin substrate).

[0081] The conductive film for the light-shielding layer can be, for example, a metal film containing an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy film containing these elements. A laminated film containing multiple films of these elements can also be used. For example, a laminated film having a three-layer structure of titanium film-aluminum film-titanium film or a three-layer structure of molybdenum film-aluminum film-molybdenum film can be used. The conductive film for the light-shielding layer is not limited to a three-layer structure, but can also have a single-layer structure, a two-layer structure, or a laminated structure of four or more layers. Here, a laminated film with a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer is used as the conductive film for the light-shielding layer.

[0082] Next, as shown in FIG. 5B, a lower insulating layer 13 is formed to cover the light-shielding layer 12. The lower insulating layer 13 can be formed by, for example, a CVD method. The thickness of the lower insulating layer 13 is, for example, 150 nm or more and 550 nm or less. When the thickness of the lower insulating layer 13 is 150 nm or more, discontinuities in the oxide semiconductor layer 14 caused by the light-shielding layer 12 can be more effectively reduced. Furthermore, when the thickness of the lower insulating layer 13 is 550 nm or less, the on-current can be more effectively increased when the light-shielding layer 12 functions as a lower gate electrode.

[0083] The lower insulating layer 13 may be formed of a silicon oxide (SiO2) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy;x>y) layer, a silicon nitride oxide (SiNxOy;x>y) layer, or the like, as appropriate. The lower insulating layer 13 may have a stacked structure. For example, a silicon nitride layer, a silicon nitride oxide layer, or the like may be formed on the substrate 11 side (lower layer) to prevent diffusion of impurities from the substrate 11, and a silicon oxide layer, a silicon oxynitride layer, or the like may be formed on the upper layer (upper layer) to ensure insulation. In this example, a stacked film is used, with a silicon nitride layer (thickness: 100 nm to 500 nm) as the lower layer and a silicon oxide layer (thickness: 20 nm to 300 nm) as the upper layer. In this way, using an insulating layer containing oxygen as the uppermost layer of the lower insulating layer 13 (i.e., the layer in contact with the oxide semiconductor layer 14) allows oxygen vacancies in the oxide semiconductor layer 14 to be repaired, thereby reducing oxygen vacancies in the oxide semiconductor layer 14.

[0084] Next, as shown in FIG. 5C , an oxide semiconductor layer 14 having a stacked structure is formed on the lower insulating layer 13. Specifically, a sputtering method is first used to form a stacked film by forming a lower oxide semiconductor film, an intermediate oxide semiconductor film, and an upper oxide semiconductor film from the lower insulating layer 13 side. Each oxide semiconductor film has a composition and thickness corresponding to the third layer L3, the first layer L1, and the second layer L2, respectively. Here, the thickness of the upper oxide semiconductor film corresponding to the second layer L2 is 3.4% or more of the thickness tgi of the gate insulating layer 15 to be formed later. Each oxide semiconductor film may be a crystalline oxide semiconductor film or an amorphous oxide semiconductor film. The stacked film may be annealed. Here, heat treatment is performed in an air atmosphere at a temperature of 200°C to 500°C. The heat treatment time is, for example, 30 minutes to 2 hours. Thereafter, the stacked film is patterned. The stacked film can be patterned by wet etching using, for example, a PAN-based etching solution containing phosphoric acid, nitric acid, and acetic acid, or an oxalic acid-based etching solution. As a result, an oxide semiconductor layer 14 including the third layer L3, the first layer L1, and the second layer L2 in this order from the lower insulating layer 13 side is obtained.

[0085] 5D, a gate insulating layer 15 and a gate electrode 16 are formed on a part of the oxide semiconductor layer 14. Specifically, first, an insulating film and a gate conductive film are deposited in this order so as to cover the oxide semiconductor layer 14.

[0086] The insulating film can be the same as the lower insulating layer 13 (the insulating film exemplified as the lower insulating layer 13). Here, a silicon oxide (SiO2) film is formed as the insulating film, for example, by CVD. Using an oxide film such as a silicon oxide film as the insulating film can reduce oxidation defects occurring in the channel region 14a of the oxide semiconductor layer 14, thereby preventing the channel region 14a from becoming less resistant. The thickness of the insulating film (i.e., the thickness of the gate insulating layer 15) is, for example, 80 nm to 250 nm, and preferably 100 nm to 200 nm. By making the gate insulating layer 15 thin (for example, 200 nm or less), the decrease in on-current caused by the second layer L2 being disposed on the first layer L1 can be compensated for, thereby maintaining a large on-current. Furthermore, having a thickness of the gate insulating layer 15 of 100 nm or more can improve reliability.

[0087] The conductive film for the gate can be a conductive film similar to the conductive film for the light-shielding layer. The conductive film for the gate may be a Cu / Ti laminated film with a Ti film as the lower layer and a Cu film as the upper layer, or a Cu / Mo laminated film with a Mo film as the lower layer and a Cu film as the upper layer. The thickness of the conductive film for the gate is, for example, 50 nm or more and 500 nm or less.

[0088] Next, the gate conductive film is patterned by a photolithography process. Here, a resist layer is formed on the gate conductive film. Using this resist layer as a mask, the gate conductive film is etched (e.g., wet etching) to form the gate electrode 16.

[0089] Thereafter, the insulating film is etched using the resist layer or the gate electrode 16 as a mask to form the gate insulating layer 15. As already described, when the insulating film that becomes the gate insulating layer 15 is patterned, a part of the second layer L2 of the oxide semiconductor layer 14 may be etched.

[0090] Next, a resistance reduction treatment is performed on the oxide semiconductor layer 14. The resistance reduction treatment is, for example, a plasma treatment. As a result, as shown in FIG. 5E, the regions (exposed regions) of the oxide semiconductor layer 14 that do not overlap with the gate electrode 16 or the gate insulating layer 15 become low-resistance regions (source contact region 14b and drain contact region 14b) that have a lower resistivity than the regions (channel region 14a) that overlap with them. Note that the method of the resistance reduction treatment is not limited to the example given here.

[0091] Next, as shown in FIG. 5F , an upper insulating layer 19 is formed to cover the oxide semiconductor layer 14, the gate insulating layer 15, and the gate electrode 16. The upper insulating layer 19 can be formed by, for example, a CVD method. The thickness of the upper insulating layer 19 is, for example, 100 nm or more and 500 nm or less. The upper insulating layer 19 can be, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. If an insulating layer that reduces an oxide semiconductor, such as a silicon nitride layer, is used as the upper insulating layer 19, the resistivity of the region of the oxide semiconductor layer 14 that contacts the upper insulating layer 19 can be maintained low.

[0092] Next, as shown in FIG. 5G, source contact holes CHs and drain contact holes CHd are formed in the upper insulating layer 19. Specifically, the source contact holes CHs and drain contact holes CHd can be formed by a photolithography process and etching. The etching can be, for example, dry etching. In the illustrated example, during the etching, portions of the second layer L2 and the first layer L1 of the oxide semiconductor layer 14 located in the source contact holes CHs and drain contact holes CHd are also removed, and the third layer L3 of the oxide semiconductor layer 14 is exposed at the bottom surfaces of the source contact holes CHs and drain contact holes CHd.

[0093] Next, as shown in FIG. 5H, a source electrode 17 is formed on the upper insulating layer 19 and in the source contact hole CHs, and a drain electrode 18 is formed on the upper insulating layer 19 and in the drain contact hole CHd. Specifically, a source conductive film (thickness: e.g., 50 nm to 500 nm) is formed on the upper insulating layer 19 and in the source contact hole CHs and drain contact hole CHd, and then the source conductive film is patterned to form the source electrode 17 and the drain electrode 18. The source conductive film can be patterned by, for example, dry etching or wet etching. The source conductive film may be made of an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy containing these elements. For example, the source conductive film may have a three-layer structure of titanium film-aluminum film-titanium film, or a three-layer structure of molybdenum film-aluminum film-molybdenum film. The source conductive film is not limited to a three-layer structure, but may have a single layer, a two-layer structure, or a laminated structure of four or more layers. Here, a laminated film is used, with a Ti film (thickness: 15 nm to 70 nm) as the lower layer and a Cu film (thickness: 200 nm to 400 nm) as the upper layer.

[0094] Thereafter, an interlayer insulating layer covering the circuit TFT 3 and the pixel TFT 2, the pixel electrode PE, etc. are formed, thereby obtaining the TFT substrate 10.

[0095] In the manufacturing method described above, in the step of forming the oxide semiconductor layer 14, the second layer L2 is formed to have a thickness of 3.4% or more of the thickness tgi of the gate insulating layer 15. In other words, the thickness of the second layer L2 is set so that the second layer L2 remains over the entire source contact region 14b and the entire drain contact region 14c when the step of forming the gate insulating layer 15 by etching the insulating film is completed. This makes it possible to ensure a sufficient source-drain breakdown voltage of the circuit TFT 3.

[0096] [Other TFT substrate configurations] Another TFT substrate 10A used in a liquid crystal display device 100 according to an embodiment of the present invention will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view schematically illustrating the TFT substrate 10A, showing areas corresponding to two circuit TFTs, 3A and 3B, among the circuit TFTs included in the gate driver 40. The following description will focus on the differences between the TFT substrate 10A and the TFT substrate 10 shown in Fig. 4.

[0097] As shown in Fig. 6, the TFT substrate 10A has circuit TFTs 3A and 3B that have different structures. Hereinafter, the circuit TFT 3A shown on the right side of Fig. 6 will be referred to as the "first circuit TFT," and the circuit TFT 3B shown on the left side of Fig. 6 will be referred to as the "second circuit TFT." Although one first circuit TFT 3A and one second circuit TFT 3B are shown here, the TFT substrate 10A has a plurality of first circuit TFTs 3A with the structure shown in Fig. 6 and a plurality of second circuit TFTs 3B with the structure shown in Fig. 6.

[0098] The first circuit TFT3A has substantially the same structure as the circuit TFT3 shown in Fig. 4. The first circuit TFT3A has a first oxide semiconductor layer 14A, a first gate insulating layer 15A, a first gate electrode 16A, a first source electrode 17A, and a first drain electrode 18A, which correspond to the oxide semiconductor layer 14, the gate insulating layer 15, the gate electrode 16, the source electrode 17, and the drain electrode 18 in the circuit TFT3 shown in Fig. 4. However, between the first oxide semiconductor layer 14A and the lower insulating layer 13 of the first circuit TFT3A, an insulating layer 5 separate from the lower insulating layer 13 is interposed, and the first oxide semiconductor layer 14A is formed on the insulating layer 5.

[0099] The first oxide semiconductor layer 14A of the first circuit TFT 3A has a stacked structure including a first layer L1, a second layer L2, and a third layer L3, similar to the oxide semiconductor layer 14 of the circuit TFT 3. The thickness t2a of the second layer L2 in the channel region 14a is 3.4% or more of the thickness tgi of the gate insulating layer 15.

[0100] The first source electrode 17A and the first drain electrode 18A of the first circuit TFT 3A are connected to the source contact region 14b and the drain contact region 14c of the first oxide semiconductor layer 14A, respectively, through the first source contact hole CHsA and the first drain contact hole CHdA formed in the upper insulating layer 19.

[0101] The second circuit TFT3B has a second oxide semiconductor layer 14B provided on the lower insulating layer 13, a second gate insulating layer 15B provided on the second oxide semiconductor layer 14B, and a second gate electrode 16B arranged to face the second oxide semiconductor layer 14B with the second gate insulating layer 15B interposed therebetween. The second circuit TFT3B further has a second source electrode 17B and a second drain electrode 18B electrically connected to the second oxide semiconductor layer 14B.

[0102] The second oxide semiconductor layer 14B is formed as a layer separate from the first oxide semiconductor layer 14A of the first circuit TFT 3A, and has a lower mobility than the first layer L1 of the first oxide semiconductor layer 14A. In the example shown, the second oxide semiconductor layer 14B does not have a stacked structure but is a single layer.

[0103] The second gate insulating layer 15B is formed on the second oxide semiconductor layer 14B and overlaps the channel region 14a of the second oxide semiconductor layer 14B in a plan view. That is, the second gate insulating layer 15B is removed from above the source contact region 14b and the drain contact region 14c of the second oxide semiconductor layer 14B.

[0104] The second gate insulating layer 15B has a laminated structure. Specifically, the second gate insulating layer 15B includes a lower layer La and an upper layer Lb disposed on the lower layer La. The lower layer La is formed in the same layer as the insulating layer 5 located between the first oxide semiconductor layer 14A and the lower insulating layer 13 of the first circuit TFT 3A. The upper layer Lb is formed in the same layer as the first gate insulating layer 15A of the first circuit TFT 3A.

[0105] The second gate electrode 16B is disposed on the channel region 14a of the second oxide semiconductor layer 14B via the second gate insulating layer 15B.

[0106] The second source electrode 17B and the second drain electrode 18B are formed on the upper insulating layer 19. The second source electrode 17B is electrically connected to the source contact region 14b of the second oxide semiconductor layer 14B, and the second drain electrode 18B is electrically connected to the drain contact region 14c of the second oxide semiconductor layer 14B. The second source electrode 17B is connected to the source contact region 14b through a second source contact hole CHsB formed in the upper insulating layer 19, and the second drain electrode 18B is connected to the drain contact region 14c through a second drain contact hole CHdB formed in the upper insulating layer 19.

[0107] As described above, the TFT substrate 10A includes a mixture of the first circuit TFT 3A and the second circuit TFT 3B. The second oxide semiconductor layer 14B of the second circuit TFT 3B has a lower mobility than the first layer L1 of the first oxide semiconductor layer 14A of the first circuit TFT 3A, making it easier for the second circuit TFT 3B to have a higher source-drain breakdown voltage than the first circuit TFT 3A. By using the second circuit TFT 3B as a circuit TFT that requires a particularly high source-drain breakdown voltage among the multiple circuit TFTs in the gate driver 40 and the first circuit TFT 3A as a circuit TFT that can tolerate a slightly lower source-drain breakdown voltage, the size of the gate driver 40 can be reduced while maintaining the reliability of the gate driver 40.

[0108] The second oxide semiconductor layer 14B of the second circuit TFT 3B is not particularly limited in composition as long as it has a lower mobility than the first layer L1 of the first oxide semiconductor layer 14A. The thickness of the second oxide semiconductor layer 14B is preferably 30 nm or more, and more preferably 40 nm or more, from the viewpoint of suppressing discontinuities in the second oxide semiconductor layer 14B caused by the light-shielding layer 12. Furthermore, from the viewpoint of reducing steps occurring in the upper insulating layer 19, the thickness of the second oxide semiconductor layer 14B is preferably 80 nm or less.

[0109] A method for manufacturing the TFT substrate 10A will be described with reference to Figures 7A to 7J. Figures 7A to 7J are cross-sectional views illustrating the steps of the method for manufacturing the TFT substrate 10A.

[0110] 7A, a light-shielding layer 12 is formed on a substrate 11. Specifically, a conductive film for the light-shielding layer is formed on an insulating substrate 11 by a sputtering method or the like, and then the conductive film for the light-shielding layer is patterned, thereby forming the light-shielding layer 12.

[0111] 7B, a lower insulating layer 13 is formed to cover the light-shielding layer 12. The lower insulating layer 13 can be formed by, for example, a CVD method.

[0112] 7C, the second oxide semiconductor layer 14B is formed on the lower insulating layer 13. Specifically, first, an oxide semiconductor film is formed by sputtering, and then the oxide semiconductor film is patterned, thereby forming the second oxide semiconductor layer 14B.

[0113] Next, as shown in FIG. 7D, an insulating film 5' is deposited to cover the second oxide semiconductor layer 14B. This insulating film 5' is later patterned to form the insulating layer 5 and the lower layer La of the second gate insulating layer 15B. The lower insulating layer 13 can be formed by, for example, a CVD method. The insulating film 5' can be the same as the lower insulating layer 13.

[0114] 7E, a first oxide semiconductor layer 14A having a stacked structure is formed on the insulating film 5′. Specifically, first, a lower oxide semiconductor film, an intermediate oxide semiconductor film, and an upper oxide semiconductor film are formed from the insulating film 5′ side by sputtering to form a stacked film, and then the stacked film is patterned to form the first oxide semiconductor layer 14A.

[0115] 7F, a first gate insulating layer 15A and a first gate electrode 16A are formed on a part of the first oxide semiconductor layer 14A, and a second gate insulating layer 15B and a second gate electrode 16B are formed on a part of the second oxide semiconductor layer 14B. Specifically, first, a further insulating film and a gate conductive film are deposited in this order so as to cover the first oxide semiconductor layer 14A and the insulating film 5′.

[0116] Next, the gate conductive film is patterned by a photolithography process. Here, a resist layer is formed on the gate conductive film, and the gate conductive film is etched (e.g., wet etching) using this resist layer as a mask to form the first gate electrode 16A and the second gate electrode 16B.

[0117] Thereafter, the resist layer or the first gate electrode 16A and the second gate electrode 16B are used as a mask to etch the further insulating film and the insulating film 5', thereby forming the first gate insulating layer 15A and the second gate insulating layer 15B including the lower layer La and the upper layer Lb. At this time, the insulating film 5' is patterned so that part of it becomes the lower layer La of the second gate insulating layer 15B and the other part becomes the insulating layer 5.

[0118] Next, the first oxide semiconductor layer 14A and the second oxide semiconductor layer 14B are subjected to a resistance reduction treatment. The resistance reduction treatment is, for example, a plasma treatment. As a result, as shown in FIG. 7G, the regions (exposed regions) of the first oxide semiconductor layer 14A that do not overlap with either the first gate electrode 16A or the first gate insulating layer 15A become low-resistance regions (source contact region 14b and drain contact region 14b) that have a lower resistivity than the regions (channel region 14a) that overlap with either the first gate electrode 16A or the first gate insulating layer 15A. Similarly, the regions (exposed regions) of the second oxide semiconductor layer 14B that do not overlap with either the second gate electrode 16B or the second gate insulating layer 15B become low-resistance regions (source contact region 14b and drain contact region 14b) that have a lower resistivity than the regions (channel region 14a) that overlap with either the second gate electrode 16B or the second gate insulating layer 15B. Note that the method of the resistance reduction treatment is not limited to the example given here.

[0119] 7H, an upper insulating layer 19 is formed to cover the first oxide semiconductor layer 14A, the second oxide semiconductor layer 14B, etc. The upper insulating layer 19 can be formed by, for example, a CVD method.

[0120] Next, as shown in FIG. 7I, a first source contact hole CHsA, a first drain contact hole CHdA, a second source contact hole CHsB, and a second drain contact hole CHdB are formed in the upper insulating layer 19. Specifically, these can be formed by a photolithography process and etching. The etching can be, for example, dry etching. In the illustrated example, during the etching, portions of the second layer L2 and the first layer L1 of the first oxide semiconductor layer 14A located within the first source contact hole CHsA and the first drain contact hole CHdA are also removed, exposing the third layer L3 of the first oxide semiconductor layer 14A at the bottom surfaces of the first source contact hole CHsA and the first drain contact hole CHdA.

[0121] 7J, a first source electrode 17A is formed on the upper insulating layer 19 and in the first source contact hole CHsA, and a first drain electrode 18A is formed on the upper insulating layer 19 and in the first drain contact hole CHdA. At this time, a second source electrode 17B is formed on the upper insulating layer 19 and in the second source contact hole CHsB, and a second drain electrode 18B is formed on the upper insulating layer 19 and in the second drain contact hole CHdB. Specifically, a source conductive film is formed on the upper insulating layer 19 and in the first source contact hole CHsA, first drain contact hole CHdA, second source contact hole CHsB, and second drain contact hole CHdB, and then the source conductive film is patterned to form the first source electrode 17A, first drain electrode 18A, second source electrode 17B, and second drain electrode 18B.

[0122] Thereafter, an interlayer insulating layer that covers the first circuit TFT 3A, the second circuit TFT 3B, and the pixel TFT 2, the pixel electrode PE, etc. are formed, thereby obtaining the TFT substrate 10A.

[0123] [Other configurations of TFT substrate] Still another TFT substrate 10B used in the liquid crystal display device 100 according to the embodiment of the present invention will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view schematically showing the TFT substrate 10B, illustrating a region corresponding to a certain circuit TFT3 among the circuit TFTs included in the gate driver 40. The following description will focus on the differences between the TFT substrate 10B and the TFT substrate 10 shown in Fig. 4.

[0124] 8, the TFT substrate 10B differs from the TFT substrate 10 shown in FIG. 4 in that the oxide semiconductor layer 14 of the circuit TFT3 does not include the third layer L3. The oxide semiconductor layer 14 has a laminated structure including a first layer L1 and a second layer L2, and the thickness t2a of the second layer L2 in the channel region 14a is 3.4% or more of the thickness tgi of the gate insulating layer 15. This makes it possible to ensure a sufficient source-drain breakdown voltage of the circuit TFT3.

[0125] 8, the second layer L2 of the oxide semiconductor layer 14 is removed in the source contact hole CHs and the drain contact hole CHd. The source electrode 17 is in contact with a portion of the second layer L2 of the oxide semiconductor layer 14 exposed on the side surface of the source contact hole CHs and a portion of the first layer L1 exposed on the bottom surface of the source contact hole CHs. The drain electrode 18 is in contact with a portion of the second layer L2 of the oxide semiconductor layer 14 exposed on the side surface of the drain contact hole CHd and a portion of the first layer L1 exposed on the bottom surface of the drain contact hole CHd. This structure increases the contact area between the source electrode 17 and / or the drain electrode 18 and the oxide semiconductor layer 14, and by directly contacting the source electrode 17 and / or the drain electrode 18 with the first layer L1, the contact resistance can be more effectively reduced.

[0126] [Gate driver configuration] A specific example of the configuration of the gate driver will be described. The gate driver may have various known configurations, but the configuration disclosed in U.S. Patent Application Publication No. 2020 / 0135132 will be used as an example.

[0127] FIG. 9 is a schematic plan view illustrating a liquid crystal display device 100A provided with a first gate driver 40A and a second gate driver 40B having the configuration disclosed in US Patent Application Publication No. 2020 / 0135132.

[0128] 9, the liquid crystal display device 100A has a display region DR defined by a plurality of pixels P, and a non-display region FR located on the periphery of the display region DR. The liquid crystal display device 100A also includes a first gate driver 40A and a second gate driver 40B that drive gate bus lines GL(1) to GL(i), and a source driver 50 that drives source bus lines SL(1) to SL(j).

[0129] The first gate driver 40A, the second gate driver 40B, and the source driver 50 are arranged in the non-display region FR. The first gate driver 40A and the second gate driver 40B are GDM circuits. The first gate driver 40A is arranged on the left side of the display region DR, and the second gate driver 40B is arranged on the right side of the display region DR. In other words, the first gate driver 40A and the second gate driver 40B are arranged on one end side and the other end side of the gate bus lines GL(1) to GL(i), respectively.

[0130] FIG. 10 is a diagram showing the overall configuration of the first gate driver 40A and the second gate driver 40B.

[0131] The first gate driver 40A and the second gate driver 40B each operate based on a four-phase clock signal consisting of a first gate clock signal GCK1, a second gate clock signal GCK2, a third gate clock signal GCK3, and a fourth gate clock signal GCK4.

[0132] The first gate driver 40A has a first shift register 41A and a first output buffer unit 42A. The first shift register 41A has a plurality of cascaded bistable circuits SR (denoted as SR(n-2), SR(n), SR(n+2), SR(n+4) in FIG. 10). The first output buffer unit 42A has a plurality of buffer circuits Buff (denoted as Buff(n-2), Buff(n-1), Buff(n), Buff(n+1), Buff(n+2), Buff(n+3) in FIG. 10).

[0133] The number of the bistable circuits SR in the first shift register 41A is half the number i of pixel rows (i.e., i / 2). In contrast, the number of the buffer circuits Buff in the first output buffer unit 42A is the same as the number i of pixel rows (i.e., i). Each bistable circuit SR in the first shift register 41A corresponds to two buffer circuits Buff and controls the two buffer circuits Buff by providing its output signal to the two buffer circuits Buff.

[0134] The second gate driver 40B has a second shift register 41B and a second output buffer unit 42B. The second shift register 41B has a plurality of cascaded bistable circuits SR (denoted as SR(n-1), SR(n+1), SR(n+3) in FIG. 10). The second output buffer unit 42B has a plurality of buffer circuits Buff (denoted as Buff(n-2), Buff(n-1), Buff(n), Buff(n+1), Buff(n+2), Buff(n+3) in FIG. 10).

[0135] The number of the plurality of bistable circuits SR in the second shift register 41B is half the number i of pixel rows (i.e., i / 2). In contrast, the number of the plurality of buffer circuits Buff in the second output buffer unit 42B is the same as the number i of pixel rows (i.e., i). Each bistable circuit SR in the second shift register 41B corresponds to two buffer circuits Buff and controls the two buffer circuits Buff by providing its output signal to the two buffer circuits Buff.

[0136] As described above, the first output buffer unit 42A of the first gate driver 40A and the second output buffer unit 42B of the second gate driver 40B each have buffer circuits Buffs in the same number as the number of pixel rows, so that buffer circuits Buffs are connected to both ends of each gate bus line GL. A four-phase clock signal is supplied to each of the first gate driver 40A and the second gate driver 40B. The same gate clock signal is supplied to two buffer circuits Buffs connected to the same gate bus line GL. Each buffer circuit Buff receives the output signal of the corresponding bistable circuit SR and the corresponding gate clock signal, and generates a scanning signal to be supplied to the corresponding gate bus line GL. For example, in the first output buffer unit 42A, the buffer circuit Buff(n) corresponding to the nth gate bus line GL(n) receives the output signal of the bistable circuit S(n) and the first gate clock signal GCK1, generates a scanning signal, and supplies it to the nth gate bus line GL(n). In addition, the buffer circuit Buff(n-1) corresponding to the (n-1)th gate bus line GL(n-1) receives the output signal of the bistable circuit S(n) and the fourth gate clock signal GCK4 to generate a scanning signal, which is supplied to the (n-1)th gate bus line GL(n-1).

[0137] Next, the configuration of the gate drivers will be described in more detail using the first gate driver 410A as an example. Figure 11 is a schematic circuit diagram showing the configuration of the first gate driver 40A.

[0138] The first shift register 41A of the first gate driver 40A includes cascaded bistable circuits SR(n) and SR(n+2). The output terminal of the bistable circuit SR(n) is connected to the input terminal of a buffer circuit Buff(n-1) corresponding to the (n-1)th gate bus line GL(n-1) and the input terminal of a buffer circuit Buff(n) corresponding to the nth gate bus line GL(n). The output terminal of the bistable circuit SR(n+2) is connected to the input terminal of a buffer circuit Buff(n+1) corresponding to the (n+1)th gate bus line GL(n+1) and the input terminal of a buffer circuit Buff(n+2) corresponding to the (n+2)th gate bus line GL(n+2). The fourth gate clock signal GCK4, the first gate clock signal GCK1, the second gate clock signal GCK2, and the third gate clock signal GCK3 are input to the buffer circuits Buff(n-1), Buff(n), Buff(n+1), and Buff(n+2), respectively.

[0139] Hereinafter, one bistable circuit SR and its corresponding two buffer circuits Buff may be collectively referred to as a "unit circuit." In the example shown in Figure 11, the bistable circuit SR(n) and the buffer circuits Buff(n-1) and Buff(n) form one unit circuit, and the bistable circuit SR(n+2) and the buffer circuits Buff(n+1) and Buff(n+2) form another unit circuit.

[0140] The basic configuration of each unit circuit will be described with reference to Fig. 12. Fig. 12 is a circuit diagram showing the basic configuration of a unit circuit including a bistable circuit SR(n). The unit circuit shown in Fig. 12 includes the bistable circuit SR(n) and buffer circuits Buff(n-1) and Buff(n).

[0141] The bistable circuit SR(n) includes two N-channel thin-film transistors TA1 and TA2. The drain terminal of the thin-film transistor TA1 is connected to a high-level power supply line VDD, and the source terminal of the thin-film transistor TA2 is connected to a low-level power supply line VSS. The source terminal of the thin-film transistor TA1 and the drain terminal of the thin-film transistor TA2 are connected to each other, and the connection point between them corresponds to the output terminal of the bistable circuit SR(n). Node NAA(n), which includes this output terminal, will be referred to below as the "first state node."

[0142] The gate terminal of the thin-film transistor TA1 corresponds to the set terminal S, and the gate terminal of the thin-film transistor TA2 corresponds to the reset terminal R. The set terminal S is connected to the (n-2)th gate bus line GL(n-2), and the reset terminal R is connected to the (n+3)th gate bus line GL(n+3).

[0143] The bistable circuit SR(n) enters either a "set state" or a "reset state" by charging or discharging an electric charge in the capacitance connected to the first state node NAA(n). Specifically, when a high-level voltage is applied to the set terminal S, the bistable circuit SR(n) enters the "set state," in which the voltage of the first state node NAA(n) is high. When a high-level voltage is applied to the reset terminal R, the bistable circuit SR(n) enters the "reset state," in which the voltage of the first state node NAA(n) is low. A high-level signal is output from the output terminal of a bistable circuit SR(n) in the "set state."

[0144] The buffer circuit Buff(n-1) includes a buffer transistor TB1, which is an N-channel thin-film transistor, and a boost capacitor CbsA. A fourth gate clock signal GCK4 is applied to the drain terminal of the buffer transistor TB1. The gate terminal of the buffer transistor TB1 corresponds to the input terminal of the buffer circuit Buff(n-1) and is connected to the first state node NAA(n). The source terminal of the buffer transistor TB1 corresponds to the output terminal of the buffer circuit Buff(n-1) and is connected to the gate terminal of the buffer transistor TB1 via the boost capacitor CbsA and to the (n-1)th gate bus line GL(n-1).

[0145] The buffer circuit Buff(n) includes a buffer transistor TB2, which is an N-channel thin-film transistor, and a boost capacitor CbsB. The buffer circuit Buff(n) further includes an N-channel thin-film transistor MS. A first gate clock signal GCK1 is applied to the drain terminal of the buffer transistor TB2. The gate terminal of the buffer transistor TB2 is connected to the first-state node NAA(n) via the thin-film transistor MS. Of the conduction terminals of the thin-film transistor MS, the terminal connected to the first-state node NAA(n) corresponds to the input terminal of the buffer circuit Buff(n). The source terminal of the buffer transistor TB2 corresponds to the output terminal of the buffer circuit Buff(n), and is connected to the gate terminal of the buffer transistor TB2 via the boost capacitor CbsB, as well as to the (n)th gate bus line GL(n).

[0146] The gate terminal of the thin-film transistor MS is connected to a high-level power supply line VDD. Hereinafter, the voltage of the high-level power supply line VDD will be referred to as the "high-level power supply voltage" and will be denoted by the same reference symbol "VDD." If the thin-film transistor MS has a threshold voltage Vth(MS), it is in an off state when the voltages of both its source terminal and drain terminal are higher than VDD-Vth(MS).

[0147] Therefore, even if a pulse of the first gate clock signal GCK1 increases the voltage of the gate terminal of the buffer transistor TB2 of the buffer circuit Buff(n) via the boost capacitor CbsB, i.e., the voltage of the node (hereinafter referred to as the "second-state node") NBA(n) including the gate terminal, when the buffer transistor TB2 of the buffer circuit Buff(n) is in the on state, the voltage increase does not affect the voltage of the first-state node NAA(n).Furthermore, even if a pulse of the fourth gate clock signal GCK4 increases the voltage of the gate terminal of the buffer transistor TB1 of the buffer circuit Buff(n-1) via the boost capacitor CbsA, i.e., the voltage of the first-state node NAA(n), the voltage increase does not affect the voltage of the second-state node NBA(n).

[0148] This is because the thin-film transistor MS, based on its characteristics as a field-effect transistor, operates as a transmission gate that transmits voltages equal to or less than VDD-Vth(MS) and does not transmit voltages exceeding VDD-Vth(MS). The thin-film transistor MS operating as such a transmission gate functions to prevent the boost effect at one of the first-state node NAA(n) and the second-state node NBA(n) from affecting the other node. Hereinafter, the thin-film transistor MS will also be referred to as a "boost isolation transistor."

[0149] Fig. 13 is a circuit diagram showing an example of the detailed configuration of a unit circuit including a bistable circuit SR(n). In the example shown in Fig. 13, the bistable circuit SR(n) has N-channel thin-film transistors M1, M2, M3, M5, M6, M6+, M8, M9, and M14. The set terminal S is connected to the (n-2)th gate bus line GL(n-2), and the reset terminal R is connected to the (n+3)th gate bus line GL(n+3).

[0150] The thin-film transistors M1 and M9 correspond to the thin-film transistors TA1 and TA2, respectively, shown in Fig. 12. The connection point of the thin-film transistors M1 and M9 forms the output terminal of the bistable circuit SR(n), and the node including this output terminal is the first-state node NAA(n).

[0151] The bistable circuit SR(n) also has a clear terminal CLR as an input terminal for a clear signal for initialization, and the gate terminals of the thin-film transistors M2 and M3 are connected to the clear terminal CLR. Note that, hereinafter, the node NB(n) including the connection point of the thin-film transistors M5 and M6 will be referred to as the "third state node."

[0152] The buffer circuit Buff(n-1) has the same configuration as the buffer circuit Buff(n-1) shown in FIG. 12 and includes an N-channel thin-film transistor (buffer transistor) M10A and a boost capacitor CbsA. A fourth gate clock signal GCK4 is applied to the drain terminal of the buffer transistor M10A. A source terminal of the buffer transistor M10A is connected to the (n-1)th gate bus line GL(n-1).

[0153] The buffer circuit Buff(n) has the same configuration as the buffer circuit Buff(n) shown in FIG. 12 and includes an N-channel thin-film transistor (buffer transistor) M10B, an N-channel thin-film transistor (boost isolation transistor) MS, and a boost capacitor CbsB. A first gate clock signal GCK1 is applied to the drain terminal of the buffer transistor M10B. The source terminal of the buffer transistor M10A is connected to the (n)th gate bus line GL(n). The gate terminal of the buffer transistor M10B is connected to the first-state node NAA(n) via the boost isolation transistor MS, and the node including this gate terminal is the second-state node NAB(n).

[0154] The operation of the gate driver having the configuration illustrated here is disclosed in U.S. Patent Application Publication No. 2020 / 0135132, and therefore will not be described here, the entire disclosure of which is incorporated herein by reference.

[0155] [Example of application of circuit TFT3 structure] An example in which the structure of the circuit TFT3 shown in FIG. 4 is applied to the unit circuit shown in FIG. 13 will be described.

[0156] 13, a high-level power supply voltage is applied to one of the source terminal and drain terminal of the thin-film transistor M1, and a low-level voltage is applied to the other terminal for most of one frame. Also, a voltage exceeding the peak-to-peak voltage Vpp of the gate clock signal is applied between the source and drain of the thin-film transistors M2, M8, and M9.

[0157] Therefore, it can be said that the thin-film transistors M1, M2, M8, and M9 are circuit TFTs for which a particularly high source-drain breakdown voltage is desired, and therefore it is preferable to employ the structure of the circuit TFT3 shown in FIG.

[0158] Furthermore, for circuit TFTs that require a particularly high source-drain breakdown voltage, the circuit TFT3 structure may be adopted and tandemized. "Tandemization" here refers to replacing one circuit TFT with two or more circuit TFTs (i.e., at least one pair) connected in series. Replacing each of the thin-film transistors M1, M2, M8, and M9 with two or more circuit TFTs connected in series can further improve the reliability of the GDM circuit.

[0159] Fig. 14 shows a configuration in which the thin-film transistor M9 is tandemly connected. In the example shown in Fig. 14, the thin-film transistor M9 is replaced with two thin-film transistors (circuit TFTs) M9A and M9B connected in series. Note that although an example in which the thin-film transistor M9 is tandemly connected is shown here, the thin-film transistors M1, M2, and M8 may also be tandemly connected in a similar manner.

[0160] Furthermore, for circuit TFTs for which a particularly high source-drain breakdown voltage is desired, the structure of circuit TFT3 may be adopted, and its channel length CL may be set to be longer than the channel lengths CL of the other circuit TFTs. This can also further improve the reliability of the GDM circuit. In this case, the GDM circuit will contain a mixture of circuit TFTs with a first channel length CL1 and circuit TFTs with a second channel length CL2 that is longer than the first channel length CL1.

[0161] [Example of application of the structure of the first circuit TFT3A and the second circuit TFT3B] An example in which the structures of the first circuit TFT 3A and the second circuit TFT 3B shown in FIG. 6 are applied to the unit circuit shown in FIG. 13 will be described.

[0162] As already explained, in the unit circuit shown in FIG. 13, thin-film transistors M1, M2, M8, and M9 are circuit TFTs for which a particularly high source-drain breakdown voltage is desired. Therefore, it is preferable to adopt the structure of the second circuit TFT 3B shown in FIG. 6 for thin-film transistors M1, M2, M8, and M9. Furthermore, while adopting the structure of the second circuit TFT 3B for thin-film transistors M1, M2, M8, and M9, modifications may be made to form tandem structures or to make their channel lengths CL longer than the channel lengths CL of the other circuit TFTs (in which case, a GDM circuit would contain a circuit TFT having a first channel length CL1 and a circuit TFT having a second channel length CL2 longer than the first channel length CL1).

[0163] 13, a gate clock signal with a duty ratio of approximately 50% is applied to one of the source terminal and drain terminal of each of the thin-film transistors M10A and M10B, and a low-level voltage is applied to the other terminal for most of one frame. While it is preferable for the thin-film transistors M10A and M10B to have a high source-drain breakdown voltage, the source-drain breakdown voltage may be somewhat lower than that of the thin-film transistors M1, M2, M8, and M9. Therefore, by adopting the structure of the first circuit TFT3A for the thin-film transistors M10A and M10B, it is possible to reduce the size of the GDM circuit while ensuring the reliability of the GDM.

[0164] [About oxide semiconductors] The oxide semiconductor (also referred to as a metal oxide or an oxide material) contained in the oxide semiconductor layer of the oxide semiconductor TFT may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor whose c-axis is oriented substantially perpendicular to the layer surface.

[0165] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a stacked structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described in, for example, JP 2014-0073911 A. The entire disclosure of JP 2014-0073911 A is incorporated herein by reference.

[0166] The oxide semiconductor layer may contain at least one metal element selected from the group consisting of In, Ga, and Zn. In this embodiment, the oxide semiconductor layer contains, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

[0167] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline, and a crystalline In-Ga-Zn-O based semiconductor in which the c-axis is oriented approximately perpendicular to the layer plane is preferred as the crystalline In-Ga-Zn-O based semiconductor.

[0168] The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed, for example, in the aforementioned Japanese Patent Application Laid-Open Nos. 2014-0073911, 2012-134475, and 2014-2090627. For reference, the entire disclosures of Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-2090627 are incorporated herein by reference. TFTs having an In-Ga-Zn-O-based semiconductor layer have high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one-hundredth that of an a-Si TFT). Therefore, they are suitable for use as driver TFTs (e.g., TFTs included in a driver circuit provided on the same substrate as a display area, around a display area including multiple pixels) and pixel TFTs (TFTs provided in pixels).

[0169] The oxide semiconductor layer may contain other oxide semiconductors instead of In-Ga-Zn-O-based semiconductors. For example, it may contain In-Sn-Zn-O-based semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). In-Sn-Zn-O-based semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, an In-W-Zn-O based semiconductor, or the like. [Industrial Applicability]

[0170] According to an embodiment of the present invention, it is possible to provide an active matrix substrate that includes a scanning signal line drive circuit including an oxide semiconductor TFT and that can achieve both a high source-drain breakdown voltage and high mobility in the oxide semiconductor TFT. [Explanation of symbols]

[0171] 1 Display panel 2 pixel TFT 3 circuit TFT 3A 1st circuit TFT 3B 2nd circuit TFT 5. Insulation layer 10, 10A, 10B Active matrix substrate (TFT substrate) 11 Circuit Board 12 Light blocking layer 13 Lower insulating layer 14 Oxide semiconductor layer 14A First oxide semiconductor layer 14B Second oxide semiconductor layer 14a Channel region 14b Source contact region (first contact region) 14c Drain contact region (second contact region) 15 Gate insulating layer 15A First gate insulating layer 15B Second gate insulating layer 16 gate electrode 16A First gate electrode 16B Second gate electrode 17 Source electrode 17A First source electrode 17B Second source electrode 18 Drain electrode 18A First drain electrode 18B Second drain electrode 19 Upper insulating layer 20 Counter substrate (color filter substrate) 30 Liquid crystal layer 40 Scanning signal line driving circuit (gate driver) 40A 1st Gate Driver 40B Second gate driver 41A First shift register 41B Second shift register 42A 1st output buffer section 42B Second output buffer section 50 Video signal line drive circuit (source driver) 100 LCD display device DR display area FR hidden area P pixel GL Scanning signal line (gate bus line) SL Video signal line (source bus line) PE pixel electrode CE common electrode SR1~SRi unit circuit CHs source contact hole CHsA 1st source contact hole CHsB Second source contact hole CHd Drain contact hole CHdA First drain contact hole CHdB Second drain contact hole L1 First oxide semiconductor layer L2 Second layer of oxide semiconductor layer L3 Third oxide semiconductor layer La Lower layer of the second gate insulating layer Lb Upper layer of the second gate insulating layer

Claims

1. A substrate; a plurality of scanning signal lines supported by the substrate; a scanning signal line driving circuit for driving the plurality of scanning signal lines, the scanning signal line driving circuit having a plurality of oxide semiconductor TFTs; An active matrix substrate comprising: the plurality of oxide semiconductor TFTs include a plurality of first oxide semiconductor TFTs, Each of the first oxide semiconductor TFTs is a first oxide semiconductor layer including a channel region and a first contact region and a second contact region located on both sides of the channel region, respectively; a first gate electrode disposed on the channel region of the first oxide semiconductor layer via a first gate insulating layer; a first source electrode electrically connected to the first contact region; a first drain electrode electrically connected to the second contact region; the first oxide semiconductor layer has a stacked structure including a first layer and a second layer that is located between the first layer and the first gate insulating layer and is an uppermost layer of the first oxide semiconductor layer, the second layer having a mobility lower than that of the first layer; an active matrix substrate, wherein the thickness of the second layer in the channel region is 3.4% or more of the thickness of the first gate insulating layer;

2. 2. The active matrix substrate according to claim 1, wherein the second layer in the channel region has a thickness of 5 nm or more.

3. 3. The active matrix substrate according to claim 1, wherein the first oxide semiconductor layer further includes a third layer located on an opposite side of the first layer from the second layer, the third layer having a lower mobility than the first layer.

4. 3. The active matrix substrate according to claim 1, wherein the plurality of first oxide semiconductor TFTs include at least one pair of first oxide semiconductor TFTs connected in series.

5. the plurality of oxide semiconductor TFTs include an oxide semiconductor TFT having a first channel length CL1; 3. The active matrix substrate according to claim 1, wherein the plurality of first oxide semiconductor TFTs include a first oxide semiconductor TFT having a second channel length CL2 that is longer than the first channel length CL1.

6. the plurality of oxide semiconductor TFTs further include a plurality of second oxide semiconductor TFTs; Each second oxide semiconductor TFT is a second oxide semiconductor layer separate from the first oxide semiconductor layer, the second oxide semiconductor layer having a lower mobility than the first layer of the first oxide semiconductor layer; 3 . The active matrix substrate according to claim 1 , further comprising: a second gate electrode disposed on a portion of the second oxide semiconductor layer with a second gate insulating layer interposed therebetween.

7. The active matrix substrate according to claim 6 , wherein the plurality of second oxide semiconductor TFTs include at least one pair of second oxide semiconductor TFTs connected in series.

8. the plurality of oxide semiconductor TFTs include an oxide semiconductor TFT having a first channel length CL1; The active matrix substrate according to claim 6 , wherein the plurality of second oxide semiconductor TFTs include a second oxide semiconductor TFT having a second channel length CL2 greater than the first channel length CL1.

9. The active matrix substrate according to claim 1 , wherein the first gate insulating layer does not overlap the first contact region and the second contact region of the first oxide semiconductor layer in a plan view.

10. an upper insulating layer covering the first oxide semiconductor layer and the first gate electrode; the upper insulating layer has a source contact hole for electrically connecting the first source electrode to the first contact region and a drain contact hole for electrically connecting the first drain electrode to the second contact region; 3. The active matrix substrate according to claim 1, wherein the second layer of the first oxide semiconductor layer is present at least in a region of the first contact region that does not overlap with the source contact hole, and is present at least in a region of the second contact region that does not overlap with the drain contact hole.

11. the second layer of the first oxide semiconductor layer is removed in a portion of the first contact region and a portion of the second contact region; The active matrix substrate according to claim 1 , wherein the first source electrode and the first drain electrode are in direct contact with the first layer of the first oxide semiconductor layer.

12. 3. The active matrix substrate according to claim 1, wherein the scanning signal line driving circuit is monolithically formed on the active matrix substrate.

13. 3. The active matrix substrate according to claim 1, wherein the first oxide semiconductor layer includes an In--Ga--Zn--O based semiconductor.

14. A display device comprising the active matrix substrate according to claim 1 or 2.

15. 3. A method for manufacturing an active matrix substrate according to claim 1, comprising the steps of: Step (A) of forming the first oxide semiconductor layer; After the step (A), a step (B) of depositing an insulating film on the first oxide semiconductor layer; a step (C) of forming the first gate insulating layer by etching the insulating film after the step (B); Including, a thickness of the second layer of the first oxide semiconductor layer formed in the step (A) is set so that the second layer remains over the entire region that will become the first contact region and the entire region that will become the second contact region when the step (C) is completed.

Images