Power supply controller and power supply device

Abstract

To shift a timing of switching among a plurality of channels.SOLUTION: A first DC / DC converter (4[1]) generates a first output voltage (VOUT[1]) from a first input voltage (VIN[1]) through switching operation of a first switching output stage (12[1]). A second DC / DC converter (4[2]) generates a second output voltage (VOUT[2]) from a second input voltage (VIN[2]) through switching operation of a second switching output stage (12[2]). A phase adjustment circuit (30) adjusts a phase of switching operation of each switching output stage based on a ratio between the first input voltage and the first output voltage and a ratio between the second input voltage and the second output voltage.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device and a power supply device. [Background technology]

[0002] Power supply devices (composite power supply devices) equipped with multiple channels of DC / DC converters that obtain output voltages from input voltages through switching operations are used in a variety of systems. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-174080

[0004] [overview] In this type of power supply device, if the switching timings of the channels overlap, this can lead to an increase in noise and the like.

[0005] A power supply control device according to one embodiment of the present disclosure is configured to control the operation of a power supply having a plurality of DC / DC converters, wherein the plurality of DC / DC converters include a first DC / DC converter configured to generate a first output voltage from a first input voltage through switching operation of a first switching output stage, and a second DC / DC converter configured to generate a second output voltage from a second input voltage through switching operation of a second switching output stage, and the power supply control device further comprises: a first control drive circuit configured to control the switching operation of the first switching output stage in accordance with the first output voltage; a second control drive circuit configured to control the switching operation of the second switching output stage in accordance with the second output voltage; and a phase adjustment circuit configured to adjust the phase of the switching operation of each switching output stage based on a ratio between the first input voltage and the first output voltage and a ratio between the second input voltage and the second output voltage. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic configuration block diagram of a power supply device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external perspective view of a power supply control device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing a state in which a multi-channel DC / DC converter is provided in a power supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing a state in which a DC / DC converter with multiple channels is provided in a power supply device according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic configuration diagram of a power supply control device according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is an explanatory diagram of a switching operation in the first channel according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a configuration diagram of a switching circuit in the first channel according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is an explanatory diagram of a switching operation in the second channel according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a configuration diagram of a switching circuit in the second channel according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a timing chart when the first delay process is performed according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a timing chart when the second delay process is performed according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a timing chart when the first and second delay processes are performed according to an embodiment of the present disclosure. [Figure 13] FIG. 13 relates to Example EX1_A belonging to an embodiment of the present disclosure and is a diagram illustrating the configuration of DC / DC converters of the first and second channels. [Figure 14]FIG. 14 is a timing chart for explaining the operation of the DC / DC converter of the first channel according to Example EX1_A belonging to the embodiment of the present disclosure. [Figure 15] FIG. 15 is a timing chart for explaining the operation of the DC / DC converter of the second channel according to Example EX1_A belonging to the embodiment of the present disclosure. [Figure 16] FIG. 16 is a timing chart for explaining the contents of the delay process according to Example EX1_A belonging to the embodiment of the present disclosure. [Figure 17] FIG. 17 is a timing chart for explaining the contents of the delay process according to Example EX1_A belonging to the embodiment of the present disclosure. [Figure 18] FIG. 18 relates to Example EX2_A belonging to an embodiment of the present disclosure and is a diagram illustrating the configuration of DC / DC converters of the first and second channels. [Figure 19] FIG. 19 is a timing chart for explaining the operation of the DC / DC converter of the first channel according to Example EX2_A belonging to the embodiment of the present disclosure. [Figure 20] FIG. 20 is a timing chart for explaining the operation of the DC / DC converter of the second channel according to Example EX2_A belonging to the embodiment of the present disclosure. [Figure 21] FIG. 21 is a timing chart for explaining the contents of the delay process according to Example EX2_A of the embodiment of the present disclosure. [Figure 22] FIG. 22 is a timing chart for explaining the contents of the delay process according to Example EX2_A belonging to the embodiment of the present disclosure. [Figure 23] FIG. 23 relates to Example EX3_A belonging to an embodiment of the present disclosure and is a diagram illustrating the configuration of DC / DC converters of the first and second channels. [Figure 24] FIG. 24 is a timing chart for explaining the contents of the delay process according to Example EX3_A belonging to the embodiment of the present disclosure. [Figure 25]FIG. 25 is a timing chart for explaining the contents of the delay process according to Example EX3_A belonging to the embodiment of the present disclosure. [Figure 26] FIG. 26 is an internal configuration diagram of a delay setting circuit according to Example EX4 of the embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components, and may omit or abbreviate the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs. For example, the clock signal referred to by "CLK" (see FIG. 5) described below may be written as clock signal CLK or abbreviated as signal CLK, but they all refer to the same thing.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a particular reference represents a potential seen from ground.

[0009] A level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a transition from a low level to a high level is sometimes referred to as a rising edge, and a transition from a high level to a low level is sometimes referred to as a falling edge. The timing at which a rising edge occurs is sometimes referred to as rising edge timing, and the timing at which a falling edge occurs is sometimes referred to as falling edge timing.

[0010] For any transistor configured as a FET (field effect transistor) exemplified by a MOSFET, the on-state refers to a state in which the drain and source of the transistor are conducting, and the off-state refers to a state in which the drain and source of the transistor are non-conducting (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0011] Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off. For any transistor, the switching from the off-state to the on-state may be particularly referred to as turn-on, and the switching from the on-state to the off-state may be particularly referred to as turn-off. The timing at which any transistor turns on (the timing of switching from the off-state to the on-state) may be referred to as turn-on timing. The timing at which any transistor turns off (the timing of switching from the on-state to the off-state) may be referred to as turn-off timing.

[0012] The connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection unless otherwise specified. <​​​​​1 is a schematic block diagram of a power supply device 1 according to an embodiment of the present disclosure. The power supply device 1 includes a power supply control device 2 and a discrete component group 3 made up of a plurality of discrete components externally connected to the power supply control device 2. The power supply control device 2 may be an electronic component classified as a PMIC (Power Management IC). In the following description, wiring provided outside the power supply control device 2 may be specifically referred to as external wiring.

[0015] Figure 2 shows an external perspective view of the power supply control device 2. The power supply control device 2 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing CS to the outside of the power supply control device 2. The power supply control device 2 is formed by sealing the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the power supply control device 2 and the type of housing CS of the power supply control device 2 shown in Figure 2 are merely examples, and can be designed as desired.

[0016] As shown in Fig. 3, the power supply device 1 is provided with n channels of DC / DC converters 4, i.e., n DC / DC converters 4. In this embodiment, unless otherwise specified, n represents any integer equal to or greater than 2. The n channels of DC / DC converters 4 can also be expressed as n channels of power supply devices, in which case the power supply device 1 can also be referred to as a composite power supply device having n channels of power supply devices (4).

[0017] The n channels are comprised of the first to n-th channels. Each DC / DC converter 4 is connected to an input voltage V IN is supplied, and the input voltage V IN is converted into power to produce an output voltage V OUT The input voltage V IN and output voltage V OUT are different DC voltages. The input voltage V IN or output voltage V OUT can be a negative DC voltage, but in the following, the input voltage VIN and output voltage V OUT is a positive DC voltage.

[0018] The DC / DC converter 4 of one or more of the first to n-th channels may be a switching regulator. IN By stepping down the input voltage V IN Lower output voltage V OUT A step-down switching regulator that generates an input voltage V IN By boosting the input voltage V IN Higher output voltage V OUT The DC / DC converter 4 of one or more of the first to n-th channels may be a linear regulator.

[0019] A total of n output voltages V for the first to nth channels OUT are different DC voltages. A Output voltage V at the channel OUT and the value of the i B Output voltage V at the channel OUT There may be cases where the value of i A and i B represents any natural number less than or equal to n. A Input voltage V at the channel IN is the i B Input voltage V at the channel IN The input voltage V of any one of the first to nth channels may be the same as or different from IN is the power supply voltage of the power supply control device 2 (power supply voltage V PW ) may also be used.

[0020] As shown in FIG. 4, the DC / DC converter 4 in the i-th channel, the input voltage V IN , output voltage V OUT , respectively, in particular, the DC / DC converter 4[i], the input voltage V IN [i], output voltage VOUT The input voltage V IN to output voltage V OUT The power supply control device 2 controls the operation (power conversion) of the power supply device 1. That is, the power supply control device 2 controls the operation (power conversion) of the DC / DC converter 4 for each channel.

[0021] One or more switching regulators and one or more linear regulators may be mixed among the total of n DC / DC converters 4 in the first to nth channels. However, in this embodiment, two or more switching regulators are included among the total of n DC / DC converters 4 in the first to nth channels, and the DC / DC converters 4 of the first and second channels are included among these two or more switching regulators.

[0022] FIG. 5 shows a schematic configuration diagram of the power supply control device 2. However, in FIG. 5, the components of the DC / DC converters 4 of the third to n-th channels are not shown. As part of the above-mentioned multiple external terminals provided in the power supply control device 2, FIG. 5 shows a power supply terminal PIN, a ground terminal GND, and terminals Ta[1], Tb[1], Ta[2], and Tb[2]. A power supply voltage V is supplied to the power supply terminal PIN from a voltage source (not shown). PW The power supply voltage V PW has a positive DC voltage value. When the power supply device 1 is installed in a vehicle such as an automobile, a power supply voltage V PW The ground terminal GND is connected to ground.

[0023] The power supply control device 2 includes switching circuits 10[1] and 10[2]. The switching circuits 10[1] and 10[2] are components of the DC / DC converters 4[1] and 4[2], respectively. The switching circuit 10[1] includes a control drive circuit 11[1] and an output stage 12[1], which is a switching output stage. The switching circuit 10[2] includes a control drive circuit 11[2] and an output stage 12[2], which is a switching output stage. The output stage 12[1] includes transistors 13[1] and 14[1]. The output stage 12[2] includes transistors 13[2] and 14[2]. The transistors 13[1] and 13[2] are P-channel MOSFETs, and the transistors 14[1] and 14[2] are N-channel MOSFETs. However, a variation in which the transistors 13[1] and 13[2] are N-channel MOSFETs can also be used.

[0024] The transistor 13[1] is provided between the terminals Ta[1] and Tb[1], and the transistor 14[1] is provided between the terminal Tb[1] and ground. Specifically, the source of the transistor 13[1] is connected to the terminal Ta[1]. The drains of the transistors 13[1] and 14[1] are commonly connected to the terminal Tb[1]. The source of the transistor 14[1] is connected to ground. In addition to the ground terminal GND, a power ground terminal (not shown) connected to ground may be provided as an external terminal of the power supply control device 2, and the source of the transistor 14[1] may be connected to the power ground terminal. The transistor 13[2] is provided between the terminals Ta[2] and Tb[2], and the transistor 14[2] is provided between the terminal Tb[2] and ground. Specifically, the source of the transistor 13[2] is connected to the terminal Ta[2]. The drains of the transistors 13[2] and 14[2] are commonly connected to the terminal Tb[2]. The source of transistor 14[2] is connected to ground. A power ground terminal (not shown) connected to ground may be provided as an external terminal of the power supply control device 2 in addition to the ground terminal GND, and the source of transistor 14[2] may be connected to the power ground terminal.

[0025] The control drive circuit 11[1] is connected to the gates of the transistors 13[1] and 14[1]. The control drive circuit 11[1] outputs an output voltage V OUT [1] and reference voltage V REF [1] is supplied and the signal SET[1] is supplied. The output voltage V OUT The target voltage in [1] is represented by the symbol "V TG [1]” The target voltage V TG [1] has a predetermined positive DC voltage value. The control drive circuit 11[1] outputs an output voltage V OUT [1] to the target voltage V TG The control drive circuit 11 [1] performs switching control to stabilize the output voltage V OUT [1] and reference voltage V REF The transistors 13[1] and 14[1] are alternately turned on and off by controlling the gate voltages of the transistors 13[1] and 14[1] based on the signal SET[1]. At this time, the control drive circuit 11[1] controls the switching of the output stage 12[1] using pulse width modulation synchronized with the signal SET[1]. The output voltage V OUT [1] to the target voltage V TG To achieve the stabilizing switching control in [1], a coil and a capacitor connected to the output stage 12 [1] are required, which will be described later.

[0026] The switching operation of the control drive circuit 11[1] is performed in the output stage 12[1]. The switching operation of the output stage 12[1] is, in other words, the switching operation in the first channel. As shown in FIG. 6, in the switching operation in the first channel (the switching operation of the output stage 12[1]), the state of the output stage 12[1] alternates between states STa[1] and STb[1]. State STa[1] is a high-side-on state in which the transistor 13[1] is turned on and the transistor 14[1] is turned off. State STb[1] is a low-side-on state in which the transistor 13[1] is turned off and the transistor 14[1] is turned on. In order to reliably prevent the transistors 13[1] and 14[1] from being turned on simultaneously, the control drive circuit 11[1] may perform dead time processing to turn off both the transistors 13[1] and 14[1] for a short dead time when switching the state of the output stage 12[1] between states STa[1] and STb[1]. For the sake of convenience, the dead time processing by the control drive circuit 11[1] will be ignored below.

[0027] 7 shows a schematic internal configuration of the control drive circuit 11[1]. The control drive circuit 11[1] includes resistors 111[1] and 112[1], a control circuit 113[1], and a driver 114[1]. An output voltage V OUT [1] is applied, and the second terminal of resistor 111[1] and the first terminal of resistor 112[1] are commonly connected at node 115[1]. The second terminal of resistor 112[1] is connected to ground. Node 115[1] is connected to the resistance ratio of resistors 111[1] and 112[1] and the output voltage V OUT [1] The feedback voltage V FB [1] is generated. The feedback voltage V FB [1] and the reference voltage V REF The control circuit 113[1] is supplied with a feedback voltage V FB [1] and reference voltage V REFA control signal CNT[1] is output to the driver 114[1] so that the error between the transistors 13[1] and 14[1] converges to zero. At this time, the control circuit 113[1] generates the control signal CNT[1] using pulse width modulation synchronized with the signal SET[1]. The driver 114[1] controls the gate voltages of the transistors 13[1] and 14[1] according to the control signal CNT[1], thereby turning the transistors 13[1] and 14[1] on and off individually.

[0028] Referring again to FIG. 5, the control drive circuit 11[2] is connected to the gates of the transistors 13[2] and 14[2]. The output voltage V OUT [2] and reference voltage V REF [2] is supplied and the signal SET[2] is supplied. The output voltage V OUT The target voltage in [2] is represented by the symbol "V TG [2]” The target voltage V TG [2] has a predetermined positive DC voltage value. The control drive circuit 11[2] outputs an output voltage V OUT [2] to the target voltage V TG The control drive circuit 11 [2] performs switching control to stabilize the output voltage V OUT [2] and reference voltage V REF The transistors 13[2] and 14[2] are alternately turned on and off by controlling the gate voltages of the transistors 13[2] and 14[2] based on the signal SET[2]. At this time, the control drive circuit 11[2] controls the switching of the output stage 12[2] using pulse width modulation synchronized with the signal SET[2]. The output voltage V OUT [2] is the target voltage V TG To achieve the stabilizing switching control in [2], a coil and a capacitor connected to the output stage 12 [2] are required, which will be described later.

[0029] The switching operation of the control drive circuit 11[2] is performed in the output stage 12[2]. The switching operation of the output stage 12[2] is, in other words, the switching operation in the second channel. As shown in FIG. 8, in the switching operation in the second channel (the switching operation of the output stage 12[2]), the state of the output stage 12[2] alternates between states STa[2] and STb[2]. State STa[2] is a high-side-on state in which the transistor 13[2] is turned on and the transistor 14[2] is turned off. State STb[2] is a low-side-on state in which the transistor 13[2] is turned off and the transistor 14[2] is turned on. In order to reliably prevent the transistors 13[2] and 14[2] from being turned on simultaneously, the control drive circuit 11[2] may perform dead time processing to turn off both the transistors 13[2] and 14[2] for a short dead time when switching the state of the output stage 12[2] between states STa[2] and STb[2]. For the sake of convenience, the dead time processing by the control drive circuit 11[2] will be ignored below.

[0030] 9 shows the schematic internal configuration of the control drive circuit 11[2]. The control drive circuit 11[2] includes resistors 111[2] and 112[2], a control circuit 113[2], and a driver 114[2]. An output voltage V OUT [2] is applied, and the second terminal of resistor 111[2] and the first terminal of resistor 112[2] are commonly connected at node 115[2]. The second terminal of resistor 112[2] is connected to ground. Node 115[2] is connected to the resistance ratio of resistors 111[2] and 112[2] and the output voltage V OUT [2] The feedback voltage V FB [2] is generated. The feedback voltage V FB [2] and the reference voltage V REF The control circuit 113[2] is supplied with a feedback voltage V FB [2] and reference voltage V REFA control signal CNT[2] is output to the driver 114[2] so that the error between the transistors 13[2] and 14[2] converges to zero. At this time, the control circuit 113[2] generates the control signal CNT[2] using pulse width modulation synchronized with the signal SET[2]. The driver 114[2] controls the gate voltages of the transistors 13[2] and 14[2] according to the control signal CNT[2], thereby turning the transistors 13[2] and 14[2] on and off individually.

[0031] The power supply control device 2 (see FIG. 5) includes switching circuits 10[1] and 10[2], as well as an oscillator 20, a phase adjustment circuit 30, a reference voltage generation circuit 40, and an internal power supply circuit 50. The oscillator 20 generates and outputs a clock signal CLK. The clock signal CLK is a rectangular wave signal that alternates between high and low signal levels. The frequency of the clock signal CLK is defined as a clock frequency f CLK The clock frequency f CLK may be fixed at a predetermined frequency or may be varied using a spread spectrum technique. In the following, the clock frequency f CLK is treated as having a constant value.

[0032] The phase adjustment circuit 30 includes a delay setting circuit 31 and a delay insertion circuit 32. The phase adjustment circuit 30 receives an input voltage V IN [1] and V IN [2] and output voltage V OUT [1] and V OUT The delay insertion circuit 32 generates signals SET[1] and SET[2] based on the clock signal CLK supplied from the oscillator 20, and outputs the signal SET[1] to the control drive circuit 11[1] and the signal SET[2] to the control drive circuit 11[2]. Like the clock signal CLK, the signals SET[1] and SET[2] are square wave signals that alternate between high and low signal levels, and the frequencies of the signals SET[1] and SET[2] are the clock frequency f CLKThe delay insertion circuit 32 executes at least one of a first delay process that generates a signal SET[1] by applying a delay to the clock signal CLK and a second delay process that generates a signal SET[2] by applying a delay to the clock signal CLK.

[0033] FIG. 10 shows the waveforms of the signals CLK, SET[1], and SET[2] when only the first delay process is performed in the delay insertion circuit 32. FIG. 11 shows the waveforms of the signals CLK, SET[1], and SET[2] when only the second delay process is performed in the delay insertion circuit 32. FIG. 12 shows the waveforms of the signals CLK, SET[1], and SET[2] when both the first and second delay processes are performed in the delay insertion circuit 32. Note that the duty cycles of the signals CLK, SET[1], and SET[2] are arbitrary. Significant information exists in the rising edge timing of each of the signals CLK, SET[1], and SET[2]. The length of the high-level period of each of the signals CLK, SET[1], and SET[2] (the length of the period during which each of the signals CLK, SET[1], and SET[2] is at a high level) is constant.

[0034] The delay time of the rising edge timing of the signal SET[1] from the rising edge timing of the clock signal CLK is defined as delay time t DLY The delay time of the rising edge timing of the signal SET[2] from the rising edge timing of the clock signal CLK is called delay time t DLY When the first delay process is performed by the delay insertion circuit 32, “t DLY [1]>0” (see FIG. 10) and the delay time t DLY When only the first delay process is performed in the delay insertion circuit 32, the rising edge timing of the clock signal CLK and the rising edge timing of the signal SET[2] are the same. DLY When the second delay process is performed in the delay insertion circuit 32, it can be considered that "t DLY[2]>0” (see FIG. 11), and the delay time t DLY When only the second delay process is performed in the delay insertion circuit 32, the rising edge timing of the clock signal CLK and the rising edge timing of the signal SET[1] are the same. DLY When both the first and second delay processes are executed in the delay insertion circuit 32, as shown in FIG. DLY [1]>0” and “t DLY [2]>0” and the delay time t DLY [1] and t DLY [2] are different from each other.

[0035] The delay setting circuit 31 sets the input voltage V IN [1] and V IN [2] and output voltage V OUT [1] and V OUT Based on [2], the delay time t DLY [1] or t DLY [2] is set, or the delay time t DLY [1] and t DLY [2] is set (details will be explained later). Delay time t DLY The setting of [1] adjusts the phase of the switching operation of the output stage 12[1], and the delay time t DLY The setting of [2] adjusts the phase of the switching operation of the output stage 12[2].

[0036] The reference voltage generating circuit 40 generates the above-mentioned reference voltage V REF [1] and V REF [2] Generates and outputs multiple reference voltages, including the reference voltage V REF [1] and V REF [2] each has a predetermined positive DC voltage value.

[0037] The internal power supply circuit 50 is connected to the power supply terminal PIN and supplies the power supply voltage V PW Each circuit in the power supply control device 2 generates one or more internal power supply voltages based on the power supply voltage V PWor based on the internal power supply voltage generated by the internal power supply circuit 50.

[0038] Below, several specific configuration examples, operation examples, application techniques, modified techniques, etc. related to the power supply device 1 or the power supply control device 2 will be described among several embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in that embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the following embodiments can also be applied to any of the other embodiments (i.e., any two or more of the multiple embodiments can be combined).

[0039] <<Example EX1_A>> Example EX1_A will be described. In Example EX1_A, DC / DC converters 4[1] and 4[2] are both step-down switching regulators. Figure 13 shows the configuration of DC / DC converters 4[1] and 4[2] and peripheral circuits according to Example EX1_A. The power supply control device 2 according to Example EX1_A has terminals Tc[1] and Tc[2] as two external terminals.

[0040] A DC / DC converter 4[1] according to Example EX1_A will be described. When the DC / DC converter 4[1] is a step-down switching regulator, the DC / DC converter 4[1] includes a switching circuit 10[1], a coil L[1], and a capacitor C[1]. The terminals Ta[1], Tb[1], and Tc[1] are also considered to be included in the components of the DC / DC converter 4[1]. When the DC / DC converter 4[1] is a step-down switching regulator, the terminals Ta[1], Tb[1], and Tc[1] function as a first channel input terminal, a coil connection terminal, and a feedback terminal, respectively, and the transistors 13[1] and 14[1] function as a switching transistor (output transistor) and a synchronous rectifier transistor, respectively. The coil L[1] and the capacitor C[1] are components of the discrete component group 3 and are provided outside the power supply control device 2.

[0041] When the DC / DC converter 4 [1] is a step-down switching regulator, the terminal Ta [1] is connected to the input voltage V supplied from a DC voltage source (not shown). IN [1], and therefore the input voltage V IN When the DC / DC converter 4[1] is a step-down switching regulator, the terminal Tb[1] is connected to the first end of the coil L[1], the second end of the coil L[1] and the first end of the capacitor C[1] are connected to the output node OUT[1], the second end of the capacitor C[1] is connected to ground, the output node OUT[1] is connected to the terminal Tc[1] through an external wiring, and the output voltage V is supplied to the output node OUT[1]. OUT If the DC / DC converter 4[1] is a step-down switching regulator, the output voltage V applied to the terminal Tc[1] OUT [1] is supplied to the control drive circuit 11[1] and the delay setting circuit 31, and the input voltage V applied to the terminal Ta[1] IN [1] is supplied to the delay setting circuit 31.

[0042] 14 shows a timing chart of the DC / DC converter 4[1] according to the embodiment EX1_A. The length of the switching period of the output stage 12[1] is the period length t CYC The period length t CYC is the clock frequency f CLK The control drive circuit 11[1] according to the embodiment EX1_A provides a period in each switching cycle in which the output stage 12[1] is set to the high side on state STa[1] and a period in which it is set to the low side on state STb[1] (see FIG. 6). In each switching cycle, the length of the period in which the output stage 12[1] is set to the high side on state STa[1] is defined as time t HON [1]. In each switching period, the period length t CYC Time t HON The ratio of [1] is called the duty ratio H_DUTY[1]. HON [1]=t CYC ×H_DUTY[1]”.

[0043] In Example EX1_A, the control drive circuit 11[1] switches the state of the output stage 12[1] from the low-side on state STb[1] to the high-side on state STa[1] in response to the rising edge of the signal SET[1] (although not shown, there is also a case where both the transistors 13[1] and 14[1] are switched from the off state to the high-side on state STa[1]). HON When [1] has elapsed, the control drive circuit 11[1] switches the state of the output stage 12[1] from the high-side on state STa[1] to the low-side on state STb[1].

[0044] In each switching period of the DC / DC converter 4[1] according to the embodiment EX1_A, the terminal Tb[1] is approximately equal to the input voltage V IN A square wave signal fluctuating between the voltages of [1] and ground is generated, and the square wave signal at terminal Tb[1] is rectified and smoothed by a rectifying and smoothing circuit consisting of coil L[1] and capacitor C[1], and an output voltage V is generated at output node OUT[1]. OUT The control drive circuit 11[1] according to the embodiment EX1_A generates “V FB [1]>V REF When "V[1]" is established, the duty ratio H_DUTY[1] is decreased and "V FB [1] <V REF When [1]" is established, the duty ratio H_DUTY[1] increases during the time t HON [1] is feedback controlled. This allows the voltage V FB [1] and V REF [1] approaches or remains substantially zero, and therefore the output voltage V OUT [1] is the target voltage V TG [1] The target voltage V TG [1] is the resistance ratio of resistors 111[1] and 112[1] and the reference voltage V REF [1] is determined.

[0045] The DC / DC converter 4[2] according to Example EX1_A will be described. In Example EX1_A, the DC / DC converter 4[2] is also a step-down switching regulator like the DC / DC converter 4[1]. Therefore, the configuration and operation of the DC / DC converter 4[2] are similar to those of the DC / DC converter 4[1]. That is, when the DC / DC converter 4[2] is a step-down switching regulator, the DC / DC converter 4[2] includes a switching circuit 10[2], a coil L[2], and a capacitor C[2]. Terminals Ta[2], Tb[2], and Tc[2] can also be considered to be included in the components of the DC / DC converter 4[2]. When the DC / DC converter 4[2] is a step-down switching regulator, the terminals Ta[2], Tb[2], and Tc[2] function as the input terminal, coil connection terminal, and feedback terminal of the second channel, respectively. Furthermore, the transistors 13[2] and 14[2] function as a switching transistor (output transistor) and a synchronous rectification transistor, respectively. The coil L[2] and the capacitor C[2] are components of the discrete component group 3, and are provided outside the power supply control device 2.

[0046] When the DC / DC converter 4 [2] is a step-down switching regulator, the terminal Ta [2] is connected to the input voltage V supplied from a DC voltage source (not shown). IN [2], and therefore the input voltage V IN When the DC / DC converter 4[2] is a step-down switching regulator, the terminal Tb[2] is connected to the first end of the coil L[2], the second end of the coil L[2] and the first end of the capacitor C[2] are connected to the output node OUT[2], the second end of the capacitor C[2] is connected to ground, the output node OUT[2] is connected to the terminal Tc[2] through external wiring, and the output voltage V is supplied to the output node OUT[2]. OUT If the DC / DC converter 4 [2] is a step-down switching regulator, the output voltage V applied to the terminal Tc [2] is OUT [2] is supplied to the control drive circuit 11[2] and the delay setting circuit 31, and the input voltage V applied to the terminal Ta[2]IN [2] is supplied to the delay setting circuit 31.

[0047] 15 shows a timing chart of the DC / DC converter 4[2] according to the embodiment EX1_A. The control drive circuit 11[2] according to the embodiment EX1_A provides a period in each switching cycle in which the output stage 12[2] is set to the high side on state STa[2] and a period in which it is set to the low side on state STb[2] (see FIG. 8). In each switching cycle, the length of the period in which the output stage 12[2] is set to the high side on state STa[2] is defined as time t HON [2]. In each switching period, the period length t CYC Time t HON The ratio of [2] is called the duty ratio H_DUTY[2]. HON [2]=t CYC ×H_DUTY[2]”.

[0048] In the embodiment EX1_A, the control drive circuit 11[2] switches the state of the output stage 12[2] from the low-side on state STb[2] to the high-side on state STa[2] in response to the rising edge of the signal SET[2] (although not shown, there is also a case where both the transistors 13[2] and 14[2] are switched from the off state to the high-side on state STa[2]). HON When the time [2] has elapsed, the control drive circuit 11[2] switches the state of the output stage 12[2] from the high-side on state STa[2] to the low-side on state STb[2].

[0049] In each switching period of the DC / DC converter 4[2] according to the embodiment EX1_A, the terminal Tb[2] is approximately equal to the input voltage V IN A square wave signal fluctuating between the voltages of [2] and ground is generated, and the square wave signal at terminal Tb[2] is rectified and smoothed by the rectifying and smoothing circuit consisting of coil L[2] and capacitor C[2], and the output voltage V is generated at output node OUT[2]. OUT The control drive circuit 11[2] according to the embodiment EX1_A generates “V FB [2]>V REFWhen "V[2]" is established, the duty ratio H_DUTY[2] is decreased and "V FB [2] <V REF When [2]" is established, the duty ratio H_DUTY[2] increases during the time t HON [2] is feedback controlled. This allows the voltage V FB [2] and V REF [2] approaches or remains substantially zero, and therefore the output voltage V OUT [2] is the target voltage V TG [2] The target voltage V TG [2] is the resistance ratio of resistors 111[2] and 112[2] and the reference voltage V REF [2] is determined as follows.

[0050] When the switching timing of the output stage of multiple switching regulators overlaps, jitter occurs. Jitter increases the ripple of the output voltage, which in turn leads to an increase in radiated noise. For this reason, it is necessary to shift the switching timing between multiple switching regulators. In Example EX1_A, if "V IN [1]=V IN [2]” If the target voltage is V TG [1] and V TG Since the relationship between the duty ratios H_DUTY[1] and H_DUTY[2] can be determined from the ratio between the input voltage V IN [1] and V IN [2] is 5V and the target voltage V TG [1] and V TG When H_DUTY[1] and H_DUTY[2] are 2V and 3V, respectively, the reference method shows that "(H_DUTY[1], H_DUTY[2]) = (0.4, 0.6)" in the steady state. In the reference method, the switching timing can be shifted based on the relationship between the duty ratios H_DUTY[1] and H_DUTY[2]. For example, the cycle length t CYC If is 200ns (nanoseconds), then time t HON [1] and t HON[2] are 80 ns and 120 ns, respectively, so the timing of switching can be shifted by performing delay processing to delay the rising edge timing of signal SET[2] by 40 ns from the rising edge timing of clock signal CLK.

[0051] However, the input voltage V IN [1] and V IN In a configuration where [2] may differ, further ingenuity is required. IN [1] and V IN [2] may be the same or may differ from each other.

[0052] Therefore, the delay setting circuit 31 is IN [1] and output voltage V OUT Based on [1], the duty ratio H_DUTY[1] is derived according to the following equation (11), and the input voltage V IN [2] and output voltage V OUT Based on [2], the duty ratio H_DUTY[2] is derived according to the following equation (12). CYC is known, and the delay setting circuit 31 determines the time t HON [1] and t HON [2] is derived. However, the duty ratios H_DUTY[1] and H_DUTY[2] and the time t HON [1] and t HON [2] is the duty ratio H_DUTY[1] and H_DUTY[2] in the steady state and the time t HON [1] and t HON [2]. The steady state is the output voltage V OUT [1] and V OUT [2] is the target voltage V TG [1] and V TG [2] is the stable state. H_DUTY[1]=V OUT [1] / V IN [1] (11) H_DUTY[2]=V OUT [2] / VIN [2] (12) t HON [1]=t CYC ×H_DUTY[1] (13) t HON [2]=t CYC ×H_DUTY[2] ···(14)

[0053] The delay setting circuit 31 calculates the time t HON [1] and t HON The success or failure of the formulas (15a) and (15b) is determined by comparing [2]. Note that the t HON [1], t HON [2], H_DUTY[1] and H_DUTY[2] are the values ​​that satisfy the equations (11) to (14). HON [1], t HON [2], H_DUTY[1] and H_DUTY[2]. t HON [1] <t HON [2] (15a) t HON [1]>t HON [2] (15b)

[0054] The case where equation (15a) is satisfied is referred to as case CS1a. Fig. 16 shows a timing chart for case CS1a. In case CS1a, the delay setting circuit 31 controls the delay insertion circuit 32 so that only the second delay process is performed among the first and second delay processes described above, and sets the delay time t DLY [2] (thus setting the delay time t DLY In case CS1a, the delay setting circuit 31 sets the delay time t so that the following equations (16a) and (17a) are satisfied. DLY In case CS1a, assuming that equation (17a) is satisfied, DLY [2]=t HON[1] / J" (J is a real number greater than 1, for example, 2). In case CS1a, the phase of the switching operation of the output stage 12[2] (in other words, the phase of the switching of the transistor 13[2]) is delayed by a delay time t DLY [2] is adjusted to be slower by the amount corresponding to time t HON [2] has a periodic length t CYC A smaller upper limit is set, and the time t HON Even if [2] coincides with the upper limit, the delay time t DLY [2] can be set. 0 <t DLY [2] <t HON [1] (16a) t DLY [2]+t HON [2] <t CYC (17a)

[0055] In case CS1a, the equations (16a) and (17a) are satisfied, and therefore the requirements X1 and X2 are satisfied.

[0056] The requirement X1 is a condition that the timing of switching from the low-side on state STb[1] to the high-side on state STa[1] in the output stage 12[1] is different from the timing of switching from the low-side on state STb[2] to the high-side on state STa[2] in the output stage 12[2], and is different from the timing of switching from the high-side on state STa[2] to the low-side on state STb[2] in the output stage 12[2]. The requirement X2 is a condition that the timing of switching from the high-side on state STa[1] to the low-side on state STb[1] in the output stage 12[1] is different from the timing of switching from the low-side on state STb[2] to the high-side on state STa[2] in the output stage 12[2], and is different from the timing of switching from the high-side on state STa[2] to the low-side on state STb[2] in the output stage 12[2].

[0057] The case where equation (15b) holds is referred to as case CS1b. Fig. 17 shows a timing chart for case CS1b. In case CS1b, the delay setting circuit 31 controls the delay insertion circuit 32 so that only the first delay process of the above-mentioned first and second delay processes is performed, and also controls the delay time t DLY Set [1] (thus delay time t DLY In case CS1b, the delay setting circuit 31 sets the delay time t so that the following equations (16b) and (17b) are satisfied. DLY In case CS1b, assuming that equation (17b) is satisfied, DLY [1]=t HON [2] / J" (J is a real number greater than 1, for example, 2). In case CS1b, the phase of the switching operation of the output stage 12[1] (in other words, the phase of the switching of the transistor 13[1]) is delayed by a delay time t DLY [1] is adjusted to be slower by the amount corresponding to time t HON [1] has a periodic length t CYC A smaller upper limit is set, and the time t HON Even if [1] coincides with the upper limit, the delay time t DLY [1] can be set. 0 <t DLY [1] <t HON [2] (16b) t DLY [1]+t HON [1] <t CYC (17b)

[0058] In case CS1b, the equations (16b) and (17b) are satisfied, and therefore the requirements X1 and X2 are satisfied.

[0059] The delay setting circuit 31 calculates the time t HON [1] and t HON[2] are equal to each other, the delay time t DLY [2] may be set, or the delay time t DLY [1] may be set, and in either case, the requirements X1 and X2 are satisfied.

[0060] When the requirements X1 and X2 are met, the switching timing of the output stage 12[1] and the switching timing of the output stage 12[2] do not overlap. The phase adjustment circuit 30 adjusts the phase of the switching operation of the output stage 12[1] and the phase of the switching operation of the output stage 12[2] so that the requirements X1 and X2 are met. As a result of this adjustment, the timing of switching the transistor 13[1] from OFF to ON differs from the timing of switching the transistor 13[2] from OFF to ON and the timing of switching the transistor 13[2] from ON to OFF, and the timing of switching the transistor 13[1] from OFF to ON differs from the timing of switching the transistor 13[2] from OFF to ON and the timing of switching the transistor 13[2] from ON to OFF.

[0061] In case CS1a (see FIG. 16), the phase of the switching operation of output stage 12[1] corresponds to the phase of the turn-on timing of transistor 13[1] from the rising edge timing of clock signal CLK, and is therefore 0 radians. In case CS1a, the phase of the switching operation of output stage 12[2] corresponds to the phase of the turn-on timing of transistor 13[2] from the rising edge timing of clock signal CLK, and is therefore 2π×t DLY [2] / t CYC In case CS1b (see FIG. 17), the phase of the switching operation of the output stage 12[2] corresponds to the phase of the turn-on timing of the transistor 13[2] seen from the rising edge timing of the clock signal CLK, and is therefore 0 radians. In case CS1b, the phase of the switching operation of the output stage 12[1] corresponds to the phase of the turn-on timing of the transistor 13[1] seen from the rising edge timing of the clock signal CLK, and is therefore 2π×tDLY [1] / t CYC "It is radian.

[0062] In this way, in the embodiment EX1_A, the switching timing of the output stage 12[1] and the switching timing of the output stage 12[2] can be appropriately shifted. Therefore, jitter is suppressed, and the output voltage V OUT [1] and V OUT [2] The ripple is suppressed, and as a result, the radiated noise is also suppressed.

[0063] <<Example EX1_B>> An example EX1_B will be described. In the example EX1_B, a modified technique for the example EX1_A will be described based on the matters shown in the example EX1_A. In the example EX1_A, the delay setting circuit 31 controls the delay insertion circuit 32 so that both the first and second delay processes are performed, and sets the delay time t DLY [1] and t DLY [2] can be set (i.e., "t DLY [1]>0” and “t DLY [2]>0” is also acceptable).

[0064] In this case, in case CS1a where the above formula (15a) is satisfied, the delay setting circuit 31 sets the delay time t so that the following formulas (16a_1) and (17a_1) are satisfied instead of the above formulas (16a) and (17a). DLY [1] and t DLY In case CS1b where the above equation (15b) is satisfied, the delay setting circuit 31 sets the delay time t so that the following equations (16b_1) and (17b_1) are satisfied instead of the above equations (16b) and (17b). DLY [1] and t DLY [2]. In either case, requirements X1 and X2 are met. 0 <t DLY [1] <t DLY [2] <t HON [1]+t DLY [1] ···(16a_1) t DLY [2]+tHON [2] <t CYC +t DLY [1] ···(17a_1) 0 <t DLY [2] <t DLY [1] <t HON [2]+t DLY [2] ···(16b_1) t DLY [1]+t HON [1] <t CYC +t DLY [2] ···(17b_1)

[0065] The delay setting circuit 31 calculates the time t HON [1] and t HON [2] are equal to each other, the delay time t DLY [1] and t DLY [2] can be set, which satisfies the requirements X1 and X2.

[0066] <<Example EX2_A>> Example EX2_A will be described. In Example EX2_A, DC / DC converters 4[1] and 4[2] are both step-up switching regulators. Figure 18 shows the configuration of DC / DC converters 4[1] and 4[2] and peripheral circuits according to Example EX2_A. The power supply control device 2 according to Example EX2_A has two external terminals, terminals Td[1] and Td[2].

[0067] A DC / DC converter 4[1] according to Example EX2_A will be described. When the DC / DC converter 4[1] is a step-up switching regulator, the DC / DC converter 4[1] includes a switching circuit 10[1], a coil L[1], and a capacitor C[1]. The terminals Ta[1], Tb[1], and Td[1] are also considered to be included in the components of the DC / DC converter 4[1]. When the DC / DC converter 4[1] is a step-up switching regulator, the terminals Ta[1], Tb[1], and Td[1] function as a first channel output terminal, a coil connection terminal, and an input voltage information acquisition terminal, respectively. Furthermore, the transistors 13[1] and 14[1] function as a synchronous rectifier transistor and a switching transistor (output transistor), respectively. The coil L[1] and the capacitor C[1] are components of the discrete component group 3 and are provided outside the power supply control device 2.

[0068] When the DC / DC converter 4[1] is a step-up switching regulator, the terminal Tb[1] is connected to the first end of the coil L[1], and the second end of the coil L[1] is connected to the input voltage V IN [1] is connected to the input node IN[1], and the terminal Ta[1] is the output voltage V OUT The first terminal of the capacitor C[1] is connected to the output node OUT[1], the second terminal of the capacitor C[1] is connected to ground, and the terminal Td[1] is connected to the input node IN[1] through external wiring. If the DC / DC converter 4[1] is a step-up switching regulator, the output voltage V applied to the terminal Ta[1] OUT [1] is supplied to the control drive circuit 11[1] and the delay setting circuit 31, and the input voltage V applied to the terminal Td[1] IN [1] is supplied to the delay setting circuit 31. However, in addition to the terminal Ta[1], an external terminal connected to the output node OUT[1] is provided in the power supply control device 2, and the output voltage V OUT [1] may be supplied to the control drive circuit 11[1] and the delay setting circuit 31.

[0069] 19 shows a timing chart of the DC / DC converter 4[1] according to the embodiment EX2_A. As described above, the length of the switching period of the output stage 12[1] is set to the period length t CYC The period length t CYC is the clock frequency f CLK The control drive circuit 11[1] according to the embodiment EX2_A provides a period in each switching cycle in which the output stage 12[1] is set to the low-side ON state STb[1] and a period in which it is set to the high-side ON state STa[1] (see FIG. 6). In each switching cycle, the length of the period in which the output stage 12[1] is set to the low-side ON state STb[1] is defined as time t LON [1]. In each switching period, the period length t CYC Time t LON The ratio of [1] is called the duty ratio L_DUTY[1]. LON [1]=t CYC ×L_DUTY[1]”.

[0070] In Example EX2_A, the control drive circuit 11[1] switches the state of the output stage 12[1] from the high-side on state STa[1] to the low-side on state STb[1] in response to the rising edge of the signal SET[1] (although not shown, there is also a case where both the transistors 13[1] and 14[1] are switched from the off state to the low-side on state STb[1]). LON When [1] has elapsed, the control drive circuit 11[1] switches the state of the output stage 12[1] from the low-side on state STb[1] to the high-side on state STa[1].

[0071] In each switching period of the DC / DC converter 4[1] according to the embodiment EX2_A, energy is stored in the coil L[1] in the low-side ON state STb[1], and a current due to the stored energy in the coil L[1] flows toward the output node OUT[1] through the transistor 13[1] in the high-side ON state STa[1]. FB [1]>V REFWhen "V[1]" is established, the duty ratio L_DUTY[1] decreases and "V FB [1] <V REF When [1]" is established, the duty ratio L_DUTY[1] increases during the time t LON [1] is feedback controlled. This allows the voltage V FB [1] and V REF [1] approaches or remains substantially zero, and therefore the output voltage V OUT [1] is the target voltage V TG [1] The target voltage V TG [1] is the resistance ratio of resistors 111[1] and 112[1] and the reference voltage V REF [1] is determined.

[0072] The DC / DC converter 4[2] according to Example EX2_A will be described. In Example EX2_A, the DC / DC converter 4[2] is also a step-up switching regulator like the DC / DC converter 4[1], so the configuration and operation of the DC / DC converter 4[2] are similar to those of the DC / DC converter 4[1]. That is, when the DC / DC converter 4[2] is a step-up switching regulator, the DC / DC converter 4[2] includes a switching circuit 10[2], a coil L[2], and a capacitor C[2]. The terminals Ta[2], Tb[2], and Td[2] can also be considered to be included in the components of the DC / DC converter 4[2]. When the DC / DC converter 4[2] is a step-up switching regulator, the terminals Ta[2], Tb[2], and Td[2] function as the output terminal, coil connection terminal, and input voltage information acquisition terminal of the second channel, respectively, and the transistors 13[2] and 14[2] function as a synchronous rectifier transistor and a switching transistor (output transistor), respectively. The coil L[2] and the capacitor C[2] are components of the discrete component group 3 and are provided outside the power supply control device 2.

[0073] When the DC / DC converter 4[2] is a step-up switching regulator, the terminal Tb[2] is connected to the first end of the coil L[2], and the second end of the coil L[2] is connected to the input voltage VIN [2] is connected to the input node IN[2], and the terminal Ta[2] is the output voltage V OUT The first end of the capacitor C[2] is connected to the output node OUT[2], the second end of the capacitor C[2] is connected to ground, and the terminal Td[2] is connected to the input node IN[2] through external wiring. If the DC / DC converter 4[2] is a step-up switching regulator, the output voltage V applied to the terminal Ta[2] is OUT [2] is supplied to the control drive circuit 11[2] and the delay setting circuit 31, and the input voltage V applied to the terminal Td[2] IN [2] is supplied to the delay setting circuit 31. However, in addition to the terminal Ta[2], an external terminal connected to the output node OUT[2] is provided in the power supply control device 2, and the output voltage V OUT [2] may be supplied to the control drive circuit 11[2] and the delay setting circuit 31.

[0074] 20 shows a timing chart of the DC / DC converter 4[2] according to the embodiment EX2_A. The control drive circuit 11[2] according to the embodiment EX2_A provides a period in each switching cycle in which the output stage 12[2] is set to the low-side ON state STb[2] and a period in which it is set to the high-side ON state STa[2] (see FIG. 8). In each switching cycle, the length of the period in which the output stage 12[2] is set to the low-side ON state STb[2] is defined as time t LON [2]. In each switching period, the period length t CYC Time t LON The ratio of [2] is called the duty ratio L_DUTY[2]. LON [2]=t CYC ×L_DUTY[2]”.

[0075] In Example EX2_A, the control drive circuit 11[2] switches the state of the output stage 12[2] from the high-side on state STa[2] to the low-side on state STb[2] in response to the rising edge of the signal SET[2] (although not shown, there is also a case where both the transistors 13[2] and 14[2] are switched from the off state to the low-side on state STb[2]). LON When [2] has elapsed, the control drive circuit 11[2] switches the state of the output stage 12[2] from the low-side on state STb[2] to the high-side on state STa[2].

[0076] In each switching period of the DC / DC converter 4[2] according to the embodiment EX2_A, energy is stored in the coil L[2] in the low-side ON state STb[2], and a current due to the stored energy in the coil L[2] flows toward the output node OUT[2] through the transistor 13[2] in the high-side ON state STa[2]. FB [2]>V REF When "V[2]" is established, the duty ratio L_DUTY[2] is decreased and "V FB [2] <V REF When [2]" is established, the duty ratio L_DUTY[2] increases during the time t LON [2] is feedback controlled. This allows the voltage V FB [2] and V REF [2] approaches or remains substantially zero, and therefore the output voltage V OUT [2] is the target voltage V TG [2] The target voltage V TG [2] is the resistance ratio of resistors 111[2] and 112[2] and the reference voltage V REF [2] is determined as follows.

[0077] In the embodiment EX2_A, the switching timing is shifted in the same manner as in the embodiment EX1_A. Specifically, the delay setting circuit 31 shifts the switching timing by a delay time equal to the input voltage V IN [1] and output voltage V OUTBased on [1], the duty ratio L_DUTY[1] is derived according to the following equation (21), and the input voltage V IN [2] and output voltage V OUT Based on [2], the duty ratio L_DUTY[2] is derived according to the following equation (22). CYC is known, and the delay setting circuit 31 determines the time t LON [1] and t LON [2] is derived. However, the duty ratios L_DUTY[1] and L_DUTY[2] and the time t LON [1] and t LON [2] is the duty ratio L_DUTY[1] and L_DUTY[2] in the steady state and the time t LON [1] and t LON [2]. The steady state is the output voltage V OUT [1] and V OUT [2] is the target voltage V TG [1] and V TG [2] is the stable state. L_DUTY[1]=1-V IN [1] / V OUT [1] (21) L_DUTY[2]=1-V IN [2] / V OUT [2] (22) t LON [1]=t CYC ×L_DUTY[1] ···(23) t LON [2]=t CYC ×L_DUTY[2] ···(24)

[0078] The delay setting circuit 31 calculates the time t LON [1] and t LON The success or failure of formulas (25a) and (25b) is determined by comparing [2]. Note that the t in each formula shown below in Example EX2_A and each formula shown in Example EX2_B described later LON [1], t LON[2], L_DUTY[1] and L_DUTY[2] are the values ​​that satisfy the equations (21) to (24). LON [1], t LON [2], L_DUTY[1] and L_DUTY[2]. t LON [1] <t LON [2] (25a) t LON [1]>t LON [2] (25b)

[0079] The case where equation (25a) is satisfied is referred to as case CS2a. Figure 21 shows a timing chart for case CS2a. In case CS2a, the delay setting circuit 31 controls the delay insertion circuit 32 so that only the second delay process is performed out of the first and second delay processes described above, and also controls the delay time t DLY [2] (thus setting the delay time t DLY In case CS2a, the delay setting circuit 31 sets the delay time t so that the following equations (26a) and (27a) are satisfied. DLY In case CS2a, assuming that equation (27a) is satisfied, DLY [2]=t LON [1] / J" (J is a real number greater than 1, for example, 2). In case CS2a, the phase of the switching operation of the output stage 12[2] (in other words, the phase of the switching of the transistor 14[2]) is delayed by a delay time t DLY [2] is adjusted to be slower by the amount corresponding to time t LON [2] has a periodic length t CYC A smaller upper limit is set, and the time t LON Even if [2] coincides with the upper limit, the delay time t DLY [2] can be set. 0 <t DLY [2] <t LON [1] (26a) t DLY [2]+t LON [2] <tCYC (27a)

[0080] In case CS2a, the requirements X1 and X2 are satisfied by satisfying the formulas (26a) and (27a). The meanings of the requirements X1 and X2 are as shown in Example EX1_A.

[0081] The case where equation (25b) holds is referred to as case CS2b. Fig. 22 shows a timing chart for case CS2b. In case CS2b, the delay setting circuit 31 controls the delay insertion circuit 32 so that only the first delay process of the above-mentioned first and second delay processes is performed, and also controls the delay time t DLY Set [1] (thus delay time t DLY In case CS2b, the delay setting circuit 31 sets the delay time t so that the following equations (26b) and (27b) are satisfied. DLY In case CS2b, we set "t DLY [1]=t LON [2] / J" (J is a real number greater than 1, for example, 2). In case CS2b, the phase of the switching operation of the output stage 12[1] (in other words, the phase of the switching of the transistor 14[1]) is delayed by a delay time t DLY [1] is adjusted to be slower by the amount corresponding to time t LON [1] has a periodic length t CYC A smaller upper limit is set, and the time t LON Even if [1] coincides with the upper limit, the delay time t DLY [1] can be set. 0 <t DLY [1] <t LON [2] (26b) t DLY [1]+t LON [1] <t CYC (27b)

[0082] In case CS2b, the equations (26b) and (27b) are satisfied, and therefore the requirements X1 and X2 are satisfied.

[0083] The delay setting circuit 31 calculates the time t LON [1] and t LON [2] are equal to each other, the delay time t DLY [2] may be set, or the delay time t DLY [1] may be set, and in either case, the requirements X1 and X2 are satisfied.

[0084] When the requirements X1 and X2 are met, the switching timing of the output stage 12[1] and the switching timing of the output stage 12[2] do not overlap. The phase adjustment circuit 30 adjusts the phase of the switching operation of the output stage 12[1] and the phase of the switching operation of the output stage 12[2] so that the requirements X1 and X2 are met. As a result of this adjustment, the timing of switching the transistor 14[1] from OFF to ON differs from the timing of switching the transistor 14[2] from OFF to ON and the timing of switching the transistor 14[2] from ON to OFF, and the timing of switching the transistor 14[1] from OFF to ON differs from the timing of switching the transistor 14[2] from OFF to ON and the timing of switching the transistor 14[2] from ON to OFF.

[0085] In case CS2a (see FIG. 21), the phase of the switching operation of the output stage 12[1] corresponds to the phase of the turn-on timing of the transistor 14[1] from the rising edge timing of the clock signal CLK, and is therefore 0 radians. In case CS2a, the phase of the switching operation of the output stage 12[2] corresponds to the phase of the turn-on timing of the transistor 14[2] from the rising edge timing of the clock signal CLK, and is therefore 2π×t DLY [2] / t CYCIn case CS2b (see FIG. 22), the phase of the switching operation of the output stage 12[2] corresponds to the phase of the turn-on timing of the transistor 14[2] relative to the rising edge timing of the clock signal CLK, and is therefore 0 radians. In case CS2b, the phase of the switching operation of the output stage 12[1] corresponds to the phase of the turn-on timing of the transistor 14[1] relative to the rising edge timing of the clock signal CLK, and is therefore 2π×t DLY [1] / t CYC "It is radian.

[0086] In this way, in the embodiment EX2_A, the switching timing of the output stage 12[1] and the switching timing of the output stage 12[2] can be appropriately shifted. Therefore, jitter is suppressed, and the output voltage V OUT [1] and V OUT [2] The ripple is suppressed, and as a result, the radiated noise is also suppressed.

[0087] <<Example EX2_B>> An example EX2_B will be described. In the example EX2_B, a modified technique for the example EX2_A will be described based on the matters shown in the example EX2_A. In the example EX2_A, the delay setting circuit 31 controls the delay insertion circuit 32 so that both the first and second delay processes are performed, and sets the delay time t DLY [1] and t DLY [2] can be set (i.e., "t DLY [1]>0” and “t DLY [2]>0” is also acceptable).

[0088] In this case, in case CS2a where the above formula (25a) is satisfied, the delay setting circuit 31 sets the delay time t so that the following formulas (26a_1) and (27a_1) are satisfied instead of the above formulas (26a) and (27a). DLY [1] and t DLY In case CS2b where the above equation (25b) is satisfied, the delay setting circuit 31 sets the delay time t so that the following equations (26b_1) and (27b_1) are satisfied instead of the above equations (26b) and (27b).DLY [1] and t DLY [2]. In either case, requirements X1 and X2 are met. 0 <t DLY [1] <t DLY [2] <t LON [1]+t DLY [1] ···(26a_1) t DLY [2]+t LON [2] <t CYC +t DLY [1] ···(27a_1) 0 <t DLY [2] <t DLY [1] <t LON [2]+t DLY [2] ···(26b_1) t DLY [1]+t LON [1] <t CYC +t DLY [2] ···(27b_1)

[0089] The delay setting circuit 31 calculates the time t LON [1] and t LON [2] are equal to each other, the delay time t DLY [1] and t DLY [2] can be set, which satisfies the requirements X1 and X2.

[0090] <<Example EX3_A>> Example EX3_A will be described. In Example EX3_A, the DC / DC converter 4[1] is a step-down switching regulator, while the DC / DC converter 4[2] is a step-up switching regulator. Figure 23 shows the configuration of the DC / DC converters 4[1] and 4[2] and peripheral circuits according to Example EX3_A. The power supply control device 2 according to Example EX3_A has two external terminals, terminals Tc[1] and Td[2].

[0091] The configuration and operation of the DC / DC converter 4[1] in the embodiment EX3_A are the same as those of the DC / DC converter 4[1] in the embodiment EX1_A. The configuration and operation of the DC / DC converter 4[2] in the embodiment EX3_A are the same as those of the DC / DC converter 4[2] in the embodiment EX2_A.

[0092] For the delay setting circuit 31 according to the embodiment EX3_A, as described in the embodiment EX1_A, the input voltage V IN [1] and output voltage V OUT [1] is supplied and the input voltage V IN [2] and output voltage V OUT [2] is provided.

[0093] The delay setting circuit 31 is connected to the input voltage V IN [1] and output voltage V OUT Based on [1], the duty ratio H_DUTY[1] is derived according to the following equation (31), and the input voltage V IN [2] and output voltage V OUT Based on [2], the duty ratio L_DUTY[2] is derived according to the following equation (32). The equation (31) is the same as the equation (11) shown in the embodiment EX1_A, and the equation (32) is the same as the equation (22) shown in the embodiment EX2_A. For the delay setting circuit 31, the period length t CYC is known, and the delay setting circuit 31 determines the time t HON [1] and t LON [2] is derived. Equation (33) is the same as equation (13) shown in Example EX1_A, and equation (34) is the same as equation (24) shown in Example EX2_A. The duty ratios H_DUTY[1] and L_DUTY[2] and the time t HON [1] and t LON [2] is the duty ratio H_DUTY[1] and L_DUTY[2] in the steady state and the time t HON [1] and t LON [2]. The steady state is the output voltage V OUT [1] and V OUT[2] is the target voltage V TG [1] and V TG [2] is the stable state. H_DUTY[1]=V OUT [1] / V IN [1] (31) L_DUTY[2]=1-V IN [2] / V OUT [2] (32) t HON [1]=t CYC ×H_DUTY[1] (33) t LON [2]=t CYC ×L_DUTY[2] ···(34)

[0094] The delay setting circuit 31 calculates the time t HON [1] and t LON The success or failure of formulas (35a) and (35b) is determined by comparing [2]. Note that the t in each formula shown below in Example EX3_A and each formula shown in Example EX3_B described later HON [1], t LON [2], H_DUTY[1] and L_DUTY[2] are the values ​​that satisfy the equations (31) to (34). HON [1], t LON [2], H_DUTY[1] and L_DUTY[2]. t HON [1] <t LON [2] (35a) t HON [1]>t LON [2] (35b)

[0095] The case where equation (35a) holds is referred to as case CS3a. Figure 24 shows a timing chart for case CS3a. In case CS3a, the delay setting circuit 31 controls the delay insertion circuit 32 so that only the second delay process is performed out of the first and second delay processes described above, and also controls the delay time t DLY [2] (thus setting the delay time t DLYIn case CS3a, the delay setting circuit 31 sets the delay time t so that the following equations (36a) and (37a) are satisfied. DLY In case CS3a, assuming that equation (37a) is satisfied, DLY [2]=t HON [1] / J" (J is a real number greater than 1, for example, 2). In case CS3a, the phase of the switching operation of the output stage 12[2] (in other words, the phase of the switching of the transistor 14[2]) is delayed by a delay time t DLY [2] is adjusted to be slower by the amount corresponding to time t LON [2] has a periodic length t CYC A smaller upper limit is set, and the time t LON Even if [2] coincides with the upper limit, the delay time t DLY [2] can be set. 0 <t DLY [2] <t HON [1] (36a) t DLY [2]+t LON [2] <t CYC (37a)

[0096] In case CS3a, the requirements X1 and X2 are satisfied by satisfying the formulas (36a) and (37a). The meanings of the requirements X1 and X2 are as shown in Example EX1_A.

[0097] The case where equation (35b) holds is referred to as case CS3b. Fig. 25 shows a timing chart for case CS3b. In case CS3b, the delay setting circuit 31 controls the delay insertion circuit 32 so that only the first delay process of the above-mentioned first and second delay processes is performed, and also controls the delay time t DLY Set [1] (thus delay time t DLY In case CS3b, the delay setting circuit 31 sets the delay time t so that the following equations (36b) and (37b) are satisfied.DLY In case CS3b, assuming that equation (37b) is satisfied, DLY [1]=t LON [2] / J" (J is a real number greater than 1, for example, 2). In case CS3b, the phase of the switching operation of the output stage 12[1] (in other words, the phase of the switching of the transistor 13[1]) is delayed by a delay time t DLY [1] is adjusted to be slower by the amount corresponding to time t HON [1] has a periodic length t CYC A smaller upper limit is set, and the time t HON Even if [1] coincides with the upper limit, the delay time t DLY [1] can be set. 0 <t DLY [1] <t LON [2] (36b) t DLY [1]+t HON [1] <t CYC (37b)

[0098] In case CS3b, the equations (36b) and (37b) are satisfied, and therefore the requirements X1 and X2 are satisfied.

[0099] The delay setting circuit 31 calculates the time t HON [1] and t LON [2] are equal to each other, the delay time t DLY [2] may be set, or the delay time t DLY [1] may be set, and in either case, the requirements X1 and X2 are satisfied.

[0100] When the requirements X1 and X2 are met, the switching timing of the output stage 12[1] and the switching timing of the output stage 12[2] do not overlap. The phase adjustment circuit 30 adjusts the phase of the switching operation of the output stage 12[1] and the phase of the switching operation of the output stage 12[2] so that the requirements X1 and X2 are met. As a result of this adjustment, the timing of switching the transistor 13[1] from OFF to ON differs from the timing of switching the transistor 14[2] from OFF to ON and the timing of switching the transistor 14[2] from ON to OFF, and the timing of switching the transistor 13[1] from OFF to ON differs from the timing of switching the transistor 14[2] from OFF to ON and the timing of switching the transistor 14[2] from ON to OFF.

[0101] In case CS3a (see FIG. 24), the phase of the switching operation of output stage 12[1] corresponds to the phase of the turn-on timing of transistor 13[1] from the rising edge timing of clock signal CLK, and is therefore 0 radians. In case CS3a, the phase of the switching operation of output stage 12[2] corresponds to the phase of the turn-on timing of transistor 14[2] from the rising edge timing of clock signal CLK, and is therefore 2π×t DLY [2] / t CYC In case CS3b (see FIG. 25), the phase of the switching operation of the output stage 12[2] corresponds to the phase of the turn-on timing of the transistor 14[2] relative to the rising edge timing of the clock signal CLK, and is therefore 0 radians. In case CS3b, the phase of the switching operation of the output stage 12[1] corresponds to the phase of the turn-on timing of the transistor 13[1] relative to the rising edge timing of the clock signal CLK, and is therefore 2π×t DLY [1] / t CYC "It is radian.

[0102] In this way, in the embodiment EX3_A, the switching timing of the output stage 12[1] and the switching timing of the output stage 12[2] can be appropriately shifted. Therefore, jitter is suppressed, and the output voltage V OUT [1] and V OUT [2] The ripple is suppressed, and as a result, the radiated noise is also suppressed.

[0103] <<Example EX3_B>> An example EX3_B will be described. In the example EX3_B, a modified technique for the example EX3_A will be described based on the matters shown in the example EX3_A. In the example EX3_A, the delay setting circuit 31 controls the delay insertion circuit 32 so that both the first and second delay processes are performed, and sets the delay time t DLY [1] and t DLY [2] can be set (i.e., "t DLY [1]>0” and “t DLY [2]>0” is also acceptable).

[0104] In this case, in case CS3a where the above formula (35a) is satisfied, the delay setting circuit 31 sets the delay time t so that the following formulas (36a_1) and (37a_1) are satisfied instead of the above formulas (36a) and (37a). DLY [1] and t DLY In case CS3b where the above equation (35b) is satisfied, the delay setting circuit 31 sets the delay time t so that the following equations (36b_1) and (37b_1) are satisfied instead of the above equations (36b) and (37b). DLY [1] and t DLY [2]. In either case, requirements X1 and X2 are met. 0 <t DLY [1] <t DLY [2] <t HON [1]+t DLY [1] ···(36a_1) t DLY [2]+t LON [2] <t CYC +t DLY [1] ···(37a_1) 0 <t DLY [2] <t DLY [1] <t LON [2]+t DLY [2] ···(36b_1) t DLY [1]+t HON [1] <t CYC +t DLY [2] ···(37b_1)

[0105] The delay setting circuit 31 calculates the time t HON [1] and t LON [2] are equal to each other, the delay time t DLY [1] and t DLY [2] can be set, which satisfies the requirements X1 and X2.

[0106] <<Example EX4>> An example EX4 will be described below. Fig. 26 shows the internal configuration of the delay setting circuit 31. The delay setting circuit 31 includes an AD conversion circuit 31a, an arithmetic circuit 31b, and a delay determination circuit 31c.

[0107] The input voltage V IN [1] and V IN [2] and output voltage V OUT [1] and V OUT [2] is supplied as an analog voltage signal. The AD conversion circuit 31a converts the input voltage V IN [1] and V IN [2] and output voltage V OUT [1] and V OUT [2] are converted into digital signals, and digital signal D IN [1], D IN [2], D OUT [1] and D OUT [2] to generate a digital signal D IN [1], D IN [2], D OUT [1] and D OUT [2] are the voltage V IN [1], VIN [2], V OUT [1], V OUT The AD conversion circuit 31a has a digital value proportional to the analog voltage value of the voltage V IN [1], V IN [2], V OUT [1] and V OUT [2] may have a total of four AD converters that individually convert the voltage V into a digital signal. However, the total number of AD converters provided in the AD conversion circuit 31a may be three or less. For example, the AD conversion circuit 31a may be provided with a single AD converter, and the single AD converter may be used in a time-division manner to convert the voltage V IN [1], V IN [2], V OUT [1] and V OUT [2] may be converted into a digital signal.

[0108] The arithmetic circuit 31b receives the digital signal D IN [1], D IN [2], D OUT [1] and D OUT The calculation of the calculation circuit 31b in the examples EX1_A and EX1_B is performed based on the duty ratios H_DUTY[1] and H_DUTY[2] and the time t HON [1] and t HON The calculation of the calculation circuit 31b in the examples EX2_A and EX2_B is a calculation to derive the duty ratios L_DUTY[1] and L_DUTY[2] and the time t LON [1] and t LON The calculation of the calculation circuit 31b in the examples EX3_A and EX3_B is a calculation to derive the duty ratios H_DUTY[1] and L_DUTY[2] and the time t HON [1] and t LON The calculation circuit 31b may include a divider for implementing the calculation of each equation.

[0109] The delay determination circuit 31c determines the delay time t based on the duty ratio and time derived by the calculation circuit 31b. DLY [1] and tDLY [2] is determined. The delay time t DLY [1] and t DLY [2] is the delay time t set by the calculation setting circuit 31 DLY [1] and t DLY [2]. However, as mentioned above, the delay time t DLY [1] and t DLY If both the DC / DC converters 4[1] and 4[2] are step-down switching regulators, the delay determination circuit 31c determines the delay time t based on the duty ratio and time derived by the calculation circuit 31b in the manner shown in the embodiment EX1_A or EX1_B. DLY [1] and t DLY If the DC / DC converters 4[1] and 4[2] are both step-up switching regulators, the delay determination circuit 31c determines the delay time t[2] by the method shown in the embodiment EX2_A or EX2_B based on the duty ratios and time derived by the calculation circuit 31b. DLY [1] and t DLY If the DC / DC converter 4[1] is a step-down switching regulator and the DC / DC converter 4[2] is a step-up switching regulator, the delay determination circuit 31c determines the delay time t based on the duty ratio and time calculated by the calculation circuit 31b using the method shown in the embodiment EX3_A or EX3_B. DLY [1] and t DLY [2] is determined.

[0110] <<Example EX5>> Example EX5 will be described. While the method for shifting the switching timing has been described focusing on two switching regulators, the same can be applied to three or more switching regulators. Consider a case where DC / DC converters 4[1] to 4[m] are switching regulators (m is an integer satisfying "3≦m≦n"). Each of DC / DC converters 4[3] to 4[m] has the same configuration as DC / DC converter 4[1] in Example EX1_A or Example EX2_A. Therefore, DC / DC converter 4[i], which is one of DC / DC converters 4[1] to 4[m], includes output stage 12[i] consisting of transistors 13[i] and 14[i], control drive circuit 11[i], coil L[i], and capacitor C[i]. When the DC / DC converter 4[i] is a step-down switching regulator, the transistor 13[i] functions as a switching transistor (output transistor), and when the DC / DC converter 4[i] is a step-up switching regulator, the transistor 14[i] functions as a switching transistor (output transistor).

[0111] The phase adjustment circuit 30 adjusts the input voltage V IN [1]~V IN [m] and output voltage V OUT [1]~V OUT Based on [m], for each integer i that satisfies "1≦i≦m", the phases of the switching operations of output stages 12[1] to 12[m] can be adjusted so that the turn-on timing of the switching transistor in DC / DC converter 4[i] differs from the turn-on timing and turn-off timing of the switching transistor in DC / DC converter 4[j], and so that the turn-off timing of the switching transistor in DC / DC converter 4[i] differs from the turn-on timing and turn-off timing of the switching transistor in DC / DC converter 4[j]. Here, j represents an integer equal to or less than m and different from i.

[0112] <<Example EX6>> Example EX6 will be described.

[0113] In the power supply control device 2 according to this embodiment, the input voltage V IN Therefore, even if the output voltage V OUT [1] is the input voltage V IN [2] The mode or output voltage V OUT [2] is the input voltage V IN The aspect used as [1] can also be adopted.

[0114] When the DC / DC converter 4[i] is a step-down switching regulator, the transistor 14[i] functions as a rectifier element (synchronous rectifier element). The rectifier element may be a diode. That is, when the DC / DC converter 4[i] is a step-down switching regulator, the transistor 14[i] may be replaced with a rectifier diode having an anode connected to ground and a cathode connected to the terminal Tb[i]. When the DC / DC converter 4[i] is a step-up switching regulator, the transistor 13[i] functions as a rectifier element (synchronous rectifier element). The rectifier element may be a diode. That is, when the DC / DC converter 4[i] is a step-up switching regulator, the transistor 13[i] may be replaced with a rectifier diode having an anode connected to the terminal Tb[i] and a cathode connected to the terminal Ta[i].

[0115] The phase adjustment circuit 30 has a function of determining the timing at which the level of the clock signal CLK switches from the first level to the second level as a reference timing, and setting the turn-on timing of the switching transistor of each channel based on the reference timing. DLY When [i]>0”, the delay time t DLY [i] represents the delay amount of the turn-on timing of the switching transistor of the i-th channel as viewed from the reference timing. In the above embodiment, it is assumed that the first level is a low level and the second level is a high level, but it may be modified so that the first level is a high level and the second level is a low level.

[0116] Furthermore, with regard to any signal or voltage, the relationship between the high level and the low level thereof may be reversed from that described above without departing from the spirit of the above.

[0117] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0118] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0119] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0120] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0121] A power supply control device according to one aspect of the present disclosure is a power supply control device (2) configured to control the operation of a power supply device (1) having a plurality of DC / DC converters (4), wherein the plurality of DC / DC converters are configured to convert a first input voltage (V IN [1]) to the first output voltage (V OUT a first DC / DC converter (4[1]) configured to generate a second input voltage (V [1]) and a second switching output stage (12[2]) configured to generate a second input voltage (V IN [2]) to the second output voltage (V OUT and a second DC / DC converter (4[2]) configured to generate a first output voltage corresponding to the first switching output stage, and the power supply control device has a configuration (first configuration) comprising: a first control drive circuit (11[1]) configured to control the switching operation of the first switching output stage in accordance with the first output voltage; a second control drive circuit (11[2]) configured to control the switching operation of the second switching output stage in accordance with the second output voltage; and a phase adjustment circuit (30) configured to adjust the phase of the switching operation of each switching output stage based on the ratio between the first input voltage and the first output voltage and the ratio between the second input voltage and the second output voltage.

[0122] This allows the switching timing between the first and second DC / DC converters to be appropriately shifted even if the first and second input voltages are different, thereby suppressing jitter and ripple in each output voltage due to jitter, thereby suppressing radiation noise.

[0123] In the power supply control device according to the first configuration, in the switching operation of the first switching output stage, the state of the first switching output stage is alternately switched between a first state and a second state, and in the switching operation of the second switching output stage, the state of the second switching output stage is alternately switched between a third state and a fourth state, and the phase adjustment circuit may be configured (second configuration) to adjust the phase based on the ratio between the first input voltage and the first output voltage and the ratio between the second input voltage and the second output voltage so that the switching timing of the state of the first switching output stage and the switching timing of the state of the second switching output stage differ from each other.

[0124] In the power supply control device according to the first configuration, the first DC / DC converter and the second DC / DC converter are step-down switching regulators (see FIG. 13), the first switching output stage has a first switching transistor (13[1]) provided between a first input terminal (Ta[1]) configured to receive the first input voltage and a first coil connection terminal (Tb[1]), and a first rectifier element (14[1]) provided between the first coil connection terminal and ground, and the first DC / DC converter is an output stage, the first control drive circuit, a first coil (L[1]) provided between the first coil connection terminal and a first output node (OUT[1]) to which the first output voltage is applied, and a first capacitor (C[1]) provided between the first output node and ground, wherein the first drive control circuit switches the first switching transistor between on and off in a switching operation of the first switching output stage according to the first output voltage, and the second switching output stage has a second input terminal (Ta[2]) configured to receive the second input voltage; and a second coil connection terminal (Tb[2]), and a second rectifier element (14[2]) provided between the second coil connection terminal and ground, the second DC / DC converter having the second switching output stage, the second control drive circuit, a second coil (L[2]) provided between the second coil connection terminal and a second output node (OUT[2]) to which the second output voltage is applied, and a second capacitor (C[2]) provided between the second output node and ground, the second drive control circuit switches the second switching transistor between on and off in a switching operation of the second switching output stage according to the second output voltage, and the phase adjustment circuit adjusts the phase based on the ratio between the first input voltage and the first output voltage and the ratio between the second input voltage and the second output voltage so that the switching timing between on and off of the first switching transistor and the switching timing between on and off of the second switching transistor are different from each other (third configuration).

[0125] In the power supply control device according to the first configuration, the first DC / DC converter and the second DC / DC converter are step-up switching regulators (see FIG. 18), and the first switching output stage has a first switching transistor (14[1]) provided between a first coil connection terminal (Tb[1]) and ground, and a first rectifier element (13[1]) provided between the first coil connection terminal and a first output terminal (Ta[1]) to which the first output voltage is applied, and the first DC / DC converter is and the first control drive circuit, a first coil (L[1]) provided between a first input node (IN[1]) to which the first input voltage is applied and the first coil connection terminal, and a first capacitor (C[1]) provided between the first output terminal and ground, wherein the first drive control circuit switches the first switching transistor between on and off in a switching operation of the first switching output stage according to the first output voltage, and the second switching output stage is a second switching transistor provided between a second coil connection terminal (Tb[2]) and ground. a second switching transistor (14[2]) and a second rectifier element (13[2]) provided between the second coil connection terminal and a second output terminal (Ta[2]) to which the second output voltage is applied, the second DC / DC converter having the second switching output stage, the second control drive circuit, a second coil (L[2]) provided between a second input node (IN[2]) to which the second input voltage is applied and the second coil connection terminal, and a second capacitor (C[2]) provided between the second output terminal and ground, the second drive control circuit switches the second switching transistor between on and off in a switching operation of the second switching output stage according to the second output voltage, and the phase adjustment circuit adjusts the phase based on the ratio between the first input voltage and the first output voltage and the ratio between the second input voltage and the second output voltage so that the switching timing between on and off of the first switching transistor and the switching timing between on and off of the second switching transistor are different from each other (fourth configuration).

[0126] In the power supply control device according to the first configuration, the first DC / DC converter is a step-down switching regulator, and the second DC / DC converter is a step-up switching regulator (see FIG. 23), and the first switching output stage has a first switching transistor (13[1]) provided between a first input terminal (Ta[1]) configured to receive the first input voltage and a first coil connection terminal (Tb[1]), and a first rectifier element (14[1]) provided between the first coil connection terminal and ground, and the first DC / DC converter The inverter has the first switching output stage, the first control drive circuit, a first coil (L[1]) provided between the first coil connection terminal and a first output node (OUT[1]) to which the first output voltage is applied, and a first capacitor (C[1]) provided between the first output node and ground, and the first drive control circuit switches the first switching transistor between on and off in a switching operation of the first switching output stage according to the first output voltage, and the second switching output stage has a second coil connection terminal (Tb[2]) and and a second rectifier element (13[2]) provided between the second coil connection terminal and a second output terminal (Ta[2]) to which the second output voltage is applied, and the second DC / DC converter has the second switching output stage, the second control drive circuit, a second coil (L[2]) provided between a second input node (IN[2]) to which the second input voltage is applied and the second coil connection terminal, and a second capacitor (C[2]) provided between the second output terminal and ground, and The second drive control circuit may be configured to switch the second switching transistor between on and off in a switching operation of the second switching output stage according to the second output voltage, and the phase adjustment circuit may be configured to adjust the phase based on the ratio between the first input voltage and the first output voltage and the ratio between the second input voltage and the second output voltage so that the switching timing between on and off of the first switching transistor and the switching timing between on and off of the second switching transistor differ from each other (fifth configuration).

[0127] The power supply control device according to any one of the third to fifth configurations includes an oscillator (20) configured to generate a clock signal (CLK) having a first level and a second level alternately, and the phase adjustment circuit sets the turn-on timing of each switching transistor based on a reference timing at which the level of the clock signal switches from the first level to the second level, and in adjusting the phase, adjusts a first delay time (t DLY [1]) and a second delay time (t DLY [1]) may be adjusted (sixth configuration).

[0128] In the power supply control device according to the sixth configuration, the phase adjustment circuit adjusts the ratio of the first output voltage to the first input voltage (V OUT [1] / V IN [1]) than the ratio of the second output voltage to the second input voltage (V OUT [2] / V IN [2]) is larger, the first delay time is set to be equal to or larger than zero and the second delay time is set to be larger than the first delay time, and when the ratio of the first output voltage to the first input voltage is larger than the ratio of the second output voltage to the second input voltage, the second delay time is set to be equal to or larger than zero and the first delay time is set to be larger than the second delay time (seventh configuration).

[0129] In the power supply control device according to any one of the first to seventh configurations, the first input voltage and the second input voltage may be different from each other (eighth configuration).

[0130] A power supply device according to one aspect of the present disclosure has a configuration (ninth configuration) that includes a plurality of DC / DC converters formed using the power supply control device according to any one of the first to eighth configurations. [Explanation of symbols]

[0131] 1 Power supply 2 Power supply control device 3 Discrete components 4, 4[i] DC / DC converter CS chassis V IN , V IN [i] Input voltage V OUT , V OUT [i] Output voltage PIN power terminal GND Ground terminal Ta[i]~Td[i] terminals 10[i] Switching circuit 11[i] Control drive circuit 12[i] Output stage 13[i], 14[i] Transistors 20 oscillators 30 Phase adjustment circuit 31 Delay setting circuit 32 Delay Insertion Circuit 40 Reference voltage generation circuit 50 Internal power circuit V PW Power supply voltage V REF [i] Reference voltage SET[i] signal t DLY [i] Delay time 111[i], 112[i] Resistor 113[i] Control circuit 114[i] driver L[i] coil C[i] capacitor OUT[i] output node IN[i] Input node 31a AD conversion circuit 31b Arithmetic circuit 31c Delay decision circuit

Claims

1. 1. A power supply control device configured to control operation of a power supply having a plurality of DC / DC converters, comprising: the plurality of DC / DC converters include a first DC / DC converter configured to generate a first output voltage from a first input voltage by a switching operation of a first switching output stage, and a second DC / DC converter configured to generate a second output voltage from a second input voltage by a switching operation of a second switching output stage; The power supply control device includes: a first control and drive circuit configured to control a switching operation of the first switching output stage in response to the first output voltage; a second control drive circuit configured to control a switching operation of the second switching output stage in response to the second output voltage; a phase adjustment circuit configured to adjust the phase of the switching operation of each switching output stage based on a ratio between the first input voltage and the first output voltage and a ratio between the second input voltage and the second output voltage. , power control device.

2. In a switching operation of the first switching output stage, a state of the first switching output stage is alternately switched between a first state and a second state, and in a switching operation of the second switching output stage, a state of the second switching output stage is alternately switched between a third state and a fourth state, The phase adjustment circuit adjusts the phase based on the ratio between the first input voltage and the first output voltage and the ratio between the second input voltage and the second output voltage so that the timing of switching the state of the first switching output stage and the timing of switching the state of the second switching output stage differ from each other. The power supply control device according to claim 1 .

3. the first DC / DC converter and the second DC / DC converter are step-down switching regulators, the first switching output stage includes a first switching transistor provided between a first input terminal configured to receive the first input voltage and a first coil connection terminal, and a first rectifier element provided between the first coil connection terminal and ground; the first DC / DC converter includes the first switching output stage, the first control drive circuit, a first coil provided between the first coil connection terminal and a first output node to which the first output voltage is applied, and a first capacitor provided between the first output node and ground; the first drive control circuit switches the first switching transistor between on and off in a switching operation of the first switching output stage according to the first output voltage; the second switching output stage includes a second switching transistor provided between a second input terminal configured to receive the second input voltage and a second coil connecting terminal, and a second rectifying element provided between the second coil connecting terminal and ground; the second DC / DC converter includes the second switching output stage, the second control drive circuit, a second coil provided between the second coil connecting terminal and a second output node to which the second output voltage is applied, and a second capacitor provided between the second output node and ground; the second drive control circuit switches the second switching transistor between on and off in a switching operation of the second switching output stage according to the second output voltage; The phase adjustment circuit adjusts the phase based on a ratio between the first input voltage and the first output voltage and a ratio between the second input voltage and the second output voltage so that a switching timing between on and off of the first switching transistor and a switching timing between on and off of the second switching transistor differ from each other. The power supply control device according to claim 1 .

4. the first DC / DC converter and the second DC / DC converter are step-up switching regulators, the first switching output stage includes a first switching transistor provided between a first coil connection terminal and ground, and a first rectifier element provided between the first coil connection terminal and a first output terminal to which the first output voltage is applied; the first DC / DC converter includes the first switching output stage, the first control drive circuit, a first coil provided between a first input node to which the first input voltage is applied and the first coil connection terminal, and a first capacitor provided between the first output terminal and ground; the first drive control circuit switches the first switching transistor between on and off in a switching operation of the first switching output stage according to the first output voltage; the second switching output stage includes a second switching transistor provided between a second coil connection terminal and ground, and a second rectifier element provided between the second coil connection terminal and a second output terminal to which the second output voltage is applied; the second DC / DC converter includes the second switching output stage, the second control drive circuit, a second coil provided between a second input node to which the second input voltage is applied and the second coil connection terminal, and a second capacitor provided between the second output terminal and ground; the second drive control circuit switches the second switching transistor between on and off in a switching operation of the second switching output stage according to the second output voltage; The phase adjustment circuit adjusts the phase based on a ratio between the first input voltage and the first output voltage and a ratio between the second input voltage and the second output voltage so that a switching timing between on and off of the first switching transistor and a switching timing between on and off of the second switching transistor differ from each other. The power supply control device according to claim 1 .

5. the first DC / DC converter is a step-down switching regulator, and the second DC / DC converter is a step-up switching regulator; the first switching output stage includes a first switching transistor provided between a first input terminal configured to receive the first input voltage and a first coil connection terminal, and a first rectifier element provided between the first coil connection terminal and ground; the first DC / DC converter includes the first switching output stage, the first control drive circuit, a first coil provided between the first coil connection terminal and a first output node to which the first output voltage is applied, and a first capacitor provided between the first output node and ground; the first drive control circuit switches the first switching transistor between on and off in a switching operation of the first switching output stage according to the first output voltage; the second switching output stage includes a second switching transistor provided between a second coil connection terminal and ground, and a second rectifier element provided between the second coil connection terminal and a second output terminal to which the second output voltage is applied; the second DC / DC converter includes the second switching output stage, the second control drive circuit, a second coil provided between a second input node to which the second input voltage is applied and the second coil connection terminal, and a second capacitor provided between the second output terminal and ground; the second drive control circuit switches the second switching transistor between on and off in a switching operation of the second switching output stage according to the second output voltage; The phase adjustment circuit adjusts the phase based on a ratio between the first input voltage and the first output voltage and a ratio between the second input voltage and the second output voltage so that a switching timing between on and off of the first switching transistor and a switching timing between on and off of the second switching transistor differ from each other. The power supply control device according to claim 1 .

6. an oscillator configured to generate a clock signal having alternating first and second levels; The phase adjustment circuit sets the turn-on timing of each switching transistor based on a reference timing at which the level of the clock signal switches from the first level to the second level, and in adjusting the phase, adjusts at least one of a first delay time of the turn-on timing of the first switching transistor from the reference timing and a second delay time of the turn-on timing of the second switching transistor from the reference timing.

6. The power supply control device according to claim 3.

7. The phase adjustment circuit sets the first delay time to zero or more and sets the second delay time to a value greater than the first delay time when a ratio of the second output voltage to the second input voltage is greater than a ratio of the first output voltage to the first input voltage, and sets the second delay time to zero or more and sets the first delay time to a value greater than the second delay time when a ratio of the first output voltage to the first input voltage is greater than a ratio of the second output voltage to the second input voltage. The power supply control device according to claim 6 .

8. The first input voltage and the second input voltage are different from each other.

6. The power supply control device according to claim 1.

9. A power supply control device according to any one of claims 1 to 5, comprising a plurality of DC / DC converters formed using the power supply control device. , power supply.

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