Semiconductor device

Abstract

To provide a semiconductor device capable of increasing a mutual inductance while suppressing an increase in a mounting area of a positive electrode terminal and a negative electrode terminal.SOLUTION: A semiconductor device (1) includes: a semiconductor element (10); a substrate (20) where the semiconductor element (10) is mounted; and a positive electrode terminal (30) and a negative electrode terminal (40) disposed on a first side (20a) side extending in a first direction (D1) of the substrate (20). Each of the positive electrode terminal (30) and the negative electrode terminal (40) has rising portions (31, 32, 41, 42) which each extend in a direction intersecting a mounting surface of the semiconductor element (10) on the substrate (20). Three or more of the rising portions (31, 32) of the positive electrode terminal (30) in total and three or more of the rising portions (41, 42) of the negative electrode terminal (40) in total are arranged side by side alternately to face each other.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a positive terminal and a negative terminal. [Background technology]

[0002] Conventionally, semiconductor devices have a circuit board on which semiconductor elements are mounted, and are used in inverter devices, etc. In such semiconductor devices, main terminals connected to external conductors, such as a positive terminal and a negative terminal, are arranged on one side of the board (see, for example, Patent Documents 1 to 4 and Non-Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-098425 [Patent Document 2] Patent Publication No. 2021-120975 [Patent Document 3] International Publication No. 2020 / 170553 [Patent Document 4] International Publication No. 2019 / 142863 [Non-patent literature]

[0004] [Non-Patent Document 1] Bodo's Power Systems, March 2024, p.26-30 Summary of the Invention [Problem to be solved by the invention]

[0005] In semiconductor devices, in order to suppress surge voltages, it is conceivable to increase the mutual inductance during switching by stacking the positive and negative terminals vertically to increase the opposing area. However, increasing the opposing area of ​​the positive and negative terminals increases the mounting area. Furthermore, since it is not possible to provide wiring directly below the positive and negative terminals, this imposes restrictions on the pattern layout on the board.

[0006] An object of the present invention is to provide a semiconductor device that can increase mutual inductance while suppressing an increase in the mounting area of ​​the positive and negative terminals. [Means for solving the problem]

[0007] In one aspect, the semiconductor device comprises a semiconductor element, a substrate on which the semiconductor element is mounted, and a positive terminal and a negative terminal arranged on a first edge of the substrate extending in a first direction, each of the positive terminal and the negative terminal having a raised portion extending in a direction intersecting the mounting surface of the semiconductor element on the substrate, and the raised portion of the positive terminal and the raised portion of the negative terminal are positioned alternately opposite each other, totaling three or more. [Effects of the Invention]

[0008] According to the above aspect, it is possible to increase the mutual inductance while suppressing an increase in the mounting area of ​​the positive terminal and the negative terminal. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view showing a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a plan view showing a positive electrode terminal and a negative electrode terminal in the embodiment. [Figure 3] FIG. 2 is a perspective view showing a positive electrode terminal and a negative electrode terminal in the embodiment. [Figure 4] FIG. 2 is a left side view showing a positive electrode terminal and a negative electrode terminal in the embodiment. [Figure 5]FIG. 10 is a top perspective view showing a positive electrode terminal and a negative electrode terminal according to a modified example of the embodiment. [Figure 6] FIG. 10 is a left side perspective view showing a positive electrode terminal and a negative electrode terminal according to a modified example of the embodiment. [Figure 7] FIG. 10 is a perspective view showing a positive electrode terminal and a negative electrode terminal in a comparative example. [Figure 8] 10A and 10B are explanatory diagrams for explaining a mounting space and an opposing area in an embodiment and a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiment described below, and can be appropriately modified and implemented within the scope of the present invention.

[0011] FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment.

[0012] 2 to 4 are a plan view, a perspective view, and a left side view showing the positive electrode terminal 30 and the negative electrode terminal 40 in one embodiment.

[0013] 1 to 4 and FIGS. 5 to 7 (described later), the thickness direction of the semiconductor element 10 is defined as the Z direction, and of the X and Y directions that are perpendicular to the Z direction and perpendicular to each other, the first direction D1 in which the first side 20a of the laminated substrate 20 on which the positive electrode terminal 30 and the negative electrode terminal 40 are arranged extends is defined as the X direction. In some cases, the positive side of the X direction may be referred to as the front, the negative side of the X direction as the rear, the positive side of the Y direction as the left, the negative side of the Y direction as the right, the positive side of the Z direction as the up, and the negative side of the Z direction as the down. These directions are used for convenience of explanation, and the corresponding relationship between the X, Y, and Z directions may change depending on the attitude of the semiconductor device 1, etc.

[0014] 1 includes a plurality of semiconductor elements 10, a laminated substrate 20, a positive terminal 30, a negative terminal 40, an output terminal 50, control terminals 61-63, 65, a sense terminal 64, temperature sense terminals 66, 67, a temperature sense unit 68, a case 70 (shown by a two-dot chain line), wiring W (including first to third control wiring W1-W3), and first to third relay units R1-R3. Note that only some of the wiring W is labeled with a reference symbol in FIG. 1.

[0015] As an example, the semiconductor device 1 is applied to a power conversion device such as an inverter device for an industrial or automotive motor, together with a cooler (not shown) disposed below the laminated substrate 20. In the following description, detailed descriptions of known configurations, functions, operations, assembly methods, etc. that are the same as or similar to those of the semiconductor device 1 will be omitted.

[0016] A plurality of semiconductor elements 10 are mounted on each of the first circuit pattern 22a, the fifth circuit pattern 22e, and the sixth circuit pattern 22f of the laminated substrate 20 by, for example, a conductive bonding material (not shown) such as solder.

[0017] The switching element of the semiconductor element 10 may be, for example, a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), or the like. The diode element of the semiconductor element 10 may be, for example, a SiC-SBD (Schottky Barrier Diode), a JBS (Junction Barrier Schottky) diode, an MPS (Merged PN Schottky) diode, a PN diode, or the like. The semiconductor element 10 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or other switching element, or an RC (Reverse Conducting) IGBT element that integrates the IGBT element with a diode element such as an FWD (Free Wheeling Diode) connected in anti-parallel to the switching element. This type of semiconductor element 10 has electrodes (not shown) on its lower and upper surfaces, and the electrodes on its upper surface are connected to wiring W via bonding to the circuit layer of the laminated substrate 20. The wiring W is a metallic bonding wire, but may be replaced with a lead formed by processing a metal plate such as a copper plate. In this specification, "connection" includes electrical connection.

[0018] The laminated substrate 20 is an example of a substrate on which the semiconductor element 10 is mounted. The laminated substrate 20 has an insulating substrate 21, circuit layers (first to fourteenth circuit patterns 22a to 22n), and a heat dissipation layer 23 (not shown). The laminated substrate 20 is, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate, and has a rectangular shape in a plan view.

[0019] The insulating substrate 21 may be a ceramic substrate formed of a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or a composite material of aluminum oxide (Al2O3) and zirconium oxide (ZrO2). The insulating substrate 21 may be, for example, a substrate formed of an insulating resin such as epoxy resin, a substrate formed by impregnating a base material such as glass fiber with an insulating resin, or a substrate formed by coating the surface of a flat metal core with an insulating resin. In the example shown in FIG. 1, the insulating substrate 21 is provided separately on the positive side in the Y direction and the negative side in the Y direction, but these insulating substrates 21 may also be provided integrally. Furthermore, while FIG. 1 shows one semiconductor unit including the semiconductor element 10, the laminated substrate 20, the positive terminal 30, the negative terminal 40, the output terminal 50, etc., the semiconductor device 1 may be provided with, for example, three semiconductor units constituting a three-phase inverter circuit. As such, the number of semiconductor elements 10 and the laminated substrates 20 is not particularly limited.

[0020] The heat dissipation layer 23 provided on the lower surface of the insulating substrate 21 functions as a heat-conducting member that conducts heat generated in the inverter circuit to a cooler made of copper or the like, and may also be called a heat sink, conductor pattern, or heat dissipation pattern. The heat dissipation layer 23 is formed, for example, from a metal plate or metal foil made of copper, aluminum, or the like. In FIG. 1, the heat dissipation layer 23 is represented by a dashed line because it is hidden by the insulating substrate 21. The cooler has a metal plate (heat sink) made of, for example, copper, and is attached to the water jacket. The cooler has fins that dissipate heat to the refrigerant flowing through the water jacket. The heat dissipation layer 23 of the laminated substrate 20 is connected to the upper surface of the metal plate of the cooler by a bonding material such as solder.

[0021] A circuit layer including first to fourteenth circuit patterns 22a to 22n is provided on the upper surface of insulating substrate 21. Each of circuit patterns 22a to 22n will be described later; the circuit layer is a member that functions as a wiring member in an inverter circuit, and is formed of, for example, a metal plate or metal foil such as copper or aluminum. The circuit layer (first to fourteenth circuit patterns 22a to 22n) may also be called a conductor layer, conductive layer, conductor pattern, wiring pattern, etc.

[0022] The positive electrode terminal 30 and the negative electrode terminal 40 are arranged on a first side 20a of the laminated substrate 20 extending in a first direction D1 (X direction). The output terminal 50 is arranged on a second side 20b of the laminated substrate 20 facing the first side 20a in a second direction D2 (Y direction). The positive electrode terminal 30, the negative electrode terminal 40, and the output terminal 50 may each be integrally formed from a metal plate such as copper or a copper alloy.

[0023] The positive terminal 30 may be called a P terminal or an input terminal, the negative terminal 40 may be called an N terminal or an output terminal, and the output terminal 50 may be called an M terminal or an intermediate terminal.

[0024] 2 to 4, the positive electrode terminal 30 and the negative electrode terminal 40 have first rising portions 31, 41, second rising portions 32, 42, connecting portions 33, 43, and external connection portions 34, 44. In FIG. 4, to easily distinguish between the positive electrode terminal 30 and the negative electrode terminal 40, only the negative electrode terminal 40 is shown with a dotted pattern.

[0025] The first rising portions 31, 41 and the second rising portions 32, 42 extend in a direction (Z direction) intersecting the mounting surface (top surface) of the laminated substrate 20 on which the semiconductor element 10 is mounted. Furthermore, the first rising portions 31, 41 and the second rising portions 32, 42 are supported, for example, at their ends on the negative side of the Y direction (i.e., the ends on the side of the first side 20a of the laminated substrate 20) by connecting portions 33, 43 described below, and extend in the second direction D2 (positive side of the Y direction) toward the second side 20b of the laminated substrate 20. In this way, the first rising portions 31, 41 and the second rising portions 32, 42 extend in the Y direction and the Z direction. Note that the first rising portions 31, 41 and the second rising portions 32, 42 can be called vertical portions because they extend in the Z direction. However, the first rising portions 31, 41 and the second rising portions 32, 42 may extend in the Y direction and in a direction different from the Z direction (a direction intersecting the XY plane).

[0026] The first rising portion 31 of the positive electrode terminal 30, the first rising portion 41 of the negative electrode terminal 40, the second rising portion 32 of the positive electrode terminal 30, and the second rising portion 42 of the negative electrode terminal 40 are aligned in this order facing each other on the positive side of the X direction (first direction D1). These rising portions 31, 32, 41, and 42 may be aligned closely, separated by a gap G (see FIGS. 2 and 4) of less than 10 mm, such as around 1 mm. These three gaps G may be the same or nearly the same.

[0027] The number of the rising portions (first rising portion 31 and second rising portion 32) of the positive electrode terminal 30 and the rising portions (first rising portion 41 and second rising portion 42) of the negative electrode terminal 40 that are alternately arranged opposite each other may be three or more in total. Preferably, the number of the rising portions alternately arranged on the positive electrode terminal 30 and the negative electrode terminal 40 is the same. More preferably, the number of the first rising portions 31 and second rising portions 32 of the positive electrode terminal 30 and the first rising portions 41 and second rising portions 42 of the negative electrode terminal 40 is four in total. Furthermore, the direction in which the rising portions (first rising portion 31 and second rising portion 32) of the positive electrode terminal 30 and the rising portions (first rising portion 41 and second rising portion 42) of the negative electrode terminal 40 face each other is not limited to the first direction D1 (X direction), but may be the second direction D2 (Y direction), or may be any direction intersecting the Z direction.

[0028] The first rising portions 31, 41 and the second rising portions 32, 42 have joining portions 31a, 32a, 41a, 42a provided at the ends on the positive side in the Y direction. The joining portions 31a, 32a of the positive electrode terminal 30 are joined to the first circuit pattern 22a of the laminated substrate 20 shown in FIG. 1 by, for example, a conductive joining material (not shown) such as solder, ultrasonic bonding, or the like. The joining portions 41a, 42a of the negative electrode terminal 40 are joined to the second circuit pattern 22b of the laminated substrate 20 by, for example, a conductive joining material (not shown) such as solder, ultrasonic bonding, or the like. The second circuit pattern 22b is located on the first side 20a side (negative side in the Y direction) of the first circuit pattern 22a. The first circuit pattern 22a and the second circuit pattern 22b are located in a region including the center of the laminated substrate 20 in the X direction. In FIG. 4, the bonded portions 41a, 42a of the rising portions 41, 42 of the negative electrode terminal 40 are hidden by the bonded portions 31a, 32a of the rising portions 31, 32 of the positive electrode terminal 30 and do not appear. That is, the bonded portions 31a, 32a of the positive electrode terminal 30 and the bonded portions 41a, 42a of the negative electrode terminal 40 are located at the same position in the X direction. Note that the positive electrode terminal 30 may be bonded to the second circuit pattern 22b, and the negative electrode terminal 40 may be bonded to the first circuit pattern 22a. In this case, the current path described below will be reversed, and therefore the configuration and arrangement of the semiconductor element 10 may be appropriately changed accordingly.

[0029] The connecting portion 33 of the positive terminal 30 connects the first rising portion 31 and the second rising portion 32 at the upper ends of the negative Y-direction ends of the first rising portion 31 and the second rising portion 32 (i.e., the ends opposite the laminated substrate 20, which are on the positive Z-direction side).

[0030] The connecting portion 43 of the negative electrode terminal 40 connects the first rising portion 41 and the second rising portion 42 at the lower ends of the negative Y-direction ends of the first rising portion 41 and the second rising portion 42 (i.e., the ends on the laminated substrate 20 side, which are on the negative Z-direction side).

[0031] In this way, the first rising portion 31 and the second rising portion 32 of the positive electrode terminal 30 are supported at the upper end, and the first rising portion 41 and the second rising portion 42 of the negative electrode terminal 40 are supported at the lower end, but the positive electrode terminal 30 may be supported at the lower end, and the negative electrode terminal 40 may be supported at the upper end.

[0032] The external connection portions 34, 44 of the positive terminal 30 and the negative terminal 40 are fixed to the case 70 together with the external conductors by, for example, screws and nuts in the screw hole portions. In this way, the positive terminal 30 and the negative terminal 40 are each connected to the external conductors. The external connection portions 34, 44, for example, extend horizontally at the portion having the screw hole, bend downward from the end of this horizontal portion on the positive side in the Y direction, and then bend further toward the positive side in the Y direction. The external connection portions 34, 44 may be integrally connected to the coupling portions 33, 43 and the external connection portions 34, 44 at the positive side in the Y direction.

[0033] The case 70 has, for example, a rectangular cylindrical shape with the central axis in the Z direction, and houses the semiconductor element 10, the laminated substrate 20, etc. in a sealed state with a sealing material (e.g., epoxy resin, silicone gel, etc.) not shown. The case 70 is formed using an insulating resin material such as PPS (Poly Phenylene Sulfide) or PA (Poly Amide).

[0034] As shown in FIG. 1, the output terminal 50 has joined portions 51 and 52 and external connection portions 53 and .

[0035] The bonded portions 51 and 52 are provided at the end of the output terminal 50 on the negative side in the Y direction. The bonded portion 51 is bonded to the third circuit pattern 22c, and the bonded portion 52 is bonded to the fourth circuit pattern 22d, for example, by a conductive bonding material (not shown) such as solder, ultrasonic bonding, or the like. The third circuit pattern 22c is located on one side of the first circuit pattern 22a in the first direction D1 (the negative side in the X direction). The fourth circuit pattern 22d is located on the other side of the first circuit pattern 22a in the first direction D1 (the positive side in the X direction). Thus, the first circuit pattern 22a is located between the third circuit pattern 22c and the fourth circuit pattern 22d in the X direction. The third circuit pattern 22c and the fourth circuit pattern 22d may be symmetrical with respect to an axis of symmetry extending in the Y direction (for example, an axis passing through the center of the laminated substrate 20 in the X direction).

[0036] The external connection parts 53 and 54 are fixed to the case 70 together with the external conductor by, for example, screws and nets in the screw holes. In this manner, the output terminal 50 is connected to the external conductor. Note that the output terminal 50 has a current path branched into the external connection part 53 and the external connection part 54, but may have a single external connection part.

[0037] As an example, twelve semiconductor elements 10 are mounted on the first circuit pattern 22a to which the positive terminal 30 (joined portions 31a, 32a) is joined. Six of the semiconductor elements 10 are mounted on an end of the first circuit pattern 22a on the third circuit pattern 22c side (negative side in the X direction) in a substantially straight line in the Y direction and connected to the third circuit pattern 22c via wiring W. The remaining six semiconductor elements 10 are mounted on an end of the first circuit pattern 22a on the fourth circuit pattern 22d side (positive side in the X direction) in a substantially straight line in the Y direction and connected to the fourth circuit pattern 22d via wiring W. This allows current to flow in the following order: the positive terminal 30, the first circuit pattern 22a, the multiple semiconductor elements 10, the third circuit pattern 22c or the fourth circuit pattern 22d, and the output terminal 50. Although the number of semiconductor elements 10 mounted on the first circuit pattern 22a is not particularly limited, it is preferable that the number of semiconductor elements 10 connected to the third circuit pattern 22c is the same as the number of semiconductor elements 10 connected to the fourth circuit pattern 22d.

[0038] A fifth circuit pattern 22e is provided on the first side 20a side (i.e., the negative side in the Y direction) of the third circuit pattern 22c. The fifth circuit pattern 22e is connected to the third circuit pattern 22c by a plurality of wirings W. Six, for example, semiconductor elements 10 are mounted on the fifth circuit pattern 22e. The third circuit pattern 22c and the fifth circuit pattern 22e may be provided integrally.

[0039] A sixth circuit pattern 22f is provided on the first side 20a side (i.e., the negative side in the Y direction) of the fourth circuit pattern 22d. The sixth circuit pattern 22f is connected to the fourth circuit pattern 22d by a plurality of wirings W. Six, for example, semiconductor elements 10 are mounted on this sixth circuit pattern 22f. The fourth circuit pattern 22d and the sixth circuit pattern 22f may be provided integrally.

[0040] Here, the number of semiconductor elements 10 mounted on the fifth circuit pattern 22e and the number of semiconductor elements 10 mounted on the sixth circuit pattern 22f are not particularly limited, but it is preferable that the number of semiconductor elements 10 mounted on the fifth circuit pattern 22e and the number of semiconductor elements 10 mounted on the sixth circuit pattern 22f are the same.

[0041] The fifth circuit pattern 22e is located on one side in the first direction D1 (negative side in the X direction) of the second circuit pattern 22b to which the negative terminal 40 (joined portions 41a, 42a) is joined, and the sixth circuit pattern 22f is located on the other side in the first direction D1 (positive side in the X direction) of the second circuit pattern 22b.

[0042] The six semiconductor elements 10 mounted on the fifth circuit pattern 22e and the six semiconductor elements 10 mounted on the sixth circuit pattern 22f are each connected to the second circuit pattern 22b via wiring W. This allows a current to flow in the order of the output terminal 50, the third circuit pattern 22c or the fourth circuit pattern 22d, the fifth circuit pattern 22e or the sixth circuit pattern 22f, the semiconductor elements 10, the second circuit pattern 22b, and the negative terminal 40.

[0043] The control terminals 61 and 63 and the sense terminal 64 are disposed on the negative side of the laminate substrate 20 in the X direction. The control terminals 62 and 65 are disposed on the positive side of the laminate substrate 20 in the X direction. The control terminals 61 and 62 are, for example, gate terminals, and the control terminals 63 and 65 are, for example, auxiliary terminals (auxiliary emitter terminals or auxiliary source terminals). The sense terminal 64 is, for example, an auxiliary collector terminal or auxiliary drain terminal.

[0044] First to third relay portions R1 to R3 are provided between the six semiconductor elements 10 arranged at the end of the first circuit pattern 22a on the third circuit pattern 22c side (negative side in the X direction) and the six semiconductor elements 10 arranged at the end of the first circuit pattern 22a on the fourth circuit pattern 22d side (positive side in the X direction). These relay portions R1 to R3 may form part of a circuit layer, similar to the first circuit pattern 22a of the laminated substrate 20.

[0045] Of the twelve semiconductor elements 10 mounted on the first circuit pattern 22a, six semiconductor elements 10 on the negative side in the Y direction are connected to the first relay portion R1 by the first control wiring W1 (wiring W). Of the twelve semiconductor elements 10 mounted on the first circuit pattern 22a, six semiconductor elements 10 on the positive side in the Y direction are connected to the second relay portion R2 by the first control wiring W1. The second relay portion R2 is aligned with the first relay portion R1 in the second direction D2 (Y direction) with the third relay portion R3 in between, and is located on the positive side in the Y direction relative to the first relay portion R1. Therefore, the lengths of the first control wiring W1 between each semiconductor element 10 and the first relay portion R1 or the second relay portion R2 are substantially the same. Although all twelve semiconductor elements 10 may be connected to a single relay portion by the first control wiring W1, it is preferable that they are connected to one of multiple relay portions, such as the first relay portion R1 or the second relay portion R2 (the closer relay portion).

[0046] The seventh circuit pattern 22g extends linearly in the second direction D2 (Y direction) on the negative side of the third circuit pattern 22c in the X direction. Two second control wirings W2 (wirings W) extend in the X direction with the same length and connect the first relay portion R1 or the second relay portion R2 to the seventh circuit pattern 22g. The third control wiring W3 (wirings W) extends in the X direction and connects the seventh circuit pattern 22g to the control terminal 61.

[0047] The control terminal 62 is connected to a twelfth circuit pattern 22l provided so as to surround both sides in the X direction and the positive side in the Y direction of the second circuit pattern 22b by wiring W extending in the X direction. The twelfth circuit pattern 22l is also connected to the semiconductor elements 10 mounted on the fifth circuit pattern 22e and the sixth circuit pattern 22f by multiple wirings W of the same length.

[0048] The control terminal 63 is connected to an eighth circuit pattern 22h that extends linearly in the second direction D2 (Y direction) on the negative side of the seventh circuit pattern 22g in the X direction by a wire W. The eighth circuit pattern 22h is connected to the second relay portion R2 by a wire W. Furthermore, the second relay portion R2 is connected to the third circuit pattern 22c and the fourth circuit pattern 22d by two wires W that have the same length.

[0049] On the positive side in the X direction of the fourth circuit pattern 22d, a ninth circuit pattern 22i and a tenth circuit pattern 22j are provided, which extend linearly in the second direction D2 (Y direction).

[0050] An eleventh circuit pattern 22k extending linearly in the first direction D1 (X direction) is provided at the end on the positive side in the Y direction of the laminated substrate 20. The eleventh circuit pattern 22k is connected to the control sense terminal 64 and the first circuit pattern 22a by wiring W.

[0051] A thirteenth circuit pattern 22m extending linearly in the second direction D2 (Y direction) is provided on the positive side of the sixth circuit pattern 22f in the X direction. Furthermore, a fourteenth circuit pattern 22n extending linearly in the first direction D1 (X direction) is provided on the end of the laminated substrate 20 on the negative side in the Y direction. The thirteenth circuit pattern 22m and the fourteenth circuit pattern 22n are connected by wiring W. The fourteenth circuit pattern 22n is connected to the second circuit pattern 22b by wiring W.

[0052] The temperature sensing terminals 66, 67 are arranged on the negative side in the X direction at the end on the negative side in the Y direction of the laminated substrate 20, and are connected to a temperature sensing unit 68 by wiring W. This temperature sensing unit 68 can be configured, for example, by two circuit patterns that form part of the circuit layer of the laminated substrate 20 and a thermistor provided between them.

[0053] 5 and 6 are a top perspective view and a left perspective view showing a positive electrode terminal 130 and a negative electrode terminal 140 according to a modification of the embodiment.

[0054] The positive electrode terminal 130 of this modified example may be similar to the above-described positive electrode terminal 30, except that an upper end support portion 133 is provided instead of the connecting portion 33. Furthermore, the negative electrode terminal 140 of this modified example may be similar to the above-described negative electrode terminal 40, except that a lower end support portion 143 is provided instead of the connecting portion 43. That is, the first raised portions 131, 141, the second raised portions 132, 142, and the external connection portions 134, 144 of the positive electrode terminal 130 and the negative electrode terminal 140 may be similar to the first raised portions 31, 41, the second raised portions 32, 42, and the external connection portions 34, 44 of the positive electrode terminal 30 and the negative electrode terminal 40.

[0055] Therefore, the first rising portions 131, 141 and the second rising portions 132, 142 have joined portions 131a, 132a, 141a, 142a provided at the ends on the positive side in the Y direction. Furthermore, the first rising portion 131 of the positive electrode terminal 130, the first rising portion 141 of the negative electrode terminal 140, the second rising portion 132 of the positive electrode terminal 130, and the second rising portion 142 of the negative electrode terminal 140 are aligned in this order facing each other on the positive side in the X direction (first direction D1). That is, the rising portions of the positive electrode terminal 130 (the first rising portion 131 and the second rising portion 132) and the rising portions of the negative electrode terminal 140 (the first rising portion 141 and the second rising portion 142) are aligned alternately. These rising portions 131, 132, 141, 142 may be arranged closely spaced apart, for example, with a gap G (see FIG. 6) of less than 10 mm, such as around 1 mm. Note that in FIG. 6, the three gaps G appear to have different lengths, but this is because the end of the negative electrode terminal 140 on the positive side in the Y direction is located on the negative side in the Y direction relative to the end of the positive electrode terminal 130 on the positive side in the Y direction; in reality, the three gaps G are the same or nearly the same.

[0056] The upper end support portion 133 of the positive electrode terminal 130 extends the same length as the first rising portion 131 and the second rising portion 132 in the second direction D2 (negative side of the Y direction), and supports the upper ends of the first rising portion 131 and the second rising portion 132 (i.e., the ends on the positive side of the Z direction, opposite the laminated substrate 20). As a result, the upper end support portion 133 connects the first rising portion 131 and the second rising portion 132. The first rising portion 131 and the second rising portion 132, together with the upper end support portion 133, form a downward U-shaped plate shape.

[0057] The lower end support portion 143 of the negative electrode terminal 140 extends the same length as the first rising portion 141 and the second rising portion 142 in the second direction D2 (negative side in the Y direction) and supports the lower ends of the first rising portion 141 and the second rising portion 142 (i.e., the ends on the laminated substrate 20 side, which are on the negative side in the Z direction). As a result, the lower end support portion 143 connects the first rising portion 141 and the second rising portion 142. The first rising portion 141 and the second rising portion 142 form an upward U-shaped plate together with the lower end support portion 143. The lower end support portion 143 extends further in the negative side in the X direction than the first rising portion 141. The joining portion 141a of the first rising portion 141 of the negative electrode terminal 140 is located on the negative side in the X direction than the first rising portion 141. Therefore, the joined portion 141 a of the first rising portion 141 can also be considered to be provided on the lower end support portion 143 .

[0058] As described above, in this embodiment, the positive electrode terminal 30 and the negative electrode terminal 40 (or the positive electrode terminal 130 and the negative electrode terminal 140 in the modified example) have first rising portions 31, 41 and second rising portions 32, 42 (or the first rising portions 131, 141 and the second rising portions 132, 142 in the modified example) that are positioned alternately opposite each other in the X direction.

[0059] 7 has horizontal portions 231, 241 extending in the XY direction, and these horizontal portions 231, 241 are positioned opposite each other in the vertical direction (Z direction). Note that the horizontal portions 231, 241 are provided at their ends on the positive side in the Y direction with joined portions 231a, 231b, 241a, 241b to be joined to a substrate (not shown). The positive terminal 230 and the negative terminal 240 also have external connection portions 232, 242 to be connected to an external conductor.

[0060] 8 shows a schematic diagram of a structure in which four first rising portions 31, 41 and four second rising portions 32, 42 are arranged alternately facing each other in the X direction in one embodiment, and a structure in which two horizontal portions 231, 241 are arranged facing each other in the Z direction in a comparative example. In the one embodiment, four plates each having a width of 1 mm (X direction), a height of 3 mm (Z direction), and a depth of 10 mm (Y direction) are arranged with a gap of 1 mm between them. In the comparative example, two plates each having a width of 7 mm (X direction), a height of 1 mm (Z direction), and a depth of 10 mm (Y direction) are arranged with a gap of 1 mm between them.

[0061] In both the embodiment and the comparative example, the mounting area is the same (70 mm 2 ), same height (3mm), same mounting space (210mm 3 ) but the opposing area is a total of 90 mm 2 The total for the comparison example is 70 mm. 2 This is a value that is about 128% of the above. Therefore, it can be said that the mutual inductance can be increased more in the embodiment. In other words, when the opposing areas of the embodiment and the comparative example are the same, it can be said that the mounting area and height of the positive electrode terminal 30 and the negative electrode terminal 40 in the embodiment in a plan view can be made smaller than the mounting area of ​​the positive electrode terminal 230 and the negative electrode terminal 240 in the comparative example in a plan view.

[0062] In the present embodiment described above, the semiconductor device 1 includes a semiconductor element 10, a laminated substrate 20 (an example of a substrate) on which the semiconductor element 10 is mounted, and a positive terminal 30 and a negative terminal 40 arranged on a first side 20a of the laminated substrate 20 extending in a first direction D1 (X direction). The positive terminal 30 and the negative terminal 40 each have a first rising portion 31, 41 and a second rising portion 32, 42 (an example of a rising portion) extending in a direction (Z direction) intersecting the mounting surface of the laminated substrate 20 on which the semiconductor element 10 is mounted. The first rising portion 31 and the second rising portion 32 of the positive terminal 30 and the first rising portion 41 and the second rising portion 42 of the negative terminal 40 are positioned side by side, alternately facing each other, in a total of four (an example of three or more).

[0063] This increases the opposing area between the positive terminal 30 and the negative terminal 40, thereby increasing the mutual inductance during switching of the semiconductor element 10. Furthermore, since the first rising portion 31 and the second rising portion 32 of the positive terminal 30 and the first rising portion 41 and the second rising portion 42 of the negative terminal 40 extend in the Z direction and alternately face each other in the horizontal direction, the opposing area and therefore the mutual inductance can be increased in a small mounting area (mounting space) compared to the comparative example in which the horizontal portions 231, 241 of the positive terminal 230 and the negative terminal 240 face each other in the Z direction. Therefore, according to this embodiment, the mutual inductance can be increased while suppressing an increase in the mounting area of ​​the positive terminal 30 and the negative terminal 40. This makes it possible to suppress the generation of surge voltages (di / dt surge noise) during switching (for example, during high-speed switching when the semiconductor element 10 is a SiC module). Furthermore, by suppressing an increase in the mounting area of ​​the positive electrode terminal 30 and the negative electrode terminal 40, it is possible to increase the degree of freedom in the pattern layout of the circuit layer of the laminated substrate 20 and to mount a higher-rated semiconductor element 10. Furthermore, because the first rising portions 31 and second rising portions 32 of the positive electrode terminal 30 and the first rising portions 41 and second rising portions 42 of the negative electrode terminal 40 alternately face each other in the horizontal direction, it is possible to reduce the occurrence of bending of the positive electrode terminal 30 and the negative electrode terminal 40 compared to the comparative example in which the horizontal portions 231, 241 of the positive electrode terminal 230 and the negative electrode terminal 240 face each other in the Z direction. This makes it possible to ensure an insulation distance between the positive electrode terminal 30 and the negative electrode terminal 40 and to prevent loads from being applied to the joints of the positive electrode terminal 30 and the negative electrode terminal 40 with the laminated substrate 20. Furthermore, by suppressing the occurrence of surge voltage by increasing mutual inductance, it is possible to avoid increasing the cross-sectional area or lengthening the terminal wiring length, unlike the mode of suppressing the occurrence of surge voltage by reducing self-inductance, i.e., the mode of increasing the cross-sectional area (area perpendicular to the current path) of the positive terminal 30 and the negative terminal 40 or lengthening the terminal wiring length.

[0064] In addition, in this embodiment, the first rising portion 31 and the second rising portion 32 of the positive electrode terminal 30 and the first rising portion 41 and the second rising portion 42 of the negative electrode terminal 40 are positioned side by side in the first direction D1 (X direction).

[0065] This allows the width in the X direction of the mounting area of ​​the positive electrode terminal 30 and the negative electrode terminal 40 to be narrower than in an embodiment in which the first rising portion 31 and the second rising portion 32 of the positive electrode terminal 30 and the first rising portion 41 and the second rising portion 42 of the negative electrode terminal 40 are aligned in the second direction D2 (Y direction). This makes it easier to arrange the semiconductor element 10 and the circuit layer on both sides of the first rising portions 31, 41 and the second rising portions 32, 42 in the X direction.

[0066] In addition, in this embodiment, each of the multiple rising portions (first rising portion 31 and second rising portion 32) of the positive electrode terminal 30 and the multiple rising portions (first rising portion 41 and second rising portion 42) of the negative electrode terminal 40 is supported at the end portion on the first side 20a side of the laminated substrate 20, and extends in the second direction D2 (Y direction) toward the second side 20b of the laminated substrate 20 that faces the first side 20a in the second direction D2 (Y direction).

[0067] This allows the first rising portion 31 and the second rising portion 32 of the positive electrode terminal 30 and the first rising portion 41 and the second rising portion 42 of the negative electrode terminal 40 to face each other in the X direction with a simple configuration. Furthermore, since the width in the X direction of the mounting area of ​​the positive electrode terminal 30 and the negative electrode terminal 40 can be narrowed, it becomes easier to arrange the semiconductor element 10 and the circuit layer on both sides of the first rising portion 31, 41 and the second rising portion 32, 42 in the X direction. Furthermore, if members such as the lower end support portion 143 and the upper end support portion 133 of the modified example are omitted below the second rising portion 32 of the positive electrode terminal 30 or above the first rising portion 41 of the negative electrode terminal 40, the second rising portion 32 can be extended downward and the first rising portion 41 can be extended upward.

[0068] In addition, in this embodiment and its variant, the first rising portions 31, 131 and the second rising portions 32, 132, which are examples of one of the multiple rising portions (first rising portions 31, 131 and second rising portions 32, 132) of the positive terminal 30, 130 and the multiple rising portions (first rising portions 41, 141 and second rising portions 42, 142) of the negative terminal 40, 140, are supported at their upper ends (the ends opposite the laminated substrate 20 in a direction (Z direction) intersecting the mounting surface (top surface) of the laminated substrate 20) by, for example, a connecting portion 33 or an upper end support portion 133, and the first rising portions 41, 141 and the second rising portions 42, 142, which are examples of the other rising portions, are supported at their lower ends (the ends on the laminated substrate 20 side in the intersecting direction (Z direction)) by, for example, a connecting portion 43 or a lower end support portion 143.

[0069] This allows the positive terminals 30, 130 to be stably held in positions that do not interfere with the multiple raised portions (first raised portions 31, 131 and second raised portions 32, 132) of the positive terminals 30, 130 and the multiple raised portions (first raised portions 41, 141 and second raised portions 42, 142) of the negative terminals 40, 140, thereby reducing bending of the positive terminals 30, 130 and the negative terminals 40, 140.

[0070] In addition, in a modified example of this embodiment (Figures 5 and 6), the two above-mentioned one rising portions (first rising portion 131 and second rising portion 132) form a U-shaped plate shape together with the upper end support portion 133 located at the upper end, and the two above-mentioned other rising portions (first rising portion 141 and second rising portion 142) form a U-shaped plate shape together with the lower end support portion 143 located at the lower end.

[0071] This makes it possible to more stably hold the multiple rising portions (first rising portion 131 and second rising portion 132) of the positive terminal 130 and the multiple rising portions (first rising portion 141 and second rising portion 142) of the negative terminal 140, and further reduce bending of the positive terminal 130 and the negative terminal 140. It is also possible to increase the mutual inductance between the upper end support portion 133 and the rising portion of the negative terminal 140 (the upper end of the first rising portion 141), and between the lower end support portion 143 and the rising portion of the positive terminal 130 (the lower end of the second rising portion 132).

[0072] In addition, in this embodiment, the positive electrode terminal 30 (an example of one of the positive electrode terminal 30 and the negative electrode terminal 40) is joined to the first circuit pattern 22a of the laminated substrate 20, and the negative electrode terminal 40 (an example of the other terminal) is joined to the second circuit pattern 22b located on the first side 20a side of the first circuit pattern 22a.

[0073] This allows the positive electrode terminal 30 and the negative electrode terminal 40 to be arranged to extend in the Y direction, thereby narrowing the width in the X direction of the mounting area of ​​the positive electrode terminal 30 and the negative electrode terminal 40. This makes it easier to arrange the semiconductor element 10 and the circuit layer on both sides of the first rising portions 31, 41 and the second rising portions 32, 42 in the X direction.

[0074] Furthermore, in this embodiment, the semiconductor device 1 includes an output terminal 50 arranged on the side of the second side 20b of the laminated substrate 20 that faces the first side 20a of the laminated substrate 20 in the second direction D2 (Y direction). The output terminal 50 is joined to a third circuit pattern 22c located on one side in the first direction D1 (the negative side in the X direction) of the first circuit pattern 22a, and a fourth circuit pattern 22d located on the other side in the first direction D1 (the positive side in the X direction) of the first circuit pattern 22a.

[0075] This allows the current path to be parallel to the third circuit pattern 22c and the fourth circuit pattern 22d, thereby suppressing the occurrence of surge voltage. Also, the semiconductor element 10 and circuit layers can be arranged on both sides in the X direction of the first circuit pattern 22a to which the positive electrode terminal 30 is joined.

[0076] In addition, in this embodiment, the semiconductor device 1 has a plurality of semiconductor elements 10 mounted on the first circuit pattern 22a, and the number of semiconductor elements 10 connected to the third circuit pattern 22c is the same as the number of semiconductor elements 10 connected to the fourth circuit pattern 22d (for example, six each).

[0077] This allows current to flow evenly on both sides (third circuit pattern 22c and fourth circuit pattern 22d) in the X direction of the first circuit pattern 22a to which the positive electrode terminal 30 is joined.

[0078] In the present embodiment, the semiconductor device 1 includes a plurality of semiconductor elements 10 mounted on a fifth circuit pattern 22e located on the first side 20a of the third circuit pattern 22c, and a plurality of semiconductor elements 10 mounted on a sixth circuit pattern 22f located on the first side 20a of the fourth circuit pattern 22d. The number of semiconductor elements 10 mounted on the fifth circuit pattern 22e and the number of semiconductor elements 10 mounted on the sixth circuit pattern 22f are the same (for example, six each).

[0079] This makes it possible to suppress the occurrence of surge voltage by parallelizing the current path between the fifth circuit pattern 22e and the sixth circuit pattern 22f, and further parallelizing the current path between the semiconductor elements 10. Also, it is possible to make the current flow evenly between the fifth circuit pattern 22e and the sixth circuit pattern 22f.

[0080] In the present embodiment, the fifth circuit pattern 22e is located on one side in the first direction D1 (the negative side in the X direction) with respect to the second circuit pattern 22b, and the sixth circuit pattern 22f is located on the other side in the first direction D1 (the positive side in the X direction) with respect to the second circuit pattern 22b. The plurality of semiconductor elements 10 mounted on the fifth circuit pattern 22e and the plurality of semiconductor elements 10 mounted on the sixth circuit pattern 22f are each connected to the second circuit pattern 22b.

[0081] This allows current to flow uniformly through the second circuit pattern 22b on both sides in the X direction of the second circuit pattern 22b to which the negative electrode terminal 40 is joined (the fifth circuit pattern 22e and the sixth circuit pattern 22f).

[0082] In this embodiment, the semiconductor device 1 also includes a control terminal 61 and a plurality of control wirings (wirings W). The plurality of control wirings connect the plurality of semiconductor elements 10 mounted on the first circuit pattern 22a to the control terminal 61. The plurality of control wirings also includes a plurality of first control wirings W1 that connect the plurality of semiconductor elements 10 to one or more relay portions R1, R2 provided on the first circuit pattern 22a.

[0083] This allows the lengths of the multiple first control wirings W1 connecting the multiple semiconductor elements 10 and the relay portions R1 and R2 to be approximately the same, thereby allowing the gate delay times of the multiple semiconductor elements 10 to be controlled to be approximately constant.

[0084] In addition, in this embodiment, the multiple semiconductor elements 10 mounted on the first circuit pattern 22a (the number connected to the third circuit pattern 22c by wiring W is the same as the number connected to the fourth circuit pattern 22d by wiring W) are connected to any of the multiple relay parts R1, R2 positioned side by side in the second direction D2 (Y direction).

[0085] As a result, the semiconductor elements 10 can be connected by the first control wiring W1 to either the first relay portion R1 or the second relay portion R2 that is disposed between the semiconductor elements 10 lined up in the second direction D2 and connected to the third circuit pattern 22c by the wiring W and the semiconductor elements 10 lined up in the second direction D2 and connected to the fourth circuit pattern 22d by the wiring W, whichever is closer depending on the position of the semiconductor elements 10 in the Y direction. Therefore, the lengths of the multiple first control wirings W1 that connect the multiple semiconductor elements 10 and the relay portions R1, R2 can be made even closer to the same length.

[0086] In this embodiment, the plurality of control wires includes a plurality of second control wires W2 and a plurality of third control wires W3. The plurality of second control wires W2 connect a plurality of relay portions (first relay portion R1 and second relay portion R2) aligned in the second direction D2 (Y direction) to the seventh circuit pattern 22g extending in the second direction D2 (Y direction). The third control wire W3 connects the seventh circuit pattern 22g and the control terminal 61.

[0087] This allows not only the lengths of the multiple first control wirings W1 connecting the semiconductor element 10 and the multiple relay sections (first relay section R1 and second relay section R2) but also the lengths of the multiple second control wirings W2 connecting the multiple relay sections and the seventh circuit pattern 22g extending in the second direction D2 (Y direction) to be made closer to the same length.

[0088] The inventions described in the claims of the present application as originally filed are as follows:

[0089] <Appendix 1> A semiconductor element; a substrate on which the semiconductor element is mounted; a positive electrode terminal and a negative electrode terminal arranged on a first side of the substrate extending in a first direction, Each of the positive electrode terminal and the negative electrode terminal has a rising portion extending in a direction intersecting a mounting surface of the substrate on which the semiconductor element is mounted, The rising portions of the positive electrode terminal and the rising portions of the negative electrode terminal are alternately positioned opposite each other, and a total of three or more of them are arranged side by side. A semiconductor device characterized by:

[0090] <Appendix 2> The rising portion of the positive electrode terminal and the rising portion of the negative electrode terminal are positioned side by side in the first direction. 2. The semiconductor device according to claim 1,

[0091] <Appendix 3> The plurality of rising portions of the positive electrode terminal and the plurality of rising portions of the negative electrode terminal are supported at an end portion on the first side and extend in the second direction toward a second side of the substrate that faces the first side in the second direction. 3. The semiconductor device according to claim 2.

[0092] <Appendix 4> One of the plurality of rising portions of the positive electrode terminal and the plurality of rising portions of the negative electrode terminal is supported at an end portion on the opposite side to the substrate in the intersecting direction, and the other of the plurality of rising portions is supported at an end portion on the substrate side in the intersecting direction. 3. The semiconductor device according to claim 2.

[0093] <Appendix 5> The two one rising portions form a U-shaped plate shape together with a support portion located at an end of the one rising portion on the opposite side from the substrate in the intersecting direction, The two other rising portions form a U-shaped plate shape together with a support portion located at an end of the two other rising portions on the substrate side in the intersecting direction. 5. The semiconductor device according to claim 4,

[0094] <Appendix 6> one of the positive electrode terminal and the negative electrode terminal is bonded to a first circuit pattern of the substrate; The other of the positive electrode terminal and the negative electrode terminal is joined to a second circuit pattern of the substrate that is located on the first side of the first circuit pattern. 2. The semiconductor device according to claim 1,

[0095] <Appendix 7> an output terminal disposed on a second side of the substrate that faces the first side of the substrate in a second direction; The output terminal is joined to a third circuit pattern of the substrate located on one side of the first circuit pattern in the first direction, and to a fourth circuit pattern of the substrate located on the other side of the first circuit pattern in the first direction. 7. The semiconductor device according to claim 6,

[0096] <Appendix 8> a plurality of the semiconductor elements mounted on the first circuit pattern; The number of the semiconductor elements connected to the third circuit pattern is equal to the number of the semiconductor elements connected to the fourth circuit pattern. 8. The semiconductor device according to claim 7,

[0097] <Appendix 9> a plurality of the semiconductor elements mounted on a fifth circuit pattern of the substrate located on the first side of the third circuit pattern; a plurality of the semiconductor elements mounted on a sixth circuit pattern of the substrate located on the first side of the fourth circuit pattern, The number of the semiconductor elements mounted on the fifth circuit pattern is the same as the number of the semiconductor elements mounted on the sixth circuit pattern. 8. The semiconductor device according to claim 7,

[0098] <Appendix 10> the fifth circuit pattern is located on one side of the second circuit pattern in the first direction, the sixth circuit pattern is located on the other side in the first direction with respect to the second circuit pattern, The plurality of semiconductor elements mounted on the fifth circuit pattern and the plurality of semiconductor elements mounted on the sixth circuit pattern are each connected to the second circuit pattern. 10. The semiconductor device according to claim 9,

[0099] <Appendix 11> A control terminal; a plurality of control wirings connecting the plurality of semiconductor elements mounted on the first circuit pattern to the control terminals; The plurality of control wirings include a plurality of first control wirings that connect the plurality of semiconductor elements to one or more relay portions provided on the first circuit pattern. 9. The semiconductor device according to claim 8,

[0100] <Appendix 12> The plurality of semiconductor elements mounted on the first circuit pattern are connected to any of the plurality of relay portions positioned side by side in the second direction. 12. The semiconductor device according to claim 11,

[0101] <Appendix 13> The plurality of control wirings include a plurality of second control wirings that connect the plurality of relay portions that are aligned in the second direction to a seventh circuit pattern of the substrate that extends in the second direction, and a third control wiring that connects the seventh circuit pattern to the control terminal. 13. The semiconductor device according to claim 12. [Industrial Applicability]

[0102] As described above, the present invention has the effect of increasing mutual inductance while suppressing an increase in the mounting area of ​​the positive and negative terminals, and is useful for semiconductor devices such as power semiconductor devices. [Explanation of symbols]

[0103] 1. Semiconductor device 10 Semiconductor elements 20 Multilayer substrate (substrate) 20a Side 1 20b Side 2 21 Insulating substrate 22a to 22n 1st to 14th circuit patterns 23 Heat dissipation layer 30 Positive terminal 31 First rising section 31a Part to be joined 32 Second rising section 32a Part to be joined 33 Connecting part 34 External connection part 40 Negative terminal 41 First rising section 41a Part to be joined 42 Second rising section 42a Part to be joined 43 Connecting part 44 External connection part 50 output terminal 51,52 Part to be joined 53,54 External connection part 61~63,65 Control terminals 64 Sense terminal 66,67 Temperature sense terminal 68 Temperature sensor 70 cases 130 Positive terminal 131 First rising section 131a Part to be joined 132 Second rising section 132a Part to be joined 133 Upper end support part 134 External connection part 140 Negative terminal 141 First rising section 141a Part to be joined 142 Second rising section 142a Part to be joined 143 Lower end support part 144 External connection part 230 Positive terminal 231 Horizontal part 231a,231b Part to be joined 232 External connection part 240 Negative extremes 241 Horizontal section 241a, 241b Joints 242 External connection part D1 Direction 1 D2 Direction 2 G gap R1~R3 ​​1st~3rd middle section W wiring W1~W3 Control Lines 1~3

Claims

1. A semiconductor element; a substrate on which the semiconductor element is mounted; a positive electrode terminal and a negative electrode terminal arranged on a first side of the substrate extending in a first direction, Each of the positive electrode terminal and the negative electrode terminal has a rising portion extending in a direction intersecting a mounting surface of the substrate on which the semiconductor element is mounted, The rising portions of the positive electrode terminal and the rising portions of the negative electrode terminal are alternately positioned opposite each other, and a total of three or more of them are arranged side by side. A semiconductor device characterized by:

2. The rising portion of the positive electrode terminal and the rising portion of the negative electrode terminal are positioned side by side in the first direction.

2. The semiconductor device according to claim 1.

3. The plurality of rising portions of the positive electrode terminal and the plurality of rising portions of the negative electrode terminal are supported at an end portion on the first side and extend in the second direction toward a second side of the substrate that faces the first side in the second direction.

3. The semiconductor device according to claim 2.

4. One of the plurality of rising portions of the positive electrode terminal and the plurality of rising portions of the negative electrode terminal is supported at an end portion on the opposite side to the substrate in the intersecting direction, and the other of the plurality of rising portions is supported at an end portion on the substrate side in the intersecting direction.

3. The semiconductor device according to claim 2.

5. The two one rising portions form a U-shaped plate shape together with a support portion located at an end of the one rising portion on the opposite side from the substrate in the intersecting direction, The two other rising portions form a U-shaped plate shape together with a support portion located at an end of the two other rising portions on the substrate side in the intersecting direction.

5. The semiconductor device according to claim 4.

6. one of the positive electrode terminal and the negative electrode terminal is bonded to a first circuit pattern of the substrate; The other of the positive electrode terminal and the negative electrode terminal is joined to a second circuit pattern of the substrate that is located on the first side of the first circuit pattern.

2. The semiconductor device according to claim 1.

7. an output terminal disposed on a second side of the substrate that faces the first side of the substrate in a second direction; The output terminal is joined to a third circuit pattern of the substrate located on one side of the first circuit pattern in the first direction, and a fourth circuit pattern of the substrate located on the other side of the first circuit pattern in the first direction.

7. The semiconductor device according to claim 6.

8. a plurality of the semiconductor elements mounted on the first circuit pattern; The number of the semiconductor elements connected to the third circuit pattern is equal to the number of the semiconductor elements connected to the fourth circuit pattern.

8. The semiconductor device according to claim 7.

9. a plurality of the semiconductor elements mounted on a fifth circuit pattern of the substrate located on the first side of the third circuit pattern; a plurality of the semiconductor elements mounted on a sixth circuit pattern of the substrate located on the first side of the fourth circuit pattern, The number of the semiconductor elements mounted on the fifth circuit pattern is the same as the number of the semiconductor elements mounted on the sixth circuit pattern.

8. The semiconductor device according to claim 7.

10. the fifth circuit pattern is located on one side in the first direction with respect to the second circuit pattern, the sixth circuit pattern is located on the other side in the first direction with respect to the second circuit pattern, The plurality of semiconductor elements mounted on the fifth circuit pattern and the plurality of semiconductor elements mounted on the sixth circuit pattern are each connected to the second circuit pattern.

10. The semiconductor device according to claim 9.

11. A control terminal; a plurality of control wirings connecting the plurality of semiconductor elements mounted on the first circuit pattern to the control terminals, The plurality of control wirings include a plurality of first control wirings that connect the plurality of semiconductor elements to one or more relay portions provided on the first circuit pattern.

9. The semiconductor device according to claim 8.

12. The plurality of semiconductor elements mounted on the first circuit pattern are connected to any of the plurality of relay portions positioned side by side in the second direction.

12. The semiconductor device according to claim 11.

13. The plurality of control wirings include a plurality of second control wirings that connect the plurality of relay portions that are aligned in the second direction to a seventh circuit pattern of the substrate that extends in the second direction, and a third control wiring that connects the seventh circuit pattern to the control terminal.

13. The semiconductor device according to claim 12.

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