Semiconductor device

Abstract

To provide a semiconductor device including a capacitor that can have a large capacity.SOLUTION: A semiconductor device of the present disclosure includes a main conductive region DT0, a first conductive region DT1, a second conductive region DT2, a first first-side dielectric layer (first inner dielectric layer D11), a second first-side dielectric layer (second inner dielectric layer D12), a first second-side dielectric layer (first outer dielectric layer D21), and a second second-side dielectric layer (second outer dielectric layer D22). A main trench extends from the surface of an epitaxial semiconductor layer 1D to a depth penetrating a base epitaxial semiconductor layer 1B, and the main conductive region DT0 is electrically connected to a semiconductor substrate 1A. A first trench and a second trench respectively extend from the surface of the epitaxial semiconductor layer 1D to a depth reaching the base epitaxial semiconductor layer 1B, and the first conductive region DT1 and the second conductive region DT2 are electrically insulated from the base epitaxial semiconductor layer 1B.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a deep trench isolation (DTI) structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 153693

[0004] [overview] The present disclosure provides a semiconductor device including a capacitor capable of having a large capacitance.

[0005] The semiconductor device of the present disclosure comprises an underlying epitaxial semiconductor layer, a buried semiconductor layer, and an epitaxial semiconductor layer sequentially stacked on a semiconductor substrate, and comprises, in a plan view, a main trench, a first trench formed on a first side of the main trench, a second trench formed on a second side of the main trench, a first sinker region formed on the first side of the first trench, and a second sinker region formed on the second side of the second trench, a main conductive region buried in the main trench, a first conductive region buried in the first trench, a second conductive region buried in the second trench, a first first-side dielectric layer provided between the main conductive region and the first conductive region, and a first sinker region formed on the first side of the second trench. a second first-side dielectric layer provided between the main conductive region and the first sinker region, a first second-side dielectric layer provided between the main conductive region and the second conductive region, and a second second-side dielectric layer provided between the second conductive region and the second sinker region, wherein the main trench extends from the surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer, the main conductive region is electrically connected to the semiconductor substrate, the first trench and the second trench each extend from the surface of the epitaxial semiconductor layer to a depth reaching the underlying epitaxial semiconductor layer, and the first conductive region and the second conductive region are electrically insulated from the underlying epitaxial semiconductor layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view of a semiconductor chip. [Figure 2] FIG. 2 is a plan view of a device region according to the first example. [Figure 3] FIG. 3 is a plan view of a device region according to the second example. [Figure 4] 4A and 4B are a cross-sectional view of the device region shown in FIG. 2 taken along the line AA (FIG. 4A) and a circuit diagram (FIG. 4B). [Figure 5] FIG. 5 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 6]FIG. 6 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 7] FIG. 7 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 8] FIG. 8 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 9] FIG. 9 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 10] FIG. 10 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 11] FIG. 11 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 12] FIG. 12 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 13] FIG. 13 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device. [Figure 14] FIG. 14 is a diagram illustrating a longitudinal cross-sectional configuration of a device according to an example.

[0007] [Detailed explanation] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in each drawing are designated by the same reference numerals, and redundant explanations will be omitted.

[0008] FIG. 1 is a plan view of a semiconductor chip.

[0009] The semiconductor chip 100 (semiconductor device) has a rectangular parallelepiped shape. The semiconductor chip 100 has a first main surface 3 on one side. A back surface is located on the opposite side of the first main surface 3. The semiconductor chip 100 has a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the back surface. The thickness direction of the semiconductor chip 100 is defined as the Z-axis direction, the direction perpendicular to the Z-axis is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The depth direction of the semiconductor chip 100 is defined as the positive direction of the Z-axis, and the negative direction of the Z-axis indicates the direction from the back surface of the semiconductor substrate toward the first main surface 3 (top surface).

[0010] The first main surface 3 and the back surface are each perpendicular to the Z axis. The planar shape (shape in plan view) of the first main surface 3 when viewed from the normal direction (Z axis direction) of the first main surface 3 is rectangular (quadrilateral). The back surface of the semiconductor substrate also has a rectangular (quadrilateral) shape in plan view. The first side surface 5A and the second side surface 5B, which constitute two opposing sides of the rectangle in plan view, each extend along the X axis direction. The third side surface 5C and the fourth side surface 5D, which constitute the other two opposing sides of the rectangle in plan view, each extend along the Y axis direction. These adjacent side surfaces are orthogonal in plan view, but can also intersect at an angle other than orthogonal.

[0011] The semiconductor chip 100 includes a plurality of device regions 10 provided on the first main surface 3. There is a gap between each device region 10 and each side surface (first side surface 5A to fourth side surface 5D) of the semiconductor chip 100. The number, arrangement, and shape of the device regions 10 are arbitrary and are not limited to a specific number, arrangement, or shape.

[0012] Various devices are formed in each device region 10. In this example, at least one device region 10 includes a device 50.

[0013] An example of the device 50 is a field-effect transistor. The field-effect transistor in this example is a metal insulator semiconductor field-effect transistor (MISFET). A metal-oxide-semiconductor field-effect transistor (MOSFET) can be used as the MISFET. The MOSFET in this embodiment is an extended drain (ED) MOSFET. An exemplary EDMOS-FET includes an N-type well region where N-type carriers drift on the drain region side. Field-effect transistors can also be used as power transistors. Known drain-source voltages for MISFETs include high voltage (HV: e.g., 100 V to 1000 V), medium voltage (MV: e.g., 30 V to 100 V), and low voltage (LV: e.g., 1 V to 30 V).

[0014] FIG. 2 is a plan view of a device region according to the first example.

[0015] A device 50 is disposed in the device region 10. Note that in FIG. 2, the insulating region formed on the substrate surface is omitted. A plurality of annular trenches are formed to surround the device 50. A main conductive region DT0 is buried in the annular main trench TR0. A first conductive region DT1 is buried in an annular first trench TR1 located inside the main trench TR0. A second conductive region DT2 is buried in an annular second trench TR2 located outside the main trench TR0.

[0016] A first sinker region S1 is formed inside the first annular trench TR1, and a second sinker region S2 is formed outside the second annular trench TR2.

[0017] A first inner dielectric layer D11 is provided between the main conductive region DT0 and the first conductive region DT1. A second inner dielectric layer D12 is provided between the first conductive region DT1 and the first sinker region S1. A first outer dielectric layer D21 is provided between the main conductive region DT0 and the second conductive region. A second outer dielectric layer D22 is provided between the second conductive region DT2 and the second sinker region S2.

[0018] The main electrode E0 is electrically connected to the main conductive region DT0. The first electrode E11 is electrically connected to the first conductive region DT1. The second electrode E21 is electrically connected to the second conductive region DT2. The first sinker electrode E12 is electrically connected to the first sinker region S1. The second sinker electrode E22 is electrically connected to the second sinker region S2.

[0019] In this example, the first trench TR1 surrounds the device 50 in plan view. The second trench TR2 surrounds the main trench TR0 in plan view. The region inside the trench on the device 50 side and the region outside the trench are electrically isolated in the region on the substrate surface side. The presence of multiple trenches increases the isolation effect.

[0020] FIG. 3 is a plan view of a device region according to the second example.

[0021] 3 omits the illustration of the insulating region formed on the substrate surface. The device region 10 of the second example differs from the device region of the first example in that no devices such as active elements are formed in the annular trench, and the space region inside the annular trench extends along the Y-axis. The other structures in the device region 10 of the second example are identical to those in the device region of the first example. In other words, the device region of the second example does not include any active elements, and only a capacitor formed from the annular trench is included as a device.

[0022] 4A and 4B are a cross-sectional view of the device region shown in FIG. 2 taken along the line AA (FIG. 4A) and a circuit diagram (FIG. 4B).

[0023] The semiconductor device in the device region includes a substrate 1. The substrate 1 includes a semiconductor substrate 1A, an underlying epitaxial semiconductor layer 1B formed on the semiconductor substrate 1A, a buried semiconductor layer 1C formed on the underlying epitaxial semiconductor layer 1B, and an epitaxial semiconductor layer 1D formed on the buried semiconductor layer 1C.

[0024] In this example, each semiconductor region in the device region has a first conductivity type of P-type and a second conductivity type of N-type, but these conductivity types are interchangeable. An exemplary P-type impurity (trivalent element) is boron (B). An exemplary N-type impurity (pentavalent element) is phosphorus (P) or arsenic (As). Also, an exemplary material for each semiconductor region is Si (silicon), but other semiconductor materials may also be used.

[0025] The conductivity type of the semiconductor substrate 1A is P-type. The conductivity type of the underlying epitaxial semiconductor layer 1B is P-type. The conductivity type of the buried semiconductor layer 1C is N-type. The conductivity type of the epitaxial semiconductor layer 1D is N-type. The impurity concentration of the epitaxial semiconductor layer 1D is set lower than the impurity concentration of the buried semiconductor layer 1C. A PN junction is formed between the underlying epitaxial semiconductor layer 1B and the buried semiconductor layer 1C. The impurity concentration of the buried semiconductor layer 1C can be set relatively high, so that the electric field strength in the buried semiconductor layer 1C is high. A device 50 capable of operating at a high voltage can be formed in the epitaxial semiconductor layer 1D.

[0026] A device 50 is formed in the epitaxial semiconductor layer 1D.

[0027] A first sinker region S1 is formed in the epitaxial semiconductor layer 1D. The first sinker region S1 surrounds the device 50 in a plan view. The conductivity type of the first sinker region S1 is P-type, but it can also be N-type. A first sinker region contact region 12 is formed on the surface of the first sinker region S1, and the surface of the first sinker region contact region 12 is connected to a first sinker electrode E12. The conductivity type of the first sinker region contact region 12 can be the same as the conductivity type of the first sinker region S1. The impurity concentration of the first sinker region contact region 12 is set higher than the impurity concentration of the first sinker region S1.

[0028] The first conductive region DT1 extends from the surface position of the epitaxial semiconductor layer 1D to the underlying epitaxial semiconductor layer 1B. The first conductive region DT1 is made of polysilicon or the like doped with P-type impurities. The first conductive region DT1 surrounds the first sinker region S1 in plan view. The surface of the first conductive region DT1 is connected to the first electrode E11. The first conductive region DT1 is insulated from adjacent semiconductor regions (the underlying epitaxial semiconductor layer 1B, the buried semiconductor layer 1C, and the first sinker region S1) by the second inner dielectric layer D12.

[0029] The main conductive region DT0 extends from the surface of the epitaxial semiconductor layer 1D to the interior of the semiconductor substrate 1A. The main conductive region DT0 is made of polysilicon or the like doped with P-type impurities. In a plan view, the main conductive region DT0 surrounds the first conductive region DT1. The surface of the main conductive region DT0 is connected to the main electrode E0. The main conductive region DT0 is electrically connected to the semiconductor substrate 1A.

[0030] The second conductive region DT2 extends from the surface position of the epitaxial semiconductor layer 1D to the underlying epitaxial semiconductor layer 1B. The second conductive region DT2 is made of polysilicon or the like doped with P-type impurities. The second conductive region DT2 surrounds the main conductive region DT0 in plan view. The surface of the second conductive region DT2 is connected to the second electrode E21. The second conductive region DT2 is insulated from adjacent semiconductor regions (the underlying epitaxial semiconductor layer 1B, the buried semiconductor layer 1C, and the second sinker region S2) by the second outer dielectric layer D22.

[0031] A second sinker region S2 is formed in the epitaxial semiconductor layer 1D. In a plan view, the second sinker region S2 surrounds the second conductive region DT2. The conductivity type of the second sinker region S2 is P-type, but it can also be N-type. A second sinker region contact region 22 is formed on the surface of the second sinker region S2, and the surface of the second sinker region contact region 22 is connected to a second sinker electrode E22. The conductivity type of the second sinker region contact region 22 can be the same as the conductivity type of the second sinker region S2. The impurity concentration of the second sinker region contact region 22 is set higher than the impurity concentration of the second sinker region S2.

[0032] The surface of the epitaxial semiconductor layer 1D is covered with an insulating region 18. The portion where the insulating region 18 is formed may constitute STI (shallow trench isolation). The material of the insulating region 18 is, for example, an insulator such as SiO2. The insulating region 18 may also be a field oxide film.

[0033] The first inner dielectric layer D11 is made of an insulator such as SiO2 and extends from the lower surface of the insulating region 18 to a position reaching the semiconductor substrate 1A. The second inner dielectric layer D12 is made of an insulator such as SiO2 and extends from the lower surface of the insulating region 18 to a position reaching the underlying epitaxial semiconductor layer 1B and is connected to the first inner dielectric layer D11. The first outer dielectric layer D21 is made of an insulator such as SiO2 and extends from the lower surface of the insulating region 18 to a position reaching the semiconductor substrate 1A. The second outer dielectric layer D22 is made of an insulator such as SiO2 and extends from the lower surface of the insulating region 18 to a position reaching the underlying epitaxial semiconductor layer 1B and is connected to the first outer dielectric layer D21.

[0034] The conductivity type of the first sinker region S1 is P type, and the conductivity type of the second sinker region S2 is P type. The conductivity type of the sinker region can also be N type, but if it is P type, it will have the same conductivity type as the conductive region in the trench (DT0, DT1, DT2: P-type impurity-doped polysilicon), and it is thought that the waveform based on capacitance will be improved compared to N type. Furthermore, if the conductivity type of the sinker region is P type, a PN junction is formed with the epitaxial semiconductor layer 1D, and therefore electrical isolation is also achieved between the sinker region and the epitaxial semiconductor layer.

[0035] The semiconductor device of the first example includes a device 50 formed in an epitaxial semiconductor layer 1D, and in plan view, the main trench is annular and surrounds the device 50. The device 50 of the example includes a field effect transistor formed in a semiconductor well region 14 (see FIG. 14) made of a P-type semiconductor, and the shortest distance DX between the semiconductor well region 14 (device 50) and the first sinker region S1 satisfies the following relationship:

[0036] 2 μm≦DX≦10 μm.

[0037] Next, the circuit diagram of Fig. 4(B) will be explained. The structure of Fig. 4(A) includes four capacitors (C12, C11, C21, C22) as shown in Fig. 4(B).

[0038] The first inner capacitor C11 comprises a primary conductive region DT0, a first conductive region DT1, and a first inner dielectric layer D11 sandwiched between the primary conductive region DT0 and the first conductive region DT1.

[0039] The second inner capacitor C12 includes a first conductive region DT1, a first sinker region S1, and a second inner dielectric layer D12 sandwiched between the first conductive region DT1 and the first sinker region S1.

[0040] The first outer capacitor C21 comprises a primary conductive region DT0, a secondary conductive region DT2, and a first outer dielectric layer D21 sandwiched between the primary conductive region DT0 and the second conductive region DT2.

[0041] The second outer capacitor C22 comprises a second conductive region DT2, a second sinker region S2, and a second outer dielectric layer D22 sandwiched between the second conductive region DT2 and the second sinker region S2.

[0042] The second inner capacitor C12, the first inner capacitor C11, the first outer capacitor C21, and the second outer capacitor C22 are electrically connected in series. By selecting two desired electrodes from the electrode group of each capacitor, a capacitor having a capacitance between the selected electrodes can be obtained. Note that, as a typical example of use, the main electrode E0 is used as a substrate terminal, and only the second inner capacitor C12 and the second outer capacitor C22 are used as capacitors, but the use example is not limited to this.

[0043] Next, a method for manufacturing the semiconductor device shown in FIG. 4 will be described.

[0044] FIG. 5 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0045] First, a base epitaxial semiconductor layer 1B is grown on a semiconductor substrate 1A. Next, a buried semiconductor layer 1C is formed on the base epitaxial semiconductor layer 1B. Then, an epitaxial semiconductor layer 1D is grown on the buried semiconductor layer 1C. Each semiconductor layer can be formed by supplying a gas containing raw materials (e.g., Si) and impurities onto the exposed surface of the substrate. The impurities can be added using ion implantation or diffusion. For example, the buried semiconductor layer 1C can be formed using ion implantation. An oxide film OX is formed on the surface of the epitaxial semiconductor layer 1D. The oxide film OX is a natural oxide film or an intentionally formed oxide film, and can remain on the surface of the epitaxial semiconductor layer 1D in subsequent processes (FIGS. 6 to 13). That is, the oxide film OX may or may not be formed on the epitaxial semiconductor layer 1D. An example of a method for forming an epitaxial layer is a CVD method using a silicon-containing gas such as silane (SiH4).

[0046] FIG. 6 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0047] Next, a first mask layer MSK1 is formed on the surface of the epitaxial semiconductor layer 1D. When forming the first mask layer MSK1, first, a resist is applied to the surface of the epitaxial semiconductor layer 1D, then an annular non-cured region is set in a plan view and exposed to light, and then the resist is developed. As a result, the resist in the non-cured region is removed, and the first mask layer MSK1 is formed with a first opening OP1 patterned in a plan view.

[0048] FIG. 7 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0049] Next, the substrate 1 is etched through the first opening OP1 in the first mask layer MSK1 to form a trench. The etching is performed from the surface of the epitaxial semiconductor layer 1D, through the buried semiconductor layer 1C, and until it reaches the interior of the underlying epitaxial semiconductor layer 1B. Because the aspect ratio of the trench is high, anisotropic etching can be used. An exemplary anisotropic etching (dry etching) method is reactive ion etching (RIE). Exemplary etching gases that can be used include, but are not limited to, fluorocarbons and gases containing halogens such as SF6.

[0050] Next, a first sinker region S1 and a second sinker region S2 are formed using an ion implantation method. In this example, the conductivity type of the first sinker region S1 and the second sinker region S2 is P-type, so P-type impurities are implanted into the inner surface of the trench. An exemplary P-type impurity is boron (B). Note that the conductivity type of the first sinker region S1 and the second sinker region S2 can also be N-type. During ion implantation, the ion traveling direction is tilted with respect to the depth direction (Z-axis) of the substrate 1. After the Nth ion implantation is completed, the substrate 1 is rotated, for example, around the ion traveling direction as the central axis, and the N+1th ion implantation is performed (N is a natural number). For example, the substrate 1 is rotated 90 degrees from the initial position for three times, for a total of four ion implantations. Note that the rotation angle and the number of rotations are not limited to these.

[0051] By ion implantation of P-type impurities, the P-type impurities are added to the epitaxial semiconductor layer 1D in the region near the inner surface of the trench, forming a first sinker region S1 and a second sinker region S2. The P-type impurities are also added to the inner surfaces of the buried semiconductor layer 1C and the underlying epitaxial semiconductor layer 1B, which are near the inner surface of the trench. However, since the N-type impurity concentration of the buried semiconductor layer 1C is higher than the P-type impurity concentration of the sinker region and the conductivity type of the underlying epitaxial semiconductor layer 1B is already P-type, no significant change in the impurity doping state occurs in these regions. When P-type impurities are implanted into the high-concentration buried semiconductor layer 1C and the region near the boundary with its adjacent layers, an electric field relaxation effect can be expected. After the ion implantation is completed, the first mask layer MSK1 can be peeled off and removed. The first mask layer MSK1 can also be peeled off before the ion implantation.

[0052] FIG. 8 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0053] Next, an insulating film is formed on the surface of the substrate 1, and a second inner dielectric layer D12 and a second outer dielectric layer D22 made of this insulating film are formed in the trench. When the insulating film is an oxide film (SiO2), the oxide film can be formed using thermal oxidation of silicon, CVD (chemical vapor deposition), or sputtering. An example of a raw material for the CVD method is TEOS ((Si(OC2H5)4):tetraethoxysilane). After the insulating film is formed on the surface of the substrate 1, the insulating film on the substrate surface region excluding the inner surface of the trench can be removed using CMP (chemical mechanical polishing) or the like, if necessary. The insulating film may also be left unremoved. Note that the material for the dielectric layer may be a material other than SiO2.

[0054] After forming the second inner dielectric layer D12 and the second outer dielectric layer D22, a conductive material DT is deposited to fill the trenches. The conductive material DT is also deposited on the surface of the epitaxial semiconductor layer 1D. The conductive material DT is polysilicon doped with P-type impurities. The deposition method can be, for example, sputtering, or CVD using a Si-containing gas such as silane.

[0055] FIG. 9 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0056] Next, the region of the conductive material DT located on the front surface side of the substrate 1 is removed by CMP or the like, thereby exposing the top of the second inner dielectric layer D12, the top of the second outer dielectric layer D22, the top of the first sinker region S1, and the top of the second sinker region S2.

[0057] FIG. 10 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0058] Next, a second mask layer MSK2 is formed on the surface of the substrate 1. To form the second mask layer MSK2, first, a resist is applied to the surface of the epitaxial semiconductor layer 1D, then an annular non-cured region is set in a plan view and exposed to light, and the resist is then developed. This removes the resist from the non-cured region, forming the second mask layer MSK2 in which a second opening OP2 is patterned and annular in a plan view. The second opening OP2 is located on the surface of the conductive material DT. The opening width of the second opening OP2 is smaller than the opening width of the upper portion of the trench filled with the conductive material DT.

[0059] FIG. 11 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0060] Next, the substrate 1 is etched through the second opening OP2 (see FIG. 10) of the second mask layer MSK2 to form a main trench TR0. The etching is performed from the surface of the epitaxial semiconductor layer 1D, through the buried semiconductor layer 1C and the underlying epitaxial semiconductor layer 1B, and until it reaches the interior of the semiconductor substrate 1A. Because the main trench TR0 has a high aspect ratio, anisotropic etching can be used. An exemplary anisotropic etching (dry etching) method is RIE. The etching gas may be, but is not limited to, a fluorocarbon or a gas containing a halogen, such as SF6.

[0061] FIG. 12 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0062] Next, an insulating film is formed on the surface of the substrate 1, and a first inner dielectric layer D11 and a first outer dielectric layer D21 made of this insulating film are formed in the main trench. When the insulating film is an oxide film (SiO2), the oxide film can be formed using thermal oxidation of silicon, CVD (chemical vapor deposition), or sputtering. TEOS is an example of a raw material for the CVD method. After forming the insulating film on the surface of the substrate 1, the insulating film in the substrate surface region except for the inner surface of the main trench can be removed using CMP (chemical mechanical polishing) or the like. This insulating film may also be left unremoved. Note that the material of the dielectric layer may be a material other than SiO2.

[0063] After forming the first inner dielectric layer D11 and the first outer dielectric layer D21, a conductive material is deposited to fill the main trench, forming a main conductive region DT0 inside the main trench. The main conductive region DT0 is also deposited on the surface of the epitaxial semiconductor layer 1D. This conductive material is polysilicon doped with P-type impurities. While sputtering can be used as a deposition method, CVD using a Si-containing gas such as silane can also be used.

[0064] FIG. 13 is a diagram showing a vertical cross-sectional structure of a semiconductor device for explaining a method for manufacturing the semiconductor device.

[0065] Next, of the conductive material constituting the main conductive region DT0, a region located on the surface side of the substrate 1 is removed by CMP or the like, thereby exposing the top of the second inner dielectric layer D12, the top of the first outer dielectric layer D21, the top of the first inner dielectric layer D11, the top of the second outer dielectric layer D22, the top of the first sinker region S1, and the top of the second sinker region S2.

[0066] Finally, as shown in FIG. 4A, an insulating region 18 is formed on the surface of the epitaxial semiconductor layer 1D. The insulating region 18 has a pattern with openings in areas where various electrodes (main electrode E0, first electrode E11, second electrode E21, first sinker electrode E12, and second sinker electrode E22) will be formed. Methods for forming the insulating region 18 include thermal oxidation of the exposed surface of the epitaxial semiconductor layer 1D, or etching the exposed surface and then embedding silicon dioxide by CVD. A first sinker region contact region 12 is formed on the surface of the first sinker region S1, and a second sinker region contact region 22 is formed on the surface of the second sinker region S2. The contact regions can be formed by adding the same impurities as the sinker regions.

[0067] When the trench structure described above surrounds a device 50 in plan view, it functions as a deep trench isolation structure (DTI). After the isolation structure is formed, a device 50 such as a transistor can be formed in the region surrounded by the isolation structure.

[0068] FIG. 14 is a diagram illustrating a longitudinal cross-sectional configuration of a device according to an example.

[0069] The FET, an active element constituting the device 50, is made of silicon (Si) and includes an N-type well region 51, a P-type well region 52, a source region SR, a drain region DR, a gate insulating film GX, and a gate electrode G1. Each well region is formed within a P-type semiconductor well region 14. The N-type well region 51 is made of an N-type semiconductor, and the P-type well region 52 is made of a P-type semiconductor. The source region SR and the drain region DR are made of an N-type semiconductor. The gate insulating film GX is made of SiO2. The gate electrode G1 can be made of polysilicon, but may also contain metals such as copper (Cu) or aluminum (Al), alloys containing one or more metals, or compounds of metal and silicon (silicides). The FET may also include a second transistor Q2 having a symmetrical structure to the transistor structure consisting of these elements. The FET may also be a DMOS-FET. A P-type contact region may also be provided adjacent to the source region SR.

[0070] Next, the materials and impurity concentrations of the above-mentioned semiconductor regions will be described.

[0071] The semiconductor material constituting the semiconductor chip 100 described above is silicon (Si). Compound semiconductors can also be used as the semiconductor material constituting the semiconductor chip 100. Compound semiconductors include III-V compound semiconductors, IV-IV compound semiconductors, and alloy semiconductors using these semiconductors. Ga-containing semiconductors such as GaAs and GaN can be used as III-V compound semiconductors. Si-containing semiconductors such as SiC and SiGe can be used as IV-IV compound semiconductors.

[0072] More specifically, the material of the semiconductor substrate 1A is silicon (Si). The material of the semiconductor substrate 1A can also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). The conductivity type of the semiconductor substrate 1A is P-type (first conductivity type), and the impurity concentration (C 1A ) is, for example, 1×10 14 cm -3 ~5×10 18cm -3 The thickness of the semiconductor substrate 1A is, for example, 250 μm to 800 μm.

[0073] The material of the underlying epitaxial semiconductor layer 1B can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the underlying epitaxial semiconductor layer 1B is P-type (first conductivity type). The impurity concentration (C 1B ) is, for example, 1×10 13 cm -3 ~5×10 16 cm -3 can be set to.

[0074] The material of the buried semiconductor layer 1C can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the buried semiconductor layer 1C is N-type (second conductivity type), and the impurity concentration (C 1C ) is, for example, 1×10 17 cm -3 ~1×10 19 cm -3 The thickness of the buried semiconductor layer 1C can be set to, for example, 1 μm to 5 μm.

[0075] The material of the epitaxial semiconductor layer 1D can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the epitaxial semiconductor layer 1D is N-type (second conductivity type), and the impurity concentration (C 1D ) is, for example, 5×10 14 cm -3 ~1×10 17 cm -3 The thickness of the epitaxial semiconductor layer 1D can be set to, for example, 3 μm to 20 μm. In this example, the impurity concentration is 1D <C 1A <C 1C It is also possible to set the conductivity type of the epitaxial semiconductor layer 1D to P type in order to reduce the drain capacitance of an N-channel DMOS transistor or the like.

[0076] The impurity concentration (C S1) and the impurity concentration (C S2 ) is given by the following relationship (1×10 15 cm -3 ≦C S1 ≦1×10 19 cm -3 , 1×10 15 cm -3 ≦C S2 ≦1×10 19 cm -3 ) is satisfied.

[0077] The impurity concentration of the epitaxial semiconductor layer 1D is C S1 or C S2 can be set smaller than

[0078] The material of the N-type well region 51 can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the N-type well region 51 is N-type (second conductivity type), and the impurity concentration (C 51 ) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the N-type well region 51 can be set to, for example, 0.5 μm to 4 μm.

[0079] The material of the P-type well region 52 can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the P-type well region 52 is P type (first conductivity type), and the impurity concentration (C 52 ) is, for example, 1×10 16 cm -3 ~1×10 18 cm -3 The thickness of the P-type well region 52 can be set to, for example, 0.5 μm to 4 μm.

[0080] The material of the P-type semiconductor well region 14 can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the P-type semiconductor well region 14 is P-type (first conductivity type), and the impurity concentration (C 14 ) is, for example, 1×10 15 cm -3 ~1×10 17 cm-3 The impurity concentration can be made lower than that of the P-type well region 52. The thickness of the P-type semiconductor well region 14 can be set to, for example, 1 μm to 10 μm.

[0081] The material of the source region SR and the drain region DR can be the same as the semiconductor material of the semiconductor substrate 1A. The conductivity type of the source region SR and the drain region DR is N-type (second conductivity type), and the impurity concentration (C SR , C DR ) is, for example, 1×10 19 cm -3 ~5×10 21 cm -3 The thickness of the source region SR and the drain region DR can be set to, for example, 0.2 μm to 1 μm, but a structure in which the depth is made shallower or deeper is also possible.

[0082] The main conductive region DT0, the first conductive region DT1, and the second conductive region DT2 can be doped with a high concentration of impurities. A high concentration of impurities may be doped into a region of the semiconductor substrate 1A located below the main conductive region DT0. The impurity concentration of each of these conductive regions is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following can be used as the material for these conductive regions instead of polysilicon: tungsten, copper, or the like. (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0083] [A1] A semiconductor device comprising an underlying epitaxial semiconductor layer 1B, a buried semiconductor layer 1C, and an epitaxial semiconductor layer 1D sequentially stacked on a semiconductor substrate 1A, and comprising, in a plan view, a main trench TR0, a first trench TR1 formed on a first side of the main trench TR0, a second trench TR2 formed on a second side of the main trench TR0, a first sinker region S1 formed on the first side of the first trench TR1, and a second sinker region S2 formed on a second side of the second trench TR2, a main conductive region DT0 buried in the main trench TR0, a first conductive region DT1 buried in the first trench TR1, a second conductive region DT2 buried in the second trench TR2, a first first-side dielectric layer (first inner dielectric layer D11)) provided between the main conductive region DT0 and the first conductive region DT1, and a first sinker region S1 formed on the first side of the second trench TR2. a second first-side dielectric layer (second inner dielectric layer D12) provided between the main conductive region DT0 and the second conductive region DT2, a first second-side dielectric layer (first outer dielectric layer D21) provided between the main conductive region DT0 and the second conductive region DT2, and a second second-side dielectric layer (second outer dielectric layer D22) provided between the second conductive region DT2 and the second sinker region S2, wherein the main trench TR0 extends from the surface of the epitaxial semiconductor layer 1D to a depth penetrating the underlying epitaxial semiconductor layer 1B, and the main conductive region DT0 is electrically connected to the semiconductor substrate 1A, and the first trench TR1 and the second trench TR2 each extend from the surface of the epitaxial semiconductor layer 1D to a depth reaching the underlying epitaxial semiconductor layer 1B, and the first conductive region DT1 and the second conductive region DT2 are electrically insulated from the underlying epitaxial semiconductor layer 1B.

[0084] [A2] A semiconductor device according to [A1], comprising: a main electrode E0 electrically connected to the main conductive region DT0; a first electrode E11 electrically connected to the first conductive region DT1; a second electrode E21 electrically connected to the second conductive region DT2; a first sinker electrode E12 electrically connected to the first sinker region S1; and a second sinker electrode E22 electrically connected to the second sinker region S2.

[0085] [A3] A semiconductor device according to [A1], wherein the conductivity type of the semiconductor substrate 1A is a first conductivity type, the conductivity type of the underlying epitaxial semiconductor layer 1B is a first conductivity type, the conductivity type of the buried semiconductor layer 1C is a second conductivity type, and the conductivity type of the epitaxial semiconductor layer 1D is a second conductivity type.

[0086] [A4] The semiconductor device according to [A3], wherein the conductivity type of the first sinker region S1 is the first conductivity type, and the conductivity type of the second sinker region S2 is the first conductivity type.

[0087] [A5] Impurity concentration C of the first sinker region S1 S1 and the impurity concentration C of the second sinker region S2 S2 is related to the following: 1 x 10 15 cm -3 ≦C S1 ≦1×10 19 cm -3 , 1×10 15 cm -3 ≦C S2 ≦1×10 19 cm -3 The semiconductor device according to [A4], which satisfies the above.

[0088] [A6] The semiconductor device according to [A5], further comprising: a device 50 formed in the epitaxial semiconductor layer 1D; in a plan view, the main trench TR0 is annular and surrounds the device 50; the first side is an inner side and the second side is an outer side; the device 50 comprises a field effect transistor formed in a semiconductor well region 14 of a first conductivity type; and a shortest distance DX between the semiconductor well region 14 and the first sinker region S1 satisfies the following relationship: 2 μm≦DX≦10 μm.

[0089] [A7] The semiconductor device according to [A1], further comprising a device 50 formed in the epitaxial semiconductor layer 1D, wherein, in a planar view, the main trench TR0 is annular and surrounds the device 50, the first side being an inner side, and the second side being an outer side.

[0090] [A8] The semiconductor device according to [A7], wherein the first trench TR1 surrounds the device 50 in plan view.

[0091] [A9] The semiconductor device according to [A8], wherein the second trench TR2 surrounds the main trench TR0 in plan view.

[0092] [A10] The main conductive region DT0, the first conductive region DT1, and the first first-side dielectric layer sandwiched between the main conductive region DT0 and the first conductive region DT1 constitute a first first-side capacitor (first inner capacitor C11), the first conductive region DT1, the first sinker region S1, and the second first-side dielectric layer sandwiched between the first conductive region DT1 and the first sinker region S1 constitute a second first-side capacitor (second inner capacitor C12), and the main conductive region DT0, the second conductive region DT2, and the first second-side dielectric layer (first outer dielectric layer D21) sandwiched between the main conductive region DT0 and the second conductive region DT2 constitute a first The semiconductor device according to any one of [A1 to A9], wherein the second conductive region DT2, the second sinker region S2, and the second second-side dielectric layer (second outer dielectric layer D22) sandwiched between the second conductive region DT2 and the second sinker region S2 constitute a second second-side capacitor (second outer capacitor C22), and the second first-side capacitor (second inner capacitor C12), the first first-side capacitor (first inner capacitor C11), the first second-side capacitor (first outer capacitor C1), and the second second-side capacitor (second outer capacitor C22) are electrically connected in series.

[0093] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0094] 1...Substrate 1A...Semiconductor substrate 1B: Underlying epitaxial semiconductor layer 1C...Buried semiconductor layer 1D...epitaxial semiconductor layer 3...First main surface 5A…1st side 5B…Second side 5C…Third side 5D…Fourth side 10...Device area 12...Contact area for first sinker area 14...Well area 18...Isolation area 22...Contact area for second sinker area 50…devices 51...N-type well region 52...P-type well region 100...Semiconductor chip C11...First inner capacitor C12: Second inner capacitor C21: First outer capacitor C22: Second outer capacitor D11...First inner dielectric layer D12: Second inner dielectric layer D21...first outer dielectric layer D22: Second outer dielectric layer DR...Drain region DT…Conductive material DX: Shortest distance DT0…Main conduction area DT1…first conductive region DT2…Second conductive region E0…Main electrode E11…1st electrode E12...First sinker electrode E21…Second electrode E22...Electrode for second sinker G1: Gate electrode GX...Gate insulating film MSK1: First mask layer MSK2: Second mask layer OP1…1st opening OP2...Second opening OX...oxide film Q2: Second transistor SR...Source region S1: First sinker area S2: Second sinker area TR0...Main trench TR1: First trench TR2: Second trench

Claims

1. The semiconductor device includes an underlying epitaxial semiconductor layer, a buried semiconductor layer, and an epitaxial semiconductor layer, which are sequentially stacked on a semiconductor substrate; In plan view, The main trench and a first trench formed on a first side of the main trench; a second trench formed on a second side of the main trench; a first sinker region formed on a first side of the first trench; a second sinker region formed on a second side of the second trench; Equipped with a primary conductive region embedded within the primary trench; a first conductive region embedded in the first trench; a second conductive region embedded in the second trench; a first first-side dielectric layer provided between the main conductive region and the first conductive region; a second first-side dielectric layer provided between the first conductive region and the first sinker region; a first second-side dielectric layer provided between the primary conductive region and the second conductive region; a second second-side dielectric layer provided between the second conductive region and the second sinker region; Equipped with the main trench extends from a surface of the epitaxial semiconductor layer to a depth penetrating the underlying epitaxial semiconductor layer, and the main conductive region is electrically connected to the semiconductor substrate; the first trench and the second trench each extend from a surface of the epitaxial semiconductor layer to a depth reaching the underlying epitaxial semiconductor layer, and the first conductive region and the second conductive region are electrically insulated from the underlying epitaxial semiconductor layer. Semiconductor device.

2. a main electrode electrically connected to the main conductive region; a first electrode electrically connected to the first conductive region; a second electrode electrically connected to the second conductive region; a first sinker electrode electrically connected to the first sinker region; a second sinker electrode electrically connected to the second sinker region; Equipped with The semiconductor device according to claim 1 .

3. the conductivity type of the semiconductor substrate is a first conductivity type; the conductivity type of the underlying epitaxial semiconductor layer is a first conductivity type; the conductivity type of the buried semiconductor layer is the second conductivity type; The conductivity type of the epitaxial semiconductor layer is the second conductivity type. The semiconductor device according to claim 1 .

4. the conductivity type of the first sinker region is a first conductivity type; The conductivity type of the second sinker region is the first conductivity type. The semiconductor device according to claim 3 .

5. The impurity concentration C of the first sinker region Ｓ１ and the impurity concentration C of the second sinker region Ｓ２ is the following relation: 1×10 １５ cm －３ ≦C Ｓ１ ≦1×10 １９ cm －３ 、 1×10 １５ cm －３ ≦C Ｓ２ ≦1×10 １９ cm －３ 、 fulfill, The semiconductor device according to claim 4 .

6. a device formed in the epitaxial semiconductor layer; In plan view, the main trench is annular and surrounds the device; the first side is an inner side and the second side is an outer side; the device comprises a field effect transistor formed in a semiconductor well region of a first conductivity type; a shortest distance DX between the semiconductor well region and the first sinker region satisfies the following relationship: 2 μm≦DX≦10 μm; The semiconductor device according to claim 5 .

7. a device formed in the epitaxial semiconductor layer; In plan view, the main trench is annular and surrounds the device; The first side is an inner side and the second side is an outer side. The semiconductor device according to claim 1 .

8. In a plan view, the first trench surrounds the device. The semiconductor device according to claim 7 .

9. In a plan view, the second trench surrounds the main trench. The semiconductor device according to claim 8 .

10. the main conductive region, the first conductive region, and the first first-side dielectric layer sandwiched between the main conductive region and the first conductive region constitute a first first-side capacitor; the first conductive region, the first sinker region, and the second first-side dielectric layer sandwiched between the first conductive region and the first sinker region constitute a second first-side capacitor; the primary conductive region, the second conductive region, and the first second-side dielectric layer sandwiched between the primary conductive region and the second conductive region constitute a first second-side capacitor; the second conductive region, the second sinker region, and the second second-side dielectric layer sandwiched between the second conductive region and the second sinker region constitute a second second-side capacitor; the second first-side capacitor, the first first-side capacitor, the first second-side capacitor, and the second second-side capacitor are electrically connected in series; The semiconductor device according to any one of claims 1 to 9.

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