Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of improving adhesion between a base part and a resin sealing part.SOLUTION: A semiconductor device includes a base part 12 in which at least an upper surface thereof is metal, one or a plurality of components which are mounted on the base part so as to sandwich a first conductive member 16 and include a semiconductor chip, second conductive members 18A and 18B which are provided on the base part, contain sintered metal or a metallic powder-containing resin, and are not mounted with the one or plurality of components, and a resin sealing part 14 which comes in contact with the base part, the one or plurality of components and the second conductive member on the base part, and seals the one or plurality of components, wherein the second conductive member is separated from the first conductive member.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] It is known that a semiconductor chip is mounted on a base and then sealed with resin. Known techniques include roughening the surface of the base, roughening a portion of the surface of the base where the semiconductor chip is not mounted, and not providing a plating layer in the portion of the surface of the base where the semiconductor chip is not mounted (e.g., Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-287741 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-161098 [Patent Document 3] Japanese Patent Application Laid-Open No. 2018-85480 Summary of the Invention [Problem to be solved by the invention]

[0004] The metal on the surface of the base portion and the resin, which is the main component of the resin encapsulation portion, have poor adhesion. Therefore, due to factors such as differences in the linear expansion coefficients of the base portion and the resin encapsulation portion, the resin encapsulation portion may peel off from the base portion. Therefore, roughening the surface of the base portion can improve the adhesion between the base portion and the resin encapsulation portion. Furthermore, not providing a layer with poor adhesion to the resin encapsulation portion in a certain region can improve the adhesion between the base portion and the resin encapsulation portion. However, if the entire surface of the base portion is roughened, increasing the roughness to improve adhesion makes it difficult to mount a semiconductor chip. If regions where a semiconductor chip is not mounted are roughened or not provided with a layer with poor adhesion, the mounting area for the semiconductor chip is limited, reducing design freedom.

[0005] An object of the present disclosure is to provide a semiconductor device capable of improving adhesion between a base portion and a resin sealing portion, and a method for manufacturing the same. [Means for solving the problem]

[0006] An embodiment of the present disclosure is a semiconductor device comprising: a base portion having at least an upper surface made of metal; one or more components including a semiconductor chip mounted on the base portion with a first conductive member sandwiched therebetween; a second conductive member provided on the base portion, comprising sintered metal or a resin containing metal powder, and not carrying the one or more components; and a resin sealing portion on the base portion that contacts the base portion, the one or more components, and the second conductive member and seals the one or more components, wherein the second conductive member is separated from the first conductive member.

[0007] An embodiment of the present disclosure is a semiconductor device comprising: a base portion having at least a metal upper surface; one or more components including a semiconductor chip mounted on the base portion with a first conductive member sandwiched therebetween; a second conductive member provided on the base portion, comprising sintered metal or a resin containing metal powder, and not carrying the one or more components; and a resin sealing portion on the base portion that contacts the base portion, the one or more components, and the second conductive member and seals the one or more components, wherein the second conductive member is connected to the first conductive member and is separated from the one or more components by a distance equal to or greater than the sum of the thickness of the first conductive member between the semiconductor chip and the base portion and the thickness of the semiconductor chip.

[0008] An embodiment of the present disclosure is a method for manufacturing a semiconductor device, comprising: a step of forming a first conductive member and a second conductive member on a base portion having at least a metal upper surface; a step of, after the step of forming the first conductive member and the second conductive member, mounting one or more components including a semiconductor chip on the first conductive member while not mounting the one or more components on the second conductive member; and a step of forming a resin sealing portion on the base portion that contacts the base portion, the one or more components, and the second conductive member and seals the one or more components, wherein the second conductive member is separated from the first conductive member or is connected to the first conductive member and is separated from the one or more components by a distance equal to or greater than the sum of the thickness of the first conductive member between the semiconductor chip and the base portion and the thickness of the semiconductor chip. [Effects of the Invention]

[0009] According to the present disclosure, the adhesion between the base portion and the resin sealing portion can be improved. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 3 is a flowchart showing the manufacturing method of the first embodiment. [Figure 4A] FIG. 4A is a plan view of the conductive member 18 in the first embodiment. [Figure 4B] FIG. 4B is a plan view of the conductive member 18 in the first embodiment. [Figure 4C] FIG. 4C is a plan view of the conductive member 18 in the first embodiment. [Figure 5A] FIG. 5A is a cross-sectional view of the conductive member 18 in the first embodiment. [Figure 5B] FIG. 5B is a cross-sectional view of the conductive member 18 in the first embodiment. [Figure 5C]FIG. 5C is a cross-sectional view of the conductive member 18 in the first embodiment. [Figure 6A] FIG. 6A is a plan view showing another example of the conductive member 18 in the first embodiment. [Figure 6B] FIG. 6B is a cross-sectional view taken along line AA in FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view taken along line AA in FIG. 6A. [Figure 7A] FIG. 7A is a plan view showing yet another example of the conductive member 18 in the first embodiment. [Figure 7B] FIG. 7B is a cross-sectional view taken along line AA in FIG. 7A. [Figure 8] FIG. 8 is a plan view of the semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view taken along line AA in FIG. [Figure 10] FIG. 10 is a circuit diagram of the paths 50 and 52 in the second embodiment. [Figure 11] FIG. 11 is a plan view of a semiconductor device according to a first modification of the second embodiment. [Figure 12] FIG. 12 is a plan view of a semiconductor device according to a second modification of the second embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor device according to a third modification of the second embodiment. [Figure 14] FIG. 14 is a plan view of a semiconductor device according to a fourth modification of the second embodiment. [Figure 15] FIG. 15 is a circuit diagram of paths 50 and 52 in a fourth modified example of the second embodiment. [Figure 16] FIG. 16 is a plan view of a semiconductor device according to a fifth modification of the second embodiment. [Figure 17] FIG. 17 is a circuit diagram of paths 50 and 52 in a fifth modified example of the second embodiment. [Figure 18] FIG. 18 is a plan view of a semiconductor device according to a sixth modification of the second embodiment. [Figure 19] FIG. 19 is a circuit diagram of paths 50 and 52 in a sixth modified example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0012] (1) An embodiment of the present disclosure is a semiconductor device comprising: a base portion having at least a metal upper surface; one or more components including a semiconductor chip mounted on the base portion with a first conductive member sandwiched therebetween; a second conductive member provided on the base portion, comprising a sintered metal or a resin containing metal powder, on which the one or more components are not mounted; and a resin sealing portion on the base portion, in contact with the base portion, the one or more components, and the second conductive member, and sealing the one or more components, wherein the second conductive member is separated from the first conductive member. This improves adhesion between the base portion and the resin sealing portion. (2) An embodiment of the present disclosure includes a base portion having at least a metal top surface, one or more components including a semiconductor chip mounted on the base portion with a first conductive member sandwiched therebetween, a second conductive member provided on the base portion and including a sintered metal or a resin containing metal powder, on which the one or more components are not mounted, and a resin sealing portion on the base portion that contacts the base portion, the one or more components, and the second conductive member and seals the one or more components, wherein the second conductive member is connected to the first conductive member and is separated from the one or more components by at least the sum of the thickness of the first conductive member between the semiconductor chip and the base portion and the thickness of the semiconductor chip, thereby improving adhesion between the base portion and the resin sealing portion. (3) In the above (1) or (2), the first conductive member and the second conductive member may be made of the same material, thereby reducing the number of types of conductive members. (4) In any of (1) to (3) above, when viewed in the thickness direction of the base, at least a portion of the second conductive member may overlap a bonding wire having a first end connected to one of the one or more components, thereby improving adhesion between the base and the resin-sealed portion in areas where adhesion is weak. (5) In any one of (1) to (3) above, the device may include an input lead for inputting a high-frequency signal and an output lead for outputting a high-frequency signal, wherein the one or more components are provided between the input lead and the output lead, and the length of at least one bonding wire among a plurality of bonding wires provided in a path electrically connecting the input lead and the output lead, as viewed in the thickness direction of the base, may be greater than any of the lengths of the input leads and the output leads of the one or more components in a first direction in which they are arranged, and at least a portion of the second conductive member may overlap the at least one bonding wire as viewed in the thickness direction of the base, thereby improving adhesion between the base and the resin-sealed portion in a location where adhesion is weak. (6) In any one of (1) to (3) above, the device may include an input lead for inputting a high-frequency signal and an output lead for outputting a high-frequency signal, wherein the one or more components are provided between the input lead and the output lead, and the length of at least one bonding wire among a plurality of bonding wires provided in a path electrically connecting the input lead and the output lead, as viewed in the thickness direction of the base, may be greater than both lengths in a first direction in which the input leads and the output leads of the one or more components are arranged, and at least a portion of the second conductive member may be located from the at least one bonding wire in a second direction perpendicular to the first direction and the thickness direction of the base, thereby improving adhesion between the base and the resin-sealed portion in a location where adhesion would be weak. (7) In the above (6), a plurality of paths may be provided, each including the input lead, the output lead, the one or more components, and a plurality of bonding wires provided on the paths, and at least a portion of the second conductive member may be provided between the at least one bonding wire of adjacent paths among the plurality of paths. This improves adhesion between the base portion and the resin sealing portion in areas where adhesion is weak. (8) In any of the above (5) to (7), the semiconductor chip may have a transistor that amplifies a high-frequency signal input to the input lead and outputs the amplified high-frequency signal to the output lead, and the at least one bonding wire may be included in a matching circuit that matches impedance between the input lead and the transistor or a matching circuit that matches impedance between the transistor and the output lead, thereby improving adhesion between the base and the resin sealing portion in areas where adhesion is weak. (9) In any one of the above (1) to (8), the second conductive member may have a constriction in a cross section parallel to the thickness direction of the base portion, thereby further improving adhesion between the base portion and the resin sealing portion. (10) In any one of the above (1) to (8), the second conductive member may have a first portion extending on the base in a third direction, and a second portion extending on the base in a fourth direction intersecting the third direction and provided between the first portion and the base at a location where the second conductive member intersects with the first portion, thereby further improving adhesion between the base and the resin sealing portion. (11) An embodiment of the present disclosure is a method for manufacturing a semiconductor device, comprising: forming a first conductive member and a second conductive member on a base portion having at least a metal upper surface; after the forming of the first conductive member and the second conductive member, mounting one or more components including a semiconductor chip on the first conductive member while not mounting the one or more components on the second conductive member; and forming a resin encapsulation portion on the base portion, the resin encapsulation portion contacting the base portion, the one or more components, and the second conductive member and encapsulating the one or more components, wherein the second conductive member is separated from the first conductive member or connected to the first conductive member and is separated from the one or more components by at least the sum of the thickness of the first conductive member between the semiconductor chip and the base portion and the thickness of the semiconductor chip. This easily improves adhesion between the base portion and the resin encapsulation portion.

[0013] [Details of the embodiments of the present disclosure] Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0014] (Semiconductor device of the first embodiment) The first embodiment is an example in which a semiconductor chip is mounted as a single component on a base portion. Fig. 1 is a plan view of the semiconductor device according to the first embodiment. Fig. 1 shows a perspective view of a resin sealing portion 14. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. The thickness direction of the base portion 12 is the Z direction, the arrangement direction of the leads 15A and 15B is the X direction, and the direction perpendicular to the X direction and the Z direction is the Y direction.

[0015] 1 and 2, the semiconductor device 100 according to the first embodiment includes a base portion 12, a resin sealing portion 14, leads 15A and 15B, a conductive member 16, conductive members 18A and 18B, a semiconductor chip 20, and bonding wires 31 and 33.

[0016] The base portion 12 functions, for example, as a heat spreader that diffuses heat generated in the semiconductor chip 20. At least the top surface of the base portion 12 is made of metal. The semiconductor chip 20 is mounted on the base portion 12 with a conductive member 16 sandwiched therebetween. The semiconductor chip 20 includes a substrate 21 and electrodes 22, 23, and 24. The electrodes 22 and 23 are provided on the substrate 21, and the electrode 24 is provided below the substrate 21. The conductive member 16 joins the base portion 12 and the electrode 24.

[0017] The resin sealing portion 14 is on the base portion 12 and is in contact with the base portion 12, the semiconductor chip 20, and the conductive members 18A and 18B, sealing the semiconductor chip 20. The lower surface of the base portion 12 is exposed from the resin sealing portion 14. The lower surface of the base portion 12 may be covered by the resin sealing portion 14. First ends of the leads 15A and 15B are provided within the resin sealing portion 14, and second ends of the leads 15A and 15B are exposed from the resin sealing portion 14. The bonding wire 31 electrically connects the electrode 22 to the first end of the lead 15A. The bonding wire 33 electrically connects the electrode 23 to the first end of the lead 15B. The conductive members 18A and 18B are provided on the base portion 12, and no components such as the semiconductor chip 20 are mounted on the base portion 12. The conductive member 18A is provided between the bonding wires 31 and 33 and the base portion 12 so as to overlap with the bonding wire 31 when viewed from the Z direction. Two conductive members 18B sandwich bonding wire 31 in the Y direction, and another two conductive members 18B sandwich bonding wire 33 in the Y direction.

[0018] The material of the base portion 12 is, for example, copper, a copper-based alloy, a laminate material containing copper (for example, a copper layer, a molybdenum layer and a copper layer), aluminum, or an aluminum alloy. The surface of the base portion 12 may be plated with gold, for example. The material of the leads 15A and 15B is a metal such as copper, a copper-based alloy, or an iron-based alloy. The material of the bonding wires 31 and 33 is, for example, gold, silver, copper, aluminum, or an alloy mainly containing any of these. The material of the resin sealing portion 14 is, for example, an epoxy resin containing a filler. The filler is, for example, an inorganic insulator filler such as silicon oxide.

[0019] The material of the conductive member 16 is, for example, sintered metal, resin containing metal powder, or solder such as gold-tin (AuSn) or gold-silicon (AuSi). The material of the conductive members 18A and 18B is, for example, sintered metal or resin containing metal powder. Sintered metal is made by sintering a paste containing metal powder such as silver, copper, or gold. The components of sintered metal are mostly silver, copper, or gold. Metal powder-containing resin is made by hardening a resin containing metal powder. The metal powder is, for example, silver, copper, or gold. The resin is, for example, epoxy resin. The content of metal powder in the metal powder-containing resin is, for example, 50% by mass or more and 95% by mass or less, and as another example, 70% by mass or more and 90% by mass or less.

[0020] The semiconductor chip 20 includes, for example, a transistor. The transistor is, for example, a Laterally Diffused Metal Oxide Semiconductor (LDMOS) or a Gallium Nitride High Electron Transistor (GaN-HEMT). The transistor may also be a MOSFET (MOS Field Effect Transistor) or a bipolar transistor.

[0021] The substrate 21 is, for example, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a gallium arsenide substrate. The electrodes 22 to 24 include, for example, gold, aluminum, copper, silver, or nickel.

[0022] (Manufacturing method of the first embodiment) 3 is a flowchart showing the manufacturing method of the first embodiment. As shown in FIG. 3, a lead frame is formed (step S10). The lead frame includes a base portion 12 and leads 15A and 15B. The leads 15A and 15B connect the multiple base portions 12. Next, the lead frame is plated (step S11). In the plating process, a metal such as gold that has good wettability with the conductive member 16 is plated. A plating film is provided on the lead frame.

[0023] Next, the conductive members 16, 18A, and 18B are applied onto the base portion 12 (step S12). For example, a solution containing the conductive members 16, 18A, and 18B is contained in a tube, and the solution is discharged in a linear form from the tube.

[0024] Next, the semiconductor chip 20 is mounted on the conductive member 16 (step S14). Next, the conductive members 16, 18A, and 18B are hardened (step S15). For example, by heat treating the base portion 12, the solvent containing the conductive members 16, 18A, and 18B evaporates, and the conductive members 16, 18A, and 18B harden. This fixes the semiconductor chip 20 onto the base portion 12.

[0025] Next, bonding wires 31 and 33 are formed (step S16). For example, the first and second ends of bonding wire 31 are bonded to electrode 22 and lead 15A, respectively, and the first and second ends of bonding wire 33 are bonded to electrode 23 and lead 15B, respectively. Next, resin sealing portion 14 is formed (step S17). Resin sealing portion 14 is formed using, for example, a transfer molding method.

[0026] Next, plating is performed on the portions of the base portion 12 and the leads 15A and 15B exposed from the resin sealing portion 14 (step S18). For example, tin or solder is plated on the lower surface of the base portion 12 and the surfaces of the leads 15A and 15B exposed from the resin sealing portion 14. Next, the leads 15A and 15B are cut to separate the semiconductor device 100 (step S19). In this way, the semiconductor device 100 according to the first embodiment is manufactured.

[0027] (Description of the First Embodiment) Since the semiconductor chip 20 is mounted using the conductive member 16, at least the top layer of the base portion 12 is a metal layer. The surface of the base portion 12 may be gold-plated to improve the wettability of the conductive member 16. Because the top surface of the base portion 12 is metal, the adhesion between the base portion 12 and the resin sealing portion 14 is weak. For this reason, in FIG. 1 , in an area 54 on the base portion 12 where the semiconductor chip 20 and other components are not mounted, the resin sealing portion 14 may peel off from the base portion 12 due to thermal stress caused by the difference in the linear expansion coefficient between the base portion 12 and the resin sealing portion 14.

[0028] One way to prevent the resin sealing portion 14 from peeling off from the base portion 12 is to reduce the exposed area of ​​the surface of the base portion 12. However, for example, when the bonding wires 31 and 33 are lengthened, this reduces the degree of freedom in arranging the semiconductor chip 20. Another way is to roughen the surface of the base portion 12, as in Patent Document 1. However, this requires an additional step to roughen the surface of the base portion 12. Furthermore, if the surface roughness of the roughened surface is increased in order to improve adhesion, it becomes difficult to mount the semiconductor chip 20.

[0029] It is possible to roughen the area of ​​the top surface of the base portion 12 where the semiconductor chip 20 is not mounted, without roughening the area where the semiconductor chip 20 is mounted. However, for example, if the top surface of the base portion 12 is partially roughened before step S12 in Fig. 3, the degree of freedom in arranging the semiconductor chip 20 is reduced. Furthermore, if the top surface of the base portion 12 is partially roughened after step S15 in Fig. 3, the number of roughening steps increases, and furthermore, debris is generated due to the roughening.

[0030] If the plating film on the base portion 12 reduces the adhesion between the resin sealing portion 14 and the base portion 12, it is possible to plate the area of ​​the top surface of the base portion 12 where the semiconductor chip 20 is to be mounted, and not plate the area where the semiconductor chip 20 is not to be mounted, in step S11. However, the wettability of the conductive member 16 is poor in the unplated area, making it impossible to mount the semiconductor chip 20. This reduces the degree of freedom in arranging the semiconductor chip 20.

[0031] In the first embodiment, in the method for manufacturing the semiconductor device 100, conductive members 16, 18A, and 18B are formed on the base portion 12 as in step S12. Thereafter, as in step S14, the semiconductor chip 20 is mounted on the conductive member 16 (first conductive member), and no components are mounted on the conductive members 18A and 18B (second conductive members). As in step S15, a resin sealing portion 14 is formed on the base portion 12, in contact with the base portion 12, the semiconductor chip 20, and the conductive members 18A and 18B, and sealing the semiconductor chip 20.

[0032] In the semiconductor device 100, the provision of the conductive members 18A and 18B improves the adhesion between the resin sealing portion 14 and the base portion 12. The conductive members 18A and 18B contain sintered metal or a resin containing metal powder. This allows the conductive members 18A and 18B to be easily provided in areas of the top surface of the base portion 12 where the semiconductor chip 20 is not mounted. Furthermore, as in step S12 of FIG. 3, the conductive members 18A and 18B can be formed in the same process as the conductive member 16. As in step S14, the conductive members 18A and 18B can be cured in the same process as the curing of the conductive member 16. This simplifies the manufacturing process. Furthermore, since the conductive members 18A and 18B can be formed in areas where the semiconductor chip 20 is not mounted, the degree of freedom in arranging the semiconductor chip 20 can be improved.

[0033] The material of the conductive member 16 and the materials of the conductive members 18A and 18B may be the same or different. By using the same material for the conductive member 16 and the conductive members 18A and 18B, the conductive member 16 and the conductive members 18A and 18B can be formed using the same material in step S12. This allows the number of types of conductive members to be reduced.

[0034] From the viewpoint of preventing peeling of the resin sealing portion 14 from the base portion 12, the conductive members 18A and 18B can be provided in an area 54 where the semiconductor chip 20 and other components are not provided. For example, components are often not provided in the area of ​​the bonding wires 31 and 33 whose first ends are connected to the semiconductor chip 20. Therefore, like the conductive member 18A, at least a portion of the conductive member 18A can be disposed between the bonding wires 31 and 33 and the base portion 12.

[0035] 4A to 4C are plan views of the conductive member 18 in the first embodiment. As in FIG. 4A, the conductive member 18 may have a dotted planar shape. As in FIG. 4B, the conductive member 18 may have a planar shape of connected dots. As in FIG. 4C, the conductive member 18 may have a linear planar shape. In step S12, when forming the conductive member 18 by discharging a highly viscous solution containing the conductive member 18 from a tube, the conductive member 18 having the planar shape shown in FIGS. 4A to 4C can be formed by controlling the pressure with which the tube is pressed.

[0036] 5A to 5C are cross-sectional views of the conductive member 18 in the first embodiment. FIGS. 5A to 5C are cross-sectional views taken along line AA in FIGS. 4A to 4C. As shown in FIG. 5A, the cross-sectional shape of the conductive member 18 may be a semicircle or a partial ellipse. For example, when a highly viscous solution containing the conductive member 18 is discharged from a tube from a position near the base portion 12, the conductive member 18 will have a cross-sectional shape as shown in FIG. 5A.

[0037] 5B, the cross-sectional shape of the conductive member 18 may be a shape in which a circle or an ellipse is connected to a semicircle or semiellipse. For example, when a highly viscous solution containing the conductive member 18 is discharged from a tube from a position away from the base portion 12 in the Z direction, the conductive member 18 has a cross-sectional shape as shown in FIG.

[0038] As shown in Fig. 5C, the cross-sectional shape of the conductive member 18 may be a shape in which a circle or an ellipse is connected to the circle or ellipse in Fig. 5B. As shown in Figs. 5B and 5C, the conductive member 18 has constrictions 40 in a cross section parallel to the Z direction. This makes it more difficult for the resin sealing portion 14 to peel off from the base portion 12. By providing a plurality of constrictions 40 in the Z direction, it becomes more difficult for the resin sealing portion 14 to peel off from the base portion 12.

[0039] 5B and 5C, if the width of the constriction 40 is W2 and the maximum width of the conductive member 18 above the constriction 40 is W1, then width W2 is smaller than width W1. When the resin sealing portion 14 comes into contact with the constriction 40, the resin sealing portion 14 is less likely to peel off from the base portion 12. Width W2 may be 0.9 times or less than width W1. From the viewpoint of preventing the conductive member 18 from being separated in the Z direction by the constriction 18, width W2 may be 0.1 times or more than width W1.

[0040] FIG. 6A is a plan view showing another example of the conductive member 18 in the first embodiment. FIGS. 6B and 6C are cross-sectional views taken along the line AA in FIG. 6A. As shown in FIG. 6A, the conductive member 18 has linear portions 42A (first portion) and 42B (second portion) when viewed from the Z direction. The portion 42A extends along the base portion 12 in the X direction (third direction). The portion 42B extends along the base portion 12 in the Y direction (fourth direction intersecting with the third direction) and is provided between the portion 42A and the base portion 12 at the intersection with the portion 42A. This results in a complex shape of the conductive member 18 at the intersection between the portions 42A and 42B. For example, a space 43 is formed between the portions 42A and 42B. The resin sealing portion 14 comes into contact with the complex shape, making it more difficult for the resin sealing portion 14 to peel off from the base portion 12.

[0041] As shown in FIG. 6C, the conductive member 18 has portions 42A to 42D. When viewed from the Z direction, portion 42C overlaps portion 42A, and portion 42D overlaps portion 42B. Portion 42C is provided between portion 42B and the base portion 12, and portion 42D is provided between portion 42C and the base portion 12. This makes the shape of the conductive member 18 at the intersections between portions 42A and 42C and portions 42B and 42D more complex than in FIG. 6B. For example, more spaces 43 are formed than in FIG. 6B. This makes it more difficult for the resin sealing portion 14 to peel off from the base portion 12 because the resin sealing portion 14 comes into contact with the complex shape.

[0042] FIG. 7A is a plan view showing yet another example of the conductive member 18 in the first embodiment. FIG. 7B is a cross-sectional view taken along line AA in FIG. 7A. As shown in FIG. 7A, the conductive member 18 has linear portions 42A, 42B, and 42F. The portion 42F extends substantially parallel to the portion 42B and is provided between the portion 42A and the base portion 12 at the point where the portion 42F intersects with the portion 42A. In this manner, there may be multiple portions 42B and 42F intersecting with the portion 42A. This results in multiple points where the portion 42A intersects with the portions 42B and 42F. This results in a complex shape of the conductive member 18. For example, a space 43 is formed between the portions 42A and 42B and 42F. The resin sealing portion 14 comes into contact with the complex shape, making it more difficult for the resin sealing portion 14 to peel off from the base portion 12. Although an example has been described in which the portions 42A to 42D and 42F are linear when viewed in the Z direction, the portions 42A to 42D and 42F may be curved when viewed in the Z direction.

[0043] (Second embodiment) The second embodiment is an example in which one or more components mounted on the base portion 12 include a semiconductor chip that handles high-frequency signals. Fig. 8 is a plan view of the semiconductor device according to the second embodiment. Fig. 9 is a cross-sectional view taken along line AA in Fig. 8. Fig. 10 is a circuit diagram of paths 50 and 52 in the second embodiment.

[0044] 8 and 9, the semiconductor device 102 has two paths 50 and 52. Each of the paths 50 and 52 has a semiconductor chip 20, a passive chip 25, bonding wires 31 to 33, and leads 15A and 15B. The passive chip 25 and the semiconductor chip 20 are arranged in the X direction between the leads 15A and 15B.

[0045] The semiconductor chip 20 includes a substrate 21 and electrodes 22 to 24. Electrodes 22 and 23 are provided on the substrate 21, and electrode 24 is provided below the substrate 21. The passive chip 25 includes a substrate 26 and electrodes 27 and 28. Electrode 27 is provided on the substrate 26, and electrode 28 is provided below the substrate 26. Electrodes 24 and 28 are bonded to the base 12 with a conductive member 16 sandwiched therebetween. As a result, the base 12 is electrically connected to and short-circuited with electrodes 24 and 28 via the conductive member 16. The substrate 26 is a dielectric substrate made of, for example, alumina or barium titanate. The substrate 26 and the electrodes 27 and 28 sandwiching the substrate 26 function as a capacitor.

[0046] Bonding wire 31 electrically connects lead 15A and electrode 27. Bonding wire 32 electrically connects electrodes 27 and 22. Bonding wire 33 electrically connects electrode 23 and lead 15B.

[0047] Conductive member 18A is provided between bonding wire 31 and base portion 12 in the Z direction. Conductive member 18B is provided between bonding wire 31 of path 50 and bonding wire 31 of path 52. Conductive members 18C and 18B are provided to sandwich bonding wire 31 of path 50 and to sandwich bonding wire 31 of path 52. Conductive member 18D is provided between a region of path 50 other than bonding wire 31 and a region of path 52 other than bonding wire 31. Conductive members 18D and 18E are provided to sandwich a region of path 50 other than bonding wire 31 and to sandwich a region of path 52 other than bonding wire 31.

[0048] 10, paths 50 and 52 include an input terminal Tin, an output terminal Tout, an inductor L1, a capacitor C1, and a transistor Q1. A first end of the inductor L1 is electrically connected to a node N1, and a second end of the inductor L1 is electrically connected to the input terminal Tin. A first end of the capacitor C1 is electrically connected to the node N1, and a second end of the capacitor C1 is electrically connected to a reference potential such as ground. The transistor Q1 is an FET, and its source S is electrically connected to the reference potential and its gate G is electrically connected to the node N1. Its drain D is electrically connected to the output terminal Tout.

[0049] The matching circuit 44 is a low-pass filter type matching circuit and includes an inductor L1 and a capacitor C1. The matching circuit 44 matches the impedance seen from the input terminal Tin to the impedance seen from the matching circuit 44 to the impedance seen from the matching circuit 44 to the transistor Q1. A high-frequency signal input to the input terminal Tin is input to the gate G of the transistor Q1 via the matching circuit 44. The high-frequency signal amplified by the transistor Q1 is output from the drain D to the output terminal Tout. For example, when the semiconductor device 102 is used in a base station for mobile communications, the frequency of the high-frequency signal is 0.5 GHz or higher and 20 GHz or lower.

[0050] The input terminal Tin and the output terminal Tout in FIG. 10 correspond to the leads 15A and 15B in FIGS. 8 and 9, respectively. The inductor L1 in FIG. 10 corresponds to the bonding wire 31 in FIGS. 8 and 9. The capacitor C1 in FIG. 10 corresponds to the passive chip 25 in FIGS. 8 and 9. The transistor Q1 in FIG. 10 corresponds to the semiconductor chip 20 in FIGS. 8 and 9. The gate G, the drain D1, and the source S correspond to the electrodes 22, 23, and 24 in FIG. 9, respectively. The reference potential in FIG. 10 corresponds to the base portion 12 in FIGS. 8 and 9.

[0051] As shown in FIGS. 8 to 10 , when the matching circuit 44 is provided within the semiconductor device 102, the bonding wire 31 is required to function as an inductor L1, resulting in a longer bonding wire 31. For example, the length D1 of the bonding wire 31 as viewed in the Z direction is greater than the width D2 of the semiconductor chip 20 in the X direction and the width D3 of the passive chip 25 in the X direction. In such a case, no other components are mounted in the region 54 between the lead 15A and the passive chip 25, resulting in a larger region 54 where no components are mounted. Therefore, conductive members 18A to 18C are provided. Furthermore, when the paths 50 and 52 are far apart, conductive member 18D is provided. When the paths 50 and 52 are far apart from the ends of the base portion 12, conductive member 18E is provided. This prevents the resin sealing portion 14 from peeling off from the base portion 12.

[0052] (First modified example of the second embodiment) 11 is a plan view of a semiconductor device according to a first modification of the second embodiment. As shown in FIG. 11, a semiconductor device 103 according to the first modification of the second embodiment does not include a conductive member 18A. If a conductive member 18A is provided, the high-frequency characteristics of the bonding wire 31 may change. In such a case, the conductive member 18A may not be provided. The other configurations are the same as those of the second embodiment, and a description thereof will be omitted.

[0053] (Second Modification of the Second Embodiment) 12 is a plan view of a semiconductor device according to a second modification of the second embodiment. As shown in FIG. 12, in a semiconductor device 104 according to the second modification of the second embodiment, conductive member 18F is connected to conductive member 16 on which semiconductor chip 20 is mounted on path 52. Conductive member 18G is connected to conductive member 16 on which semiconductor chip 20 is mounted on path 50. Conductive member 18F extends to the outside of passive chip 25 and bonding wire 31 in the positive Y direction. Conductive member 18G extends to the outside of passive chip 25 and bonding wire 31 in the negative Y direction, and further extends to between bonding wire 31 and base portion 12 in the Z direction.

[0054] The conductive members 18F and 18G can be formed by continuously discharging the solution from the tube from the conductive member 16 in step S12 of FIG. 3 . In FIG. 9 , the total thickness of the conductive member 16 between the semiconductor chip 20 and the base portion 12 and the thickness of the semiconductor chip 20 is Tc. When the semiconductor chip 20 and the passive chip 25 are mounted using the conductive member 16, the amount of the conductive member 16 protruding from the semiconductor chip 20 and the passive chip 25 is less than the thickness Tc. Therefore, the distance D4 between the conductive members 18F and 18G and the semiconductor chip 20 is set to be equal to or greater than the thickness Tc. The conductive member 18F is provided in place of the conductive members 18C and 18E of the second embodiment. The conductive member 18G is provided in place of the conductive members 18A, 18C, and 18E of the second embodiment. The other configurations are the same as those of the second embodiment, and therefore, description thereof will be omitted.

[0055] (Third modified example of the second embodiment) FIG. 13 is a plan view of a semiconductor device according to a third modification of the second embodiment. As shown in FIG. 13, in a semiconductor device 105 according to the third modification of the second embodiment, a conductive member 18H is provided between the conductive member 16 on which the semiconductor chip 20 of the path 50 is mounted and the conductive member 16 on which the semiconductor chip 20 of the path 52 is mounted. Another conductive member 18H is provided between the conductive member 16 on which the passive chip 25 of the path 50 is mounted and the conductive member 16 on which the passive chip 25 of the path 52 is mounted. A distance D4 between the conductive member 18H and the semiconductor chip 20 and the passive chip 25 is equal to or greater than the thickness Tc. The conductive member 18H is provided in place of the conductive member 18D of the second embodiment. The other configurations are the same as those of the second embodiment, and therefore a description thereof will be omitted.

[0056] As in the second and third modifications of the second embodiment, the conductive members 18F to 18H are connected to the conductive member 16 and are spaced apart from the semiconductor chip 20 and the passive chip 25 by a distance equal to or greater than the thickness Tc. This allows the conductive members 18F to 18H to be formed by discharging the solution that will form the conductive members 18F to 18H continuously with the solution that will form the conductive member 16 in step S12 of FIG. 3. The distance D4 may be 1.5 mm or greater, or 2 mm or greater. The distance D4 may be 1.5 times or greater than the thickness Tc, or may be 2 times or greater. If the distance D4 is too long, the base portion 12 will become large. From this perspective, the distance D4 may be 5 mm or less. The distance D4 may be 5 times or less than the thickness Tc. (Fourth Modification of the Second Embodiment) Fig. 14 is a plan view of a semiconductor device according to a fourth modified example of the second embodiment. Fig. 15 is a circuit diagram of paths 50 and 52 in the fourth modified example of the second embodiment. As shown in Fig. 14, the semiconductor device 106 according to the fourth modified example of the second embodiment does not include a passive chip 25. The bonding wire 31 electrically connects the lead 15A and the electrode 22.

[0057] As shown in FIG. 15 , the paths 50 and 52 of the semiconductor device 106 do not include matching circuits. For example, if the frequency of the high-frequency signal is between 1 MHz and 1 GHz, a matching circuit for matching impedance may not be provided within the semiconductor device 106. Reducing the planar area of ​​the base portion 12 reduces heat dissipation, so increasing the area of ​​the base portion 12 lengthens the bonding wire 31. While the bonding wire 33 may be lengthened, the bonding wire 33 outputting the amplified high-frequency signal may be shortened to improve high-frequency characteristics. Therefore, the region 54 between the lead 15A and the semiconductor chip 20 in FIG. 14 becomes wider. Therefore, 18A to 18C are provided in the region 54. The other configurations are the same as those of the second embodiment, and therefore a description thereof will be omitted.

[0058] (Fifth Modification of the Second Embodiment) Fig. 16 is a plan view of a semiconductor device according to a fifth modified example of the second embodiment. Fig. 17 is a circuit diagram of paths 50 and 52 according to the fifth modified example of the second embodiment. As shown in Fig. 16, in a semiconductor device 108 according to the fifth modified example of the second embodiment, the bonding wire 33 is longer than the bonding wire 31. The conductive member 18A is provided between the bonding wire 33 and the base portion 12. The conductive member 18B is provided between the bonding wire 33 of the path 50 and the bonding wire 33 of the path 52 in the Y direction. The conductive members 18B and 18C sandwich the bonding wire 33 in the Y direction.

[0059] As shown in FIG. 17, the paths 50 and 52 of the semiconductor device 108 include an input terminal Tin, an output terminal Tout, a capacitor C1, an inductor L2, and a transistor Q1. A node N1 is electrically connected to the input terminal Tin. A first end of the inductor L2 is connected to the drain of the transistor Q1, and a second end of the inductor L2 is electrically connected to the output terminal Tout. Outside the semiconductor device 108, a capacitor C2 is shunt-connected to the output terminal Tout. The matching circuit 45 includes an inductor L2 and a capacitor C2. The matching circuit 45 matches the impedance seen from the drain D toward the matching circuit 45 with the impedance seen from the matching circuit 45 toward the downstream side. The inductor L2 in FIG. 17 corresponds to the bonding wire 33 in FIG. 16. The bonding wire 33 is lengthened to increase the inductance of the inductor L2. This widens the region 54 between the semiconductor chip 20 and the lead 15B in FIG. 16. Therefore, conductive members 18A to 18C are provided in the region 54. The other configurations are the same as those of the second embodiment.

[0060] (Sixth Modification of the Second Embodiment) FIG. 18 is a plan view of a semiconductor device according to a sixth modified example of the second embodiment. FIG. 19 is a circuit diagram of paths 50 and 52 in the sixth modified example of the second embodiment. As shown in FIG. 18, in a semiconductor device 110 according to the sixth modified example of the second embodiment, a passive chip 25A is mounted on the base portion 12 between the semiconductor chip 20 and the lead 15B in the X direction, with a conductive member 16 sandwiched between them, along the paths 50 and 52. The passive chip 25A includes a substrate 26 and electrodes 27 and 28, and has the same structure as the passive chip 25. A bonding wire 33 electrically connects the electrode 23 of the semiconductor chip 20 to the electrode 27 of the passive chip 25A. A bonding wire 34 electrically connects the electrode 27 of the passive chip 25A to the lead 15B.

[0061] As shown in FIG. 19, the paths 50 and 52 of the semiconductor device 110 include a capacitor C2. The first end of the capacitor C2 is electrically connected to the node N2, and the second end is electrically connected to the reference potential. The first end of the inductor L2 is electrically connected to the drain D, and the second end is electrically connected to the node N2. The node N2 is electrically connected to the output terminal Tout. The capacitor C2 in FIG. 19 corresponds to the passive chip 25A in FIG. 18. As described above, in the sixth modification of the second embodiment, the external capacitor C2 in the fifth modification of the second embodiment is provided inside the semiconductor device 110. The bonding wire 33 corresponding to the inductor L2 in FIG. 18 is lengthened. Therefore, the region 54 between the semiconductor chip 20 and the passive chip 25A is widened. Therefore, conductive members 18A to 18C are provided in the region 54. The other configurations are the same as those in the fifth modification of the second embodiment.

[0062] In a semiconductor device that handles high-frequency signals, as in the second embodiment and its modified examples, one or more components, such as a semiconductor chip 20 and passive chips 25 and 25A, are provided between a lead 15A (input lead) that inputs a high-frequency signal and a lead 15B (output lead) that outputs a high-frequency signal. Multiple bonding wires 31 to 34 are provided along paths 50 and 52 that electrically connect the leads 15A and 15B. As shown in FIG. 8 , the length D1 of at least one bonding wire 31 among the bonding wires 31 to 33 as viewed in the Z direction is greater than both the length D2 of the semiconductor chip 20 in the X direction (the direction in which the leads 15A and 25B are arranged) and the length D3 of the passive chip 25 in the Y direction. In such a case, the region 54 becomes wider in the X direction, making the resin encapsulation portion 14 more likely to peel off from the base portion 12. Therefore, a conductive member 18A is provided between the bonding wire 31 and the base portion 12. This prevents the resin encapsulation portion 14 from peeling off from the base portion 12.

[0063] The conductive members 18B and 18C are positioned in the Y direction (a second direction perpendicular to the first direction and the thickness direction of the base portion) from the bonding wire 31. This prevents the resin sealing portion 14 from peeling off from the base portion 12. The length D1 of the bonding wire 31 may be 1.5 times or more, or even twice or more, the lengths D2 and D3. The length D1 may be 10 times or less the lengths D2 and D3.

[0064] A plurality of paths 50 and 52 are provided, each including leads 15A, 15B, a semiconductor chip 20, a passive chip 25, and bonding wires 31 to 33. In this case, no components are mounted near the area between the bonding wire 31 of path 50 and the bonding wire 31 of path 52. This makes it easier for the resin encapsulation portion 14 to peel off from the base portion 12. Therefore, a conductive member 18B is provided between the bonding wires 31 of adjacent paths 50 and 52 among the plurality of paths. This makes it possible to prevent the resin encapsulation portion 14 from peeling off from the base portion 12.

[0065] The semiconductor chip 20 has a transistor Q1 that amplifies a high-frequency signal input to the lead 15A and outputs the amplified high-frequency signal to the lead 15B. In this case, as in the second embodiment, the inductance of the inductor L1 of the matching circuit 44 that matches the impedance between the lead 15A and the transistor Q1 becomes large. Therefore, the bonding wire 31 corresponding to the inductor L1 becomes long. Therefore, the region 54 becomes wide. Therefore, by providing at least one of the conductive members 18A to 18C, peeling of the resin sealing portion 14 from the base portion 12 can be prevented.

[0066] As in the fifth and sixth modifications of the second embodiment, the inductance of the inductor L2 included in the matching circuit 45 that matches the impedance between the transistor Q1 and the lead 15B becomes large. Therefore, the bonding wire 33 corresponding to the inductor L2 becomes long. Therefore, the region 54 becomes wide. Therefore, by providing at least one of the conductive members 18A to 18C, it is possible to prevent the resin sealing portion 14 from peeling off from the base portion 12.

[0067] In the second embodiment and its modified example, an example in which there are two paths 50 and 52 has been described, but there may be one path, or three or more paths.

[0068] From the viewpoint of improving the adhesion between the resin sealing portion 14 and the base portion 12, the maximum width in the X direction and the maximum width in the Y direction of the conductive members 18A to 18G can be 0.1 mm or more, and can be 0.2 mm or more. From the viewpoint of reducing the number of conductive members 18, the maximum width in the X direction and the maximum width in the Y direction of the conductive members 18 can be 20 mm or less, and can be 1 mm or more. The number of conductive members 18 may be one. The number of conductive members 18 can be more than the number of components mounted on the base portion 12.

[0069] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0070] 12: Base section 14:Resin sealing part 15A (input lead), 15B (output lead): Lead 16: Conductive member (first conductive member) 18, 18A, 18B, 18C, 18D, 18E, 18F, 18G, 18H: Conductive member (second conductive member) 20: Semiconductor chip (component) 21, 26; substrate 22, 23, 24, 27, 28: Electrode 25, 25A: Passive chip (component) 31, 32, 33, 34: Bonding wire 42A (1st part), 42B (2nd part), 42C, 42C, 42D, 42F: Part 44, 45: Matching circuit 50, 52: Route 54: Area 100, 102, 103, 104, 105, 106, 108, 110: semiconductor device C1, C2: Capacitors L1, L2: inductors Q1: Transistor Tin: Input terminal Tout: Output terminal

Claims

1. a base portion having at least a top surface made of metal; one or more components including a semiconductor chip mounted on the base with a first conductive member sandwiched therebetween; a second conductive member provided on the base portion, the second conductive member including a sintered metal or a resin containing metal powder, and on which the one or more components are not mounted; a resin sealing portion on the base portion, the resin sealing portion being in contact with the base portion, the one or more components, and the second conductive member, and sealing the one or more components; Equipped with The second conductive member is separated from the first conductive member.

2. a base portion having at least a top surface made of metal; one or more components including a semiconductor chip mounted on the base with a first conductive member sandwiched therebetween; a second conductive member provided on the base portion, the second conductive member including a sintered metal or a resin containing metal powder, and on which the one or more components are not mounted; a resin sealing portion on the base portion, the resin sealing portion being in contact with the base portion, the one or more components, and the second conductive member, and sealing the one or more components; Equipped with A semiconductor device, wherein the second conductive member is connected to the first conductive member and is separated from the one or more components by a distance equal to or greater than the sum of the thickness of the first conductive member between the semiconductor chip and the base portion and the thickness of the semiconductor chip.

3. 3. The semiconductor device according to claim 1, wherein the first conductive member and the second conductive member are made of the same material.

4. 3. The semiconductor device according to claim 1, wherein, when viewed from the thickness direction of the base portion, at least a portion of the second conductive member overlaps with a bonding wire having a first end connected to one of the one or more components.

5. An input lead for receiving a high frequency signal and an output lead for outputting a high frequency signal, the one or more components are provided between the input lead and the output lead, and the length of at least one bonding wire among a plurality of bonding wires provided in a path electrically connecting the input lead and the output lead, as viewed in the thickness direction of the base portion, is greater than any of the lengths of the input lead and the output lead of the one or more components in a first direction in which they are arranged; 3. The semiconductor device according to claim 1, wherein at least a portion of the second conductive member overlaps with the at least one bonding wire when viewed in a thickness direction of the base portion.

6. An input lead for receiving a high frequency signal and an output lead for outputting a high frequency signal, the one or more components are provided between the input lead and the output lead, and the length of at least one bonding wire among a plurality of bonding wires provided in a path electrically connecting the input lead and the output lead, as viewed in the thickness direction of the base portion, is greater than any of the lengths of the input lead and the output lead of the one or more components in a first direction in which they are arranged; 3. The semiconductor device according to claim 1, wherein at least a portion of the second conductive member is located in a second direction perpendicular to the first direction and the thickness direction of the base portion from the at least one bonding wire.

7. a plurality of paths are provided, each including the input lead, the output lead, the one or more components, and a plurality of bonding wires provided on the path; 7. The semiconductor device according to claim 6, wherein at least a portion of said second conductive member is provided between said at least one bonding wire of adjacent paths among said plurality of paths.

8. the semiconductor chip has a transistor that amplifies a high-frequency signal input to the input lead and outputs the amplified high-frequency signal to the output lead; 6. The semiconductor device according to claim 5, wherein the at least one bonding wire is included in a matching circuit that matches impedance between the input lead and the transistor or a matching circuit that matches impedance between the transistor and the output lead.

9. 3. The semiconductor device according to claim 1, wherein the second conductive member has a constriction in a cross section parallel to a thickness direction of the base portion.

10. 3. The semiconductor device of claim 1, wherein the second conductive member has a first portion extending in a third direction on the base portion, and a second portion extending in a fourth direction on the base portion that intersects with the third direction and is provided between the first portion and the base portion at the point where the second conductive member intersects with the first portion.

11. forming a first conductive member and a second conductive member on a base portion having at least a top surface made of metal; a step of mounting one or more components including a semiconductor chip on the first conductive member after the step of forming the first conductive member and the second conductive member, and not mounting the one or more components on the second conductive member; forming a resin sealing portion on the base portion, the resin sealing portion being in contact with the base portion, the one or more components, and the second conductive member and sealing the one or more components; Including, A method for manufacturing a semiconductor device, wherein the second conductive member is separated from the first conductive member or connected to the first conductive member and is separated from the one or more components by a distance equal to or greater than the sum of the thickness of the first conductive member between the semiconductor chip and the base portion and the thickness of the semiconductor chip.

Images