Dynamic random access memory structure

Abstract

PURPOSE: To provide a dynamic random access memory structure, which may have higher design flexibility and better electrical performance.SOLUTION: A dynamic random access memory structure includes a substrate, a word line structure, a first doped region, a second doped region, a capacitor structure, a through hole, a first dielectric layer, and a bit line. The substrate includes a first surface and a second surface opposite to each other. The word line structure is disposed adjacent to the first surface. The first doped region and the second doped region are located in the substrate and separated from each other. The capacitor structure is located on the first surface. The capacitor structure is electrically connected to the first doped region. The through hole is located in the substrate. The through hole is electrically connected to the second doped region. The first dielectric layer is located between the through hole and the substrate. The bit line is located on the second surface. The bit line is electrically connected to the through hole.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to memory structures, and more particularly to dynamic random access memory (DRAM) structures. [Background technology]

[0002] Currently, dynamic random access memories are being developed. Dynamic random access memories include transistors and capacitors. In dynamic random access memories, the capacitors are used as storage nodes. However, how to further improve the design flexibility and electrical performance of dynamic random access memories has been a goal of continuous effort. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a dynamic random access memory structure with high design flexibility and excellent electrical performance. [Means for solving the problem]

[0004] The present invention provides a dynamic random access memory structure including a substrate, a word line structure, a first doped region, a second doped region, a capacitor structure, a through hole, a first dielectric layer, and a bit line. The substrate has a first surface and a second surface facing each other. The word line structure is disposed adjacent to the first surface. The first doped region and the second doped region are located within the substrate and are separated from each other. The capacitor structure is located on the first surface. The capacitor structure is electrically connected to the first doped region. The through hole is located within the substrate. The through hole is electrically connected to the second doped region. The first dielectric layer is located between the through hole and the substrate. The bit line is located on the second surface. The bit line is electrically connected to the through hole.

[0005] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the word line structure may be located on the first surface of the substrate.

[0006] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the word line structure can be located within the substrate.

[0007] According to one embodiment of the present invention, the dynamic random access memory structure described above may further include a hard mask layer located in the substrate and overlying the word line structure, and the hard mask layer may be located closer to the first surface than the word line structure.

[0008] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the word line structure can include a word line and a second dielectric layer located between the word line and the substrate.

[0009] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the first doped region and the second doped region can be located in the substrate on either side of the word line structure.

[0010] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the first doped region and the second doped region may be located in the substrate on the same side of the word line structure.

[0011] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the first doped region may be closer to the first surface than the second doped region.

[0012] According to one embodiment of the present invention, the dynamic random access memory structure described above may further include an interconnect structure located between the capacitor structure and the first doped region, and the interconnect structure may be electrically connected to the capacitor structure and the first doped region.

[0013] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the capacitor structure can directly contact the first doped region.

[0014] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the capacitor structure includes a first electrode, a second electrode, and a second dielectric layer. The first electrode is electrically connected to the first doped region. The second electrode is located on the first electrode. The second dielectric layer is located between the first electrode and the second electrode.

[0015] According to one embodiment of the present invention, the dynamic random access memory structure described above may further include an interconnect structure located between the first electrode and the first doped region, and the interconnect structure may be electrically connected to the first electrode and the first doped region.

[0016] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the first electrode can directly contact the first doped region.

[0017] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the cross-sectional shape of the first electrode may be U-shaped.

[0018] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the cross-sectional shape of the first electrode may be columnar.

[0019] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the through-hole may penetrate the second doped region.

[0020] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the through-hole may not penetrate the second doped region.

[0021] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the through holes may be through-substrate vias (TSVs).

[0022] According to one embodiment of the present invention, the dynamic random access memory structure described above may further include a second dielectric layer located between the bit line and the second surface.

[0023] According to one embodiment of the present invention, in the dynamic random access memory structure described above, the via may penetrate the second dielectric layer. [Effects of the Invention]

[0024] As described above, the dynamic random access memory structure proposed by the present invention has bit lines located on the second plane, which allows for greater flexibility in the design of components on the first plane, thereby enhancing the design flexibility of the dynamic random access memory structure. Furthermore, the bit lines located on the second plane significantly reduces the parasitic capacitance caused by the bit lines. Furthermore, the bit lines located on the second plane allows for greater flexibility in the selection of materials for the bit lines and the dielectric layer between the bit lines (e.g., low-k material or air gap), thereby reducing the resistance of the bit lines and the parasitic capacitance between the bit lines. This improves the electrical performance of the dynamic random access memory structure.

[0025] In order to make the above features and advantages of the present invention clearer and easier to understand, the following embodiments will be described in detail with reference to the accompanying drawings. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a cross-sectional view of a dynamic random access memory structure according to some embodiments of the present invention. [Figure 2] 3A-3C are cross-sectional views of dynamic random access memory structures according to some further embodiments of the present invention. [Figure 3] 1 is a cross-sectional view of a dynamic random access memory structure according to still other embodiments of the present invention. [Figure 4] 1 is a cross-sectional view of a dynamic random access memory structure according to still other embodiments of the present invention. [Figure 5] 1 is a cross-sectional view of a dynamic random access memory structure according to still other embodiments of the present invention. [Figure 6] 1 is a cross-sectional view of a dynamic random access memory structure according to still other embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. For ease of understanding, the same components will be denoted by the same reference numerals in the following description. Furthermore, the accompanying drawings are for illustrative purposes only and are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0028] FIG. 1 is a cross-sectional view of a dynamic random access memory structure according to some embodiments of the present invention.

[0029] 1 , the dynamic random access memory structure 10 includes a substrate 100, a word line structure 102, a doped region 104, a doped region 106, a capacitor structure 108, a through hole 110, a dielectric layer 112, and a bit line 114. The substrate 100 includes a first side S1 and a second side S2 facing each other. In some embodiments, the first side S1 may be a front side of the substrate 100, and the second side S2 may be a back side of the substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate.

[0030] The word line structure 102 is disposed adjacent to the first surface S1. In this embodiment, the word line structure 102 may be located on the first surface S1 of the substrate 100, although the present invention is not limited thereto. The word line structure 102 may include a word line 116 and a dielectric layer 118. In some embodiments, the material of the word line 116 is, for example, doped polysilicon, a metal, or a combination thereof. The dielectric layer 118 is located between the word line 116 and the substrate 100. In some embodiments, the material of the dielectric layer 118 is, for example, silicon oxide.

[0031] The doped regions 104 and 106 are located within the substrate 100 and are separated from each other. The doped regions 104 and 106 can function as one and the other of a source region and a drain region, respectively. In this embodiment, the doped regions 104 and 106 can be located within the substrate 100 on either side of the word line structure 102, although the present invention is not limited thereto.

[0032] The capacitor structure 108 is located on the first surface S1. The capacitor structure 108 is electrically connected to the doped region 104. In some embodiments, the dynamic random access memory structure 10 may further include an internal wiring structure 120. The internal wiring structure 120 is located between the capacitor structure 108 and the doped region 104. The internal wiring structure 120 may be electrically connected to the capacitor structure 108 and the doped region 104. In some embodiments, the internal wiring structure 120 may include a contact 122, a contact 124, and a pad 126, although the present invention is not limited thereto. Those skilled in the art can adjust the components within the internal wiring structure 120 as needed. The contact 122 is located on the doped region 104. The contact 124 is located on the contact 122. The pad 126 is located between the capacitor structure 108 and the contact 124. In some embodiments, the material of the interconnect structure 120 is, for example, tungsten, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.

[0033] The capacitor structure 108 may include an electrode 128, an electrode 130, and a dielectric layer 132. The electrode 128 is electrically connected to the doped region 104. The interconnect structure 120 is located between the electrode 128 and the doped region 104. The interconnect structure 120 may be electrically connected to the electrode 128 and the doped region 104. In this embodiment, the cross-sectional shape of the electrode 128 may be U-shaped, although the present invention is not limited thereto. In some embodiments, the material of the electrode 128 is, for example, titanium nitride, silicon, or a combination thereof. The electrode 130 is located on the electrode 128. In some embodiments, the material of the electrode 130 is, for example, titanium nitride, silicon, germanium, tungsten, or a combination thereof. The dielectric layer 132 is located between the electrode 128 and the electrode 130. In some embodiments, the material of the dielectric layer 132 is, for example, a high-k material.

[0034] The through-hole 110 is located in the substrate 100. The through-hole 110 is electrically connected to the doped region 106. In this embodiment, the through-hole 110 may penetrate the doped region 106, but the present invention is not limited thereto. As long as the through-hole 110 is electrically connected to the doped region 106, it is within the scope of the present invention. In some embodiments, the through-hole 110 may be a through-substrate via (TSV). In some embodiments, the material of the through-hole 110 is, for example, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, silicon, a composite thereof, or a combination thereof.

[0035] The dielectric layer 112 is located between the through-hole 110 and the substrate 100. In some embodiments, the material of the dielectric layer 112 is, for example, silicon oxide.

[0036] The bit lines 114 are located on the second surface S2. The bit lines 114 are electrically connected to the through holes 110, which allows the bit lines 114 to be electrically connected to the doped regions 106. In some embodiments, the material of the bit lines 114 is, for example, tungsten, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, silicon, composites thereof, or combinations thereof.

[0037] In some embodiments, the dynamic random access memory structure 10 may further include a dielectric layer 134. The dielectric layer 134 is located on the substrate 100, the word line structure 102, the capacitor structure 108, and the interconnect structure 120. In some embodiments, the dielectric layer 134 may have a multi-layer structure. In some embodiments, the material of the dielectric layer 134 is, for example, silicon oxide.

[0038] In some embodiments, the dynamic random access memory structure 10 may further include a dielectric layer 136. The dielectric layer 136 is located between the bit line 114 and the second surface S2. The via 110 may pass through the dielectric layer 136 and directly connect to the bit line 114. In other embodiments, the via 110 may be electrically connected to the bit line 114 through another via (not shown). In some embodiments, the material of the bit line 114 is, for example, silicon oxide.

[0039] As can be seen from the above-described embodiment, in the dynamic random access memory structure 10, because the bit lines 114 are located on the second surface S2, the design of the components on the first surface S1 can be made more flexible, thereby increasing the design flexibility of the dynamic random access memory structure 10. Furthermore, because the bit lines 114 are located on the second surface S2, the parasitic capacitance caused by the bit lines 114 can be significantly reduced. Furthermore, because the bit lines 114 are located on the second surface S2, the material of the bit lines 114 and the material (e.g., a low-dielectric-constant material or an air gap) of the dielectric layer (not shown) between the bit lines 114 can be flexibly selected, thereby reducing the resistance of the bit lines 114 and the parasitic capacitance between the bit lines 114. In this way, the electrical performance of the dynamic random access memory structure 10 can be improved.

[0040] FIG. 2 is a cross-sectional view of a dynamic random access memory structure according to some further embodiments of the present invention.

[0041] 1 and 2, the differences between the dynamic random access memory structure 20 of FIG. 2 and the dynamic random access memory structure 10 of FIG. 1 are as follows: In the dynamic random access memory structure 20, the word line structure 102 can be located in the substrate 100. In the dynamic random access memory structure 20, the through-holes 110 do not have to penetrate the doped regions 106, but the present invention is not limited thereto. As long as the through-holes 110 are electrically connected to the doped regions 106, they are within the scope of the present invention.

[0042] The dynamic random access memory structure 20 may further include a hard mask layer 138. The hard mask layer 138 is located in the substrate 100 and on the word line structure 102. The hard mask layer 138 may be located closer to the first surface S1 than the word line structure 102. In some embodiments, the material of the hard mask layer 138 is, for example, silicon nitride. In the dynamic random access memory structure 20, the internal wiring structure 120 may not include the through holes 122 and the through holes 124, but the present invention is not limited thereto. Those skilled in the art can adjust the components in the internal wiring structure 120 as needed. The dynamic random access memory structure 20 may further include a dielectric layer 140. The dielectric layer 140 is located between the dielectric layer 134 and the substrate 100. The pad 126 may be located in the dielectric layer 140. In some embodiments, the material of the dielectric layer 140 is, for example, silicon oxide, silicon nitride, silicon carbide nitride, or a combination thereof. In addition, in FIG. 1 and FIG. 2, the same or similar components are denoted by the same reference numerals, and the description thereof will be omitted.

[0043] FIG. 3 is a cross-sectional view of a dynamic random access memory structure according to some further embodiments of the present invention.

[0044] 2 and 3, the dynamic random access memory structure 30 in FIG. 3 differs from the dynamic random access memory structure 20 in FIG. 2 in the following respects: In the dynamic random access memory structure 30, the cross-sectional shape of the electrode 128 may be columnar. In addition, in FIGS. 2 and 3, the same or similar components are denoted by the same reference numerals, and their description will be omitted.

[0045] FIG. 4 is a cross-sectional view of a dynamic random access memory structure according to some further embodiments of the present invention.

[0046] 3 and 4, the differences between the dynamic random access memory structure 40 in FIG. 4 and the dynamic random access memory structure 30 in FIG. 3 are as follows: The dynamic random access memory structure 40 may not include the internal wiring structure 120 in FIG. 3. That is, the capacitor structure 108 may directly contact the doped region 104. For example, the electrode 128 may directly contact the doped region 104. In addition, in FIGS. 3 and 4, the same or similar components are denoted by the same reference numerals, and their description will be omitted.

[0047] FIG. 5 is a cross-sectional view of a dynamic random access memory structure according to some further embodiments of the present invention.

[0048] 3 and 5, the dynamic random access memory structure 50 of FIG. 5 differs from the dynamic random access memory structure 30 of FIG. 3 in the following ways: In the dynamic random access memory structure 50, the doped region 104 and the doped region 106 can be located in the substrate 100 on the same side of the word line structure 102. The doped region 104 can be located closer to the first surface S1 than the doped region 106. Therefore, the area of ​​the dynamic random access memory structure 50 can be effectively reduced. In some embodiments, the dynamic random access memory structure 50 is configured as a memory cell with a bit size of 4F, where F is half the minimum spacing between components.2 3 and 5, the same or similar components are denoted by the same reference numerals, and the description thereof will be omitted.

[0049] FIG. 6 is a cross-sectional view of a dynamic random access memory structure according to some further embodiments of the present invention.

[0050] 5 and 6, the differences between the dynamic random access memory structure 60 in FIG. 6 and the dynamic random access memory structure 50 in FIG. 5 are as follows: The dynamic random access memory structure 60 may not include the internal wiring structure 120 in FIG. 5. That is, the capacitor structure 108 may directly contact the doped region 104. For example, the electrode 128 may directly contact the doped region 104. In addition, in FIGS. 5 and 6, the same or similar components are denoted by the same reference numerals, and their description will be omitted. [Industrial Applicability]

[0051] As described above, in the dynamic random access memory structure of the above-described embodiment, the substrate includes a first surface and a second surface facing each other. The capacitor structure is located on the first surface, and the bit line is located on the second surface. Because the bit line is located on the second surface, the design of the components on the first surface can be more flexible, thereby increasing the design flexibility of the dynamic random access memory structure. Furthermore, because the bit line is located on the second surface, the parasitic capacitance caused by the bit line can be significantly reduced. Furthermore, because the bit line is located on the second surface, the material of the bit line and the material of the dielectric layer between the bit lines (e.g., a low-k material or an air gap) can be flexibly selected, thereby reducing the resistance of the bit line and the parasitic capacitance between the bit lines. In this way, the electrical performance of the dynamic random access memory structure can be improved.

[0052] Although the present invention has been described in detail with reference to the above embodiments, they are not intended to limit the present invention. Those skilled in the art will understand that changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the following claims. [Explanation of symbols]

[0053] 10, 20, 30, 40, 50, 60 Dynamic Random Access Memory Structure 100 boards 102 Word Line Structure 104, 106 doped region 108 Capacitor Structure 110 Through hole 112, 118, 132, 134, 136, 140 Dielectric layer 114 bit lines 116 word lines 120 Internal wiring structure 122, 124 Contact 126 Pad 128, 130 electrodes 138 Hard Mask Layer S1 1st page S2 side 2

Claims

1. a substrate having a first surface and a second surface facing each other; a word line structure disposed adjacent the first surface; a first doped region and a second doped region located within the substrate and separated from one another; a capacitor structure located on the first surface and electrically connected to the first doped region; a through hole located in the substrate and electrically connected to the second doped region; a first dielectric layer located between the through hole and the substrate; a bit line located on the second surface and electrically connected to the through hole; A dynamic random access memory structure comprising:

2. 2. The dynamic random access memory structure of claim 1, wherein said word line structure is located on said first surface of said substrate.

3. 2. The dynamic random access memory structure of claim 1 wherein said word line structure is located within said substrate.

4. further comprising a hard mask layer located within the substrate and overlying the word line structure; 4. The dynamic random access memory structure of claim 3, wherein said hard mask layer is located closer to said first surface than said word line structures.

5. the word line structure: A word line; a second dielectric layer located between the word line and the substrate; 2. The dynamic random access memory structure of claim 1, comprising:

6. 2. The dynamic random access memory structure of claim 1, wherein said first doped region and said second doped region are located in said substrate on either side of said word line structure.

7. 2. The dynamic random access memory structure of claim 1, wherein said first doped region and said second doped region are located in said substrate on the same side of said word line structure.

8. 8. The dynamic random access memory structure of claim 7, wherein said first doped region is located closer to said first surface than said second doped region.

9. 2. The dynamic random access memory structure of claim 1, further comprising an interconnect structure positioned between said capacitor structure and said first doped region and electrically connected to said capacitor structure and said first doped region.

10. 2. The dynamic random access memory structure of claim 1, wherein said capacitor structure directly contacts said first doped region.

11. The capacitor structure comprises: a first electrode electrically connected to the first doped region; a second electrode located above the first electrode; a second dielectric layer located between the first electrode and the second electrode; 2. The dynamic random access memory structure of claim 1, comprising:

12. 12. The dynamic random access memory structure of claim 11, further comprising an interconnect structure located between said first electrode and said first doped region and electrically connected to said first electrode and said first doped region.

13. 12. The dynamic random access memory structure of claim 11, wherein said first electrode directly contacts said first doped region.

14. The dynamic random access memory structure of claim 11 , wherein the cross-sectional shape of the first electrode comprises a U-shape.

15. The dynamic random access memory structure of claim 11 , wherein the cross-sectional shape of the first electrode comprises a pillar.

16. 2. The dynamic random access memory structure of claim 1, wherein said via extends through said second doped region.

17. 2. The dynamic random access memory structure of claim 1, wherein said via does not penetrate said second doped region.

18. The dynamic random access memory structure of claim 1 , wherein the through holes comprise through-substrate vias.

19. 2. The dynamic random access memory structure of claim 1 further comprising a second dielectric layer located between said bit lines and said second surface.

20. 20. The dynamic random access memory structure of claim 19, wherein the via extends through the second dielectric layer.

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