Optimized decoding scheduling in joint LDPC and raid decoding scheme

Abstract

To provide a decoding process that implements two different decoding schemes.SOLUTION: A system 100 includes a data storage device that includes an error correction code (ECC) ordering system that determines a decoding schedule in which two or more flash memory units (FMUs) that have failed an initial decoding process are to be decoded using a joint decoding scheme. The ECC ordering system generates the decoding schedule based on a metric associated with each FMU. The metric on which the decoding schedule is based is a syndrome weight associated with each FMU or is a combined bit error rate (BER) associated with each FMU. When the decoding schedule has been generated, the ECC ordering system causes a joint decoding operation to be executed on the FMUs in order specified by the decoding schedule.SELECTED DRAWING: None

Description

[Technical Field]

[0001] Data storage devices typically include error correction functionality to correct errors that occur when data is read from the data storage device. For example, when data is written to a data storage device, the data is encoded by an error correction code (ECC) low-density parity check (LDPC) encoder to generate redundant information known as parity bits. The parity bits and data are stored as ECC codewords.

[0002] When an ECC codeword is read from a data storage device, a decoder, such as an LDPC decoder, decodes the codeword and corrects any errors that may be present. Typically, LDPC decoders are used to correct random errors that occur on data storage devices.

[0003] However, LDPC decoders cannot handle the large number of errors that can occur as a result of memory defects and / or failures. Therefore, data storage devices can also incorporate redundant array of independent die (RAID) storage schemes that aim to handle errors that occur as a result of physical defects. For example, RAID storage schemes distribute data in stripes across multiple different solid state drives (SSDs) or multiple different memory dies within a single SSD, along with first and second parity information. The parity information allows for recovery of the data in the stripe if one of the SSDs or memory dies fails.

[0004] In some cases, LDPC decoding and RAID decoding are combined to increase the likelihood that errors are correctable. For example, if multiple pages fail a decoding operation, a RAID-based decoding scheme is implemented for the pages, followed by an LDPC decoding scheme. This process is repeated for each failed page.

[0005] However, if an initial decoding process fails to decode or correct a particular failed page, it is possible that the particular page may be successfully decoded during another iteration. For example, if another failed page is successfully decoded, the information corresponding to the currently corrected page may be used to correct the errors in that particular failed page. Thus, multiple decoding processes may be performed on the same failed page. However, each time a decoding process is performed on the same page, the decoding latency increases.

[0006] Therefore, it would be beneficial to reduce the latency of the decoding process by implementing two different decoding schemes. Summary of the Invention

[0007] The present disclosure describes an error correcting code (ECC) ordering system for a data storage device. In one example, the ECC ordering system is part of or otherwise associated with the error correcting code (ECC) system of the data storage device. The ECC ordering system determines a decoding order or a decoding schedule in which two or more flash memory units (FMUs) that failed an initial decoding process are decoded using a joint decoding scheme. In one example, the joint decoding scheme includes a first decoding scheme (e.g., an LDPC decoding scheme) and a second decoding scheme (e.g., a RAID decoding scheme).

[0008] For example, the FMUs may be associated with or otherwise included in a RAID stripe or XOR stripe of the second decoding scheme. When two or more FMUs fail the initial decoding process, the ECC ordering system determines the order in which the FMUs are decoded using the joint decoding scheme based on one or more metrics associated with the two or more FMUs. Once the order is determined, the ECC system performs the joint decoding scheme on the FMUs in the determined order.

[0009] In one example, the metric on which the decoding schedule is based is the syndrome weight of each FMU. In another example, the metric on which the decoding schedule is based is the combined bit error rate (BER) of each FMU. In one example, the combined BER indicates the quality of the one or more soft bits associated with each FMU and the quality of the FMU.

[0010] Thus, an example of the present disclosure describes a method that includes identifying two or more FMUs associated with a data storage device that failed an initial decoding operation performed by an error code correction system of the data storage device. The method also includes determining a metric associated with each of the two or more FMUs. A decoding schedule for the two or more FMUs is generated. In one example, the decoding schedule is based at least in part on the metric associated with each of the two or more FMUs. A joint decoding operation is then performed on a first FMU of the two or more FMUs based on the generated decoding schedule using a joint decoding scheme. In one example, the joint decoding scheme includes a first decoding scheme and a second decoding scheme.

[0011] Another example describes a data storage device including a controller and an error correcting code (ECC) system associated with the controller. In one example, the ECC system is operable to perform an initial decoding operation on FMUs associated with a stripe and determine whether any FMUs fail the initial decoding operation. If the ECC system determines that two or more FMUs fail the initial decoding operation, the ECC system determines metrics associated with each of the two or more FMUs and determines an order in which each of the two or more FMUs will undergo the joint decoding operation using a joint decoding scheme. In one example, the order in which the two or more FMUs are decoded is based at least in part on the metrics associated with each of the two or more FMUs. Further, the joint decoding scheme includes a first decoding scheme and a second decoding scheme. The ECC system also performs the joint decoding operation on the two or more FMUs in the determined order.

[0012] Yet another example describes a data storage device including a control means and an error correction means associated with the control means. In one example, the error correction means determines whether two or more memory means associated with the data storage device failed an initial decoding operation. Based at least in part on the determination that the two or more memory means failed the initial decoding operation, the error correction means determines a first metric associated with a first memory means of the two or more memory means and a second metric associated with a second memory means of the two or more memory means. The control means compares the first metric and the second metric and generates a decoding schedule based at least in part on the comparison between the first metric and the second metric. The error correction means also performs a joint decoding operation on at least one of the first memory means and the second memory means using a joint decoding scheme based at least in part on the decoding schedule. In one example, the joint decoding scheme includes a first decoding scheme and a second decoding scheme.

[0013] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Brief explanation of the drawings]

[0014] Non-limiting and non-exhaustive examples are described with reference to the following figures. [Figure 1] 1 is a block diagram of a system including a host device and a data storage device, according to an example. [Figure 2A] 1 illustrates how a memory device includes multiple memory blocks, according to an example. [Figure 2B] 1 illustrates how a memory block contains one or more pages, according to an example. [Figure 2C] 1 illustrates how a memory block includes multiple bit lines and word lines, according to an example. [Figure 3A] 1 illustrates how multiple pages within a stripe are combined to form parity information, according to an example. [Figure 3B] According to an example, page 2 and page 4 in the stripe failed the decryption process. [Figure 3C] 1 illustrates how a joint decoding scheme is used to correct errors within a page of a stripe, according to an example. [Figure 4A] 1 illustrates how multiple pages within a stripe are combined to form parity information, according to an example. [Figure 4B] 10 illustrates how pages 2 and 4 are ordered within a stripe based on a determination that pages 2 and 4 failed the decoding process, according to one example. [Figure 4C] 10 illustrates how a joint decoding scheme is used to correct errors in a page based on a determined order, according to an example. [Figure 5] 1 illustrates a method for performing a joint decoding scheme for two or more FMUs of a stripe, according to an example. [Figure 6] 1 is a perspective view of a storage device including three-dimensional (3D) stacked nonvolatile memory according to an example. [Figure 7] FIG. 2 is a block diagram of a storage device according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0015] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments or examples. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0016] Typically, data storage devices include error correction capabilities for correcting errors that occur when data is read from the data storage device. For example, as previously described, when data is written to a data storage device, the data is encoded by an error correcting code (ECC) encoder (e.g., an LDPC encoder) to generate parity bits. The parity bits are combined with the data and stored as an ECC codeword.

[0017] When an ECC codeword is read from a data storage device, a decoder (e.g., an LDPC decoder) decodes the codeword and corrects any errors that may be present. Typically, an LDPC decoder is used to correct random errors that occur on a data storage device. For example, an LDPC decoder corrects errors up to a certain bit error rate (BER).

[0018] The data storage device may also incorporate a RAID encoding / decoding scheme. For example, the RAID encoding / decoding scheme distributes data in stripes across multiple different solid-state drives (SSDs) or across multiple memory dies within a single SSD, along with first and second parity information. The parity information enables recovery of the data in the stripes if one of the SSDs or memory dies fails or if the BER of one flash memory unit (FMU) exceeds the maximum BER that the LDPC decoder can handle.

[0019] As previously described, some data storage devices implement a joint LDPC and RAID decoding scheme that has the ability to correct multiple FMUs that fail the initial decoding process. For example, if multiple FMUs fail the initial decoding operation, the joint decoding scheme is implemented for the first failed FMU and is repeated for each failed FMU in an order based on the stripe index.

[0020] Although the joint decoding scheme may have the ability to correct more errors when compared with the separate RAID decoding scheme and the separate LDPC decoding scheme, the joint decoding scheme is not without drawbacks. For example, if multiple FMUs fail the initial decoding process, the joint decoding scheme is performed based on the indexes of the FMUs. Thus, if FMU2 (located at index 2 in the stripe) and FMU4 (located at index 4 in the stripe) fail the initial decoding process, the joint decoding scheme is performed on FMU2, followed by FMU4.

[0021] However, if an initial pass of the joint decoding scheme fails to decode or correct FMU2, it is possible that FMU2 can be successfully decoded during another iteration. For example, if the joint decoding scheme successfully decodes FMU4, the corrected information in FMU4 can be used to correct the error in FMU2. Therefore, multiple decoding processes may be performed on the same failed FMU, which increases the latency of the decoding process.

[0022] To address the above, this disclosure describes an ECC ordering system for a data storage device. In one example, the ECC ordering system is part of or otherwise associated with the ECC system of the data storage device. The ECC ordering system determines an order or schedule in which two or more FMUs that fail an initial decoding process should be decoded using a joint decoding scheme. In one example, the joint decoding scheme includes a first decoding scheme (e.g., an LDPC decoding scheme) and a second decoding scheme (e.g., a RAID decoding scheme).

[0023] For example, the FMUs are associated with or otherwise included in a stripe (e.g., a RAID or XOR stripe) of a second decoding scheme. When two or more FMUs fail the initial decoding process (e.g., the BER of the FMUs exceeds the correction capability of the first decoding scheme), the ECC ordering system determines the order in which the FMUs are decoded using the joint decoding scheme based on one or more metrics of the two FMUs. Once the order is determined, the ECC system performs the joint decoding scheme on the FMUs in the determined order.

[0024] In one example, the metric on which the scheduling order is based is the syndrome weight of each FMU. In another example, the metric on which the scheduling order is based is based at least in part on the combined BER of the FMUs. In one example, the combined BER represents the quality of one or more soft bits associated with each FMU and / or the quality of the FMU. For example, the combined BER indicates the likelihood that the FMU will be successfully decoded. Thus, the FMUs are ordered from most likely to be decoded to least likely to be decoded. However, as more FMUs are successfully decoded, subsequent FMUs become more likely to be decoded. Thus, repeated iterations attempting to decode failed FMUs are reduced or eliminated.

[0025] In accordance with the above, many technical benefits can be realized, including, but not limited to, improving the quality of service in the data storage device, reducing decoding latency by reducing the number of joint decoding iterations for failed FMUs, and improving the effective error correction capabilities of the data storage device.

[0026] These advantages, along with other examples, are shown and explained in more detail with respect to Figures 1-7.

[0027] 1 is a block diagram of a system 100 including a host device 105 and a data storage device 110, according to one example. In one example, the host device 105 includes a processor 115 and memory 120 (e.g., main memory). The memory 120 includes or is otherwise associated with an operating system 125, a kernel 130, and / or applications 135.

[0028] Processor 115 may execute various instructions, such as, for example, instructions from operating system 125 and / or applications 135. Processor 115 may include circuitry such as a microcontroller, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), hardwired logic, analog circuitry, and / or various combinations thereof. In one example, processor 115 includes a system on a chip (SoC).

[0029] In one example, memory 120 is used by host device 105 to store data used or executed by processor 115. Data stored in memory 120 includes instructions provided by data storage device 110 via communication interface 140. Data stored in memory 120 also includes data used to execute instructions from operating system 125 and / or one or more applications 135. Memory 120 may be a single memory or may include multiple memories, such as, for example, one or more non-volatile memories, one or more volatile memories, or a combination thereof.

[0030] In one example, operating system 125 creates a virtual address space for applications 135 and / or other processes executed by processor 115. The virtual address space maps to locations in memory 120. Operating system 125 also includes or is otherwise associated with kernel 130. Kernel 130 manages various resources of host device 105 (e.g., memory allocation), includes instructions for handling read and write requests, and the like.

[0031] The communication interface 140 communicatively couples the host device 105 and the data storage device 110. The communication interface 140 can be a Serial Advanced Technology Attachment (SATA), PCI express (PCIe) bus, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), Ethernet, Fibre Channel, or Wi-Fi. Thus, the host device 105 and the data storage device 110 need not be physically co-located and can communicate over a network, such as a local area network (LAN) or a wide area network (WAN) such as the Internet. Furthermore, the host device 105 can interface with the data storage device 110 using a logical interface standard, such as Non-Volatile Memory Express (NVMe) or Advanced Host Controller Interface (AHCI).

[0032] Data storage device 110 includes a controller 150 and a memory device 155. In one example, controller 150 is communicatively coupled to memory device 155. Memory device 155 includes one or more memory dies (e.g., first memory die 165 and second memory die 170). Although memory dies are specifically mentioned, memory device 155 may include any non-volatile memory device, storage device, storage element, or storage medium, including NAND flash memory cells and / or NOR flash memory cells.

[0033] The memory cells may take the form of solid-state (e.g., flash) memory cells and may be single-time programmable, multi-time programmable, or multi-time programmable. Furthermore, the memory cells may be single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), penta-level cells (PLC), and / or may use any other memory technology. In one example, the memory cells are arranged in a two-dimensional configuration. In another example, the memory cells are arranged in a three-dimensional configuration.

[0034] In one example, data storage device 110 is attached to or embedded within host device 105. In another example, data storage device 110 is implemented as an external or portable device that is communicatively or selectively coupled to host device 105 and that may be detached from host device 105. In yet another example, data storage device 110 is a component (e.g., a solid-state drive (SSD)) of a network-accessible data storage system, a network-attached storage system, a cloud data storage system, or the like.

[0035] As described above, memory device 155 of data storage device 110 includes first memory die 165 and second memory die 170. Although two memory dies are shown, memory device 155 may include any number of memory dies (e.g., one memory die, two memory dies, eight memory dies, or another number of memory dies).

[0036] Memory device 155 also includes support circuits. In one example, the support circuits include read / write circuitry 160. Read / write circuitry 160 supports operation of the memory dies of memory device 155. Although read / write circuitry 160 is shown as a single component, read / write circuitry 160 may be divided into separate components, such as a read circuit and a write circuit. Read / write circuitry 160 may be external to the memory dies of memory device 155. In another example, one or more of the memory dies may include a corresponding read / write circuitry 160 operable to read data from and / or write data to storage elements within one individual memory die, independent of other read and / or write operations to any of the other memory dies.

[0037] In one example, one or more of the first memory die 165 and the second memory die 170 includes one or more memory blocks. In one example, each memory block includes one or more memory cells. A block of memory cells is the smallest number of memory cells that can be physically erased together. In one example, to increase parallelism, each of the blocks may be operated on or organized in larger blocks or metablocks. For example, blocks from different dies of memory may be logically linked together to form a metablock.

[0038] For example, referring to FIG. 2A , FIG. 2A illustrates how a memory device 200 includes multiple memory blocks, according to one example. For example, memory device 200 (e.g., a storage element, a memory die, a non-volatile memory device) includes four planes or sub-arrays (e.g., a first plane 205, a second plane 210, a third plane 215, and a fourth plane 220). In one example, the planes are integrated onto a single memory die. In another example, the planes are provided on two different memory dies (e.g., two planes on each memory die). In yet another example, the planes are provided on four separate memory dies. Although four planes are shown and described, memory device 200 can have any number of planes and / or memory dies.

[0039] In one example, each plane is divided into memory blocks that comprise memory cells. As shown in FIG. 2A , rectangles represent memory blocks, such as memory block 225, memory block 230, memory block 235, and memory block 240. There may be tens or hundreds of memory blocks in each plane of memory device 200. In one example, each memory block is a unit of erasure and may also be referred to as an erase block. For example, memory block 225, memory block 230, memory block 235, and memory block 240 contain the minimum number of memory cells that are erased together.

[0040] Additionally, various memory blocks are logically linked or grouped together (e.g., using a table in controller 150 (FIG. 1) or otherwise accessible by controller 150) to form metablocks. Metablocks are written to, read from, and / or erased as a single unit. For example, memory block 225, memory block 230, memory block 235, and memory block 240 form a first metablock, and memory block 245, memory block 250, memory block 255, and memory block 260 form a second metablock. The memory blocks used to form metablocks need not be restricted to the same relative locations within their respective planes.

[0041] In one example, each memory block is divided into pages of memory cells for operational purposes. For example, referring to Figure 2B, Figure 2B illustrates how a memory block may include one or more pages, according to one example. For example, the memory cells of memory blocks 225, 230, 235, and 240 may be divided into N different pages (denoted as P0 through PN). Although Figure 2B illustrates a specific number of pages, the memory blocks may have any number of pages of memory cells within each memory block.

[0042] In one example, a page is a unit of data programming within a memory block. Each page contains the smallest amount of data that can be programmed at one time. The smallest unit of data that can be read at one time may be smaller than a page. For example, each page can be further divided into segments or units, with each segment containing the smallest number of memory cells that can be written at one time as a basic programming operation. Data stored in a segment or unit of memory cells is referred to herein as a flash memory unit (FMU). An FMU may be a page, an ECC page, a codeword, or may otherwise include the amount of data written at one time during a basic programming operation and / or the amount of data that can be encoded and / or decoded by an ECC system (e.g., ECC system 185 (FIG. 1)) during a single encoding and / or decoding operation.

[0043] 2B as being formed from one physical page from memory block 225, memory block 230, memory block 235, and memory block 240. In the illustrated example, metapage 270 includes page P1 in each of the four memory blocks. However, the pages of metapage 270 need not have the same relative location within each memory block. Metapage 270 may be the largest unit of programming within a memory block.

[0044] The memory blocks disclosed in Figures 2A-2B are referred to herein as physical memory blocks because, as described above, they relate to groups of physical memory cells. As used herein, a logical memory block is a virtual unit of address space defined to have the same size as a physical memory block. Each logical memory block contains a range of logical memory block addresses (LBAs) associated with data received from the host. The LBAs are then mapped to one or more physical memory blocks within the data storage device 110 where the data is physically stored.

[0045] As mentioned above, each memory block may include any number of memory cells. The design, size, and organization of the memory blocks may depend on the architecture, design, and application desired for each memory die. In one example, a memory block includes a contiguous set of memory cells that share multiple word lines and bit lines.

[0046] 2C illustrates how a memory block, according to one example, includes multiple bit lines 275 and word lines 280. For example, as shown in FIG. 2C, memory block 225 includes bit lines BL0 through BLN (collectively bit lines 275), where N is the total number of bit lines. In addition, memory block 225 includes word lines WL0 through WLN (collectively word lines 280), where N is the total number of word lines. In one example, multiple memory blocks can share the same bit lines.

[0047] The word lines 280 can function as single-level cell (SLC) word lines, multi-level cell (MLC) word lines, tri-level cell (TLC) word lines, quad-level cell (QLC) word lines, penta-level cell (PLC) word lines, etc. Additionally, each memory cell may be programmable to a state that represents one or more values ​​(e.g., a threshold voltage in a flash configuration or a resistance state in a resistive memory configuration).

[0048] In the example shown in Figure 2C, four memory cells are connected in series to form a NAND string. Although four memory cells are shown, any number of memory cells (e.g., 16, 32, 64, 128, 256, or any other number) can be used. One terminal of the NAND string is connected to a corresponding bit line via a drain select gate (connected to a select gate drain line SGD), and the other terminal of the NAND string is connected to a source line via a source select gate (connected to a select gate source line SGS). Furthermore, although eight bit lines are shown in Figure 2C, any number of bit lines can be used.

[0049] 1 , as previously mentioned, data storage device 110 also includes controller 150. While a single controller 150 is shown and described, data storage device 110 may include multiple controllers. In such an example, a first controller performs a first operation or set of operations, and a second controller performs a second operation or set of operations. In one example, the first set of operations and the second set of operations are performed on the same memory die. In another example, the first set of operations is performed on a first memory die or first set of memory dies, and the second set of operations is performed on a second memory die or second set of memory dies.

[0050] Controller 150 is communicatively coupled to memory device 155 via a bus, interface, or other communication circuitry. In one example, the communication circuitry includes one or more channels to allow controller 150 to communicate with first memory die 165 and / or second memory die 170 of memory device 155. In another example, the communication circuitry includes multiple separate channels to allow controller 150 to communicate with first memory die 165 independently and / or in parallel with second memory die 170 of memory device 155.

[0051] The controller 150 receives data and / or commands from the host device 105. The controller 150 also transmits data to the host device 105. For example, the controller 150 transmits data to the host device 105 and / or receives data from the host device 105 via the communication interface 140. The controller 150 also transmits data and / or commands to the memory device 155 and / or receives data from the memory device 155.

[0052] Controller 150 sends data and corresponding write commands to memory device 155, causing memory device 155 to store the data at a specified address in memory device 155. In one example, the write command specifies a physical address of a portion of memory device 155. Controller 150 also sends data and / or commands associated with one or more background scan operations, garbage collection operations, and / or wear leveling operations.

[0053] Controller 150 also sends one or more read commands to memory device 155. In one example, the read command specifies a physical address of a portion of memory device 155 where data is stored. Controller 150 also tracks the number of program / erase cycles or other programming operations performed on or by the memory device and / or memory die of memory device 155.

[0054] Controller 150 also includes or is otherwise associated with ECC system 185 and / or ECC ordering system 180. In one example, ECC system 185 and / or ECC ordering system 180 are packaged functional hardware units designed for use with other components / systems. In another example, ECC system 185 and / or ECC ordering system 180 are portions of program code (e.g., software or firmware) executable by a processor or processing circuitry. In yet another example, ECC system 185 and / or ECC ordering system 180 are self-contained hardware and / or software components that interface with other components and / or systems. Although ECC system 185 and ECC ordering system 180 are shown as part of controller 150, ECC system 185 and / or ECC ordering system 180 may be separate from controller 150.

[0055] In one example, ECC system 185 receives data to be stored in memory device 155 and generates a codeword. For example, ECC system 185 includes an encoder that encodes the data using a first encoding scheme. In one example, the first encoding scheme is an ECC encoding scheme such as a Reed-Solomon encoder, a Bose Chaudhuri Hocquenghem (BCH) encoder, a low-density parity check (LDPC) encoder, a turbo code encoder, an encoder configured to encode one or more other ECC encoding schemes, or any combination thereof.

[0056] For example, when data is received, ECC system 185 of controller 150 encodes the data into one or more codewords. The codewords are then stored in memory device 155 (or another location). For example, when data is received, the data is divided into N data words. A first portion of the data corresponds to the first data word, and an Nth data word corresponds to the last data word of the data. ECC system 185 encodes the first data word to generate a first codeword (including the data and associated parity bits), and encodes the second data word to generate a second codeword. This is repeated for all N data words.

[0057] Additionally, ECC system 185 includes an encoder that encodes data according to a second encoding scheme. In one example, the second encoding scheme is a RAID or XOR encoding scheme that generates steep parity data. For example, if codewords corresponding to N data words have been generated (e.g., resulting in N codewords), ECC system 185 utilizes the second encoding scheme to generate stripe parity data corresponding to multiple columns of bits from each of the N codewords. For example, ECC system 185 is configured to generate first parity data corresponding to the first stripe codeword by encoding a first portion of each of the N codewords. ECC system 185 generates a second stripe codeword by encoding a second portion of each of the N codewords. This process is repeated for each portion of the codeword.

[0058] The ECC system 185 also includes a first decoder that decodes data using a first decoding scheme and a second decoder that decodes data using a second decoding scheme. In one example, the first decoding scheme is an LDPC decoding scheme and the second decoding scheme is a RAID or XOR decoding scheme. In one example, the first decoding scheme is used to decode the generated codewords and the second decoding scheme is used to decode the stripe codewords.

[0059] In one example, when a codeword is decoded, the ECC system 185 may determine that the codeword contains various errors. In some examples, the number of errors may exceed the correction capability of the first decoding scheme. In another example, the number of failed codewords may exceed the correction capability of the first decoding scheme and / or the second decoding scheme. In such examples, a joint decoding scheme is used to correct the errors. In one example, the joint decoding scheme utilizes the first decoding scheme and the second decoding scheme to correct the various errors detected by the ECC system 185.

[0060] 3A illustrates, according to one example, how multiple pages in a stripe 300 are combined to form parity information 360. In one example, the pages in a stripe 300 are FMUs that are equivalent to codewords or portions of codewords encoded using a first encoding scheme.

[0061] For example, stripe 300 includes data corresponding to N pages: page 1 310, page 2 320, page 3 330, page 4 340, and page N 350. In this example, each of the pages are XORed together (e.g., during a write or encoding operation) to generate parity information 360 (represented as an XOR page) using a RAID or XOR type encoding scheme.

[0062] During a decoding operation, an ECC system (e.g., ECC system 185 (FIG. 1)) determines that two of the pages in stripe 300 did not decode successfully. For example, referring to FIG. 3B, FIG. 3B shows that page 2 320 and page 4 340 in stripe 300 failed the decoding process. In one example, the failed decoding process is an LDPC decoding process.

[0063] 3C illustrates how a joint decoding scheme is used to correct errors within a page of stripe 300, according to an example. For example, when the ECC system determines that page 2 320 and page 4 340 failed the decoding process and / or otherwise determines that the pages are uncorrectable, the ECC system implements a joint decoding scheme. For example, as shown in FIG. 3C, the ECC system determines the hard bits to be provided to LDPC decoder 390 and the two soft bits to be provided to LDPC decoder 390 when page 2 320 is decoded.

[0064] In one example, the hard bit (represented as HB in FIG. 3C) is a copy (e.g., an uncorrected copy) of page 2 320. The first soft bit (represented as soft bit page 380 or SB1) is the natural soft bit page (or soft bit representation) of page 2 320. The second soft bit (SB2) is an XOR representation of page 2 370.

[0065] For example, to generate an XOR representation of page 2 370, the ECC system XORs page 1 310, page 3 330, page 4 340, and page N 350 with parity information 360 (e.g., XOR page) generated when the data was written / encoded. Page 2 320, the XOR representation of page 2 370, and soft bit page 380 are provided to LDPC decoder 390 to generate corrected page 2 395.

[0066] In one example, if the ECC system determines that page 2 320 was successfully decoded (e.g., resulting in corrected page 2 395), then corrected page 2 395 is used by the ECC system to correct the error in page 4 340. This process is repeated for each failing page in the stripe.

[0067] However, in some instances, page 2 320 may not be successfully decoded during the initial iteration, so the ECC system attempts to decode and correct page 4 340 using similar operations. If the decoding and correction of page 4 340 is successful, the ECC system attempts to decode and correct page 2 320 using the now corrected page 4.

[0068] A detailed description of the joint decoding scheme is described in more detail in U.S. Pat. No. 9,940,194, entitled "ECC Decoding Using RAID-Type Parity," the entire disclosure of which is incorporated herein by reference in its entirety.

[0069] 1 , as briefly described above, ECC system 185 includes or is otherwise associated with ECC ordering system 180. ECC ordering system 180 determines one or more metrics associated with each failed FMU or page (e.g., page 2 320 ( FIG. 3B )) and, based on the one or more metrics, determines a schedule or order in which the pages are decoded and / or corrected using a joint decoding scheme. In one example, the schedule or order is based at least in part on the likelihood that the FMU will be decoded and corrected.

[0070] For example, ECC ordering system 180 may determine, based on one or more metrics associated with page 4 340 and page 2 320 (FIG. 3B), that page 4 340 is more likely to be corrected using parity information (e.g., an XOR page) compared to page 2 320. Thus, ECC ordering system 180 may cause a joint decoding scheme to be performed on page 4 340 before page 2 320.

[0071] In this example, page 4 340 is corrected by the joint decoding scheme. Therefore, the now corrected page 4 can be used to correct the error in page 2 320. Because page 4 340 has been corrected, it is more likely that page 2 320 will also be corrected by the joint decoding scheme.

[0072] Compared to current solutions, where multiple iterations may be required to determine whether one or more FMUs are correctable, the latency of the decoding operations associated with the present disclosure is reduced because the ordering of FMUs is based on the likelihood of success. Thus, if page 4 340 is not decodable and / or correctable using the joint decoding scheme, there may be no need to try and correct page 2 320 (e.g., because page 4 340 was not corrected). However, it is contemplated that even if the joint decoding scheme fails to correct the error in page 4 340, the joint decoding scheme may still be performed on page 2 320.

[0073] In one example, the metric is a syndrome weight associated with the FMU. The syndrome weight is an estimate of the underlying bit error rate (BER) of the FMU. For example, the syndrome weight identifies the number of errors correctable by the ECC system 185. Therefore, when determining the order in which the joint decoding scheme should be applied to various failed FMUs, the ECC ordering system 180 determines a syndrome weight for each failed FMU and orders the FMUs from the lowest syndrome weight to the highest syndrome weight. The ECC system 180 then begins the joint decoding scheme on the failed FMUs in the determined order.

[0074] In another example, the metric is based at least in part on the combined BER of the FMUs. In one example, the combined BER of the FMUs is based at least in part on the quality of the decoded FMUs and the quality of the soft bit information (e.g., page 2 370 or SB2 (FIG. 3C)) generated from all the FMUs in the stripe.

[0075] For example, referring back to Figure 3C, the combined BER associated with page 2 320 is determined by combining page 2 320 with an XOR representation of page 2 370. Once the combined BER is determined for each FMU, ECC ordering system 180 begins a joint decoding operation using the combined BER.

[0076] In one example, the combined BER of the failed FMU is determined by measuring the syndrome weight of the failed FMU. Once the syndrome weight is determined, the BER of the failed FMU is XOR In one example, the BER of the failed FMU is determined. XOR is the formula BER XOR =1 / 2·(1-(1-2·BER) t-1 ), where t is the number of failures in the XOR page.

[0077] BER XOR Once σ is determined, the ECC ordering system 180 uses the syndrome weight to estimate the BER of the failed FMU. For example, the syndrome weight of the failed FMU is σ=½Q -1 is used to derive the Gaussian sigma of the BER using the Gaussian distribution assumption for sigma ("σ"), where

[0078]

number

[0079] In one example, the soft bit page of a failed FMU is generated by reading ±delta ("Δ") around the hard bit level associated with the failed FMU. In one example, delta indicates the number of cells within the soft bit region and the number of cells outside the soft bit region. For example, delta indicates the number of reliable bits and the number of unreliable bits. Therefore, BER1 = α BER HIGH +(1-α) BER LOW =Q(1 / 2σ).

[0080] When the BER is estimated, alpha (“α”) is calculated from the syndrome weights and the Gaussian distribution. In one example, α is calculated using the following formula:

[0081]

number

[0082] If α is calculated, the BER HIGH and BER LOW is the expression

[0083]

number

[0084] The ECC ordering system then determines α, BER using the following formula: LOW , and BER XOR Calculate the joint BER from

[0085]

number

[0086] 4A illustrates how multiple pages within a stripe 400 are combined to form parity information 460, according to one example. In one example, the pages within stripe 400 are combined in a manner similar to the pages within stripe 300 shown and described with respect to FIG. 3A. For example, stripe 400 includes data corresponding to N pages: page 1 410, page 2 420, page 3 430, page 4 440, and page N 450. Each of the pages is XORed together (e.g., during a write or encode operation) to generate parity information 460.

[0087] Similar to the example shown and described with respect to Figure 3B, during the decode operation, an ECC system (e.g., ECC system 185 (Figure 1)) determines that two of the pages in stripe 400 failed the initial decode operation and / or are uncorrectable using the first or second decode schemes. For example, referring to Figure 4B, Figure 4B shows that page 2 420 and page 4 440 failed the decode operation.

[0088] When the ECC system determines that pages in a stripe failed the initial decoding operation, the ECC ordering system generates or otherwise determines one or more metrics associated with each failed page. For example, as described above, the ECC ordering system determines a BER associated with each failed page. In another example, the ECC ordering system determines a combined BER associated with each failed page.

[0089] Once the one or more metrics associated with each failed page have been determined, the ECC ordering system generates a schedule 415 based on the one or more metrics associated with each failed page. For example, the ECC ordering system compares metric N 425 associated with page 4 440 with metric M associated with page 2 420 and, based on the comparison, determines that page 4 440 has a higher likelihood of being successfully decoded when compared to page 2 420. Thus, when a joint decoding scheme is performed on the failed pages, page 4 440 will be decoded before page 2 420.

[0090] 4C illustrates how a joint decoding scheme is used to correct errors within pages of stripe 400 based on the determined metrics, according to one example. For example, when the ECC system determines that page 2 420 and page 4 440 failed the initial decoding process and / or otherwise determines that the pages are uncorrectable, the ECC system implements the joint decoding scheme in an order determined by schedule 415.

[0091] For example, because page 4 440 is more likely to be successfully decoded, the ECC system provides an uncorrected copy of page 4 420 to the LDPC decoder 490. The ECC system also provides a first soft bit (represented as soft bit page 480 or SB1) to the LDPC decoder 490. As previously described, soft bit page 480 is the natural soft bit page read from memory (or soft bit representation) of page 4 400. The ECC system also provides a second soft bit page (SB2) to the LDPC decoder 490. In one example, the second soft bit page is an XOR representation of page 4 470.

[0092] If the LDPC successfully decodes and / or corrects page 4 440, the process is repeated with page 2 420. However, in some examples, if page 4 440 is not successfully decoded, the ECC system does not attempt to decode and / or correct page 2 420. In other examples, even if page 4 440 is not corrected, the ECC system still attempts to decode and / or correct page 2 420. However, in such examples, the ECC system does not attempt to decode page 4 440 a second time. For example, the ECC system may implement a "one-shot" joint decoding scheme in which the ECC system attempts to recover each failed page once.

[0093] 5 illustrates a method 500 for performing a joint decoding scheme on two or more FMUs of a stripe, according to one example. In one example, method 500 is performed by an ECC system and / or an ECC ordering system of a data storage device. For example, method 500 is performed by ECC system 185 and / or ECC ordering system 180 shown and described with respect to FIG. 1. Furthermore, in one example, method 500 is performed on pages of stripe 400 shown and described with respect to FIG. 4A.

[0094] Method 500 begins when the ECC system identifies 510 two or more FMUs in a stripe that failed an initial decoding process. For example, the ECC system identifies two or more FMUs that failed an initial decoding process performed by a first decoding scheme (e.g., an LDPC decoding scheme). In another example, the ECC system identifies two or more FMUs that have a BER above a threshold or are otherwise identified as containing errors and / or uncorrectable.

[0095] Based at least in part on identifying the two or more failed FMUs, the ECC system determines one or more metrics associated with each failed FMU (520). In one example, the one or more metrics indicate a syndrome weight or BER associated with each failed FMU. In another example, the one or more metrics indicate a combined BER associated with each failed FMU. In one example, the combined BER is determined using various operations described herein.

[0096] Once the one or more metrics associated with each failed FMU are determined, the ECC system generates a decoding schedule or otherwise orders the failed FMUs based on the determined metric(s) (530). In one example, the one or more metrics associated with each failed FMU indicate a likelihood or probability that the failed FMU will be successfully decoded during the joint decoding scheme. As previously described, in one example, the joint decoding scheme utilizes a first decoding scheme (e.g., an LDPC decoding scheme) and a second decoding scheme (e.g., a RAID or XOR decoding scheme).

[0097] The ECC system also initiates a joint decoding scheme for the failed FMUs based on the determined decoding schedule (540). For example, if one or more metrics indicate that a first FMU is more likely to be successfully decoded using the joint decoding scheme compared to a second FMU, the ECC system causes the joint decoding scheme to be performed on the first FMU.

[0098] If the joint decoding scheme was performed on the failed FMU, the ECC system determines whether the FMU was successfully decoded (550). If the ECC system determines that the FMU was not successfully decoded, the ECC system terminates the current decoding operation (560). For example, because the failed FMUs are ordered from most likely to be decoded to least likely to be decoded, if the joint decoding scheme fails to decode the failed FMU, there is no need to continue attempting to decode the other failed FMUs because they are less likely to be decoded. However, in other examples, even if the FMU is not successfully decoded, method 500 is repeated for the other failed FMUs.

[0099] However, if the ECC system determines (550) that the FMU was successfully decoded, the ECC system also determines (570) whether the decoding schedule includes additional FMUs that failed the initial decoding process. If the ECC system determines that there are other FMUs in the schedule that need to be decoded, the ECC system begins (540) the joint decoding scheme for the next FMU in the schedule, and the process is repeated. In one example, the newly decoded FMU is available for use in subsequent joint decoding operations.

[0100] However, if the ECC system determines (570) that there are no more failed FMUs in the decoding schedule, the ECC system terminates (560) the current decoding operation.

[0101] 6-7 illustrate example storage devices that may be used with or otherwise implement various features described herein. For example, the storage devices shown and described with respect to FIGS. 6-7 may include various systems and components similar to the systems and components shown and described with respect to FIG. 1. For example, the controller 722 shown and described with respect to FIG. 7 may be similar to the controller 150 of FIG. 1. Similarly, the memory die 708 may be similar to the first memory die 165 and / or the second memory die 170 of FIG. 1.

[0102] 6 is a perspective view of a storage device 600 including three-dimensional (3D) stacked nonvolatile memory according to one example. In this example, storage device 600 includes a substrate 610. Blocks of memory cells are included on or above substrate 610. The blocks include a first block (BLK0 620) and a second block (BLK1 630). Each block is made up of memory cells (e.g., nonvolatile memory elements). Substrate 610 also includes a peripheral region 640 having support circuitry used by the first and second blocks.

[0103] The substrate 610 also carries circuitry beneath the blocks, with one or more lower metal layers patterned into conductive paths to carry signals from the circuitry. In one example, the blocks are formed in a middle region 650 of the storage device 600. The storage device also includes an upper region 660. The upper region 660 includes one or more upper metal layers patterned into conductive paths to carry signals from the circuitry. Each block of memory cells includes a stack of memory cells. In one example, alternating levels of the stack represent word lines. While two blocks are shown, additional blocks may be used and may extend in the x and / or y directions.

[0104] In one example, the length of the plane of the substrate 610 in the x-direction represents the direction in which signal paths for word lines or control gate lines extend (e.g., word line or drain-end select gate (SGD) line direction), and the width of the plane of the substrate 610 in the y-direction represents the direction in which signal paths for bit lines extend (e.g., bit line direction). The z-direction represents the height of the storage device 600.

[0105] FIG. 7 is a functional block diagram of a storage device 700 according to one example. In one example, the storage device 700 is similar to the 3D stacked nonvolatile storage device 600 shown and described with respect to FIG. 6. In one example, the components shown in FIG. 7 are electrical circuits. In one example, the storage device 700 includes one or more memory dies 705. Each memory die 705 includes a three-dimensional memory structure 710 of memory cells (e.g., a 3D array of memory cells), control circuitry 715, and read / write circuitry 720. In another example, a two-dimensional array of memory cells may be used. The memory structure 710 is addressable by word lines using a first decoder 725 (e.g., a row decoder) and by bit lines using a second decoder 730 (e.g., a column decoder). The read / write circuitry 720 may also include multiple sense blocks 735 including SB1, SB2, ..., SBp (e.g., sense circuits) that allow a page of memory cells to be read or programmed in parallel. The sense blocks 735 may include bit line drivers.

[0106] In one example, the controller 740 is included in the same storage device 700 as one or more memory dies 705. In another example, the controller 740 is formed on a die bonded to the memory dies 705, in which case each memory die 705 can have its own controller 740. In yet another example, the controller die controls all of the memory dies 705. Although a single controller 740 is shown, the storage device 700 can include multiple controllers, each responsible for a different operation as described herein.

[0107] Commands and data are transferred between host 745 and controller 740 using data bus 750. Additionally, commands and data are transferred between controller 740 and one or more of memory dies 705 via lines 755. In one example, memory die 705 includes a set of input and / or output (I / O) pins that connect to lines 755.

[0108] The memory structure 710 also includes one or more arrays of memory cells. The memory cells may be arranged in a three-dimensional array or a two-dimensional array. The memory structure 710 includes any type of non-volatile memory formed on one or more physical levels of an array of memory cells with active regions disposed above a silicon substrate. The memory structure 710 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0109] Control circuitry 715 operates in conjunction with read / write circuitry 720 to perform memory operations (e.g., erase, program, read, etc.) on memory structure 710. Control circuitry 715 may include registers, ROM fuses, and other devices for storing default values ​​such as base voltages and other parameters.

[0110] The control circuitry 715 also includes a state machine 760, an on-chip address decoder 765, and a power control module. The state machine 760 provides chip-level control of various memory operations, such as selecting memory blocks for programming. The state machine 760 is programmable by software. In another example, the state machine 760 is implemented entirely in hardware (e.g., electrical circuitry) without the use of software.

[0111] An on-chip address decoder 765 provides an address interface between addresses used by the host 745 and / or controller 740 and hardware addresses used by the first decoder 725 and second decoder 730. A power control module 770 controls the power and voltages supplied to the word lines and bit lines during memory operations. The power control module 770 may include drivers for the word line layers, select transistors (e.g., SGS and SGD transistors), and source lines in a 3D configuration. The power control module 770 may include one or more charge pumps to generate voltages.

[0112] The control circuit 715, state machine 760, on-chip address decoder 765, first decoder 725, second decoder 730, power control module 770, sensing block 735, read / write circuit 720, and / or controller 740 may be considered one or more control circuits and / or management circuits that perform some or all of the operations described herein.

[0113] In one example, the controller 740 is an electrical circuit that may be on-chip or off-chip. Additionally, the controller 740 may include one or more processors 780, ROM 785, RAM 790, a memory interface 795, and a host interface 797, all of which may be interconnected. In one example, the one or more processors 780 are an example of control circuitry. Other examples may use state machines or other custom circuits designed to perform one or more functions. Devices such as the ROM 785 and RAM 790 may contain code, such as a set of instructions. One or more of the processors 780 may be operable to execute a set of instructions to provide some or all of the functionality described herein.

[0114] Alternatively or additionally, one or more of the processors 780 can access code from a memory device in the memory structure 710, such as a reserved area of ​​memory cells connected to one or more word lines. A memory interface 795, which communicates with one or more of the ROM 785, RAM 790, and processors 780, can be an electrical circuit that provides an electrical interface between the controller 740 and the memory die 705. For example, the memory interface 795 can change the format or timing of signals, provide buffers, isolate from surges, latch I / O, etc.

[0115] The one or more processors 780 can issue commands to the control circuitry 715 or any other components of the memory die 705 using the memory interface 795. A host interface 797, which communicates with the ROM 785, RAM 790, and one or more processors 780, can be an electrical circuit that provides an electrical interface between the controller 740 and the host 745. For example, the host interface 797 can change the format or timing of signals, provide buffers, isolate from surges, latch I / O, etc. Commands and data from the host 745 are received by the controller 740 via the host interface 797. Data sent to the host 745 can be transmitted using a data bus 750.

[0116] The memory elements in memory structure 710 can be configured so that they are connected in series or so that each element is individually accessible. As a non-limiting example, a NAND-configured flash memory device (e.g., NAND flash memory) typically includes memory elements connected in series. A NAND string is an example of a set of serially connected memory cells and select gate transistors.

[0117] NAND flash memory arrays can also be configured so that the array contains multiple NAND strings. In one example, a NAND string contains multiple memory cells that share a single bit line and are accessed as a group. Alternatively, the memory elements may be configured so that each memory element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory cells may have other configurations.

[0118] The memory cells may be arranged in an ordered array, such as multiple rows and / or columns, in a single memory device level. However, the memory elements may also be arranged in irregular or non-orthogonal configurations, or in structures that are not considered arrays.

[0119] In one example, a 3D memory structure can be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to a major surface of a substrate, such as in the y direction), with each column having multiple memory cells. The vertical columns can be arranged in a two-dimensional arrangement of memory cells, with the memory cells residing on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also be used to construct a 3D memory array.

[0120] In another example, in a 3D NAND memory array, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other 3D configurations can be contemplated, with some NAND strings containing memory elements at a single memory level and other strings containing memory elements across multiple memory levels. 3D memory arrays can also be designed with NOR and ReRAM configurations.

[0121] Based on the above, an example of the present disclosure describes a method including identifying two or more flash memory units (FMUs) associated with a data storage device that failed an initial decoding operation performed by an error code correction system of the data storage device, determining a metric associated with each of the two or more FMUs, generating a decoding schedule for the two or more FMUs based at least in part on the metric associated with each of the two or more FMUs, and performing a joint decoding operation on a first FMU of the two or more FMUs based on the generated decoding schedule using a joint decoding scheme, the joint decoding scheme including a first decoding scheme and a second decoding scheme. In one example, the first decoding scheme is a low-density parity check (LDPC) decoding scheme. In one example, the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme. In one example, the method also includes determining whether the joint decoding operation on the first FMU of the two or more FMUs was successful, and performing the joint decoding operation on a second FMU of the two or more FMUs based at least in part on determining that the joint decoding operation on the first FMU of the two or more FMUs was successful. In one example, the method also includes determining whether the joint decoding operation on a first FMU of the two or more FMUs was successful, and terminating the joint decoding operation based at least in part on determining that the joint decoding operation on the first FMU of the two or more FMUs was unsuccessful. In one example, the metric is a syndrome weight associated with each FMU of the two or more FMUs. In one example, the metric is a combined bit error rate (BER) associated with each FMU of the two or more FMUs. In one example, each FMU of the two or more FMUs is associated with a stripe.

[0122] Another example describes a data storage device comprising: a controller; and an error correcting code (ECC) system associated with the controller, wherein the ECC system is operable to: perform an initial decoding operation on flash memory units (FMUs) associated with a stripe; determine whether any FMUs failed the initial decoding operation; determine a metric associated with each of the two or more FMUs based at least in part on determining that two or more FMUs failed the initial decoding operation; determine an order in which each of the two or more FMUs will undergo the joint decoding operation using a joint decoding scheme based at least in part on the metric associated with each of the two or more FMUs, the joint decoding scheme including a first decoding scheme and a second decoding scheme; and perform the joint decoding operation on the two or more FMUs in the determined order. In one example, the ECC system is further operable to determine whether the joint decoding operation on a first FMU of the two or more FMUs was successful; and perform the joint decoding operation on a second FMU of the two or more FMUs based at least in part on determining that the joint decoding operation on the first FMU of the two or more FMUs was successful. In one example, the ECC system is further operable to determine whether the joint decoding operation on a first FMU of the two or more FMUs was successful and to terminate the joint decoding operation based at least in part on a determination that the joint decoding operation on the first FMU of the two or more FMUs was unsuccessful. In one example, the first decoding scheme is a low-density parity check (LDPC) decoding scheme. In one example, the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme. In one example, the metric is a syndrome weight associated with each FMU of the two or more FMUs. In one example, the metric is a combined bit error rate (BER) associated with each FMU of the two or more FMUs.

[0123] An example also describes a data storage device comprising: control means; and error correction means associated with the control means, wherein the error correction means is operable to: determine whether two or more memory means associated with the data storage device failed an initial decoding operation; determine a first metric associated with a first memory means of the two or more memory means based at least in part on a determination that the two or more memory means failed the initial decoding operation; determine a second metric associated with a second memory means of the two or more memory means; compare the first metric and the second metric; generate a decoding schedule based at least in part on comparing the first metric and the second metric; and perform a joint decoding operation on at least one of the first memory means and the second memory means using a joint decoding scheme based at least in part on the decoding schedule, wherein the joint decoding scheme includes the first decoding scheme and the second decoding scheme. In one example, the error correction means is further operable to determine whether the joint decoding operation on at least one of the first memory means and the second memory means was successful, and to perform the joint decoding operation on another memory means based at least in part on the determination that the joint decoding operation on at least one of the first memory means and the second memory means was successful. In one example, the error correction means is further operable to determine whether the joint decoding operation on at least one of the first memory means and the second memory means was successful, and to terminate the joint decoding operation based at least in part on the determination that the joint decoding operation on at least one of the first memory means and the second memory means was unsuccessful. In one example, the first decoding scheme is a low-density parity check (LDPC) decoding scheme and the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme. In one example, the metric is a combined bit error rate (BER) associated with each of the two or more failed memory means.

[0124] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, but rather encompass many related memory structures that are within the spirit and scope of the techniques as described herein and as understood by those skilled in the art.

[0125] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of the disclosure in any way. The aspects, examples, and details provided in this disclosure are believed to be sufficient to convey ownership and to enable others to make and use the best mode of the claimed disclosure.

[0126] The claimed disclosure should not be construed as limited to any aspect, example, or detail provided in this disclosure. Whether shown and described in combination or separately, various features (both structural and methodological) are intended to be selectively rearranged, included, or omitted to produce embodiments having a particular set of features. While explanations and examples of the present disclosure have been provided, those skilled in the art may envision variations, modifications, and alternative embodiments that are within the spirit of the broader aspects of the general inventive concepts embodied in this disclosure without departing from the broader scope of the claimed disclosure.

[0127] Aspects of the present disclosure are described above with reference to schematic flowchart illustrations and / or schematic block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the present disclosure. It will be understood that each block of the schematic flowchart illustrations and / or schematic block diagrams, and combinations of blocks in the schematic flowchart illustrations and / or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, when executed by the processor or other programmable data processing apparatus, create means for implementing the functions and / or acts specified in the blocks of the schematic flowchart illustrations and / or schematic block diagrams.

[0128] References to elements herein using designations such as "first," "second," etc. generally do not limit the quantity or order of those elements. Rather, these designations may be used as a way of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element precedes the second element. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0129] When used in the description or claims, terms of the form "at least one of A, B, or C," or "A, B, C, or any combination thereof," mean "A or B or C, or any combination of these elements." For example, the terms can include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As a further example, "at least one of A, B, or C" is intended to include A, B, C, AB, AC, BC, and ABC, as well as multiples of the same member. Similarly, "at least one of A, B, and C" is intended to include A, B, C, AB, AC, BC, and ABC, as well as multiples of the same member.

[0130] Similarly, as used herein, a phrase referring to a list of items linked with "and / or" refers to any combination of the items. By way of example, "A and / or B" is intended to include A only, B only, or a combination of A and B. As another example, "A, B, and / or C" is intended to include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, or a combination of A, B, and C.

Claims

1. 1. A method comprising: Identifying two or more flash memory units (FMUs) associated with a data storage device that failed an initial decoding operation performed by an error code correction system of the data storage device; determining a metric associated with each of the two or more FMUs; generating a decoding schedule for the two or more FMUs based at least in part on the metrics associated with each of the two or more FMUs; performing a joint decoding operation on a first FMU of the two or more FMUs based on the generated decoding schedule using a joint decoding scheme, wherein the joint decoding scheme includes a first decoding scheme and a second decoding scheme.

2. The method of claim 1 , wherein the first decoding scheme is a low-density parity-check (LDPC) decoding scheme.

3. The method of claim 1 , wherein the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme.

4. determining whether the joint decoding operation for the first FMU of the two or more FMUs was successful; performing the joint decoding operation on a second FMU of the two or more FMUs based at least in part on determining that the joint decoding operation on the first FMU of the two or more FMUs is successful; and The method of claim 1 further comprising:

5. determining whether the joint decoding operation for the first FMU of the two or more FMUs was successful; terminating the joint decoding operation based at least in part on determining that the joint decoding operation for the first FMU of the two or more FMUs was unsuccessful; and The method of claim 1 further comprising:

6. The method of claim 1 , wherein the metric is a syndrome weight associated with each FMU of the two or more FMUs.

7. The method of claim 1 , wherein the metric is a combined bit error rate (BER) associated with each FMU of the two or more FMUs.

8. The method of claim 1 , wherein each FMU of the two or more FMUs is associated with a stripe.

9. 1. A data storage device comprising: A controller; an error correction code (ECC) system associated with the controller; The ECC system comprises: performing an initial decryption operation on a flash memory unit (FMU) associated with the stripe; determining whether any FMU failed the initial decoding operation; based at least in part on determining that two or more FMUs failed the initial decoding operation; determining a metric associated with each of the two or more FMUs; determining, based at least in part on the metric associated with each of the two or more FMUs, an order in which each of the two or more FMUs is to undergo a joint decoding operation using a joint decoding scheme, the joint decoding scheme including a first decoding scheme and a second decoding scheme; performing the joint decoding operation on the two or more FMUs in the determined order; 1. A data storage device operable to:

10. The ECC system includes: determining whether the joint decoding operation for a first FMU of the two or more FMUs was successful; performing the joint decoding operation on a second FMU of the two or more FMUs based at least in part on a determination that the joint decoding operation on the first FMU of the two or more FMUs is successful; 10. The data storage device of claim 9, further operable to:

11. The ECC system includes: determining whether the joint decoding operation for a first FMU of the two or more FMUs was successful; terminating the joint decoding operation based at least in part on a determination that the joint decoding operation for the first FMU of the two or more FMUs was unsuccessful.

10. The data storage device of claim 9, further operable to:

12. The data storage device of claim 9 , wherein the first decoding scheme is a low-density parity check (LDPC) decoding scheme.

13. The data storage device of claim 9 , wherein the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme.

14. The data storage device of claim 9 , wherein the metric is a syndrome weight associated with each FMU of the two or more FMUs.

15. 10. The data storage device of claim 9, wherein the metric is a combined bit error rate (BER) associated with each FMU of the two or more FMUs.

16. 1. A data storage device comprising: a control means; error correction means associated with said control means; The error correction means comprises: determining whether two or more memory means associated with said data storage device failed an initial decryption operation; based at least in part on a determination that two or more memory means failed the initial decoding operation; determining a first metric associated with a first memory means of said two or more memory means; determining a second metric associated with a second memory means of said two or more memory means; comparing the first metric with the second metric; generating a decoding schedule based at least in part on comparing the first metric to the second metric; a data storage device operable to perform a joint decoding operation on at least one of the first memory means and the second memory means using a joint decoding scheme based at least in part on the decoding schedule, the joint decoding scheme including a first decoding scheme and a second decoding scheme.

17. The error correction means determining whether the joint decoding operation on the at least one of the first memory means and the second memory means was successful; performing the joint decoding operation on another memory means based at least in part on a determination that the joint decoding operation on the at least one of the first memory means and the second memory means was successful.

17. The data storage device of claim 16, further operable to:

18. The error correction means determining whether the joint decoding operation on the at least one of the first memory means and the second memory means was successful; terminating the joint decoding operation based at least in part on a determination that the joint decoding operation for the at least one of the first memory means and the second memory means was unsuccessful.

17. The data storage device of claim 16, further operable to:

19. 17. The data storage device of claim 16, wherein the first decoding scheme is a low-density parity check (LDPC) decoding scheme and the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme.

20. 17. The data storage device of claim 16, wherein the metric is a combined bit error rate (BER) associated with each of the two or more failed memory means.

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