Semiconductor element and manufacturing method for the same

Abstract

To provide a semiconductor element whose reliability and electric characteristics are improved, and a manufacturing method for the same.SOLUTION: A semiconductor element according to the present invention includes a substrate, a channel layer existing on the substrate, a gate structure surrounding the channel layer, source / drain patterns connected to both sides of the channel layer, a lower wiring structure existing below the substrate, and an insulating pattern existing between the source / drain patterns below the gate structure through the substrate. The insulating pattern includes a sub-insulating pattern existing below the gate structure, and a main insulating pattern existing between the sub-insulating pattern and the lower wiring structure. The sub-insulating pattern and the main insulating pattern include different insulating materials.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Semiconductor devices are used in various electronic devices, such as data storage devices and data processing processors. With the development of the electronics industry, various methods are being researched to improve the various characteristics of semiconductor devices, such as their integration density, reliability, speed, and functionality. For example, semiconductor devices with three-dimensional structures have been proposed to overcome the limitations imposed by the size reduction of semiconductor devices.

[0003] Recently, research has been conducted to improve routing congestion and scale the size of semiconductor elements by placing a power delivery network for routing signals provided to semiconductor elements on the backside of a substrate. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor element having improved reliability and improved electrical characteristics, and a method for manufacturing the same. [Means for solving the problem]

[0005] In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes a substrate, a channel layer located on the substrate, a gate structure surrounding the channel layer, source / drain patterns respectively connected to both sides of the channel layer, a lower wiring structure located below the substrate, and an insulating pattern penetrating the substrate and located below the gate structure and between the source / drain patterns, wherein the insulating pattern includes a sub-insulating pattern located below the gate structure and a main insulating pattern located between the sub-insulating pattern and the lower wiring structure, and the sub-insulating pattern and the main insulating pattern comprise different insulating materials.

[0006] In order to achieve the above object, according to one aspect of the present invention, a method for manufacturing a semiconductor device includes the steps of: forming a channel layer on a substrate, a gate structure surrounding the channel layer, and source / drain patterns respectively connected to both sides of the channel layer; forming an insulation pattern including a sub-insulation pattern and a main insulation pattern below the gate structure and penetrating the substrate; and forming a lower wiring structure below the substrate, wherein the step of forming the insulation pattern includes the steps of forming a trench through the substrate adjacent to a lower surface of the gate structure, forming a sub-insulation pattern between the trench and the gate structure, and forming a main insulation pattern filling the inside of the trench, wherein the sub-insulation pattern and the main insulation pattern include different insulating materials.

[0007] According to another aspect of the present invention, a semiconductor device is provided, which includes a lower pattern, a channel layer located on the lower pattern, a gate structure surrounding the channel layer, source / drain patterns connected to both sides of the channel layer, a lower wiring structure located below the lower pattern, a through electrode penetrating the lower pattern and located between at least a portion of the source / drain pattern and the lower wiring structure, and an insulating liner located between a side of the through electrode and the lower pattern, wherein the insulating liner has a lower nitrogen concentration as it extends away from the side of the through electrode in a direction toward the lower pattern. [Effects of the Invention]

[0008] According to the present invention, at least a portion of an insulating pattern located between two source / drain patterns can be formed by a nitridation process, and other insulating layers can be prevented from being damaged by etching materials during an etching process for forming the insulating pattern, thereby improving the reliability of a semiconductor device.

[0009] Furthermore, an insulating liner film between the rear contact electrode and the substrate can be formed by a nitridation process, which increases the volume of the rear contact electrode compared to existing processes and improves the electrical characteristics of the semiconductor device. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view illustrating a semiconductor device according to an embodiment. [Figure 2] 2 is a cross-sectional view of a first example of a semiconductor element taken along line I1-I1' in FIG. [Figure 3] 2 is a cross-sectional view of a first example of a semiconductor element taken along line I2-I2' in FIG. [Figure 4] FIG. 4 is a cross-sectional view illustrating a second example of a semiconductor device according to an embodiment. [Figure 5]FIG. 4 is a cross-sectional view illustrating a second example of a semiconductor device according to an embodiment. [Figure 6] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] 2A to 2C are diagrams illustrating a first example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] FIG. 10 is a plan view illustrating a third example of a semiconductor device according to an embodiment. [Figure 16] 1. FIG. 3 is a cross-sectional view of a third example of the semiconductor element taken along line I3-I3′ in FIG. [Figure 17] FIG. 14 is a cross-sectional view of a third example of the semiconductor element taken along line I4-I4′ in FIG. [Figure 18] 15. FIG. 16 is a cross-sectional view of a third example of the semiconductor element taken along line I5-I5' in FIG. [Figure 19] FIG. 10 is a cross-sectional view illustrating a fourth example of a semiconductor device according to an embodiment. [Figure 20] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 21] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 22]10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 23] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 24] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 26] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 27] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 28] 10A to 10C are views for explaining a third example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 29] FIG. 10 is a plan view illustrating a fifth example of a semiconductor device according to an embodiment. [Figure 30] FIG. 30 is a cross-sectional view of a fifth example of the semiconductor element taken along line I6-I6′ in FIG. 29. [Figure 31] FIG. 30 is a cross-sectional view of a fifth example of the semiconductor element taken along line I7-I7′ in FIG. 29. [Figure 32] FIG. 30 is a cross-sectional view of a fifth example of the semiconductor element taken along line I8-I8' in FIG. 29. [Figure 33] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 34] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 35] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 36] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 37] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 38] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 39] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 40] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 41] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. [Figure 42] 10A to 10C are views for explaining a fifth example of a manufacturing method for a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings, in which: FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention; FIG. 2 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention; FIG. 3 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention;

[0012] In order to clearly describe the present invention, parts that are not relevant to the description will be omitted and the same reference numerals will be used throughout the specification to refer to the same or similar components.

[0013] Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, thicknesses are exaggerated to clearly show multiple layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for the convenience of explanation.

[0014] Furthermore, when a layer, film, region, plate, or other part is said to be "on" or "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in the middle. Furthermore, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" or "above" the direction opposite to gravity.

[0015] Furthermore, throughout the specification, when a part "comprises" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified.

[0016] Furthermore, throughout this specification, "on a plane" means when the target part is viewed from above, and "on a cross section" means when the target part is cut vertically and viewed from the side.

[0017] In the drawings relating to semiconductor devices according to embodiments, examples include Gate All Around (GAA) and MBCFETs including nanowires or nanosheets. TM Although a multi-bridge channel field effect transistor (FinFET) is shown, the present invention is not limited thereto. Depending on the embodiment, the semiconductor device may include a fin-type transistor (FinFET) including a channel region of a fin-type pattern, a tunneling transistor (tunneling FET), a 3D-SFET (3D stack field effect transistor) structure, or a CFET (Complementary Field Effect Transistor) structure.

[0018] Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings.

[0019] Fig. 1 is a plan view showing a semiconductor device according to an embodiment. Fig. 2 and Fig. 3 are cross-sectional views showing a first example of a semiconductor device according to an embodiment. Specifically, Fig. 2 is a cross-sectional view of the first example of the semiconductor device taken along line I1-I1' in Fig. 1, and Fig. 3 is a cross-sectional view of the first example of the semiconductor device taken along line I2-I2' in Fig. 1.

[0020] 1 to 3, the semiconductor device according to this embodiment includes a substrate 10, a channel layer (CH) located on the substrate 10, a gate structure (GS) surrounding the channel layer (CH), source / drain patterns 150 located on both sides of each channel layer (CH), a lower wiring structure 410 located below the substrate 10, and an insulating pattern 210 located between the source / drain patterns 150 below the gate structure (GS).

[0021] The substrate 10 may be silicon-on-insulator (SOI) or bulk silicon, or alternatively, the substrate 10 may be a silicon substrate or other materials, including, but not limited to, silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0022] In other embodiments, substrate 10 is an insulating substrate. Substrate 10 may include an oxide, a nitrate, an oxynitride, or a combination thereof. For example, substrate 10 may include silicon nitride (SiNx). Although substrate 10 is shown as being a single film, this is for convenience of explanation and is not intended to be limiting.

[0023] The first and second surfaces of the substrate 10 are formed by planes parallel to a first direction (D1) and a second direction (D2) intersecting the first direction (D1). For example, the first surface of the substrate 10 is the top surface, and the second surface is the bottom surface. The top surface of the substrate 10 is opposite the bottom surface of the substrate 10 in a third direction (D3). The third direction (D3) is perpendicular to the first direction (D1) and the second direction (D2). The bottom surface of the substrate 10 is referred to as the back side of the substrate 10. In some embodiments, logic circuits in the cell region are implemented on the top surface of the substrate 10.

[0024] The semiconductor device according to this embodiment further includes a lower pattern (BP) located on the substrate 10. The lower pattern (BP) is a portion protruding in a third direction (D3) from the first surface of the substrate 10. The lower pattern (BP) is formed by etching a portion of the substrate 10 and is grown from the substrate 10 by an epitaxial growth method.

[0025] The lower patterns (BP) extend in a first direction (D1). The lower patterns (BP) are arranged spaced apart in a second direction (D2) on the first surface of the substrate 10. Source / drain patterns 150, which will be described later, are located on the lower patterns (BP). The source / drain patterns 150 are arranged spaced apart in the first direction (D1) on each lower pattern (BP).

[0026] The lower pattern (BP) includes an elemental semiconductor material such as silicon (Si) or germanium (Ge). Alternatively, the lower pattern (BP) may include a compound semiconductor. For example, the lower pattern (BP) includes a IV-IV compound semiconductor or a III-V compound semiconductor. The IV-IV compound semiconductor is, for example, a binary compound or a ternary compound including carbon (C), silicon (Si), germanium (Ge), tin (Sn), or a combination thereof. The III-V compound semiconductor is, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining a group III element such as aluminum (Al), gallium (Ga), indium (In), or a combination thereof with a group V element such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof.

[0027] The channel layer (CH) is located on the first surface of the substrate 10. As shown in FIGS. 2 and 3, when a lower pattern (BP) is located on the substrate 10, the channel layer (CH) is located on the lower pattern (BP). The channel layers (CH) are arranged spaced apart in the first direction (D1) on the substrate 10 and / or the lower pattern (BP). Each channel layer (CH) includes a plurality of semiconductor layers (110a, 110b, 110c, 110d) arranged spaced apart from each other in the third direction (D3). As an example, each of the plurality of semiconductor layers (110a, 110b, 110c, 110d) has a sheet shape. Each semiconductor layer is a nanosheet having a thickness of several nanometers along the third direction (D3).

[0028] The channel layer (CH) provides a path through which current flows between source / drain patterns 150, which will be described later. Referring to FIGS. 2 and 3, the channel layer (CH) is disposed between the source / drain patterns 150 and connects the source / drain patterns 150. The channel layer (CH) extends in a direction (e.g., a first direction (D1)) intersecting the direction in which the gate structure (GS), which will be described later, extends, and penetrates a portion of the gate structure (GS). In FIGS. 2 and 3, the channel layer (CH) is shown as having four semiconductor layers (110a, 110b, 110c, and 110d) arranged spaced apart in a third direction (D3), but is not limited thereto, and the number of stacked semiconductor layers (110a, 110b, 110c, and 110d) included in one channel layer (CH) may be variously changed.

[0029] The channel layer (CH) includes a semiconductor material. For example, the channel layer (CH) includes a Group IV semiconductor such as Si or Ge, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. In this embodiment, a lower pattern (BP) is located below the channel layer (CH). Specifically, the lower pattern (BP) is located between the substrate 10 and a lowermost sub-gate structure (S_GS) among a plurality of sub-gate structures (S_GS) described below. An upper surface of the lower pattern (BP) contacts a lower surface of the lowermost sub-gate structure (S_GS) among the plurality of sub-gate structures (S_GS).

[0030] 2 and 3, the semiconductor device does not include the lower pattern (BP). In this case, the lower surface of the lowermost sub-gate structure (S_GS) of the sub-gate structures (S_GS) is in direct contact with the substrate 10.

[0031] The semiconductor device according to this embodiment further includes a field insulating layer 105 disposed on the substrate 10. The field insulating layer 105 is disposed on the lower pattern (BP). The field insulating layer 105 is disposed on the side surfaces of the lower pattern (BP). The field insulating layer 105 is not disposed on the upper surface of the lower pattern (BP). The field insulating layer 105 entirely covers the side surfaces of the lower pattern (BP). Alternatively, unlike the illustrated example, the field insulating layer 105 may cover only a portion of the side surfaces of the lower pattern (BP). In such a case, a portion of the lower pattern (BP) protrudes in the third direction (D3) beyond the upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide, a nitrate, an oxynitride, or a combination thereof. Although the field insulating layer 105 is illustrated as a single layer, this is for convenience of explanation and is not intended to be limiting.

[0032] The gate structure (GS) is located on a substrate 10. A lower pattern (BP) or a field insulating layer 105 is located between the gate structure (GS) and the substrate 10. The gate structure (GS) extends on the substrate 10 in a direction different from the direction in which the lower pattern (BP) extends. For example, the gate structure (GS) extends on the substrate 10 in a direction (e.g., a second direction (D2)) that intersects with the direction in which the lower pattern (BP) extends. The gate structure (GS) is located on the substrate 10. The gate structures (GS) are arranged spaced apart from each other in the first direction (D1). The gate structure (GS) includes a sub-gate structure (S_GS) and a main gate structure (M_GS). The sub-gate structure (S_GS) is located on the substrate 10, and the main gate structure (M_GS) is located on the sub-gate structure (S_GS). As shown in the cross-sectional view of FIG. 3, the main gate structure (M_GS) is located on the field insulating layer 105. In this case, the sub-gate structure (S_GS) may not be located between the main gate structure (M_GS) and the field insulating layer 105 .

[0033] Each of the sub-gate structures (S_GS) is composed of multiple layers. For example, each of the sub-gate structures (S_GS) includes a sub-gate electrode 120S and a sub-gate insulating film 130S. The sub-gate structures (S_GS) and the semiconductor layers (110a, 110b, 110c, 110d) are alternately stacked in the third direction (D3). Although four sub-gate structures (S_GS) are illustrated as being spaced apart in the third direction (D3) in FIGS. 2 and 3, the number of spaced apart sub-gate structures (S_GS) is not limited thereto. For example, the gate structure (GS) may include three sub-gate structures (S_GS).

[0034] The sub-gate electrode 120S is formed on the lower pattern (BP). The sub-gate electrode 120S intersects with the lower pattern (BP). The sub-gate electrode 120S encompasses the plurality of semiconductor layers (110a, 110b, 110c, 110d). At least a portion of the sub-gate electrode 120S is located on a structure in which the sub-gate electrode 120S and the plurality of semiconductor layers (110a, 110b, 110c, 110d) are alternately stacked. The sub-gate electrode 120S, together with the main gate electrode 120M, surrounds the four sides of the plurality of semiconductor layers (110a, 110b, 110c, 110d).

[0035] The sub-gate electrode 120S includes at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride, such as titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide (TaCN), tungsten (W), aluminum (Al), Conductive metal oxides and conductive metal oxynitrides include, but are not limited to, at least one of copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Conductive metal oxides and conductive metal oxynitrides include, but are not limited to, oxidized forms of the above materials.

[0036] The sub-gate insulating film 130S extends along the upper surface of the lower pattern (BP). The sub-gate insulating film 130S is positioned along the periphery of the plurality of semiconductor layers (110a, 110b, 110c, and 110d). The sub-gate insulating film 130S is in direct contact with the lower pattern (BP) and the plurality of semiconductor layers (110a, 110b, 110c, and 110d). The sub-gate insulating film 130S is interposed between the plurality of semiconductor layers (110a, 110b, 110c, and 110d) and the sub-gate electrode 120S. The sub-gate insulating film 130S may include various insulating materials. Although not explicitly shown in FIGS. 2 and 3 , the semiconductor device according to this embodiment may further include an inner gate spacer positioned between the sub-gate insulating film 130S and a source / drain pattern 150, which will be described later.

[0037] Although the sub-gate insulating film 130S is illustrated as a single layer in one embodiment, it is not limited thereto. For example, the sub-gate insulating film 130S may be composed of multiple layers including silicon oxide (SiO2) and a high-k material. In this case, the high-k material may include a material with a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0038] The main gate structure (M_GS) is located on the sub-gate structure (S_GS) and the plurality of semiconductor layers (110a, 110b, 110c, 110d). The main gate structure (M_GS) is located on the upper surface of the uppermost semiconductor layer 110a of the plurality of semiconductor layers (110a, 110b, 110c, 110d). The main gate structure (M_GS) is located on the field insulating layer 105. The main gate structure (M_GS) covers both side surfaces of the sub-gate structure (S_GS).

[0039] The main gate structure (M_GS) includes a main gate electrode 120M and a main gate insulating film 130M.

[0040] The main gate electrode 120M is located on the sub-gate structure (S_GS) and the plurality of semiconductor layers (110a, 110b, 110c, 110d). The main gate electrode 120M includes the same material as the sub-gate electrodes 120S. For example, the main gate electrode 120M includes at least one of a metal, a metal alloy, a conductive metal nitrate, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0041] The main gate insulating film 130M extends along the side surface of the main gate electrode 120M. The main gate insulating film 130M extends along the side surface of a gate spacer 142, which will be described later. The main gate insulating film 130M includes the same material as the sub-gate insulating film 130S. The main gate insulating film 130M may include various insulating materials.

[0042] Although the main gate insulating film 130M is illustrated as a single layer in one embodiment, it is not limited thereto. For example, the main gate insulating film 130M may be composed of a multi-layer including silicon oxide (SiO2) and a high-k material. In this case, the high-k material may include a material with a higher dielectric constant than silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO).

[0043] The semiconductor device according to this embodiment further includes a capping layer 141 and a gate spacer 142 .

[0044] The gate spacers 142 are located on the side surfaces of the main gate electrode 120M. The gate spacers 142 are located on the channel layer (CH). The gate spacers 142 are not located on the side surfaces of the sub-gate electrodes 120S. The gate spacers 142 are not located on the side surfaces of the semiconductor layers (110a, 110b, 110c, 110d). Although the gate spacers 142 are shown as a single film, this is for convenience of explanation and is not intended to be limiting.

[0045] The gate spacer 142 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), silicon carbonate nitrate (SiOCN), silicon boron nitrate (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the gate spacer 142 is shown as a single film, this is for convenience of explanation and is not intended to be limiting.

[0046] The capping layer 141 is located on the main gate structure (M_GS) and the gate spacers 142. The upper surface of the capping layer 141 is flush with the upper surface of the interlayer insulating layer 190, which will be described later. Unlike what is shown in the figure, the capping layer 141 may also be located between the gate spacers 142.

[0047] The capping layer 141 includes, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon (Si) carbonitride (SiCN), silicon carbonate nitrate (SiOCN), and combinations thereof. The capping layer 141 includes a material having an etching selectivity with respect to the interlayer insulating layer 190 described below.

[0048] The source / drain patterns 150 are located on the substrate 10. A lower pattern (BP) is located between the source / drain patterns 150 and the substrate 10. However, this is not limiting, and the lower pattern (BP) may not be located between the source / drain patterns 150 and the substrate 10. A channel layer (CH) and a gate structure (GS) are located between the source / drain patterns 150. That is, the plurality of source / drain patterns 150 and the plurality of channel layers (CH) are alternately arranged along the first direction (D1) in which the lower pattern (BP) extends.

[0049] The source / drain patterns 150 are also arranged in the second direction (D2). Although not clearly shown in Figures 1 to 3, a plurality of lower patterns (BP) are arranged on the substrate 10 at intervals along the second direction (D2), and the source / drain patterns 150 are located above each lower pattern (BP). Thus, the source / drain patterns 150 are arranged at intervals along the second direction (D2) by substantially the same distance as the distance at which the plurality of lower patterns (BP) are spaced apart from each other.

[0050] The source / drain patterns 150 are located on both sides of the channel layer (CH) or the sub-gate structure (S_GS). Specifically, two source / drain patterns 150 located on one lower pattern (BP) are spaced apart in a direction (e.g., a first direction (D1)) intersecting the direction in which the gate structure (GS) extends, with the channel layer (CH) or the sub-gate structure (S_GS) between them. The source / drain patterns 150 directly contact the channel layer (CH) or the sub-gate structure (S_GS). The source / drain patterns 150 directly contact the sub-gate insulating film 130S of the sub-gate structure (S_GS). Although not shown, an inner spacer is further disposed between the source / drain patterns 150 and the sub-gate insulating film 130S. The inner spacer includes at least one of silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOx), silicon carbonate nitrate (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0051] The source / drain pattern 150 is composed of an epitaxial layer formed by selective epitaxial growth (SEG). That is, the source / drain pattern 150 is formed in the region by selective epitaxial growth (SEG) after removing at least a portion of the semiconductor pattern stacked on the bottom pattern (BP).

[0052] The source / drain patterns 150 each include a liner film 150a and a peeling film 150b. The liner film 150a is located outside the peeling film 150b. The side and bottom surfaces of the peeling film 150b are surrounded by the liner film 150a. The liner film 150a directly contacts the sub-gate structure (S_GS) and the channel layer (CH). The peeling film 150b is located on the liner film 150a. The peeling film 150b and the liner film 150a have upper surfaces of substantially the same height. However, this is not limited thereto, and unlike that shown in FIG. 2, the peeling film 150b and the liner film 150a may have upper surfaces of different heights in some regions.

[0053] The source / drain patterns 150 include a semiconductor material. The source / drain patterns 150 include, for example, silicon or germanium. The source / drain patterns 150 also include, for example, a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, the source / drain patterns 150 include, but are not limited to, silicon, silicon-germanium, germanium, and silicon carbide. In this embodiment, the liner film 150a and the peeling film 150b have different silicon (Si) or germanium (Ge) concentrations. For example, the silicon (Si) or germanium (Ge) concentration in the liner film 150a is lower than the silicon (Si) or germanium (Ge) concentration in the peeling film 150b.

[0054] The semiconductor device according to this embodiment further includes an interlayer insulating layer 190 covering the source / drain pattern 150 and the gate structure (GS). The interlayer insulating layer 190 is located on the side surfaces of the gate spacers 142, the side surfaces of the capping layer 141, and the top surface of the source / drain pattern 150. The interlayer insulating layer 190 covers at least a portion of the side surfaces of the source / drain pattern 150. The interlayer insulating layer 190 covers the field insulating layer 105. The interlayer insulating layer 190 does not cover the top surface of the capping layer 141. The interlayer insulating layer 190 fills the inside of a shallow trench isolation (STI) which will be described later.

[0055] The interlayer insulating layer 190 includes, for example, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and a low-k material. Examples of low dielectric constant materials include Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen Silses Quioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), and TriMethylSilyl. Polyimide nanofoams such as Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (TonenSilaZen), FSG (Fluoride Silicate Glass), polypropylene oxide, CDO (Carbon Doped silicon) Oxide), OSG (Organo Silicate Glass), SiLK, Amorphous Fluorinated In this embodiment, the interlayer insulating layer 190 and the field insulating layer 105 include different insulating materials, including, but not limited to, carbon, silica aerogels, silica xerogels, mesoporous silica, or a combination thereof. However, this is not limiting, and in other embodiments, the interlayer insulating layer 190 and the field insulating layer 105 may include the same insulating material.

[0056] The semiconductor device according to this embodiment further includes an upper insulating layer 195 located on the interlayer insulating layer 190. The upper insulating layer 195 is located on the upper surface of the capping layer 141 and the upper surface of the interlayer insulating layer 190. The upper insulating layer 195 and the interlayer insulating layer 190 include the same insulating material. In this case, the interface between the interlayer insulating layer 190 and the upper insulating layer 195 is not visible. For example, the upper insulating layer 195 includes at least one of silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a low-k material. In other embodiments, the upper insulating layer 195 and the interlayer insulating layer 190 may include different materials.

[0057] The insulating pattern 210 is located below the gate structure (GS) and between two adjacent source / drain patterns 150. The insulating pattern 210 prevents leakage current from flowing between two adjacent source / drain patterns 150. The insulating pattern 210 includes a main insulating pattern 212 located below the gate structure (GS) and a sub-insulating pattern 211 located between the gate structure (GS) and the main insulating pattern 212.

[0058] The sub-insulating pattern 211 is positioned below the sub-gate structure (S_GS). The sub-insulating pattern 211 has an upper surface that contacts at least a portion of the lower surface of the sub-gate structure (S_GS) located at the bottom among the plurality of sub-gate structures (S_GS) spaced apart in the third direction (D3). The upper surface of the sub-insulating pattern 211 contacts at least a portion of the sub-gate insulating film 130S included in the sub-gate structure (S_GS) located at the bottom among the plurality of sub-gate structures (S_GS) spaced apart in the third direction (D3). The lower surface of the sub-insulating pattern 211 contacts the lower surface of the main insulating pattern 212. In one embodiment, the distance between the upper and lower surfaces of the sub-insulating pattern 211 is greater than or equal to about 1 nm and less than or equal to about 10 nm. That is, the thickness of the sub-insulating pattern 211 along the third direction (D3) is about 1 nm to about 10 nm.

[0059] In this embodiment, the maximum width of the sub insulating pattern 211 in the first direction (D1) is substantially the same as the width in the first direction (D1) of the upper surface of the main insulating pattern 212 that is in contact with the lower surface of the sub insulating pattern 211. In this embodiment, the sub insulating pattern 211 has a shape in which the width in the horizontal direction (e.g., the first direction (D1) or the second direction (D2)) gradually narrows from the bottom to the top.

[0060] The sides of the sub-insulation pattern 211 are surrounded by the lower pattern (BP) and / or the field insulating layer 105. That is, the sub-insulation pattern 211 has sides that contact the lower pattern (BP) and / or the field insulating layer 105. For example, in FIG. 2, both sides of the sub-insulation pattern 211 contact the lower pattern (BP). For example, in FIG. 3, both sides of the sub-insulation pattern 211 contact the field insulating layer 105. If the semiconductor device according to this embodiment does not include a lower pattern (BP), the sub-insulation pattern 211 has sides that contact the substrate 10.

[0061] The width of the sub-insulation pattern 211 in the first direction (D1) is smaller than the width of the sub-gate structure (S_GS) in the first direction (D1). The width of the sub-insulation pattern 211 in the second direction (D2) is substantially the same as the width of the sub-gate structure (S_GS) in the second direction (D2). However, this is not limited thereto, and the width of the sub-insulation pattern 211 in the second direction (D2) may be narrower than the width of the sub-gate structure (S_GS) in the second direction (D2).

[0062] The sub-insulating pattern 211 may include various insulating materials. The sub-insulating pattern 211 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon carbonitride (SiCxNy), and silicon oxynitride (SiOxNy). In this embodiment, the sub-insulating pattern 211 is formed by a nitridation process. In some embodiments, the sub-insulating pattern 211 may include at least one of silicon nitride (SiNx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy) formed by a nitridation process. In this embodiment, the sub-insulating pattern 211 has different nitrogen concentrations depending on the position. For example, the sub-insulating pattern 211 has a lower nitrogen concentration as it moves away from the interface with the main insulating pattern 212.

[0063] The main insulating pattern 212 is located below the sub insulating pattern 211. The main insulating pattern 212 penetrates the substrate 10 in the third direction (D3). The main insulating pattern 212 extends into the lower pattern (BP). The main insulating pattern 212 has a shape in which its width in the horizontal direction (first direction (D1) or second direction (D2)) gradually narrows from the bottom to the top.

[0064] The main insulating pattern 212 has an upper surface that contacts the lower surface of the sub insulating pattern 211. The lower surface of the main insulating pattern 212 contacts the upper surface of the lower wiring structure 410, which will be described later.

[0065] The sides of the main insulating pattern 212 are surrounded by the lower pattern (BP), the substrate 10, and / or the field insulating layer 105. That is, the main insulating pattern 212 has sides that contact the lower pattern (BP), the substrate, and / or the field insulating layer 105. For example, in FIG. 2, both sides of the main insulating pattern 212 contact the lower pattern (BP) and the substrate 10. For example, in FIG. 3, both sides of the main insulating pattern 212 contact the lower pattern (BP), the substrate 10, and the field insulating layer 105. If the semiconductor device according to this embodiment does not include a lower pattern (BP), the main insulating pattern 212 has sides that contact the substrate 10 and the field insulating layer 105.

[0066] The main insulating pattern 212 can include various insulating materials, including at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy).

[0067] In this embodiment, the main insulating pattern 212 and the sub insulating pattern 211 include different insulating materials. For example, the sub insulating pattern 211 includes at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy), and the main insulating pattern 212 includes any one of silicon nitride (SiNx), silicon oxide (SiOx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy) that is not included in the sub insulating pattern 211. In another embodiment, the main insulating pattern 212 and the sub insulating pattern 211 may include the same insulating material. In this case, the interface between the main insulating pattern 212 and the sub insulating pattern 211 is not visible.

[0068] In this embodiment, the main insulating pattern 212 is formed by a process other than the sub insulating pattern 211. That is, the main insulating pattern 212 includes at least one of silicon nitride (SiNx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy) formed by a process other than the sub insulating pattern 211. For example, the main insulating pattern 212 is formed by a deposition method such as sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0069] The semiconductor device according to this embodiment further includes a through electrode 180 located on one side of the insulating pattern 210. The through electrode 180 electrically connects at least one of the source / drain patterns 150 to a lower wiring structure 410, which will be described later.

[0070] The through electrode 180 penetrates the substrate 10 and the lower pattern (BP) in the third direction (D3). The through electrode 180 is recessed into the source / drain pattern 150. As a result, the through electrode 180 contacts at least a portion of the source / drain pattern 150. Referring to FIG. 2, the through electrode 180 is shown to contact both the liner film 150a and the peeling film 150b of the source / drain pattern 150 in the recessed region of the source / drain pattern 150. However, the through electrode 180 may contact only the liner film 150a of the source / drain pattern 150. A silicide film 170 is located between the through electrode 180 and the source / drain pattern 150. The silicide film 170 extends along at least a portion of the upper surface of the through electrode 180 between the source / drain pattern 150 and the through electrode 180. The silicide film 170 is a metal silicide film. For example, the silicide film 170 includes at least one of tungsten silicide (WSi), nickel silicide (NiSi), and / or titanium silicide (TiSi).

[0071] The through electrode 180 also contacts the lower pattern (BP) and / or the substrate 10. Referring to FIG. 2, the through electrode 180 has a side surface that contacts the lower pattern (BP) and / or the substrate 10 in a region that does not horizontally overlap the source / drain pattern 150. Although not clearly shown in FIG. 2, an insulating pattern may further be located between the through electrode 180 and the substrate 10 or between the through electrode 180 and the lower pattern (BP) along the side profile of the through electrode 180.

[0072] In this embodiment, the through electrode 180 has a width that gradually narrows in the horizontal direction from the bottom surface thereof, which contacts the lower wiring structure 410 (described later), toward the source / drain pattern 150. The through electrode 180 includes at least one of a metal, a metal alloy, a conductive metal nitrate, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The metal includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitrate includes at least one of titanium nitrate (TiN), tantalum nitrate (TaN), tungsten nitrate (WN), nickel nitrate (NiN), cobalt nitrate (CoN), and platinum nitrate (PtN).

[0073] The lower wiring structure 410 is positioned on the lower surface of the substrate 10. A portion of the upper surface of the lower wiring structure 410 contacts the lower surface of the main insulating pattern 212. A portion of the upper surface of the lower wiring structure 410 contacts the lower surface of the through electrode 180. The lower wiring structure 410 includes a lower conductive pattern 411 and a lower wiring insulating layer 412. The lower conductive pattern 411 includes lower wirings spaced apart in the third direction (D3) and lower wiring vias connecting the two lower wirings. The lower conductive pattern 411 is positioned between the lower wiring insulating layers 412. The lower wiring insulating layer 412 surrounds the lower conductive pattern 411. That is, the lower wiring insulating layer 412 covers the lower conductive pattern 411, and the lower conductive pattern 411 is positioned within the lower wiring insulating layer 412.

[0074] The lower conductive pattern 411 includes a metal (for example, copper). The lower wiring insulating layer 412 includes at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a low dielectric film.

[0075] In this embodiment, an externally supplied electrical signal or power supply voltage is provided to the source / drain pattern 150 via the lower wiring structure 410 and the through electrode 180 connected thereto.

[0076] Although not explicitly shown in FIGS. 1 to 3 , the semiconductor device according to this embodiment may further include an upper wiring structure located on the upper insulating layer 195 and a contact electrode located between the upper wiring structure and the source / drain pattern 150 or between the upper wiring structure and the main gate structure (M_GS). The contact electrode connects the source / drain pattern 150 and the upper wiring structure by penetrating a portion of the interlayer insulating layer 190 and the upper insulating layer 195 located on at least one of the source / drain patterns 150. The contact electrode connects the main gate electrode 120M and the upper wiring structure by penetrating at least a portion of the upper insulating layer 195 and the capping layer 141 located on the main gate structure (M_GS). When the semiconductor device according to this embodiment includes an upper wiring structure and a contact electrode, at least a portion of an externally supplied electrical signal or power supply voltage is provided to the source / drain pattern 150 and / or the main gate electrode 120M via the upper wiring structure and the contact electrode.

[0077] The semiconductor device according to this embodiment further includes an isolation trench (STI). The semiconductor device is electrically isolated from other adjacent semiconductor devices by the isolation trench (STI). The inner surface of the isolation trench (STI) is defined by a capping layer 141, a gate spacer 142, a lower pattern (BP), a substrate 10, and an underlying wiring structure 410. The inside of the isolation trench (STI) is filled with an interlayer insulating layer 190.

[0078] FIG. 4 is a cross-sectional view showing a second example of a semiconductor device according to an embodiment. Specifically, FIG. 4 is a cross-sectional view of the second example of the semiconductor device taken along line I1-I1' in FIG. 1. The semiconductor device shown in FIG. 4 has many similarities to the previous embodiment, so the following description will focus on differences from the previous embodiment. The semiconductor device shown in FIG. 4 differs from the previous embodiment in part in the shape of the sub-insulation pattern 211 located between the gate structure (GS) and the main insulation pattern 212.

[0079] 4, in the semiconductor device according to this embodiment, the width of the sub insulation pattern 211 in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) increases and then decreases as it moves away from the main insulation pattern 212 toward the lower surface of the gate structure GS. In this embodiment, the maximum width of the sub insulation pattern 211 in the first direction (D1) or the second direction (D2) is located between the upper surface of the main insulation pattern 212 and the lower surface of the gate structure GS. Unlike the configuration shown in FIG. 4, the width of the sub insulation pattern 211 in a horizontal direction (e.g., a first direction (D1) or a second direction (D2)) may gradually increase as it moves away from the main insulation pattern 212 toward the lower surface of the gate structure GS. In this case, the sub insulation pattern 211 has its maximum width in the first direction (D1) or the second direction (D2) at a surface that contacts the lower surface of the gate structure GS.

[0080] The nitrogen concentration of the sub insulating pattern 211 gradually decreases as it moves away from the interface with the main insulating pattern 212 .

[0081] In this embodiment, the sub insulating pattern 211 is formed by a plasma nitridation process. In the plasma nitridation process, nitrogen (N) diffuses from the top surface of the main insulating pattern 212 into the bottom pattern (BP) located below the gate structure (GS), forming the sub insulating pattern 211. As a result, as shown in FIG. 4, the maximum horizontal width of the sub insulating pattern 211 is wider than the horizontal width of the top surface of the main insulating pattern 212.

[0082] FIG. 5 is a cross-sectional view of a third example of a semiconductor device according to an embodiment. Specifically, FIG. 5 is a cross-sectional view of the third example of the semiconductor device taken along line I1-I1' in FIG. 1. The semiconductor device shown in FIG. 5 has many similarities to the previous embodiment, so the following description will focus on differences from the previous embodiment. The semiconductor device shown in FIG. 5 differs from the previous embodiment in the location where the sub-insulation pattern 211 is formed.

[0083] 5, in the semiconductor device according to this embodiment, the sub-insulating pattern 211 is located between the substrate 10 and the main insulating pattern 212 and / or between the bottom pattern (BP) and the main insulating pattern 212. The sub-insulating pattern 211 is located on the side or top surface of the main insulating pattern 212. The sub-insulating pattern 211 is located along the profile of the side and top surface of the main insulating pattern 212.

[0084] In this embodiment, the nitrogen concentration of the sub insulating pattern 211 gradually decreases with increasing distance from the interface with the main insulating pattern 212. In one embodiment, the sub insulating pattern 211 is formed by a thermal nitridation process. In this thermal nitridation process, the sub insulating pattern 211 is formed by diffusing nitrogen (N) from the inner wall and bottom surface of the first trench (TR1, see FIG. 7) formed under the gate structure GS into the substrate 10 and / or the lower pattern BP. As a result, as shown in FIG. 5, the sub insulating pattern 211 is located not only between the upper surface of the main insulating pattern 212 and the lower surface of the gate structure GS, but also between the substrate 10 and the main insulating pattern 212 and / or between the lower pattern BP and the main insulating pattern 212.

[0085] 6 to 14 are diagrams for explaining a first example of a method for manufacturing a semiconductor device according to an embodiment.

[0086] 6, a lower pattern (BP), a channel layer (CH), gate structures (GS) surrounding the channel layer (CH), and source / drain patterns 150 connected to both sides of each channel layer (CH) are formed on a substrate 10. An isolation trench (STI) is formed by recessing a portion of the lower pattern (BP) and the substrate 10. An interlayer insulating layer 190 and / or an upper insulating layer 195 covers the channel layer (CH), gate structures (GS), and source / drain patterns 150. The interlayer insulating layer 190 fills the inside of the isolation trench (STI).

[0087] In this embodiment, the substrate 10 is silicon-on-insulator (SOI) or bulk silicon. Alternatively, the substrate 10 may be a silicon substrate or other materials, including, but not limited to, silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The bottom pattern (BP) is part of the substrate 10 and is grown from the substrate 10 by epitaxial growth.

[0088] 7, a first trench (TR1) penetrating the substrate 10 in the third direction (D3) is formed under the gate structure (GS). The first trench (TR1) is formed by etching at least a portion of the substrate 10 and the lower pattern (BP).

[0089] The first trench (TR1) penetrates the substrate 10 in the third direction (D3) and extends into the lower pattern (BP). The first trench (TR1) is located adjacent to the lower surface of the gate structure (GS). The first trench (TR1) does not contact the lower surface of the gate structure (GS). That is, the bottom surface of the first trench (TR1) is located away from the lower surface of the gate structure (GS). Referring to FIG. 7, the bottom surface of the first trench (TR1) refers to a surface extending from the inner side of the first trench (TR1) and adjacent to the lower surface of the gate structure (GS). The lower pattern (BP) is located between the bottom surface of the first trench (TR1) and the lower surface of the gate structure (GS). The first trench (TR1) has a shape in which its horizontal width gradually narrows toward the lower surface of the gate structure (GS).

[0090] In this embodiment, the first trench TR1 is formed by a dry etching process. For example, the process for forming the first trench TR1 may be RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma). However, the process is not limited thereto, and the first trench TR1 may also be formed by a wet etching process.

[0091] As shown in FIG. 8, a sub-insulating pattern 211 is formed between the first trench TR1 and the lower surface of the gate structure GS.

[0092] In this embodiment, the sub-insulating pattern 211 includes nitrogen, for example, the sub-insulating pattern 211 includes at least one of silicon nitride (SiNx), silicon carbonitride (SiCxNy), and silicon oxynitride (SiOxNy).

[0093] In this embodiment, the sub-insulating pattern 211 is formed by a nitridation process. For example, the sub-insulating pattern 211 is formed by a thermal nitridation or plasma nitridation process. The sub-insulating pattern 211 is formed by injecting one or more source materials including nitrogen into a chamber having predetermined temperature and pressure conditions. For example, the source material includes at least one of N2, NH3, NH4, and NO. In some embodiments, plasma is formed inside the chamber. For example, to form plasma inside the chamber, power is supplied between two electrodes located inside the chamber. At this time, the supplied power may be DC power or RF (Radio Frequency) power.

[0094] The sub-insulating pattern 211 is formed only in a partial region of the lower pattern BP. For example, referring to FIG. 8, the sub-insulating pattern 211 is formed by nitriding the lower pattern BP located between the lower surface of the gate structure GS and the bottom surface of the first trench TR1. To form the sub-insulating pattern 211 only in a partial region of the lower pattern BP, at least one process variable of the nitridation process is controlled. For example, the magnitude of an electrical bias applied between two electrodes disposed inside a chamber to generate plasma is controlled.

[0095] In this embodiment, the lower pattern BP is nitrided to change into the sub insulating pattern 211 and increase its thickness. That is, referring to both Figures 7 and 8, the distance between the upper and lower surfaces of the sub insulating pattern 211 is longer than the distance between the lower surface of the gate structure GS and the bottom surface of the first trench TR1 before the sub insulating pattern 211 is formed.

[0096] 9, a main insulating pattern 212 is formed to fill the inside of the first trench TR1. In this embodiment, the main insulating pattern 212 is formed by depositing an insulating material on the inside of the first trench TR1 and on the lower surface of the substrate 10, and then removing the insulating material deposited on the lower surface of the substrate 10. In this embodiment, the process for removing the insulating material deposited on the lower surface of the substrate 10 is a chemical mechanical polishing (CMP) process. In this embodiment, the main insulating pattern 212 is formed by a deposition method such as sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0097] In this embodiment, the main insulating pattern 212 and the sub insulating pattern 211 include different insulating materials. For example, the sub insulating pattern 211 includes at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy), and the main insulating pattern 212 includes at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy), which is not included in the sub insulating pattern 211. In another embodiment, the main insulating pattern 212 and the sub insulating pattern 211 may include the same insulating material. In this case, the interface between the main insulating pattern 212 and the sub insulating pattern 211 is not visible.

[0098] 10, a second trench (TR2) penetrating the substrate 10 in the third direction (D3) is formed under the source / drain pattern 150. The second trench (TR2) is formed by etching at least a portion of the substrate 10 and the lower pattern (BP). The second trench (TR2) penetrates the substrate 10 and the lower pattern (BP) in the third direction (D3) and extends into the source / drain pattern 150. The side of the second trench (TR2) is defined by the substrate 10, the lower pattern (BP), and the source / drain pattern 150. The bottom of the second trench (TR2) is defined by the source / drain pattern 150.

[0099] 11, a silicide film 170 is formed on a portion of the bottom and side surfaces of the second trench TR2. The silicide film 170 is conformally formed on a portion of the bottom and side surfaces of the second trench TR2. The silicide film 170 is formed on the entire bottom and side surfaces of the second trench TR2, in a region that contacts the source / drain pattern 150. However, the present invention is not limited thereto, and the silicide film 170 may also be formed on the entire bottom and side surfaces of the second trench TR2.

[0100] In this embodiment, the silicide film 170 is deposited by a deposition method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), or is formed by depositing a metal on the second trench TR2 and then performing an annealing process. The silicide film 170 includes at least one of, for example, tungsten silicide (WSi), nickel silicide (NiSi), and / or titanium silicide (TiSi).

[0101] As shown in FIG. 12 , a through electrode 180 is formed inside the second trench TR2 and on the bottom surface of the substrate 10. In this embodiment, the through electrode 180 includes a conductive material. The through electrode 180 includes at least one of, for example, a metal, a metal alloy, a conductive metal nitrate, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The metal includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitrate includes at least one of titanium nitrate (TiN), tantalum nitrate (TaN), tungsten nitrate (WN), nickel nitrate (NiN), cobalt nitrate (CoN), and platinum nitrate (PtN).

[0102] 13, a portion of the through electrode 180 formed on the same plane as the surface including the lower surface of the substrate 10 is removed. In this embodiment, the through electrode 180 formed on the lower surface of the substrate 10 is formed by a chemical mechanical polishing (CMP) process.

[0103] As shown in FIG. 14, a lower wiring structure 410 electrically connected to the through electrode 180 is formed on the lower surface of the substrate 10 .

[0104] The lower wiring structure 410 includes a lower conductive pattern 411 and a lower wiring insulating layer 412. The lower conductive pattern 411 includes lower wirings spaced apart in a third direction (D3) and lower wiring vias connecting the two lower wirings. The lower conductive pattern 411 is located between the lower wiring insulating layers 412. The lower wiring insulating layer 412 surrounds the lower conductive pattern 411. That is, the lower wiring insulating layer 412 covers the lower conductive pattern 411, and the lower conductive pattern 411 is located within the lower wiring insulating layer 412. The lower conductive pattern 411 includes a metal (e.g., copper). The lower wiring insulating layer 412 includes at least one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and a low-k film, for example.

[0105] In the manufacturing process of a semiconductor device according to this embodiment, the lower pattern BP located under the gate structure GS is only partially etched rather than completely etched to form the insulating pattern 210. Then, a portion of the lower pattern BP located between the gate structure GS and the first trench TR1 is nitrided to form the sub-insulating pattern 211. According to this embodiment, in the process of etching the substrate 10 and the lower pattern BP to form the insulating pattern 210, the insulating layer (e.g., the sub-gate insulating film 130S) included in the gate structure GS is not damaged by the etching material, thereby improving the reliability of the semiconductor device.

[0106] 15 to 18 are diagrams illustrating a third example of a semiconductor device according to an embodiment. The semiconductor device shown in FIGS. 15 to 18 has many similarities to the semiconductor device described with reference to FIGS. 1 to 5, so the following description will focus on the differences from the previous embodiment. The semiconductor device according to this embodiment differs from the previous embodiment in part in that it includes insulating liners 220 located on the side surfaces of the through electrodes 180.

[0107] Fig. 15 is a plan view showing a third example of a semiconductor device according to an embodiment. Figs. 16 to 18 are cross-sectional views showing the third example of a semiconductor device according to an embodiment. Specifically, Fig. 16 is a cross-sectional view of the third example of the semiconductor device taken along line I3-I3' in Fig. 15, Fig. 17 is a cross-sectional view of the third example of the semiconductor device taken along line I4-I4' in Fig. 15, and Fig. 18 is a cross-sectional view of the third example of the semiconductor device taken along line I5-I5' in Fig. 15.

[0108] 15 to 18, the semiconductor device according to this embodiment includes a lower pattern (BP), a channel layer (CH) located on the lower pattern (BP), a gate structure (GS) surrounding the channel layer (CH), source / drain patterns 150 located on both sides of each channel layer (CH), a lower wiring structure 410 located under the lower pattern (BP), a through electrode 180 located between the source / drain pattern 150 and the lower wiring structure 410, and an insulating liner 220 located on the side of the through electrode 180.

[0109] The semiconductor device according to this embodiment includes a substrate 10 located below the lower pattern (BP), a gate spacer 142 located on the side of the main gate electrode 120M, a capping layer 141 located on the main gate structure (M_GS), an interlayer insulating layer 190 covering the source / drain pattern 150 and the gate structure (GS), and an upper insulating layer 195 located on the interlayer insulating layer 190.

[0110] The semiconductor device according to this embodiment does not include the insulating pattern 210 described with reference to Figures 1 to 5. In the semiconductor device according to this embodiment, the substrate 10, the lower pattern (BP), the channel layer (CH), the gate structure (GS), the source / drain pattern 150, the lower wiring structure 410, the through electrode 180, the gate spacer 142, the capping layer 141, the interlayer insulating layer 190, and the upper insulating layer 195 are the same as those described with reference to Figures 1 to 5, and therefore detailed description thereof will be omitted.

[0111] The insulating liner 220 is positioned on the side of the through electrode 180. Specifically, the insulating liner 220 is positioned between the through electrode 180 and the substrate 10, between the through electrode 180 and the lower pattern (BP), and between the through electrode 180 and the source / drain pattern 150. The insulating liner 220 can prevent current from leaking to other source / drain patterns 150 that are not connected to the through electrode 180 when an electrical signal is applied to the source / drain pattern 150 from the lower wiring structure 410 via the through electrode 180.

[0112] 16 and 18, the insulating liner 220 extends from the upper surface of the lower wiring structure 410 toward the source / drain pattern 150. The insulating liner 220 penetrates the substrate 10 and the lower pattern (BP). The insulating liner 220 is recessed inside the source / drain pattern 150. In one embodiment, the width of the insulating liner 220 along the horizontal direction is greater than or equal to about 1 nm and less than or equal to about 10 nm.

[0113] The insulating liner 220 has an inner surface in contact with the through electrode 180 and an outer surface in contact with the substrate 10, the lower pattern (BP), and the source / drain pattern 150. The insulating liner 220 has a rounded upper surface. In a region adjacent to the upper surface of the lower wiring structure 410, the insulating liner 220 has a width in the horizontal direction that gradually increases toward the upper surface of the lower wiring structure 410.

[0114] The insulating liner 220 may include various insulating materials. The insulating liner 220 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon carbonitride (SiCxNy), and silicon oxynitride (SiOxNy). In this embodiment, the insulating liner 220 is formed by a nitridation process. In some embodiments, the insulating liner 220 may include at least one of silicon nitride (SiNx), silicon carbonitride (SiCxNy), and / or silicon oxynitride (SiOxNy) formed by a nitridation process. In this embodiment, the insulating liner 220 has a different nitrogen concentration depending on the position. For example, the insulating liner 220 has a lower nitrogen concentration the farther it is from the interface with the through-electrode 180. In this embodiment, the insulating liner 220 is formed by a thermal nitridation process. However, without being limited thereto, the insulating liner 220 may also be formed by a plasma nitridation process. In the nitridation process, the insulating liner 220 is formed by diffusing from the surface in contact with the through electrode 180 into the bottom pattern (BP), the substrate 10, or the source / drain pattern 150.

[0115] A silicide film 170 is located between the top surface of the through electrode 180 and the source / drain pattern 150. The silicide film 170 is located along the profile of the top surface of the through electrode 180. The silicide film 170 is not located on the side surface of the through electrode 180. In this embodiment, the silicide film 170 does not overlap the insulating liner 220 in the horizontal direction.

[0116] According to the present embodiment, the insulating liner 220 for preventing leakage paths from the through electrode 180 through the substrate 10 or the inside of the bottom pattern (BP) to the source / drain pattern 150 is formed by a nitridation process. In this case, compared to when the insulating liner 220 is formed by a deposition method such as PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition), more space for forming the through electrode 180 can be secured, thereby improving the electrical characteristics of the semiconductor device.

[0117] FIG. 19 is a cross-sectional view of a fourth example of a semiconductor device according to an embodiment. Specifically, FIG. 19 is a cross-sectional view of the fourth example of a semiconductor device taken along line I3-I3′ in FIG. 15. The semiconductor device shown in FIG. 19 has many similarities to the previous embodiment, so the following description will focus on the differences from the previous embodiment. The semiconductor device shown in FIG. 19 differs from the previous embodiment in part in the horizontal width of the insulating liner 220. Referring to FIG. 19, the horizontal width of the insulating liner 220 located between the side of the through electrode 180 and the source / drain pattern 150 is narrower than the horizontal width of the insulating liner 220 located between the side of the through electrode 180 and the bottom pattern (BP).

[0118] 19 , the width of the insulating liner 220 along the horizontal direction is narrower between the through electrode 180 and the source / drain pattern 150 than between the through electrode 180 and the substrate 10 or between the through electrode 180 and the lower pattern (BP). In this embodiment, the insulating liner 220 is formed by a nitridation process, and the nitridation rate varies depending on the nitriding material. For example, in this embodiment, the nitridation rate is slower in the source / drain pattern 150 than in the substrate 10 and the lower pattern (BP). As a result, the width of the insulating liner 220 along the horizontal direction is narrower between the side of the through electrode 180 and the source / drain pattern 150 than between the side of the through electrode 180 and the lower pattern (BP).

[0119] 20 to 28 are diagrams for explaining a third example of a method for manufacturing the semiconductor element described with reference to FIGS. 15 to 18. In FIG.

[0120] 20, a lower pattern (BP), a channel layer (CH), gate structures (GS) surrounding the channel layer (CH), and source / drain patterns 150 connected to both sides of each channel layer (CH) are formed on a substrate 10. An isolation trench (STI) is formed by recessing a portion of the lower pattern (BP) and the substrate 10. An interlayer insulating layer 190 and / or an upper insulating layer 195 covers the channel layer (CH), gate structures (GS), and source / drain patterns 150. The interlayer insulating layer 190 fills the inside of the isolation trench (STI).

[0121] 21, a third trench (TR3) is formed below the source / drain pattern 150, penetrating the substrate 10 and the lower pattern (BP) in a third direction (D3). The third trench (TR3) penetrates the substrate 10 and the lower pattern (BP) in the third direction (D3) and is recessed into the source / drain pattern 150. The third trench (TR3) is formed by etching at least a portion of the substrate 10, the lower pattern (BP), and the source / drain pattern 150. The side of the third trench (TR3) is defined by the substrate 10, the lower pattern (BP), and the source / drain pattern 150. The bottom of the third trench (TR3) is defined by the source / drain pattern 150.

[0122] In this embodiment, the third trench (TR3) is formed by a dry etching process. For example, the process for forming the third trench (TR3) may be RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma). However, the process is not limited thereto, and the third trench (TR3) may also be formed by a wet etching process.

[0123] 22, an insulating liner 220 is formed on the side and bottom surfaces of the third trench (TR3). The insulating liner 220 is also formed on the lower surface of the substrate 10. The insulating liner 220 is not located on the lower surface of the interlayer insulating layer 190 filling the inside of the isolation trench (STI). In this embodiment, the insulating liner 220 is formed by diffusing from the side and bottom surfaces of the third trench (TR3) into the lower pattern (BP), the substrate 10, and the source / drain patterns 150. The insulating liner 220 located on the lower surface of the substrate 10 is formed by diffusing from the lower surface of the substrate 10 into the inside of the substrate 10.

[0124] In this embodiment, the insulating liner 220 is formed by growing from the side and bottom surfaces of the third trench TR3 toward the inside of the third trench TR3. Therefore, referring to Figures 22 and 23, the horizontal width of the third trench TR3 after the insulating liner 220 is formed is narrower than the horizontal width of the third trench TR3 before the insulating liner 220 is formed. Furthermore, the vertical depth of the third trench TR3 after the insulating liner 220 is formed is shallower than the vertical depth of the third trench TR3 before the insulating liner 220 is formed.

[0125] 23, a portion of the insulating liner 220 located between the bottom of the third trench TR3 and the source / drain pattern 150 is removed to expose a portion of the source / drain pattern 150. At this time, a portion of the insulating liner 220 located on the bottom surface of the substrate 10 is also removed. The process of removing the portion of the insulating liner 220 is performed by an anisotropic etching process. For example, the portion of the insulating liner 220 is removed by a dry etching process using RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma). However, the method is not limited thereto, and the insulating liner 220 may also be removed by a wet etching process.

[0126] As shown in FIG. 24, a portion of the source / drain pattern 150 exposed at the bottom of the third trench TR3 is etched.

[0127] Next, as shown in FIG. 25, a silicide film 170 is formed on the bottom surface of the third trench TR3. The silicide film 170 is not formed on the sidewalls of the third trench TR3. The silicide film 170 is formed along the bottom surface of the source / drain pattern 150 exposed at the bottom surface of the third trench TR3. The silicide film 170 is formed, for example, by depositing a metal material on the sidewalls and bottom surface of the third trench TR3 and then annealing it. The silicide film 170 is formed at the interface between the source / drain pattern 150 and the metal material. The silicide film 170 is not formed at the interface between the insulating liner 220 and the metal material. After the silicide film 170 is formed, the metal material deposited on the sidewalls and bottom surface of the third trench TR3 is removed.

[0128] 26, the inside of the third trench TR3 is filled with a conductive material to form a through electrode 180. In FIG. 26, the through electrode 180 is also formed on the lower surface of the substrate 10 and on the lower surface of the interlayer insulating layer 190 that fills the shallow trench isolation (STI).

[0129] 27, a portion of the through electrode 180 formed on the same plane as the surface including the lower surface of the substrate 10 is removed. In this embodiment, the through electrode 180 formed on the lower surface of the substrate 10 is formed by a chemical mechanical polishing (CMP) process. At this time, a portion of the interlayer insulating layer 190 filling the inside of the shallow trench isolation (STI) is also removed.

[0130] As shown in FIG. 28, a lower wiring structure 410 electrically connected to the through electrodes 180 is formed on the lower surface of the substrate 10, and the semiconductor device described with reference to FIGS. 15 to 18 is manufactured.

[0131] 29 to 32 are diagrams illustrating a fifth example of a semiconductor device according to an embodiment. The semiconductor device shown in FIGS. 29 to 32 has many similarities to the semiconductor device according to the previous embodiment, and therefore the following description will focus on the differences from the previous embodiment. The semiconductor device according to this embodiment differs from the previous embodiment in part in that it includes a lower conductive layer 185 between the lower surface of the lower pattern (BP) and the lower wiring structure 410, and an insulating liner 220 is also located between the lower conductive layer 185 and the lower pattern (BP).

[0132] Fig. 29 is a plan view showing a fifth example of a semiconductor device according to an embodiment. Figs. 30 to 32 are cross-sectional views showing the fifth example of a semiconductor device according to an embodiment. Specifically, Fig. 30 is a cross-sectional view of the fifth example of the semiconductor device taken along line I6-I6' in Fig. 29, Fig. 31 is a cross-sectional view of the fifth example of the semiconductor device taken along line I7-I7' in Fig. 29, and Fig. 32 is a cross-sectional view of the fifth example of the semiconductor device taken along line I8-I8' in Fig. 29.

[0133] 29 to 32, the semiconductor device according to this embodiment further includes a lower conductive layer 185 located between the lower pattern (BP) and the lower wiring structure 410. In this embodiment, an insulating liner 220 is located between the lower pattern (BP) and the lower conductive layer 185. The semiconductor device according to this embodiment does not include a substrate 10 (see FIG. 2 or FIG. 16). However, the present invention is not limited thereto, and the semiconductor device according to this embodiment may also include a substrate 10 (see FIG. 2 or FIG. 16). In this case, the insulating liner 220 is located between the substrate 10 and the lower conductive layer 185.

[0134] The lower conductive layer 185 fills the region where at least a portion of the substrate 10 (see FIGS. 33 and 34 ), which will be described later, has been removed. The lower conductive layer 185 is located below the field insulating layer 105. The upper surface of the lower conductive layer 185 is in partial contact with the lower surface of the insulating liner 220 and the lower surface of the through-hole electrode 180. The upper surface of the lower conductive layer 185 is in partial contact with the lower surface of the field insulating layer 105. The lower surface of the lower conductive layer 185 is in contact with the upper surface of the lower wiring structure 410. In this embodiment, the horizontal width of the lower conductive layer 185 is wider than the horizontal width of the lower pattern (BP). At least a portion of the lower surface of the lower conductive layer 185 is electrically connected to the lower conductive pattern 411 included in the lower wiring structure 410.

[0135] The lower conductive layer 185 according to this embodiment includes a conductive material. For example, the lower conductive layer 185 includes at least one of a metal, a metal alloy, a conductive metal nitrate, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The metal includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), and platinum (Pt). The conductive metal nitrate includes at least one of titanium nitrate (TiN), tantalum nitrate (TaN), tungsten nitrate (WN), nickel nitrate (NiN), cobalt nitrate (CoN), and platinum nitrate (PtN).

[0136] 29 to 32, the insulating liner 220 is located between the side of the through electrode 180 and the source / drain pattern 150, between the through electrode 180 and the lower pattern (BP), and between the lower conductive layer 185 and the lower pattern (BP). In a region where the lower conductive layer 185 overlaps the lower pattern (BP) in the third direction (D3), the insulating liner 220 is located between the lower conductive layer 185 and the lower pattern (BP). In a region where the side of the through electrode 180 overlaps the lower pattern (BP) in the horizontal direction, the insulating liner 220 is located between the side of the through electrode 180 and the lower pattern (BP).

[0137] According to this embodiment, the volume of the conductive material electrically connecting the source / drain patterns 150 and the lower wiring structure 410 is increased, thereby improving the electrical characteristics of the semiconductor device.

[0138] In this embodiment, an insulating liner 220 is located between the lower conductive layer 185 and the lower pattern (BP), so that the current flowing from the lower wiring structure 410 through the lower conductive layer 185 and the through electrode 180 does not pass through the inside of the lower pattern (BP) and leak to the source / drain pattern 150.

[0139] 33 to 42 are diagrams for explaining a fifth example of a method for manufacturing the semiconductor element described with reference to FIGS. 29 to 32. In FIG.

[0140] 33, a lower pattern (BP), a channel layer (CH), gate structures (GS) surrounding the channel layer (CH), and source / drain patterns 150 connected to both sides of each channel layer (CH) are formed on a substrate 10. An isolation trench (STI) is formed by recessing a portion of the lower pattern (BP) and the substrate 10. An interlayer insulating layer 190 and / or an upper insulating layer 195 covers the channel layer (CH), the gate structures (GS), and the source / drain patterns 150. The interlayer insulating layer 190 fills the inside of the isolation trench (STI).

[0141] As shown in Figure 34, the substrate 10 is etched to form a fourth trench (TR4). Although the substrate 10 is shown as being completely etched in Figure 34, in other embodiments, the substrate 10 may be only partially etched. In this embodiment, the substrate 10 is removed by wet etching or dry etching.

[0142] In this embodiment, the bottom surface of the fourth trench TR4 contacts the bottom surface of the lower pattern BP, and the side surface of the fourth trench TR4 contacts a portion of the interlayer insulating layer 190 that fills the isolation trench STI.

[0143] 35, a fifth trench (TR5) is formed below the source / drain pattern 150, penetrating the lower pattern (BP) in the third direction (D3). The fifth trench (TR5) penetrates the lower pattern (BP) in the third direction (D3) and is recessed into the source / drain pattern 150. The fifth trench (TR5) is formed by etching at least a portion of the lower pattern (BP) and the source / drain pattern 150. The side of the fifth trench (TR5) is defined by the lower pattern (BP) and the source / drain pattern 150. The bottom of the fifth trench (TR5) is defined by the source / drain pattern 150.

[0144] In this embodiment, the fifth trench (TR5) is formed by a dry etching process. For example, the fifth trench (TR5) may be formed by reactive ion etching (RIE) or inductively coupled plasma (ICP). However, the fifth trench (TR5) may be formed by a wet etching process.

[0145] 36, an insulating liner 220 is formed on the bottom surface of the fourth trench (TR4) and the side and bottom surfaces of the fifth trench (TR5). The insulating liner 220 extends from the bottom surface of the fourth trench (TR4) to the side and bottom surfaces of the fifth trench (TR5).

[0146] The insulating liner 220 is not located on the bottom and side surfaces of the interlayer insulating layer 190 that fills the inside of the isolation trench (STI). In this embodiment, the insulating liner 220 is formed by diffusing from the side and bottom surfaces of the fifth trench (TR5) into the lower pattern (BP) and the source / drain pattern 150. The insulating liner 220 located on the bottom surface of the fourth trench (TR4) is formed by diffusing from the bottom surface of the fourth trench (TR4) into the lower pattern (BP).

[0147] In this embodiment, the insulating liner 220 is formed by growing from the side and bottom surfaces of the fifth trench TR5 toward the interior of the fifth trench TR5. Thus, referring to Figures 35 and 36, the horizontal width of the fifth trench TR5 after the insulating liner 220 is formed is narrower than the horizontal width of the fifth trench TR5 before the insulating liner 220 is formed. Furthermore, the vertical depth of the fifth trench TR5 after the insulating liner 220 is formed is shallower than the vertical depth of the fifth trench TR5 before the insulating liner 220 is formed.

[0148] 37, a portion of the insulating liner 220 located between the bottom of the fifth trench TR5 and the source / drain pattern 150 is removed to expose a portion of the source / drain pattern 150. At this time, the insulating liner 220 located on the side of the fifth trench TR5 and the bottom of the fourth trench TR4 is not removed. Therefore, at least one additional photolithography process is performed.

[0149] The process of removing the portion of the insulating liner 220 is performed by an anisotropic etching process. For example, the portion of the insulating liner 220 is removed by a dry etching process using RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma). However, the method is not limited thereto, and the insulating liner 220 can also be removed by a wet etching process.

[0150] As shown in FIG. 38, a portion of the source / drain pattern 150 exposed at the bottom of the fifth trench TR5 is etched.

[0151] Next, as shown in FIG. 39, a silicide film 170 is formed on the bottom surface of the fifth trench TR5. The silicide film 170 is not formed on the side surfaces of the fifth trench TR5. The silicide film 170 is formed along the bottom surface of the source / drain pattern 150 exposed at the bottom surface of the fifth trench TR5. The silicide film 170 is formed, for example, by depositing a metal material on the side surfaces and bottom surface of the fifth trench TR5 and then annealing the metal material. The silicide film 170 is formed at the interface between the source / drain pattern 150 and the metal material. The silicide film 170 is not formed at the interface between the insulating liner 220 and the metal material. After the silicide film 170 is formed, the metal material deposited on the side surfaces and bottom surface of the fifth trench TR5 is removed.

[0152] 40, the fifth trench TR5 is filled with a conductive material to form the through electrode 180. Then, the fourth trench TR4 is filled with a conductive material to form the lower conductive layer 185. The lower conductive layer 185 is also formed on the lower surface of the interlayer insulating layer 190 that fills the shallow trench isolation (STI).

[0153] 41, a portion of the lower conductive layer 185 formed on the same plane as the surface including the lower surface of the interlayer insulating layer 190 filling the element isolation trench (STI) is removed. At this time, the portion of the lower conductive layer 185 is removed by a chemical mechanical polishing (CMP) process.

[0154] As shown in Figure 42, a lower wiring structure 410 electrically connected to the lower conductive layer 185 is formed on the lower surface of the lower conductive layer 185, and the semiconductor element described with reference to Figures 29 to 32 is manufactured.

[0155] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0156] 10 Substrate 105 Field Insulation Layer 110a, 110b, 110c, 110d semiconductor layers 120M Main gate electrode 120S sub-gate electrode 130M Main gate insulating film 130S sub-gate insulating film 141 Capping Layer 142 Gate spacer 150 Source / Drain Pattern 150a liner membrane 150b Peeling film 170 Silicide film 180 Through electrode 185 Lower conductive layer 190 Interlayer insulating layer 195 Upper insulating layer 210 Insulation Pattern 211 Sub-insulation pattern 212 Main insulation pattern 220 Insulation Liner 410 Lower wiring structure 411 Lower conductive pattern 412 Lower wiring insulation layer BP Lower Pattern CH channel layer GS Gate Structure M_GS Main gate structure S_GS Subgate structure STI isolation trench TR Trench TR1, TR2, TR3, TR4, TR5 1st to 5th trenches

Claims

1. A substrate; a channel layer located on the substrate; a gate structure surrounding the channel layer; source / drain patterns respectively connected to both sides of the channel layer; a lower wiring structure located below the substrate; an insulating pattern extending through the substrate and positioned below the gate structure and between the source / drain patterns; the insulating pattern includes a sub-insulating pattern located under the gate structure and a main insulating pattern located between the sub-insulating pattern and the underlying wiring structure; The semiconductor device, wherein the sub insulating pattern and the main insulating pattern include different insulating materials.

2. the sub insulating pattern has a lower surface in contact with an upper surface of the main insulating pattern; 2. The semiconductor device of claim 1, wherein the sub insulating pattern has a lower nitrogen concentration as it moves away from the interface with the main insulating pattern.

3. The semiconductor device of claim 1 , wherein the sub-insulating pattern comprises silicon nitride.

4. 3. The semiconductor device of claim 2, wherein the horizontal width of the sub insulation pattern increases and then decreases as it moves away from the main insulation pattern toward the bottom surface of the gate structure.

5. 3. The semiconductor device according to claim 2, wherein the sub-insulating pattern is further located between the substrate and the main insulating pattern.

6. The semiconductor device of claim 5 , wherein the sub insulating patterns surround the side surfaces of the main insulating pattern and have a nitrogen concentration that decreases with increasing distance from the side surfaces of the main insulating pattern.

7. the sub-insulation pattern contacts a lower surface of the gate structure; The semiconductor device of claim 1 , wherein the main insulating pattern contacts an upper surface of the lower wiring structure.

8. forming a channel layer on a substrate, a gate structure surrounding the channel layer, and source / drain patterns respectively connected to both sides of the channel layer; forming an insulating pattern below the gate structure and extending through the substrate, the insulating pattern including a sub insulating pattern and a main insulating pattern; forming an underlying wiring structure beneath the substrate; The step of forming the insulating pattern includes: forming a trench through the substrate adjacent a lower surface of the gate structure; forming a sub-insulation pattern between the trench and the gate structure; forming a main insulating pattern filling the trench; 4. A method for manufacturing a semiconductor device, wherein the sub insulating pattern and the main insulating pattern include different insulating materials.

9. forming a lower pattern including silicon between the surface of the substrate and the lower surface of the gate structure; 10. The method of claim 8, wherein forming the sub-insulating pattern comprises nitriding at least a portion of the lower pattern between the lower surface of the gate structure and the upper surface of the trench.

10. The lower pattern and a channel layer located on the lower pattern; a gate structure surrounding the channel layer; source / drain patterns respectively connected to both sides of the channel layer; a lower wiring structure located below the lower pattern; a through electrode penetrating the lower pattern and positioned between at least a portion of the source / drain pattern and the lower wiring structure; an insulating liner located between a side surface of the through electrode and the lower pattern, The insulating liner has a nitrogen concentration that decreases with increasing distance from the side of the through electrode toward the lower pattern.

Images