Semiconductor device and data storage system including the same

Abstract

To provide a semiconductor device which increases a degree of integration.SOLUTION: A semiconductor device includes: a conductive layer 101; a stack structure GS including lower gate electrodes 130L, memory gate electrodes 130M, and upper gate electrodes 130U stacked sequentially on the conductive layer and spaced apart from each other in a Z direction in first and second regions and an extension region R2 between the first and second regions; first and second channel structures CHa, CHb penetrating through the stack structure in the first and second regions and extending in the Z direction, respectively; contact plugs MC2 penetrating through the upper gate electrodes from above in the extension region and electrically connected to the memory gate electrodes and the lower gate electrodes, respectively; and insulating regions SS2a, SS2b penetrating through from above to the upper gate electrodes at boundaries between the extension region and the first and second regions and separating the upper gate electrodes into a first portion in the first region, a second portion in the second region and a third portion in the extension region. Each of the memory gate electrodes and the lower gate electrodes is continuously extended while being separated from the insulating regions.SELECTED DRAWING: Figure 4a

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems requiring data storage, semiconductor devices capable of storing large amounts of data are in demand. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device that can increase the degree of integration.

[0004] It is also an object of the present invention to provide a data storage system including a semiconductor device with improved integration density. [Means for solving the problem]

[0005] In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a conductive layer, a stacked structure including a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in sequence from the conductive layer and spaced apart from each other along a first direction perpendicular to an upper surface of the conductive layer in a first region, a second region, and an extension region between the first region and the second region, a first channel structure and a second channel structure penetrating the stacked structure and extending along the first direction in the first region and the second region, respectively, isolation regions extending along a second direction perpendicular to the first direction and penetrating the stacked structure in the first region, the extension region, and the second region, and spaced apart from each other in a third direction perpendicular to the first and second directions, and a second channel structure penetrating the upper gate electrode in each of the first and second regions between the isolation regions and extending along the second direction. a first insulating region extending in the third direction; a second insulating region dividing the top gate electrode into first and second top gate electrodes at a boundary between the first region and the extension region and a boundary between the second region and the extension region, and extending in the third direction; first string selection contact plugs in the first region contacting at least one of the first top gate electrodes from above and electrically connected to the first top gate electrodes; second string selection contact plugs in the second region contacting at least one of the second top gate electrodes from above and electrically connected to the second top gate electrodes; and word line contact plugs in the extension region penetrating the top gate electrodes from above and electrically connected to the memory gate electrode and the bottom gate electrode, respectively.

[0006] In order to achieve the above object, a semiconductor device according to another aspect of the present invention includes a conductive layer, a stacked structure including a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in sequence from the conductive layer at a distance from each other along a first direction perpendicular to an upper surface of the conductive layer in a first region, a second region, and an extension region between the first region and the second region, a first channel structure and a second channel structure extending along the first direction through the stacked structure in the first region and the second region, respectively, and a gate electrode extending from above the upper gate electrode in the extension region. the memory gate electrode and the bottom gate electrode may include a word line contact plug electrically connected to the memory gate electrode and the bottom gate electrode, respectively; and insulating regions penetrating from an upper portion to the top gate electrode at a boundary between the first region and the extension region and at a boundary between the second region and the extension region, and separating the top gate electrode into a first portion in the first region, a second portion in the second region, and a third portion in the extension region, wherein the memory gate electrode and the bottom gate electrode extend continuously in the first region, the extension region, and the second region, respectively, separated from the insulating regions.

[0007] In order to achieve the above object, according to one aspect of the present invention, a data storage system includes a semiconductor memory device including a first semiconductor structure including a circuit element, a second semiconductor structure disposed on one surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element, and a controller electrically connected to the semiconductor memory device via the input / output pad and controlling the semiconductor memory device, wherein the second semiconductor structure includes a conductive layer, a first region, an extension region, and a second region disposed in a first direction parallel to an upper surface of the conductive layer, the first region, an extension region, and a second region, the second region being stacked apart from each other along a second direction perpendicular to the first direction, the stacked structure including a memory gate electrode and an upper gate electrode from the conductive layer, and the first region and the second region being stacked apart from each other along a second direction perpendicular to the first direction. and in the second region, a first channel structure and a second channel structure respectively extending in the second direction through the stacked structure; common word line contact plugs penetrating the upper gate electrodes from above in the extension region and electrically connected to the memory gate electrodes; and insulating regions penetrating from above to the upper gate electrodes at boundaries between the first region and the extension region and at boundaries between the second region and the extension region and separating the upper gate electrodes, wherein each of the common word line contact plugs is simultaneously electrically connected to the first channel structure and the second channel structure via the memory gate electrodes connected thereto. [Effects of the Invention]

[0008] According to the present invention, a contact plug that contacts the contact region of the gate electrode can be formed in a contact plug formation process without a separate step process for forming the contact region of the gate electrode in a stepped shape. Therefore, since the process for forming the contact region of the gate electrode in a stepped shape can be omitted, memory regions can be arranged on both sides of the contact region of the gate electrode. Therefore, the memory regions on both sides are simultaneously selected by the contact region of one gate electrode, and the available area for arranging the memory regions is increased, thereby improving integration.

[0009] Therefore, it is possible to provide a semiconductor device with improved integration and a data storage system including the same.

[0010] The various yet significant advantages and effects of the present invention are not limited to the above, but will be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic circuit diagram of a semiconductor device according to an exemplary embodiment; [Figure 2] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 3] FIG. 3 is a perspective view for explaining a cutting structure of the gate electrode in FIG. 2. [Figure 4a] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 4b] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 4c] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 5a] FIG. 4b is an enlarged view of a region of FIG. 4a. [Figure 5b] FIG. 4b is an enlarged view of a region of FIG. 4a. [Figure 6] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 7] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 8] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 9] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 10a] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10c]1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10d] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10e] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10f] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10g] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10h] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10i] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10j] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 10k] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 11] 1 is a schematic diagram illustrating a data storage system including a semiconductor device according to an exemplary embodiment; [Figure 12] 1 is a perspective view that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following, terms such as "top," "upper portion," "upper surface," "upper," "lower portion," "lower surface," "under," "side," etc. will be referred to based on the drawings unless otherwise indicated by reference numerals.

[0013] FIG. 1 is a schematic circuit diagram of a semiconductor device according to an exemplary embodiment.

[0014] The semiconductor device 100 according to the exemplary embodiment includes a first memory region R1a and a second memory region R1b.

[0015] Memory cell strings CSTR are arranged in each of the first and second memory regions R1a and R1b. Each memory cell string CSTR has a string structure in which transistors are connected in series, and defines one channel structure CHa or CHb. Each memory cell string CSTR is connected to a bit line BL, a common source line CSL, a word line WL, and a string select line SSL.

[0016] Each of the memory cell strings CSTR in the first memory region R1a and the second memory region R1b includes lower transistors LTa, LTb adjacent to the common source lines CSLa, CSLb, upper transistors UTa, UTb adjacent to the bit lines BL, and a plurality of memory cell transistors MCTa, MCTb disposed between the lower transistors LTa, LTb and the upper transistors UTa, UTb. The number of the lower transistors LTa, LTb and the number of the upper transistors UTa, UTb may vary depending on the embodiment.

[0017] According to an exemplary embodiment, the upper transistors UTa and UTb comprise string select transistors, the lower transistors LTa and LTb comprise ground select transistors, the word line WL is the gate electrode of the memory cell transistors MCTa and MCTb, and the string select lines SSL1 to SSL4 are the gate electrodes of the upper transistors UTa and UTb, respectively.

[0018] A plurality of memory cell strings CSTR arranged in each of the first and second memory regions R1a and R1b are connected to respective bit lines BL, respective common source lines CSLa and CSLb, and respective string selection lines SSL1 to SSL4. At this time, the memory cell strings CSTR in the first and second memory regions R1a and R1b are commonly connected to the same word line WL at the same level and connected to a decoder by one contact plug (referred to as a common word line contact plug).

[0019] Therefore, when a select signal is applied to one word line WL, the gate voltage is simultaneously applied to the memory cell transistors MCTa and MCTb connected to the corresponding word line WL in the first memory region R1a and the second memory region R1b, but only the memory cell string CSTR selected by the bit line BL and the string select lines SSL1 to SSL4 is selectively driven.

[0020] In this way, the word lines WL are connected between the first memory region R1a and the second memory region R1b, and the contact plugs are arranged to be shared for each word line WL, so that the available area of ​​the memory cell string CSTR is increased without having to arrange contact plugs individually in each memory region R1a, R1b.

[0021] A semiconductor device in which the word line contact plug of FIG. 1 can be shared will be described below with reference to FIGS. 2 to 5b.

[0022] Fig. 2 is a schematic plan view of a semiconductor device according to an exemplary embodiment, Fig. 3 is a perspective view for explaining an isolation structure of the gate electrode in Fig. 2, and Figs. 4a to 4c are schematic cross-sectional views of the semiconductor device according to an exemplary embodiment. Fig. 4a is a cross-sectional view showing a region along line I-I' of the semiconductor device in Fig. 2, Fig. 4b is a cross-sectional view showing a region along line II-II' of the semiconductor device in Fig. 2, and Fig. 4c is a cross-sectional view showing a region along line III-III' of the semiconductor device in Fig. 2. Fig. 5a is a partially enlarged view showing region "A" of Fig. 4a, and Fig. 5b is a partially enlarged view showing region "B" of Fig. 4a.

[0023] 2 to 5b, the semiconductor device 100 includes a first semiconductor structure S1 and a second semiconductor structure S2, and the first semiconductor structure S1 is stacked in the Z direction, which is the vertical direction, relative to the second semiconductor structure S2. Specifically, the first semiconductor structure S1 is disposed below the second semiconductor structure S2 in the Z direction. In an exemplary embodiment, the second semiconductor structure S2 may be disposed below the first semiconductor structure S1, conversely.

[0024] In an exemplary embodiment, the semiconductor device 100 includes a first semiconductor structure S1 including a conductive layer 101 that is a common source line CSL, and a second semiconductor structure S2 in which a peripheral circuit region is formed. The second semiconductor structure S2 forms a peripheral circuit by forming transistors and metal patterns for wiring the transistors on a substrate 201. After the peripheral circuit is formed in the second semiconductor structure S2, it is bonded to the first semiconductor structure S1 to form one semiconductor device, but the embodiment is not limited to this.

[0025] The first semiconductor structure S1 of the semiconductor device 100 includes an extension region R2, and a first memory region R1a and a second memory region R1b on both sides of the extension region R2 along the X direction.

[0026] The first memory region R1a and the second memory region R1b are memory cell regions where the memory cell strings CSTR of Fig. 1 are arranged, and are regions where the channel structures CHa and CHb are arranged. The extension region R2 corresponds to a region for electrically connecting the channel structures CHa and CHb to the second semiconductor structure S2, and for this purpose, is a region where a plurality of word line contact plugs MC2 connected to the gate electrode 130 at different levels are arranged, but is not limited to this.

[0027] The first memory region R1a and the second memory region R1b are defined as, but not limited to, each of the mats MAT when multiple mats MAT are arranged. The extension region R2 is the central region between the multiple mats, as the region arranged between the adjacent first memory region R1a and second memory region R1b.

[0028] A first string selection region R2a is disposed between the first memory region R1a and the extension region R2, and a second string selection region R2b is disposed between the second memory region R1b and the extension region R2. The first string selection region R2a and the second string selection region R2b are defined as regions where string selection contact plugs MC1a and MC1b for selecting gate electrodes 130, which are string selection lines, are disposed.

[0029] The first semiconductor structure S1 has a structure in which a first memory region R1a, a first string selection region R2a, an extension region R2, a second string selection region R2b, and a second memory region R1b are sequentially arranged in the X direction. According to the separation of the gate electrode 130, the first memory region R1a and the first string selection region R2a are defined as a first region, and the second string selection region R2b and the second memory region R1b are defined as a second region, and the first region and the second region are defined as being arranged on both sides of the extension region R2. The first semiconductor structure S1 includes a conductive layer 101 in the first memory region R1a, the first string selection region R2a, the extension region R2, the second string selection region R2b, and the second memory region R1b, a stacked structure GS (GS1 to GS4) in which gate electrodes 130 and interlayer insulating layers 120 are alternately stacked on the upper surface of the conductive layer 101, channel structures CHa and CHb arranged in the first memory region R1a and the second memory region R1b so as to penetrate the stacked structures GS1 to GS4, an isolation region MS extending in the X direction penetrating the stacked structures GS1 to GS4, and an insulating region SS penetrating a portion of the gate electrode 130. A wiring structure and a passivation layer are further included below the conductive layer 101.

[0030] A support structure DH and a word line contact plug MC2 are disposed in the extension region R2, and a support structure DH and string selection contact plugs MC1a and MC1b are disposed in the first string selection region R2a and the second string selection region R2b.

[0031] As shown in FIGS. 2 and 4a, the first memory region R1a and the second memory region R1b are arranged on both sides of the extension region R2 in the X direction and have a symmetrical structure. The first string selection region R2a and the second string selection region R2b are arranged on both sides of the extension region R2 in the X direction and have a symmetrical structure. Here, "symmetrical" does not only mean that the arrangement has an exact mirror image, but also that the arrangement has a functionally equivalent structure. Therefore, various modifications are possible, including point symmetry and line symmetry, as long as the number of contact plugs MC1a and MC1b is the same and the contact structure of the gate electrode 130 is the same.

[0032] Although the contact plugs MC1a, MC1b, and MC2 are shown in FIGS. 4a to 4c as extending to different lengths to connect each gate electrode 130 to the contact plugs MC1a, MC1b, and MC2, the present invention is not limited thereto.

[0033] The extension region R2, the first memory region R1a, and the second memory region R1b include a cell region insulating layer 150 on top of the stacked structures GS1 to GS4, and include studs 185 penetrating the cell region insulating layer 150 for electrical connection with the channel structures CHa, CHb and contact plugs MC1a, MC1b, and MC2, an upper wiring structure 180 on top of the cell region insulating layer 150, and first bonding structures 195 and 198 connected to the upper wiring structure 180.

[0034] The conductive layer 101 includes at least one of a conductive material such as doped silicon and a conductive material such as a metal or metal nitride, etc. For example, the conductive layer 101 includes a silicon layer having N-type conductivity, which is a common source.

[0035] The gate electrodes 130 are stacked vertically on the upper surface of the conductive layer 101 at intervals, and form stacked structures GS1, GS2, GS3, and GS4 together with the interlayer insulating layer 120. The gate electrodes 130 extend from the extension region R2 to the first memory region R1a and the second memory region R1b on both sides, but the upper gate electrode 130U is physically and electrically separated between the first string selection region R2a and the second string selection region R2b and the extension region R2.

[0036] The stacked structures GS1, GS2, GS3, and GS4 include multiple stacked structures GS1 to GS4 stacked vertically. While Figures 4a and 4c illustrate the stacked structures as including first to fourth stacked structures GS1, GS2, GS3, and GS4, the stacked structures are not limited to this and may include five to eight stacked structures GS1 to GSn. However, depending on the embodiment, the stacked structures GS1 to GSn may each be a single stacked structure.

[0037] The gate electrode 130 includes at least one bottom gate electrode 130L forming the gate of a ground selection transistor, memory gate electrodes 130M forming a plurality of memory cells, and a top gate electrode 130U serving as a string selection line forming the gate of a string selection transistor. Here, the bottom gate electrode 130L and the top gate electrode 130U are referred to as "bottom" and "top" based on the direction during the manufacturing process. The number of memory gate electrodes 130M forming memory cells is determined depending on the capacity of the semiconductor device 100. Depending on the embodiment, the top and bottom gate electrodes 130U and 130L may each be one, two, or more, and may have the same or different structure as the memory gate electrode 130M. In an exemplary embodiment, the number of top gate electrodes 130U is shown as three. An erase gate electrode is further disposed below the top gate electrode 130U. Furthermore, some of the gate electrodes 130, for example, the memory gate electrodes 130M adjacent to the top or bottom gate electrodes 130U and 130L, may be dummy gate electrodes, but are not limited to this.

[0038] 2 and 3, the gate electrodes 130 are separated from each other in the Y direction by an isolation region MS that extends continuously from the first memory region R1a through the extension region R2 into the second memory region R1b. The gate electrodes 130 between a pair of isolation regions MS form one memory block BLK, but the scope of the memory block BLK is not limited thereto. Some of the gate electrodes 130, for example, memory gate electrode 130M, each form one layer within one memory block BLK.

[0039] The gate electrodes 130 are stacked vertically and spaced apart from one another in the first memory region R1a, the first string selection region R2a, the extension region R2, the second string selection region R2b, and the second memory region R1b, and maintain a continuous plate shape without forming a stepped structure even in the extension region R2. The contact regions of each gate electrode 130 are defined as regions in contact with the contact plugs MC1a, MC1b, and MC2 in the first string selection region R2a, the second string selection region R2b, and the extension region R2.

[0040] The gate electrode 130 may be made of, but is not limited to, W, Ru, Mo, Nb, Ni, Co, Ti, Ta, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. According to an exemplary embodiment, the gate electrode 130 further includes a diffusion barrier layer 131, for example, the diffusion barrier layer 131 includes tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0041] The interlayer insulating layers 120 are disposed between the gate electrodes 130 to form stacked structures GS1, GS2, GS3, and GS4. Similar to the gate electrodes 130, the interlayer insulating layers 120 are also disposed to extend in the X direction and spaced apart from each other in a direction perpendicular to the top surface of the conductive layer 101. The interlayer insulating layers 120 include an insulating material such as silicon oxide or silicon nitride.

[0042] In the embodiment, the interlayer insulating layers 120 all have the same thickness. As an example, the uppermost interlayer insulating layer 121 of the interlayer insulating layers 120 has a thickness greater than the other interlayer insulating layers 120, but is not limited thereto.

[0043] The isolation region MS is disposed to extend along the X direction, penetrating at least a portion of the gate electrode 130. The isolation region MS extends along the X direction, sequentially crossing the first memory region R1a, the first string selection region R2a, the extension region R2, the second string selection region R2b, and the second memory region R1b. The isolation regions MS are disposed parallel to each other. The isolation region MS penetrates the entire stacked gate electrode 130 and is connected to the conductive layer 101. The isolation region MS extends along the X direction, but may extend partially intermittently or may be disposed in only a portion of the region. The isolation region MS has a line shape on the XY plane, but may alternatively have a shape extending along the X direction with a continuously curved side.

[0044] An isolation insulating layer 164 is disposed in the isolation region MS. The isolation insulating layer 164 has a shape with a high aspect ratio that narrows toward the conductive layer 101, but is not limited to this. The upper surface of the isolation insulating layer 164 contacts the upper insulating layer 150, and the lower surface contacts the upper surface of the conductive layer 101.

[0045] The insulating region SS includes first insulating regions SS1a and SS1b extending in the X direction and second insulating regions SS2a and SS2b extending in the Y direction between adjacent isolation regions MS. The insulating region SS selectively penetrates only the upper gate electrodes 130U1 to 130U3, i.e., the string selection lines SSL, and divides the upper gate electrodes 130U1 to 130U3 of the stacked structures GS1 to GS4 into a plurality of sub-regions RS0 to RS8.

[0046] 3, second insulating regions SS2a and SS2b separate the upper gate electrodes 130U1-130U3 by crossing the extension region R2 and the first and second string selection regions R2a and R2b in the Y direction. The second insulating regions SS2a and SS2b are respectively disposed between the extension region R2 and the first string selection region R2a and between the extension region R2 and the second string selection region R2b. When at least three upper gate electrodes 130U1-130U3 are assigned to a string selection line, the three upper gate electrodes 130U1-130U3 are simultaneously penetrated by the second insulating regions SS2a and SS2b and divided into a plurality of sub-regions RS0-RS8 that are physically / electrically separated on a plane. To this end, the second insulating regions SS2a and SS2b are formed of an insulating material 168.

[0047] The first insulating regions SS1a and SS1b include a first horizontal insulating region SS1a extending across the first memory region R1a and the first string selection region R2a in the X direction, and a second horizontal insulating region SS1b extending across the second memory region R1b and the second string selection region R2b. A plurality of first horizontal insulating regions SS1a and second horizontal insulating regions SS1b are arranged between the isolation regions MS, and like the second insulating regions SS2a and SS2b, selectively isolate only the upper gate electrodes 130U1 to 130U3.

[0048] The first insulating regions SS1a, SS1b and the second insulating regions SS2a, SS2b are arranged to have the same length in the Z direction from the top, and their bottoms are arranged at a level lower than the lower surface of the lowest upper gate electrode 130U1 among the upper gate electrodes 130U1-130U3 and higher than the lower surface of the interlayer insulating layer 120 below the lowest upper gate electrode 130U1. Therefore, the first insulating regions SS1a, SS1b and the second insulating regions SS2a, SS2b completely penetrate all of the upper gate electrodes 130U1-130U3, and the upper gate electrodes 130U1-130U3 form a plurality of sub-regions RS0-RS8 that are completely separated physically / electrically as shown in FIG. In FIG. 3, the sub-area RS0 in the extension region R2 and the upper gate electrodes 130U1 to 130U3 of each memory region and string selection region R1a, R2a / R1b, R2b are shown as being separated into four sub-areas RS1 to RS4 / RS5 to RS8, respectively, but this is not limited to this.

[0049] Such insulating regions SS1a, SS1b, SS2a, and SS2b are not arranged within the extension region R2, but separate the extension region R2 from the string selection regions R2a and R2b, and separate the string selection regions R2a and R2b into multiple sub-regions RS1 to RS8. As a result, as shown in FIG. 3, the upper gate electrodes 130U1 to 130U3 are not separated within the extension region R2, but form one plate-shaped sub-region RS0. At this time, the insulating regions SS1a, SS1b, SS2a, and SS2b selectively penetrate only the upper gate electrodes 130U1 to 130U3 and do not extend below the memory gate electrode 130M, so that the memory gate electrode 130M and the lower gate electrode 130L are not separated by the insulating regions SS1a, SS1b, SS2a, and SS2b, and the first memory region R1a, the first string selection region R2a, the extension region R2, the second string selection region R2b, and the second memory region R1b are all stacked in a single plate shape.

[0050] The first insulating regions SS1a and SS1b may extend at one end into the extension region R2 across the second insulating regions SS2a and SS2b, but are not limited to this, and are arranged to be connected to the second insulating regions SS2a and SS2b.

[0051] The first insulating regions SS1a and SS1b are disposed in the first and second memory regions R1a and R1b, crossing portions of the channel structures CHa and CHb. The first insulating regions SS1a and SS1b have a predetermined width in the Y direction and extend in the X direction between the channel structures CHa and CHb arranged in a staggered matrix. Therefore, when the channel structures CHa and CHb are arranged with the same spacing, the first insulating regions SS1a and SS1b simultaneously extend across a row of the channel structures CHa and CHb. The first insulating regions SS1a and SS1b form recesses in the upper ends of the channel structures CHa and CHb, e.g., portions of the channel structures CHa and CHb facing the three upper gate electrodes 130U, thereby removing portions of the channel structures CHa and CHb. The channel structures CHa and CHb are recessed by a length smaller than the radius of the channel structures CHa and CHb from the channel center axis to the inner wall of the channel hole. Therefore, the first insulating regions SS1a and SS1b do not pass through the channel central axes of the channel structures CHa and CHb, and are arranged so that at least half of the channel structures CHa and CHb remain on the upper surfaces, but are not limited to this. The channel structures CHa and CHb with the recessed first insulating regions SS1a and SS1b are not dummy channel structures but are effective channel structures that essentially function as memory cells. The insulating regions SS1a, SS1b, SS2a, and SS2b each include an upper isolation insulating layer 168. The upper isolation insulating layer 168 includes an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0052] The channel structures CHa and CHb are arranged in rows and columns on the conductive layer 101 in the first memory region R1a and the second memory region R1b, spaced apart from each other. The channel structures CHa and CHb include first channel structures CHa and second channel structures CHb arranged in the first memory region R1a and the second memory region R1b, respectively, and the arrangements of the first channel structures CHa and the second channel structures CHb are the same or mirror images. In each of the first memory region R1a and the second memory region R1b, the first channel structures CHa and the second channel structures CHb are arranged in a staggered pattern in one direction in the XY plane. The first channel structures CHa and the second channel structures CHb penetrate the gate electrode 130 and extend in a vertical direction perpendicular to the top surface of the conductive layer 101, for example, in the Z direction, and have a columnar shape with inclined side surfaces that narrow toward the conductive layer 101 according to the aspect ratio.

[0053] Each of the first channel structure CHa and the second channel structure CHb has a form in which first to fourth channel portions that penetrate the first to fourth stack structures GS1 to GS4 of the gate electrode 130, respectively, are connected, and has a bent portion due to a difference or change in width in the extension region R2.

[0054] As shown in the enlarged view of Figure 5a, each of the first channel structure CHa and the second channel structure CHb includes a first portion within the stacked structures GS1 to GS4 and a second portion that protrudes below the stacked structures GS1 to GS4 and contacts the conductive layer 101.

[0055] The channel layer 140 is disposed over the entire first and second portions of the first and second channel structures CHa and CHb, extending up to the top of the second portion. The channel layer 140 includes a protruding portion disposed in the second portion of the first and second channel structures CHa and CHb and protruding and exposed below the stacked structures GS1-GS4, and a non-protruding portion disposed in the first portion of the channel structures CHa and CHb. The protruding lengths of the second portions of the first and second channel structures CHa and CHb and the protruding portion of the channel layer 140 are the same, but are not limited thereto. The channel layer 140 is formed in an annular shape with its side surfaces surrounding the buried insulating layer 147 therein. However, depending on the embodiment, it may have a columnar or rectangular pillar shape without the buried insulating layer 147. The protruding portion of the channel layer 140 extends into the conductive layer 101 and makes direct contact with the conductive layer 101. The protruding portion is formed to have a gentle slope with respect to the non-protruding portion so as to maintain the annular shape, as shown in FIG. 5a. The channel layer 140 includes a semiconductor material, such as polycrystalline silicon or single crystalline silicon, which may be undoped or may include P-type or N-type impurities.

[0056] In the first and second channel structures CHa and CHb, a channel pad 149 is disposed on the channel layer 140. The channel pad 149 is disposed to cover the upper surface of the buried insulating layer 147 and to be electrically connected to the channel layer 140. The channel pad 149 includes, for example, doped polycrystalline silicon.

[0057] The channel dielectric layer 145 is disposed between the gate electrode 130 and the channel layer 140. The channel dielectric layer 145 includes a tunneling layer 141, a charge storage layer 142, and a blocking layer 143, which are stacked in sequence on the channel layer 140. The tunneling layer 141 tunnels charges to the charge storage layer 142 and includes, for example, silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. The charge storage layer 142 is a charge trap layer or a floating gate conductive layer. The blocking layer 143 includes silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. According to an exemplary embodiment, at least a portion of the channel dielectric layer 145 may form a channel dielectric layer extending horizontally along the gate electrode 130.

[0058] The channel dielectric layer 145 is removed below the stacked structures GS1 to GS4 so that the protruding portion of the channel layer 140 is exposed to the outside in the second portion. Therefore, the lower end of the channel dielectric layer 145 contacts the conductive layer 101, and the side surfaces of the channel dielectric layer 145 are arranged to surround the non-protruding portion of the channel layer 140 in the first portion.

[0059] Between the first to fourth channel portions, the channel layer 140, the channel dielectric layer 145, and the buried insulating layer 147 are connected to one another.

[0060] The support structures DH are disposed in the first string selection region R2a, the extension region R2, and the second string selection region R2b. They have the same or similar structure as the channel structures CHa and CHb, but do not perform any substantial function within the semiconductor device 100. The support structures DH are regularly arranged in rows and columns in the first string selection region R2a, the extension region R2, and the second string selection region R2b. The support structures DH have a maximum diameter equal to or larger than that of the channel structures CHa and CHb, and a diameter equal to or smaller than that of the contact plugs MC1a, MC1b, and MC2. The shape, number, and / or spacing of the support structures DH may vary. The channel structures CHa and CHb and the support structures DH have a circular or near-circular shape, but are not limited thereto, and may have an elliptical shape. The support structure DH, like the channel structures CHa and CHb, penetrates the stacked structures GS1 to GS4 and includes a vertical portion extending in the Y direction and a horizontal portion protruding from the vertical portion toward each gate electrode 130, but the shape of the support structure DH is not limited to this. The support structure DH is a supporter that prevents deformation such as warping of the stacked structures GS1 to GS4.

[0061] The first semiconductor structure S1 includes contact plugs MC1a, MC1b, and MC2 connected to the gate electrode 130 in the first string selection region R2a, the extension region R2, and the second string selection region R2b, respectively. The contact plugs MC1a, MC1b, and MC2 penetrate at least a portion of the uppermost interlayer insulating layer 121, extend downward in the Z direction, and are connected to upper surfaces of the assigned gate electrodes 130. As shown in FIGS. 2 and 3, the contact plugs MC1a, MC1b, and MC2 have a circular or elliptical shape on the XY plane and are spaced apart from each other in the X and Y directions. The contact plugs MC1a, MC1b, and MC2 are arranged in a lattice or staggered pattern.

[0062] Each of the contact plugs MC1a, MC1b, and MC2 includes a plug conductive layer 175, and a side insulating layer 160 is further disposed on a side surface of the plug conductive layer 175. In each of the contact plugs MC1a, MC1b, and MC2, the plug conductive layer 175 is in contact with and coupled to a contact region of one of the gate electrodes 130, and the side insulating layer 160 electrically insulates the plug conductive layer 175 from the gate electrode 130 adjacent to the side surface of the plug conductive layer 175. The plug conductive layer 175 continuously extends from a lower surface of the contact plug MC1a, MC1b, and MC2 that is in contact with the contact region of the gate electrode 130 to an upper surface of the contact plug MC1a, MC1b, and MC2.

[0063] In the embodiment, eight gate electrodes 130 are allocated to each of the stacked structures GS1 to GS4, and at least one contact plug MC1a, MC1b, MC2 is disposed in physical / electrical contact with each gate electrode 130. The number of gate electrodes 130 in the first to fourth stacked structures GS1 to GS4 is an example and is not limited to this.

[0064] The contact plugs MC1a, MC1b, and MC2 include string selection contact plugs MC1a and MC1b and a word line contact plug MC2.

[0065] The string selection contact plugs MC1a and MC1b are disposed in the first string contact region R2a and the second string contact region R2b, and are respectively connected to a predetermined number of upper upper gate electrodes 130U1 to 130U3 that function as string selection lines among the upper gate electrodes 130U1 to 130U3.

[0066] 1 to 5b show an example in which three string selection lines are included, and therefore, according to this description, three string selection contact plugs MC1a, MC1b coupled to the upper gate electrodes 130U1 to 130U3, which are the string selection lines, are disposed in each of the sub-areas RS1 to RS8. That is, the string selection contact plugs MC1a, MC1b coupled to the respective string selection lines are disposed in the sub-areas RS1 to RS8 of the upper gate electrode 130U, which are divided by the first and second insulating regions SS1a, SS1b, SS2a, and SS2b. In the embodiment, one string selection contact plug MC1a, MC1b is coupled to each of the upper gate electrodes 130U1 to 130U3, but, alternatively, multiple string selection contact plugs MC1a, MC1b may be coupled to one upper gate electrode 130U1 to 130U3. Therefore, the number of string selection contact plugs MC1a, MC1b assigned to each of the sub-areas RS1 to RS8 is the same, and the number of string selection contact plugs MC1a, MC1b assigned to each of the sub-areas RS1 to RS8 is an integer multiple of the number of gate electrodes functioning as string selection lines.

[0067] In each of the sub-areas RS1 to RS8, the first to third upper gate electrodes 130U1 to 130U3 are individually connected by three string selection contact plugs MC1a and MC1b to transmit electrical signals and select the channel structures CHa and CHb of the corresponding sub-areas RS1 to RS8.

[0068] The string selection contact plugs MC1a and MC1b do not protrude outside the sub-regions RS1 to RS8 of the first to third upper gate electrodes 130U1 to 130U3, and the lower ends of the first string selection contact plugs MC1a and MC1b are in direct contact with the upper surface of the uppermost upper gate electrode 130U3, the lower ends of the second string selection contact plugs MC1a and MC1b are in direct contact with the upper surface of the next-uppermost upper gate electrode 130U2, and the lower ends of the third string selection contact plugs MC1a and MC1b are in direct contact with the upper surface of the third upper gate electrode 130U1 located below the next-uppermost upper gate electrode 130U2. Therefore, the string selection contact plugs MC1a and MC1b do not extend outside the sub-regions RS1 to RS8 formed by cutting the three first to third upper gate electrodes 130U1 to 130U3, i.e., below the third upper gate electrode 130U1. The arrangement of the string selection contact plugs MC1a and MC1b in each of the sub-areas RS1 to RS8 is substantially the same.

[0069] When word line contact plugs MC2 are allocated in the extension region R2, each connected to the memory gate electrode 130M and the lower gate electrode 130L, the word line contact plugs MC2 are arranged to have different lengths so as to be connected to the gate electrodes 130M and 130L at different levels.

[0070] 2 to 5b, the first to fourth stacked structures GS1 to GS4 are shown as including eight gate electrodes 130 each, with the top three gate electrodes 130U functioning as string selection lines, leaving 29 gate electrodes 130M and 130L remaining. Word line contact plugs MC2, the lengths of which are adjusted so as to contact the top surfaces of the 29 gate electrodes 130M and 130L, are disposed within the extension region R2.

[0071] The word line contact plugs MC2 may be arranged in various ways. In the embodiment, the word line contact plugs MC2 are arranged in a row in the Y direction, lowering stepwise in the Z direction to contact the gate electrodes 130. Therefore, as shown in FIG. 4c, the word line contact plugs MC2 arranged in the Y direction increase in length in the Z direction so as to contact the fourth to seventh gate electrodes 130, respectively. In the second row, the word line contact plugs MC2 extend again to contact the eighth to eleventh gate electrodes 130, respectively. In this manner, the word line contact plugs MC2 are arranged in the X direction toward the second memory region R1b, and the word line contact plugs MC2 are arranged in the Y direction so as to increase in length. However, the word line contact plugs MC2 may be arranged in a row symmetrically, increasing in length toward the center.

[0072] In each of the contact plugs MC1a, MC1b, and MC2, the side insulating layer 160 is disposed only on the side of the plug conductive layer 175 so that the underlying gate electrode 130 and the lower surface of the plug conductive layer 175 are in direct contact with each other, and depending on the embodiment, some of the plug conductive layers 175 are disposed so as to extend to a level lower than the upper surface of the assigned gate electrode 130, but do not extend to a level lower than the lower surface of the assigned gate electrode 130. Therefore, the lower surface of the plug conductive layer 175 is located at the same level as or lower than the upper surface of the gate electrode 130 it contacts, and at a higher level than the lower surface.

[0073] 5b, each of the contact plugs MC1a, MC1b, and MC2 further includes a contact barrier layer 172 that covers a portion of the top surface, side surface, and bottom surface of the plug conductive layer 175.

[0074] The plug conductive layer 175 of the contact plugs MC1a, MC1b, and MC2 includes a conductive material, such as at least one of tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. For example, the plug conductive layer 175 includes tungsten (W). The contact barrier layer 172 includes tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0075] The side insulating layer 160 includes an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0076] The contact plugs MC1a, MC1b, and MC2 all have the same structure, differing only in length. The contact plugs MC1a, MC1b, and MC2 have a width that gradually decreases toward the conductive layer 101. The maximum width of the contact plugs MC1a, MC1b, and MC2 is greater than the maximum width of the channel structures CHa and CHb and is equal to or greater than the maximum width of the support structure DH. The contact plugs MC1a, MC1b, and MC2 have a bent portion BP at the side thereof that is bent according to the level of the gate electrode 130 they contact. Contact plugs MC1a, MC1b, and MC2 may have multiple bent portions BP according to the number of levels, but are not limited to this. For example, as shown in FIG. 5b, the third of the string selection contact plugs MC1a and MC1b includes a bent portion BP in a region that abuts the top surface of the second gate electrode 130U2 from the top, and its width decreases along the bent portion BP, gradually decreasing toward the conductive layer 101.

[0077] In the first string selection region R2a, the extension region R2, and the second string selection region R2b, the support structures DH are arranged in a regular pattern around the contact plugs MC1a, MC1b, and MC2. As an example, but not limited to, the support structures DH and the contact plugs MC1a, MC1b, and MC2 are alternately arranged as shown in FIG.

[0078] The cell region insulating layer 150 is disposed to cover the gate structures GS1 to GS4. The cell region insulating layer 150 may include multiple insulating layers depending on the embodiment. The cell region insulating layer 150 is made of an insulating material, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0079] The studs 185 and the cell wiring lines 180 constitute a cell wiring structure electrically connected to the memory cells. The studs 185 penetrate a portion of the cell region insulating layer 150 to connect to the channel structures CHa, CHb and contact plugs MC1a, MC1b, and MC2, and are electrically connected to the channel layer 140 and the gate electrode 130. The studs 185 have a plug shape, and the cell wiring lines 180 have a line shape, but are not limited thereto. The studs 185 and the cell wiring lines 180 include metals, such as tungsten (W), copper (Cu), or aluminum (Al).

[0080] An upper insulating layer 190 is further disposed on the cell region insulating layer 150 to cover the cell wiring line 180. The upper insulating layer 190 is made of an insulating material, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. An upper portion of the upper insulating layer 190 functions as a first bonding insulating layer.

[0081] The first bonding via 195, the first bonding metal layer 198, and the first bonding insulating layer form a first bonding structure of the first semiconductor structure S1. The first bonding via 195 is disposed on the cell wiring line 180, and the first bonding metal layer 198 is connected to the first bonding via 195. The top surface of the first bonding metal layer 198 is exposed to the top surface of the first semiconductor structure S1. The first bonding metal layer 198 is bonded to and connected to the second bonding metal layer 298 of the second semiconductor structure S2. The first bonding via 195 and the first bonding metal layer 198 include a conductive material, for example, copper (Cu). The first bonding insulating layer forms a dielectric-dielectric bond with the second bonding insulating layer of the second semiconductor structure S2.

[0082] Meanwhile, the second semiconductor structure S2 includes a substrate 201, a source / drain region 205 and an element isolation layer 210 in the substrate 201, a circuit element 220 arranged on the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270, a circuit wiring line 280, a second bonding via 295, and a second bonding insulating layer 298.

[0083] The substrate 201 has a bottom surface extending in the X and Y directions. An active region is defined in the substrate 201 by an isolation layer 210. A source / drain region 205 containing impurities is disposed in a portion of the active region. The substrate 201 includes a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 is provided as a bulk wafer or an epitaxial layer.

[0084] The circuit elements 220 include planar transistors. Each circuit element 220 includes a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. On either side of the circuit gate electrode 225, source / drain regions 205 are disposed in the substrate 201 as source / drain regions.

[0085] The peripheral region insulating layer 290 is disposed on the lower surface of the substrate 201 to cover the circuit elements 220. The peripheral region insulating layer 290 may include multiple insulating layers formed in different process steps. The peripheral region insulating layer 290 is made of an insulating material. A portion of the peripheral region insulating layer 290 functions as a second bonding insulating layer.

[0086] The circuit contact plugs 270 and the circuit wiring lines 280 form circuit wiring structures electrically connected to the circuit elements 220 and the source / drain regions 205. The circuit contact plugs 270 have a cylindrical shape, and the circuit wiring lines 280 have a line shape. Electrical signals are applied to the circuit elements 220 through the circuit contact plugs 270 and the circuit wiring lines 280. In an area not shown, the circuit contact plugs 270 are also connected to the circuit gate electrodes 225. The circuit wiring lines 280 are connected to the circuit contact plugs 270 and are arranged in multiple layers. The circuit contact plugs 270 and the circuit wiring lines 280 include a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al), and each may further include a diffusion barrier layer. In an exemplary embodiment, the number of layers of the circuit contact plugs 270 and the circuit wiring lines 280 may vary.

[0087] The second bonding via 295, the second bonding metal layer 298, and the second bonding insulating layer constitute a second bonding structure and are disposed under a portion of the lowest circuit wiring line 280. The second bonding via 295 has a cylindrical shape, and the second bonding metal layer 298 has a pad shape or a relatively short line shape with a circular shape on a plan view. The bottom surface of the second bonding metal layer 298 is exposed to the bottom surface of the second substrate structure S2. The second bonding via 295 and the second bonding metal layer 298 provide an electrical connection path with the first semiconductor structure S1. In an exemplary embodiment, a portion of the second bonding metal layer 298 is not connected to the circuit wiring line 280 and is disposed solely for bonding. The second bonding via 295 and the second bonding metal layer 298 include a conductive material, such as copper (Cu).

[0088] The second bonding insulating layer is defined to a predetermined thickness from the lower surface of the peripheral region insulating layer 290, and may be realized as a separate insulating layer on the lower surface of the peripheral region insulating layer 290. The second bonding insulating layer is a layer for dielectric-dielectric bonding with the first bonding insulating layer of the first semiconductor structure S1. The second bonding insulating layer also functions as a diffusion barrier layer for the second bonding metal layer 298 and includes, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0089] The first and second semiconductor structures S1 and S2 are bonded by bonding the first bonding metal layer 198 and the second bonding metal layer 298 and bonding the first bonding insulating layer and the second bonding insulating layer. The bonding between the first bonding metal layer 198 and the second bonding metal layer 298 is, for example, copper (Cu)-copper (Cu) bonding, and the bonding between the first bonding insulating layer and the second bonding insulating layer is, for example, dielectric-dielectric bonding such as SiCN-SiCN bonding. The first and second semiconductor structures S1 and S2 are bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0090] The first and second semiconductor structures S1 and S2 are packaged with the first semiconductor structure S1 located on the bottom as shown in FIGS. 4a to 4c, or alternatively, they are packaged upside down with the second semiconductor structure S2 located on the bottom.

[0091] 6 and 7 are schematic cross-sectional views of semiconductor devices according to example embodiments.

[0092] 6, in the semiconductor device 100a, the top gate electrode 130U3 of the upper gate electrodes 130U functions as a string selection line, and the first and second insulating regions SS1a, SS1b, SS2a, and SS2b extend to a level lower than the bottom surface of the top gate electrode 130U3 to separate them from each other.

[0093] The first and second string selection contact plugs MC1a and MC1b are different from the string selection contact plugs of FIGS. 2 to 5b in that they only include a plug-shaped conductive layer 177.

[0094] That is, only the conductive layer 177 is disposed in a plug shape without a separate side insulating layer, and is disposed to contact the upper surface of the uppermost gate electrode 130U3 in the first and second string selection regions R2a and R2b, respectively.

[0095] Therefore, the word line contact plugs MC2 are arranged to contact the gate electrodes 130 at a level lower than the top gate electrode 130U3, and the shape of the word line contact plugs MC2 is the same as the shape of FIG. 5b including the plug conductive layer 170 and the side insulating layer 160. As such, the shapes of the first and second string selection contact plugs MC1a and MC1b and the word line contact plug MC2 are different from each other.

[0096] 7, the semiconductor device 100b is the same as the semiconductor device of FIGS. 2 to 5b except for the structures of the string selection contact plugs MC1a and MC1b and the upper gate electrode 130U of the string selection line. The semiconductor device 100b differs from the semiconductor device of FIGS. 2 to 5b in the shapes of the first and second string selection contact plugs MC1a and MC1b and the word line contact plug MC2.

[0097] The upper gate electrode 130U includes contact regions for contacting the first and second string selection contact plugs MC1a and MC1b in the first string selection region R2a and the second string selection region R2b, and includes a stepped step structure GP so that the corresponding contact regions are exposed to the outside.

[0098] When the three upper gate electrodes 130U1-130U3 are assigned as string selection lines, the three upper gate electrodes 130U1-130U3 have a stepped structure GP whose length increases as it descends. This also forms a stepped dummy step structure GP in the extension region R2 on the opposite side, but the step width of the dummy step structure GP in the extension region R2 is different from the step width of the step structure GP in the first and second string selection regions R2a and R2b. For example, the step width of the dummy step structure GP in the extension region R2 is narrower than the step width of the step structure GP in the first and second string selection regions R2a and R2b, but this is not limiting.

[0099] String selection contact plugs MC1a and MC1b are arranged so as to be in contact with the contact regions of the string selection lines exposed by the stepped step structure GP.

[0100] The string selection contact plugs MC1a and MC1b are similarly formed of only the conductive layer 177. That is, only the conductive layer 177 is arranged in a plug shape without a separate side insulating layer, and is arranged to contact the upper surface of the exposed contact region of the upper gate electrode 130U, respectively. Therefore, the string selection contact plugs MC1a and MC1b have different lengths in each of the sub-regions RS1 to RS8.

[0101] In the extension region R2, the word line contact plugs MC2 are arranged to contact the gate electrodes 130M and 130L, which are at a lower level than the upper gate electrodes 130U1 to 130U3, respectively, and the shape of the word line contact plugs MC2 is the same as the shape of Figure 5b, including the plug conductive layer 175 and the side insulating layer 160.

[0102] 8 is a schematic plan view of a semiconductor device according to an exemplary embodiment, and FIG. 9 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment, the cross-sectional view being taken along the cutting line IV-IV' of the semiconductor device of FIG. 8.

[0103] 8 and 9, the second semiconductor structure S2 of the semiconductor device 100c is disposed below the first semiconductor structure S1. The first semiconductor structure S1 further includes an edge region R3, and further includes a through via 178, first and second horizontal conductive layers 104 and 106, a horizontal insulating layer 105, and a substrate insulating layer 121 disposed in the edge region R3. In the semiconductor device 100c, the first semiconductor structure S1 is not bonded to the second semiconductor structure S2, but is formed on the second semiconductor structure S2. As a result, the first and second semiconductor structures S1 and S2 do not include the above-mentioned bonding structure.

[0104] The edge region R3 is a region where the gate electrode 130 does not extend. In the edge region R3, sacrificial insulating layers 118 and interlayer insulating layers 120 are alternately stacked on the plate layer 103. Alternatively, a separate capping layer may be disposed, but is not limited to this. The through via 178 extends through the sacrificial insulating layer 118 and the interlayer insulating layer 120 into the second semiconductor structure S2.

[0105] The through via 178 electrically connects the upper wiring line 199 and the circuit wiring line 280 .

[0106] In particular, the upper insulating layer 190 further includes upper studs 196 in contact with the cell wiring lines 180 connected to the contact plugs MC1a, MC1b, and MC2, and upper wiring lines 199 connected to the upper studs. The upper wiring lines 199 are connected to the contact plugs MC1a, MC1b, and MC2 and to the through vias 178, respectively, to electrically connect the second semiconductor structure S2 and the contact plugs MC1a, MC1b, and MC2.

[0107] The through via 178 is electrically isolated from the plate layer 103 by the substrate insulating layer 121. The through via 178 has a bent portion corresponding to the bent portion of the channel structures CHa and CHb, but is not limited thereto, and may extend at a constant inclination from the top end to the bottom end.

[0108] The first and second horizontal conductive layers 104 and 106 are sequentially stacked on the top surface of the plate layer 103 in the first region R1. The first and second horizontal conductive layers 104 and 106, together with the plate layer 103, form a common source structure CS, which functions as a common source line of the semiconductor device 100c. The first horizontal conductive layer 104 is directly connected to the channel layer 140 under the channel structures CHa and CHb.

[0109] The first and second horizontal conductive layers 104 and 106 include a semiconductor material, such as polycrystalline silicon. In this case, at least the first horizontal conductive layer 104 is a layer doped with impurities of the same conductivity type as the plate layer 103. The second horizontal conductive layer 106 is a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 104.

[0110] The horizontal insulating layer 105 is disposed on the plate layer 103 at the same level as the first horizontal conductive layer 104 in at least a portion of the extension region R2 and the first and second string selection regions R2a and R2b. The horizontal insulating layer 105 includes first and second horizontal insulating layers alternately stacked on the plate layer 103. The horizontal insulating layer 105 is a layer that remains after a portion of it is replaced by the first horizontal conductive layer 104 during the manufacturing process of the semiconductor device 100c.

[0111] The horizontal insulating layer 105 includes silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer and the second horizontal insulating layer include different insulating materials.

[0112] The substrate insulating layer 121 is disposed in the edge region R3 so as to penetrate the plate layer 103, the horizontal insulating layer 105, and the second horizontal conductive layer 106. The substrate insulating layer 121 includes an insulating material, such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0113] 10a to 10k are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment, showing a cross section corresponding to FIG. 2a.

[0114] 10a, first, in the first semiconductor structure S1, sacrificial insulating layers 118 and interlayer insulating layers 120 are alternately stacked on a base substrate SUB, up to a top interlayer insulating layer 121. A vertical sacrificial structure 116 penetrating the mold structure is formed.

[0115] The base substrate SUB is a layer that will be removed in a subsequent process and is a semiconductor substrate such as a silicon (Si) wafer. A first mold stack structure of the mold structure is formed first, and a portion of the vertical sacrificial structure 116 penetrating the first mold stack structure is then formed. A second mold stack structure is then formed, and a portion of the vertical sacrificial structure 116 penetrating the second mold stack structure is then formed. In a similar manner, third and fourth mold stack structures and portions of the vertical sacrificial structure 116 are formed.

[0116] The sacrificial insulating layer 118 is a layer that will be replaced with the gate electrode 130 (see FIG. 2a) through a subsequent process. The sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120 and is formed of a material that can be etched with etching selectivity to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 is made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In an embodiment, the interlayer insulating layers 120 do not all need to have the same thickness, and the top interlayer insulating layer 121 has a greater thickness than the other interlayer insulating layers 120. The thicknesses of the interlayer insulating layers 120 and the sacrificial insulating layer 118 and the number of layers that constitute them may be variously changed from those shown in the drawings.

[0117] The vertical sacrificial structures 116 are formed at positions corresponding to the channel structures CHa, CHb, and support structure DH in Figure 2a. The vertical sacrificial structures 116 are formed, for example, to have the same size as the channel structures CHa, CHb, and support structure DH. The vertical sacrificial structures 116 may include, for example, but are not limited to, carbon (C).

[0118] Referring to FIG. 10b, a mask layer ML having a first opening OP1 is formed on the uppermost interlayer insulating layer 121.

[0119] The mask layer ML includes a hard mask layer and a photoresist layer. The hard mask layer includes, for example, polycrystalline silicon. The first openings OP1 are formed in regions corresponding to the contact plugs MC1a, MC1b, and MC2 in FIG. 2a and have a circular, elliptical, or similar shape. When the mask layer ML is patterned, a portion of the underlying uppermost interlayer insulating layer 121 is removed, but this is not limiting.

[0120] Referring to FIG. 10c, the mold structure is etched using the mask layer ML to form second and third openings OP2 and OP3, and the mask layer ML is then removed.

[0121] The second and third openings OP2 and OP3 are formed by extending from the first opening OP1 in the mask layer ML. The second and third openings OP2 and OP3 are formed by repeatedly performing multiple etching processes that etch the mold structure to a predetermined depth. In FIG. 10c, the sacrificial insulating layer 118 is shown exposed through the bottom surfaces of the second and third openings OP2 and OP3, but this is not limited thereto, and a portion of the interlayer insulating layer 120 above it may remain.

[0122] Referring to FIG. 10d, a preliminary contact insulating layer 160P and a contact sacrificial layer 161 are formed in the second and third openings OP2 and OP3.

[0123] The preliminary contact insulating layer 160P is conformally formed to cover the sidewalls and bottom surfaces of the second and third openings OP2 and OP3. For example, the preliminary contact insulating layer 160P is formed using an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process.

[0124] The contact sacrificial layer 161 is formed on the preliminary contact insulating layer 160P to fill the second and third openings OP2 and OP3. The contact sacrificial layer 161 contains a different material from the preliminary contact insulating layer 160P, for example, carbon (C).

[0125] Referring to FIG. 10e, portions of the vertical sacrificial structures 116 are removed to form channel structures CHa and CHb.

[0126] In the first memory region R1a and the second memory region R1b, a mask layer is formed to expose only regions corresponding to the channel structures CHa and CHb, and the exposed vertical sacrificial structures 116 are removed to form channel holes. At least a portion of the channel dielectric layer 145, the channel layer 140, the channel buried insulating layer 147, and the channel pad 149 are sequentially deposited in the channel holes to form the channel structures CHa and CHb.

[0127] The channel dielectric layer 145 is formed to have a uniform thickness using an ALD or CVD process. In this step, the channel dielectric layer 145 is formed in whole or in part, and portions extending perpendicular to the conductive layer 101 along the channel structures CHa and CHb are formed in this step. The channel layer 140 is formed on the channel dielectric layer 145 within the channel hole. The channel-filled insulating layer 147 is formed to fill the channel hole and is made of an insulating material. The channel pad 149 is made of a conductive material, such as polycrystalline silicon.

[0128] Additionally, portions of the vertical sacrificial structures 116 are removed to form support structures DH.

[0129] A mask layer is formed to expose regions corresponding to the support structures DH in the first and second string selection regions R2a and R2b and the extension region R2, and the exposed vertical sacrificial structures 116 are removed to form dummy holes. A process is performed to expand the dummy holes by partially removing the mold structure around the dummy holes. An insulating material is filled into the expanded dummy holes to form the support structures DH.

[0130] Referring to FIG. 10f, the sacrificial insulating layer 118 is removed to form the gate electrode 130.

[0131] A separation opening is formed to open a region corresponding to the separation region MS in Figures 2 and 4b. The separation opening is formed by forming a plurality of vertical holes in the region where the separation region MS will be formed, and then expanding the vertical holes through a cleaning process or the like to connect them to adjacent vertical holes. When the separation opening is formed by expanding the vertical holes, the side surface of the separation opening may include, but is not limited to, a continuously convex curved surface.

[0132] The sacrificial insulating layer 118 exposed through the separation opening is removed by, for example, wet etching, selectively removing the sacrificial insulating layer 118 with respect to the interlayer insulating layer 120, the channel structures CHa, CHb, the support structure DH, and the preliminary contact insulating layer 160P.

[0133] The gate electrode 130 is formed by depositing a conductive material in the area where the sacrificial insulating layer 118 has been removed. The conductive material may include metal, polycrystalline silicon, or metal silicide. The gate electrode 130 is formed by depositing a conductive material after forming the diffusion barrier layer 131 (see FIG. 5a). In some embodiments, a portion of the channel dielectric layer 145 is formed before forming the gate electrode 130. This results in a stack structure GS including first to fourth stack structures GS1, GS2, GS3, and GS4. After forming the gate electrode 130, an insulating material is deposited in the isolation opening to form an isolation region MS extending in the X direction, as shown in FIG. 2.

[0134] Referring to FIG. 10g, first and second insulating regions SS1a, SS1b, SS2a, and SS2b are formed penetrating the upper gate electrodes 130U1 to 130U3.

[0135] Specifically, as shown in FIGS. 2 and 3, trenches are formed to remove the upper gate electrodes 130U1 to 130U3 and the interlayer insulating layer 120 in regions corresponding to the first insulating regions SS1a, SS1b and the second insulating regions SS2a, SS2b.

[0136] Between two adjacent isolation regions MS, a first trench, which is a horizontal trench corresponding to the first insulating regions SS1a and SS1b, is formed to extend in the X direction within the first memory region R1a and the first string selection region R2a from the upper part of the top interlayer insulating layer 121, penetrate the first to third upper gate electrodes 130U1 to 130U3, and selectively cut the upper part of the fourth stack structure GS4.

[0137] The second trench is formed to extend in the X direction in the second memory region R1b and the second string selection region R2b from the upper part of the uppermost interlayer insulating layer 121, penetrate the first to third upper gate electrodes 130U1 to 130U3, and selectively cut the upper part of the fourth stacked structure GS4.

[0138] The first and second trenches are formed in the first and second memory regions R1a and R1b so as to extend while cutting a portion of the channel structures CHa and CHb.

[0139] In addition, vertical trenches are formed in regions corresponding to the second insulating regions SS2a and SS2b. The vertical trenches extend in the Y direction to separate the extension region R2 from the first and second string selection regions R2a and R2b, and are formed to selectively cut the upper portion of the fourth stacked structure GS4 from the upper portion of the uppermost interlayer insulating layer 121 through the first to third upper gate electrodes 130U1 to 130U3. Therefore, the first and second trenches and the vertical trenches do not extend to the memory gate electrodes 130M corresponding to the word lines.

[0140] An insulating material is deposited in the first and second trenches and the vertical trench to form first and second insulating regions SS1a, SS1b, SS2a, and SS2b.

[0141] Therefore, in addition to the sub-region RS0 arranged within the extension region R2, the upper gate electrodes 130U1 to 130U3 have regions cut by the isolation region MS and the first and second insulating regions SS1a, SS1b, SS2a, and SS2b, which are physically and electrically separated from each other to form a plurality of sub-regions RS1 to RS8.

[0142] 10h, contact plugs MC1a, MC1b, and MC2 are formed. Specifically, after the contact sacrificial layer 161 is selectively removed with respect to the preliminary contact insulating layer 160P, the exposed part of the preliminary contact insulating layer 160P is removed to form the contact insulating layer 160.

[0143] That is, after removing the contact sacrificial layer 161, the exposed preliminary contact insulating layer 160P is partially removed from the bottom surface. When removing the preliminary contact insulating layer 160P, the exposed gate electrode 130 is also partially recessed from the top surface. As a result, the contact insulating layer 160 is formed only on the sidewalls of the second and third openings OP2 and OP3. A conductive material is deposited in the second and third openings OP2 and OP3 to form contact plugs MC1a, MC1b, and MC2. The contact plugs MC1a, MC1b, and MC2 are physically connected to the underlying gate electrode 130.

[0144] Referring to FIG. 10i, upper wiring structures 185 and 180 and first bonding structures 195 and 198 are formed on the stacked structures GS1 to GS4.

[0145] After forming the cell region insulating layer 150, the studs 185 and the cell wiring lines 180 are formed.

[0146] The studs 185 are formed by forming stud holes that penetrate the cell region insulating layer 150 to expose the channel structures CHa, CHb and contact plugs MC1a, MC1b, and MC2, and then filling the stud holes with a conductive material. The cell wiring lines 180 are formed on the studs 185.

[0147] Next, the first bonding via 195 and the first bonding metal layer 198 constituting the first bonding structures 195, 198 are formed by further forming an upper insulating layer 190 on the stud 185, removing a portion of the upper insulating layer 190, and depositing a conductive material thereon. The top surface of the first bonding metal layer 198 is exposed through the upper insulating layer 190. This completes the preparation of the first semiconductor structure S1.

[0148] Referring to FIG. 10j, after the second semiconductor structure S2 is formed, the first semiconductor structure S1 and the second semiconductor structure S2 are bonded together.

[0149] The second semiconductor structure S2 is prepared by forming a circuit element 220, a circuit wiring structure, and a second bonding structure on the substrate 201.

[0150] An isolation layer 210 is formed in a substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 are sequentially formed on the substrate 201. The isolation layer 210 is formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 are formed using ALD or CVD. The circuit gate dielectric layer 222 is formed of silicon oxide, and the circuit gate electrode 225 is formed of at least one of, but not limited to, polysilicon or a metal silicide layer. A spacer layer 224 and source / drain regions 205 are formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. Depending on the embodiment, the spacer layer 224 may be composed of multiple layers. The source / drain regions 205 are formed by an ion implantation process.

[0151] The circuit contact plug 270 of the circuit wiring structure and the second bonding via 295 of the second bonding structure are formed by forming a portion of the peripheral region insulating layer 290, etching away a portion of it, and then filling the portion with a conductive material. The circuit wiring line 280 of the circuit wiring structure and the second bonding metal layer 298 of the second bonding structure are formed, for example, by depositing a conductive material and then patterning it. The second bonding metal layer 298 is formed so that its underside is exposed through the peripheral region insulating layer 290.

[0152] The peripheral region insulating layer 290 is made up of multiple insulating layers, and a portion of the peripheral region insulating layer 290 is formed in each step of forming the circuit wiring structure and the second bonding structure. This step prepares the second semiconductor structure S2.

[0153] The first semiconductor structure S1 and the second semiconductor structure S2 are connected by bonding the first bonding metal 198 and the second bonding metal layer 298 with pressure. At the same time, the top surfaces of the upper insulating layer 190 and the peripheral region insulating layer 290 are bonded with pressure as bonding insulating layers. The second semiconductor structure S2 is inverted on the first semiconductor structure S1 so that the second bonding metal layer 298 faces downward, and then bonding is performed. A separate carrier substrate is attached to one side of the second semiconductor structure S2, for example, one side of the substrate 201, and bonding is performed.

[0154] Referring to FIG. 10k, the base substrate SUB is removed to expose the channel layer 140.

[0155] In the bonding structure of the first semiconductor structure S1 and the second semiconductor structure S2, the base substrate SUB is removed, and a portion of the exposed channel dielectric layer 145 (see FIG. 5a) is removed to expose the channel layer 140.

[0156] Next, referring to Figure 4a, a conductive layer 101 connected to the channel layer 140 is formed to manufacture the semiconductor device 100 of Figure 4a. In some embodiments, the conductive layer 101 is formed as a conformal layer along the upper ends of the channel structures CHa, CHb and the upper end of the support structure DH.

[0157] FIG. 11 is a diagram that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment.

[0158] 11 , a data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 is a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 is a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0159] The semiconductor device 1100 is a nonvolatile memory device, such as the NAND flash memory device described above with reference to FIGS. 1 to 9. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0160] In the second structure 1100S, each memory cell string CSTR is disposed in a first memory region R1a and a second memory region R1b, and each memory cell string CSTR in the first memory region R1a and the second memory region R1b includes lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0161] 1, the memory cell strings CSTR in the first memory region R1a and the memory cell strings CSTR in the second memory region R1b are individually connected to the first and second gate lower lines LL1a, LL2a, LL1b, and LL2b, the common source lines CSLa and CSLb, and the first and second gate upper lines UL1a, UL2a, UL1b, and UL2b, which are separated from each other. Therefore, the individually connected memory cell strings CSTR are selectively connected by an electrical signal from the decoder circuit 1110.

[0162] However, the memory cell strings CSTR in the first memory region R1a and the memory cell strings CSTR in the second memory region R1b have memory cell transistors MCTa and MCTb at the same level connected to the same word line WL, and commonly transmit and receive electrical signals.

[0163] These lines are electrically connected to the decoder circuit 1110 via first connecting wires 1115 that extend from the first structure 1100F to the second structure 1100S. The bit lines BL are electrically connected to the page buffer 1120 via second connecting wires 1125 that extend from the first structure 1100F to the second structure 1100S.

[0164] In the first structure 1100F, a decoder circuit 1110 and a page buffer 1120 perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1100 communicates with the controller 1200 via an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via an input / output connecting wiring 1135 extending to the second structure 1100S within the first structure 1100F.

[0165] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the data storage system 1000 includes multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1100.

[0166] The processor 1210 controls the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that processes communication with the semiconductor device 1100. The NAND controller 1220 transfers control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, and the like, via the NAND interface 1221. The host interface 1230 provides a communication function between the data storage system 1000 and an external host. Upon receiving a control command from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0167] FIG. 12 is a perspective view that schematically illustrates a data storage system including a semiconductor device according to an exemplary embodiment.

[0168] 12, a data storage system 2000 includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0169] The main board 2001 includes a connector 2006 including a plurality of pins for coupling with an external host. The number and arrangement of the pins in the connector 2006 vary depending on the communication interface between the data storage system 2000 and the external host. In an exemplary embodiment, the data storage system 2000 communicates with the external host via any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the data storage system 2000 operates using power supplied from the external host via the connector 2006. The data storage system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0170] The controller 2002 can record data to or read data from the semiconductor package 2003 to improve the operating speed of the data storage system 2000 .

[0171] DRAM 2004 is a buffer memory for mitigating the speed difference between semiconductor package 2003, which is a data storage space, and an external host. DRAM 2004 included in data storage system 2000 also operates as a kind of cache memory, providing space for temporarily storing data during control operations for semiconductor package 2003. When data storage system 2000 includes DRAM 2004, controller 2002 includes a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0172] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b are each a semiconductor package including a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each semiconductor chip 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0173] Package substrate 2100 is a printed circuit board that includes package top pads 2130. Each semiconductor chip 2200 includes input / output pads 2210. Input / output pads 2210 correspond to input / output pads 1101 in Figure 11. Each of semiconductor chips 2200 includes the semiconductor device described above with reference to Figures 1 to 9.

[0174] In the exemplary embodiment, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV) instead of the connecting structure 2400 using a bonding wire method.

[0175] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0176] The present invention is not limited to the above-described embodiments and drawings. Therefore, various substitutions, modifications, and alterations and combinations of embodiments may be made by a person skilled in the art without departing from the technical spirit of the present invention, and these also fall within the scope of the present invention. [Explanation of symbols]

[0177] CHa and CHb channel structures DH Support Structure GS laminated structure MC1a, MC1b, MC2 contact plugs MS separation area SS1a, SS1b, SS2a, SS2b isolation area 100 Semiconductor device 101 Conductive layer 120 Interlayer insulating layer 130 gate electrode 140 Channel Layer 145 Channel Dielectric Layer 150 Cell area insulating layer 160 Contact insulating layer 175 Plug conductive layer 185 studs 190 Upper insulating layer 198 First Bonding Metal 201 Substrate 205 Source / Drain Region 220 Circuit Elements 270 Circuit Contact Plug 280 Circuit Wiring Line 290 Peripheral area insulating layer 295 Second bonding via 298 Second bonding metal layer

Claims

1. a conductive layer; a stacked structure including a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in a first direction perpendicular to an upper surface of the conductive layer in a first region, a second region, and an extension region between the first region and the second region, the lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in order from the conductive layer; a first channel structure and a second channel structure, which penetrate the laminated structure in the first region and the second region and extend along the first direction, respectively; separation regions in the first region, the extension region, and the second region, which extend through the laminated structure along a second direction perpendicular to the first direction and are spaced apart from each other in a third direction perpendicular to the first and second directions; a first insulating region extending in the second direction through the upper gate electrode in each of the first and second regions between the isolation regions; a second insulating region extending in the third direction, dividing the upper gate electrode into a first upper gate electrode and a second upper gate electrode at a boundary between the first region and the extension region and at a boundary between the second region and the extension region; a first string selection contact plug contacting at least one of the first upper gate electrodes from above in the first region and electrically connected to the first upper gate electrodes; second string selection contact plugs contacting at least one of the second upper gate electrodes from above in the second region and electrically connected to the second upper gate electrodes; and a word line contact plug extending from an upper portion of the extension region through the upper gate electrode and electrically connected to the memory gate electrode and the lower gate electrode, respectively.

2. 2. The semiconductor device of claim 1, wherein the number of the first string selection contact plugs in the first region is the same as the number of the second string selection contact plugs in the second region.

3. the first upper gate electrode and the second upper gate electrode are separated into a plurality of sub-areas by the separation region, the first insulating region, and the second insulating region; The semiconductor device of claim 1 , wherein the number of the first string selection contact plugs or the second string selection contact plugs arranged in each of the plurality of sub-areas is the same.

4. 4. The semiconductor device of claim 3, wherein the first string selection contact plug or the second string selection contact plug arranged in any one of the plurality of sub-areas contacts different upper gate electrodes.

5. 2. The semiconductor device of claim 1, wherein the memory gate electrode and the lower gate electrode connected to the word line contact plug electrically connect the first channel structure and the second channel structure in the first region and the second region, respectively.

6. 2. The semiconductor device of claim 1, wherein the word line contact plug is connected to the memory gate electrode and the bottom gate electrode, which are located at different levels from each other, respectively.

7. a conductive layer; a stacked structure including a lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in a first direction perpendicular to an upper surface of the conductive layer in a first region, a second region, and an extension region between the first region and the second region, the lower gate electrode, a memory gate electrode, and an upper gate electrode stacked in order from the conductive layer; a first channel structure and a second channel structure, which penetrate the laminated structure in the first region and the second region and extend along the first direction, respectively; word line contact plugs, which penetrate the upper gate electrode from above in the extension region and are electrically connected to the memory gate electrode and the lower gate electrode, respectively; an insulating region that penetrates from an upper portion to the upper gate electrode at a boundary between the first region and the extension region and a boundary between the second region and the extension region, and separates the upper gate electrode into a first portion in the first region, a second portion in the second region, and a third portion in the extension region; In the first region, the extension region, and the second region, the memory gate electrode and the lower gate electrode each extend continuously and are spaced apart from the insulating region.

8. a first string selection contact plug electrically connected to the upper gate electrode at the first portion; 8. The semiconductor device of claim 7, further comprising: a second string selection contact plug electrically connected to the upper gate electrode in the second portion.

9. a semiconductor memory device including a first semiconductor structure including a circuit element, a second semiconductor structure disposed on one surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor memory device through the input / output pad and controlling the semiconductor memory device; The second semiconductor structure is a conductive layer; a stacked structure including a memory gate electrode and an upper gate electrode stacked in sequence on the conductive layer, the memory gate electrode and the upper gate electrode being spaced apart from each other along a second direction perpendicular to the first direction in a first region, an extension region, and a second region arranged in a first direction parallel to an upper surface of the conductive layer; a first channel structure and a second channel structure, which penetrate the laminated structure in the first region and the second region and extend along the second direction, respectively; common word line contact plugs, which penetrate the upper gate electrodes from above in the extension region and are electrically connected to the memory gate electrodes; an insulating region that penetrates from an upper portion to the upper gate electrode at a boundary between the first region and the extension region and at a boundary between the second region and the extension region, and separates the upper gate electrode; The data storage system according to claim 1, wherein each of the common word line contact plugs is electrically connected to the first channel structure and the second channel structure simultaneously through the memory gate electrodes connected thereto.

10. The second semiconductor structure is a first string selection contact plug electrically connected to the upper gate electrode in the first region; 10. The data storage system of claim 9, further comprising: a second string select contact plug electrically connected to the upper gate electrode in the second region.

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