Semiconductor device

Abstract

To provide a semiconductor device that has small occupied area and has high degree of integration.SOLUTION: A semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is disposed between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. The semiconductor device has a contact plug penetrating the first insulating layer, the conductive layer, and the second insulating layer. The contact plug is configured to have a region in which a diameter decreases in a depth direction from the second insulating layer to the first insulating layer, at an interface serving as a boundary between the second insulating layer and the conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). These are widely used in electronic devices such as semiconductors that can be applied to transistors. Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are attracting attention.

[0005] A transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-ripple transistor using an oxide semiconductor. Low-power CPUs that utilize circuit current characteristics have been disclosed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area. Another object is to provide a semiconductor device with a high degree of integration. Another object of the present invention is to provide a semiconductor device with high speed and low power consumption. One of the objects is to provide a semiconductor device with high productivity. Another object is to provide a semiconductor device with a high yield. Another object is to provide a novel semiconductor device. It is an object of the present invention to provide a method for fabricating a semiconductor device.

[0008] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0009] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using silicon. The present invention relates to a semiconductor device having a transistor formed by the above method.

[0010] One aspect of the present invention is a semiconductor device having a first insulating layer, a conductive layer, a second insulating layer, and a contact plug. The conductive layer is provided between the first insulating layer and the second insulating layer, and the first insulating layer, the conductive layer and the The first insulating layer and the second insulating layer have overlapping regions, and the contact plug is formed between the first insulating layer and the conductive layer. The contact plug is formed so as to penetrate the second insulating layer. In the depth direction from the first insulating layer to the second insulating layer, the diameter decreases at the interface between the second insulating layer and the conductive layer. The semiconductor device is characterized by having a region where the thickness of the semiconductor substrate is small.

[0011] Another aspect of the present invention is a semiconductor device including a first transistor, a second transistor, and a contact plug. a first transistor having an active region in a silicon substrate; The second transistor has an oxide semiconductor in an active layer, and the first transistor and the second transistor The transistors each have an overlapping region, and a third transistor is provided between the first and second transistors. a first insulating layer on the first transistor, a second insulating layer on the second transistor, and One of the source electrode and the drain electrode is connected to the source electrode or the drain electrode of the second transistor. The contact plug is electrically connected to one of the gate electrodes. , a first insulating layer, one of a source electrode or a drain electrode of the second transistor, and The contact plug penetrates the second insulating layer toward the first insulating layer. In the depth direction, the second insulating layer and the source electrode or the drain electrode of the second transistor The semiconductor device is characterized by having a region whose diameter decreases at the boundary with one of the electrodes. .

[0012] The first transistor and the second transistor may form a CMOS circuit. .

[0013] The oxide semiconductor is composed of In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, It is preferred that the metal oxide contains at least one of the following: Ce, Nd or Hf.

[0014] The contact plug penetrates the oxide semiconductor layer of the second transistor. It can also be done as follows.

[0015] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising forming a first insulating layer, forming a conductive film on the first insulating layer, and The conductive film is selectively etched using the mask to form the conductive layer and the conductive A through hole is formed through the layer in the thickness direction, and a second insulating layer is formed to cover the conductive layer and the through hole. and selectively etching the second insulating layer using a second mask, An opening having a diameter larger than the diameter of the through hole is formed to expose the through hole, and the conductive layer is used as a mask. This is a method for manufacturing a semiconductor device, characterized in that the first insulating layer is selectively etched. [Effects of the Invention]

[0016] According to one embodiment of the present invention, a semiconductor device with a small area can be provided. It is possible to provide a semiconductor device with a high degree of integration, or a semiconductor device with a high operating speed. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a semiconductor device with high productivity can be provided. Alternatively, a novel semiconductor device can be provided. Alternatively, a method for manufacturing the semiconductor device can be provided.

[0017] Note that the effects of one embodiment of the present invention are not limited to these. Depending on the circumstances, the effect may be different from those mentioned above. Alternatively, for example, one aspect of the present invention may be In some cases, these effects may not be present. [Brief explanation of the drawings]

[0018] [Figure 1] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a contact plug. [Figure 6] 1A and 1B are top views illustrating a semiconductor device. [Figure 7] 1A and 1B are a cross-sectional view and a circuit diagram illustrating a semiconductor device. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] 1A and 1B are top views illustrating a semiconductor device. [Figure 10] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 13] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 17] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 18] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 25] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 26] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 27] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 28] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 29] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 30] FIG. 1 is a top view illustrating a transistor. [Figure 31] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 32] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 33] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 34] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 35] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 36] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 37] FIG. 2 is a diagram illustrating an example of the configuration of a CPU. [Figure 38] Circuit diagram of a memory element. [Figure 39] 1A to 1C illustrate electronic devices. [Figure 40] FIG. [Figure 41] FIG. [Figure 42] FIG. [Figure 43] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 44] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 45] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 46] Electron diffraction pattern of CAAC-OS. [Figure 47] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 48] Schematic diagram illustrating the film formation model of CAAC-OS and nc-OS. [Figure 49] A diagram explaining InGaZnO4 crystals and pellets. [Figure 50] Schematic diagram illustrating a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE INVENTION

[0019] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0020] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0021] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0022] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0023] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0024] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0025] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0026] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0027] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0028] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third connection path is electrically connected to Y via Z2 by an electrical path of The fourth electrical path does not include the fourth connection path, and the fourth electrical path is a drain of a transistor. (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0029] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0030] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0031] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0032] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to drawings. .

[0033] FIG. 1A is a cross-sectional view illustrating a structure of a semiconductor device of one embodiment of the present invention. The semiconductor device is a transistor 51 having an active region on a silicon substrate 40, and an oxide semiconductor The transistor 51 is a p-channel type, and the transistor 52 has a semiconductor layer as an active layer. By making the resistor 52 an n-channel type, a CMOS circuit can be formed. The transistors 51 and 52 shown in FIG. 1B form an inverter circuit 90. see).

[0034] The transistor 51 includes an active region where a channel is formed, a source region, a drain region, a gate The transistor 52 is basically composed of an insulating film and a gate electrode. The basic structure is an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. As shown in FIG. 1A, each of the transistors 51 and 52 is By overlapping some of the above components, the area occupied by the circuit can be reduced.

[0035] In addition, in the inverter circuit 90, an n-ch type semiconductor device having an active region in the silicon substrate 40 is used. This eliminates the need for the transistor process, and eliminates the need for processes such as forming p-wells and n-type impurity regions. This can eliminate the need for additional steps, significantly reducing the number of processes.

[0036] An insulating layer 81, an insulating layer 82, an insulating layer 83, and an insulating layer 84 are provided on the transistor 51. For convenience of explanation, the insulating layers 81 to 84 are collectively referred to as the first insulating layer. .

[0037] In addition, a transistor 52 is provided on the first insulating layer, and an insulating layer 85, insulating layer 86 and insulating layer 87 are provided. The insulating layers 87 are collectively referred to as the second insulating layer.

[0038] The insulating layers constituting the first insulating layer and the second insulating layer are not limited to the above-mentioned configuration. Some layers may be omitted and other insulating layers may be added.

[0039] One of the source region and the drain region of the transistor 51 is formed between the first insulating layer and the second insulating layer. The contact plug 61 is electrically connected to the insulating layer. 1 is electrically connected to the wiring 71 on the second insulating layer.

[0040] The gate electrode of the transistor 51 is formed by a contact hole passing through the first insulating layer and the second insulating layer. The contact plug 62 is electrically connected to the second insulating layer 61. It is electrically connected to the wiring 73 on top.

[0041] The other of the source region and the drain region of the transistor 51 is covered with a first insulating layer, One of the source electrode or drain electrode of the transistor 52 and a conductor penetrating the second insulating layer. The source region of the transistor 51 is electrically connected to the contact plug 63. The other of the drain regions and one of the source electrode or drain electrode of transistor 52 are Electrical connection is made via contact plug 63 .

[0042] The gate electrode of the transistor 52 is connected to a contact plug 64 that penetrates the second insulating layer. The contact plug 64 is electrically connected to the wiring 73 on the second insulating layer. That is, the gate electrode of transistor 51 and the gate electrode of transistor 52 are electrically connected. The electrode is electrically connected to the contact plug 62, the wiring 73, and the contact plug 64. It will be connected.

[0043] In FIG. 1A, the contact plugs 62 and 64 are located at positions in the depth direction. Since this is different from other contact plugs, it is indicated by different hatching.

[0044] The other of the source electrode and the drain electrode of the transistor 52 penetrates the second insulating layer. The contact plug 65 is electrically connected to the second It is electrically connected to the wiring 72 on the insulating layer.

[0045] In the semiconductor device according to one embodiment of the present invention, a plurality of transistors having overlapping regions are provided. After forming the contact plugs, the contact plugs are formed to electrically connect the plurality of transistors and The contact plug is connected to wiring, etc. By adopting such a configuration, the process is simplified. In addition, wiring can be done freely after forming the transistor. By changing a part of the process, semiconductor devices with different functions can be formed, and the design and This reduces the cost of production and manufacturing.

[0046] Here, the contact plug is formed by first forming a contact hole and then filling the contact hole with a metal. Conductors are embedded using CVD (Chemical Vapor Deposition) methods, etc. In this process, a large aspect ratio is used to reduce the area occupied. It is preferable to form a large contact hole through multiple layers and with a small aspect ratio. Forming a contact hole with a large ratio is very difficult.

[0047] The contact holes for providing the contact plugs 61 and 62 shown in FIG. The difficulty is relatively low because the first insulating layer and the second insulating layer are formed by etching. In the case of oxide insulating layers, nitride insulating layers, etc., different types can be processed under the same etching conditions. This is because in many cases,

[0048] On the other hand, the contact holes for providing the contact plugs 63 are formed by etching the insulating layer. Additionally, the source or drain electrodes (typically metal layers) of transistor 52 are etched. Since the etching conditions are different for insulating layers and metal layers, This requires switching of the etching gas and etchant, which essentially increases the number of processes. In addition, during the etching process, deposits, plasma damage, over-etching, etc. This can sometimes lead to defects.

[0049] Therefore, in one aspect of the present invention, a contact hole for providing the contact plug 63 is In order to form the transistor 52 in advance without increasing the number of steps and causing defects, A method of forming a through hole in one of the source electrode or the drain electrode is used.

[0050] 2(A) to 2(D) show process diagrams for forming the contact plug 63. The transistor 51 and a part of the insulating layer provided on the transistor 51 are not shown. The left side of the figure shows a cross-sectional view, and the right side shows a top view.

[0051] First, two layers of an oxide semiconductor layer having a three-layer structure are formed on the insulating layer 84, and the oxide semiconductor layer and The source electrode layer 32 and the drain electrode layer 33 are formed so as to be in contact with each other (see FIG. 2(A)). Here, a through hole 20 is provided in the source electrode layer 32. The through hole 20 is The drain electrode layer 33 can be formed in the same patterning step.

[0052] As shown in FIG. 3(A), the through hole 20 may also be provided in the drain electrode layer 33. When the through hole 20 provided in the main electrode layer 33 is not used, the through hole may be omitted in a later process. The contact plug or the like may be connected to the drain electrode layer 33 in a region where the source and The names of the source electrode layer 3 and the drain electrode layer 4 are interchangeable depending on the transistor operation. The names of the drain electrode layer 2 and the drain electrode layer 33 can be interchanged.

[0053] Next, the remaining layer of the oxide semiconductor layer, the gate insulating film and the gate electrode layer are formed. The basic structure of transistor 52 is completed. Then, a second insulating layer is formed on transistor 52. At this time, a part of the second insulating layer is formed in the through hole 20. Further, a resist mask 35 for forming a plurality of contact holes is formed on the second insulating layer. (See Figure 2(B)).

[0054] Then, by performing an etching process, contact holes 21 to 2(C) , the source electrode layer 32 is provided with the through hole 20. Therefore, the etching conditions for the insulating layer can be changed to the etching conditions for the metal layer. The etching process can be easily performed.

[0055] In the etching process, the contact hole 23 and the through hole 20 must not be misaligned. To prevent this, the diameter of the contact hole 23 in the second insulating layer region is set to be larger than the diameter of the through hole 20. Therefore, the contact hole 23 is preferably larger than the second insulating layer. In the depth direction from the first insulating layer to the source electrode layer 32 of the transistor 52 and the second insulating layer The diameter of the insulating layer becomes smaller at the boundary between the insulating layer and the insulating layer.

[0056] FIG. 2(B) shows an example of a resist mask in which all contact holes are formed at the same time. However, a method of sequentially forming contact holes with different depths may also be used. As shown in FIG. 3(B), a relatively deep contact hole is first formed, and then the contact hole is A method of forming a relatively shallow contact hole by temporarily filling the contact hole with organic resin. Conversely, a relatively shallow contact hole may be formed first, and then a relatively deep contact hole may be formed. A method of forming contact holes may also be used.

[0057] Then, a conductive layer is filled into the contact holes to form contact plugs 61 to A contact plug 65 is formed (see FIG. 2(D)). , according to the shape of the contact hole 23, the source electrode layer 32 of the transistor 52 and the The diameter changes at the boundary between the insulating layer 2.

[0058] 40(A) to 40(F) show the source electrode layer 3 of the transistor 52 shown in FIG. 40(A) is an enlarged view of the vicinity of the interface between the second insulating layer and the second insulating layer. However, one embodiment of the present invention is not limited to this. The shape of 20 and its surroundings can be varied in many ways.

[0059] For example, as shown in FIG. 40(B), the corner of the side wall of the contact plug 63 formed in the through hole 20 The angle of the sidewall of the contact plug 63 may be different from the angle of the other portions of the sidewall. As shown in FIG. 40(C), the diameter of the contact plug 63 changes inside the source electrode layer 32. 40(D), the contact plug may be formed inside the source electrode layer 32. The angle of the side wall of the lug 63 may be changed. The diameter of the contact plug 63 changes at the interface between the electrode layer 32 and the first insulating layer. Also, as shown in FIG. 40(F), contact plug 6 may be formed inside the first insulating layer. The diameter of 3 may be varied.

[0060] Since the sidewall of the contact plug has a slight taper angle, It can be said that the diameter changes at any point in the depth direction. In this embodiment, regardless of these diameter changes, the contact plug does not have a significant diameter change. It is characterized by having a certain region.

[0061] Note that the transistor 52 used in the semiconductor device of one embodiment of the present invention has a structure in which a semiconductor layer is formed on an oxide semiconductor layer. A source electrode and a drain electrode are formed on the It may be configured so as not to be in contact with the insulating layer 84. In such a configuration, The oxygen that is released is not taken away by the metal layer that constitutes the source electrode and the drain electrode. Therefore, the oxygen can be efficiently supplied to the oxide semiconductor layer, and the transistor 52 The electrical characteristics and reliability can be improved.

[0062] In the case of the above structure, the semiconductor device according to one embodiment of the present invention is as shown in FIG. However, a through hole may be provided in either the source electrode or the drain electrode of the transistor 52. This makes it easier to form contact holes for providing the contact plugs 63 .

[0063] In this case, when forming a contact hole for providing the contact plug 63, The oxide semiconductor layer is also etched. The oxide semiconductor layer is etched under the same etching conditions as the insulating layer. Since the thicknesses of the oxide semiconductor layers may be different, a through hole may also be provided in the oxide semiconductor layer.

[0064] For forming a contact plug 63 in a configuration in which a through hole is also provided in the oxide semiconductor layer 5A to 5D are process diagrams. are the same as the steps in FIGS. 2(A) to 2(D), and the explanation will be omitted.

[0065] 41(A) to 41(F) show the source electrode layer 32 and the front electrode layer of the transistor 52 shown in FIG. 41(A) is an enlarged view of the vicinity of the interface with the second insulating layer. However, one aspect of the present invention is not limited to this. The shape of the periphery can be varied in many ways.

[0066] For example, as shown in FIG. 41(B), the contact is formed at the interface between the source electrode layer 32 and the oxide semiconductor layer. The diameter of the plug 63 may be changed. The diameter of the contact plug 63 may vary within the semiconductor layer. 1(D), a contact plug 63 formed in the through hole 20 in the oxide semiconductor layer The angle of the sidewall of the contact plug 63 may be different from the angle of the sidewall of the other portion. In addition, as shown in FIG. 41(E), the contact is formed at the interface between the oxide semiconductor layer and the first insulating layer. The diameter of the stop plug 63 may be changed. The diameter of the contact plug 63 may be changed inside the edge layer. The contact plug 63 may have a shape that is a combination of the shapes shown.

[0067] 6A and 6B are top views of a semiconductor device according to one embodiment of the present invention. 6A is a top view of the semiconductor device shown in FIG. 6, and FIG. 6B is a top view of the semiconductor device shown in FIG. 1(A) and 4 correspond to the cross section P1-P2 shown in FIGS. 6(A) and 6(B). In the figure, OS indicates an active layer made of oxide semiconductor, and Si indicates a silicon active layer. Indicates the sexual area.

[0068] Another embodiment of the present invention is shown in FIG. 7A. The semiconductor device shown in FIG. A transistor 53 having an active region on the silicon substrate 40 and a transistor having an oxide semiconductor layer as an active layer are The transistors 53, 54 and the capacitor 55 shown in FIG. In the connection of the capacitor 55, a circuit 91 shown in the circuit diagram of FIG. The semiconductor device shown in FIG. 7A has a capacitance element 55 and a connection form of each element. Except for this, the semiconductor device can have the same structure as that of the semiconductor device shown in FIG.

[0069] Here, the gate electrode layer of the transistor 53 and the source electrode layer of the transistor 54 are A contact is provided to electrically connect one of the drain electrode layers to one of the electrode layers of the capacitor element 55. The contact plug 66 is connected to the source electrode layer of the transistor 54. Alternatively, a through hole provided in one of the drain electrode layers (common to one of the electrode layers of the capacitor element 55) Therefore, similar to the contact plug 63 shown in FIG. In the depth direction from the insulating layer toward the first insulating layer, the source electrode layer of the transistor 54 Alternatively, the diameter of the drain electrode layer decreases at the interface between one of the drain electrode layers and the second insulating layer.

[0070] In FIG. 7A, the contact plugs 66 and 67 are located at positions in the depth direction. Since this is different from other contact plugs, it is indicated by different hatching.

[0071] When the structure of the transistor 52 shown in FIG. 4 is applied to the transistor 54, the structure shown in FIG. FIG. 9A is an example of a top view of the semiconductor device shown in FIG. 9B is an example of a top view of the semiconductor device shown in FIG. 8 corresponds to the cross section taken along line Q1-Q2 shown in FIGS. 9(A) and 9(B).

[0072] The circuit 91 shown in FIG. 7B can retain memory contents even when power is not supplied, and This is an example of a semiconductor device (memory circuit) that has no limit on the number of times it can be written.

[0073] The transistor 54 including an oxide semiconductor has electrical characteristics of extremely low off-state current. For example, when the voltage between the source and drain is 0.1V, When the voltage is set to about 5V or 10V, the off-state current normalized by the channel width of the transistor is On the other hand, the current density can be reduced from several yA / μm to several zA / μm. Transistors made of other materials, such as crystalline silicon, are easier to operate at high speeds. Therefore, by combining the two, a memory with high data retention capacity and high speed operation can be achieved. The device can be configured.

[0074] In the semiconductor device shown in FIG. 7B, the potential of the gate electrode of the transistor 53 can be maintained. By utilizing this feature, it is possible to write, store, and read information as follows.

[0075] Writing and holding of data will be described. First, the potential of the wiring 77 is applied to the transistor 54. is set to a potential at which the transistor 54 is turned on, thereby turning the transistor 54 on.

[0076] By the above operation, the potential of the wiring 76 is applied to the gate electrode of the transistor 53 and the capacitor 5 5. That is, a predetermined charge is given to the node FN (write). Here, charges that give two different potential levels (hereinafter referred to as low-level charges and high-level charges) are Either the charge or the charge is given.

[0077] After that, the potential of the wiring 77 is set to a potential that turns off the transistor 54. By turning off 54, the charge given to the node FN is held (held). Since the off-state current of the transistor 54 is extremely small, the charge at the node FN remains constant for a long time. Retained.

[0078] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring 75, When an appropriate potential (read potential) is applied to the wiring 78, the amount of charge held in the node FN increases. In response, the wiring 79 assumes a different potential.

[0079] Generally, if the transistor 53 is an n-channel type, the gate electrode ( The apparent threshold voltage V when a high level charge is applied to the th_ H In this case, a low-level charge is applied to the gate electrode (node ​​FN) of the transistor 53. The apparent threshold voltage V th_L It will be lower.

[0080] Here, the apparent threshold voltage is the voltage required to turn on the transistor 53. Therefore, the potential of the wiring 78 is Vth_H and V th _L By setting the potential V0 between It can distinguish a given charge.

[0081] For example, when a high level charge is applied in a write operation, the When the potential is V0 (>V th_H ), transistor 53 is in the "ON state." When a level charge is applied, the potential of the wiring 78 becomes V0( <V th_L ) Therefore, the potential of the wiring 79 can be determined. By doing so, the stored information can be read out.

[0082] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, in a memory cell from which information is not read, The transistor 53 is in the "off state" regardless of the potential applied to the gate electrode. potential, that is, V th_H A smaller potential may be applied to the wiring 78. The transistor 53 is in the "on" state regardless of the potential applied to the electrode. Electric potential, i.e., V th_L A larger potential may be applied to the wiring 78 .

[0083] In the semiconductor device shown in FIG. 7B, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, it is possible to retain memory contents for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation This makes it possible to reduce the frequency of this extremely low, thereby significantly reducing power consumption. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if the memory is changed, it is possible to retain the stored contents for a long period of time. The device may also perform an operation of supplying power thereto.

[0084] Furthermore, in the above-described driving method, a high voltage is required to write information to the node FN. There is no problem of deterioration of the transistor 53. For example, Electrons are injected into the floating gate by applying a voltage, and electrons are released from the floating gate. Since there is no operation to pull out the transistor, problems such as deterioration of the gate insulating film of the transistor 53 do not occur. In other words, the semiconductor device according to the disclosed invention does not have the problem of conventional nonvolatile memories. There is no limit to the number of times it can be rewritten, which has been a problem, and reliability is dramatically improved. Information is written depending on the on / off state of the transistor, allowing for high-speed operation. can also be easily realized.

[0085] Components of the semiconductor device according to one embodiment of the present invention will be described below. Although the semiconductor device shown in FIG. 1A will be described, other semiconductor devices shown in this embodiment mode may also be used. The same is true for the body apparatus.

[0086] The silicon substrate 40 is not limited to a bulk silicon substrate, but may be an SOI substrate. Instead of the silicon substrate 40, germanium, silicon germanium, silicon carbide, gallium Materials include aluminum gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and organic semiconductors. A substrate that serves as a material can also be used.

[0087] The transistor 51 is not limited to a planar type transistor, but may be any of various types of transistors. For example, FIN type, TRI-GATE type, The transistor may be a gate type transistor or the like.

[0088] The insulating layer 81 can function as a protective film, and is typically a silicon nitride film or an aluminum oxide film. The insulating layer 82 and the insulating layer 87 function as a planarizing film. Typically, a silicon oxide film, a silicon oxynitride film, etc. can be used. can be done.

[0089] The insulating layer 83 can function as a hydrogen blocking film. Hydrogen in the insulating layer provided near the region terminates the dangling bonds of silicon, This has the effect of improving the reliability of the transistor 51. The hydrogen in the insulating layer provided near the oxide semiconductor layer, which is the active layer, is absorbed into the oxide semiconductor. This is one of the factors that generate carriers, which reduces the reliability of the transistor 52. Therefore, the upper layer of a transistor using a silicon-based semiconductor material is often made of an oxide. When transistors using nitride semiconductors are stacked, hydrogen diffusion is prevented between them. It is preferable to provide an insulating layer 83 having a function of trapping hydrogen in the lower layer. The confinement improves the reliability of the transistor 51 and also prevents hydrogen from flowing from the lower layer to the upper layer. The suppression of diffusion of the ions also improves the reliability of the transistor 52. can.

[0090] The insulating layer 83 may be made of, for example, silicon nitride, aluminum oxide, or aluminum oxynitride. , gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, gallium oxide Use hafnium, hafnium oxide nitride, yttria stabilized zirconia (YSZ), etc. The insulating layer 85 can also be made of these materials.

[0091] The insulating layer 84 serves as an oxygen source for the oxide semiconductor layer of the transistor 52 . Therefore, the insulating layer 84 is an insulating layer containing oxygen, and has a composition with more oxygen than the stoichiometric composition. In addition, the insulating layer 84 is preferably a gate electrode on the back gate side of the transistor 52. Since it can also function as a gate insulating film, defects can be eliminated at the interface with the oxide semiconductor layer. It is preferable that the film is one that is less likely to generate

[0092] The insulating layer 84 can typically be a silicon oxide film or a silicon oxynitride film. In addition, the insulating layer may be a laminate of a silicon nitride film or a silicon nitride oxide film and the insulating layer. The insulating layer 86 can also be made of these materials.

[0093] The contact plugs 61 to 65 are typically made of a metal material. Specifically, tungsten can be used. Titanium nitride may be provided on the wall surface and tungsten may be provided inside. The rim layer and the top surface of the contact plug are planarized by CMP (Chemical Mechanical Polishing). The (ical Polishing) method can be used.

[0094] In this embodiment, one embodiment of the present invention will be described using a configuration of an inverter circuit and a memory circuit as an example. It is also possible to apply this to other circuits. This is not limited to the above, but can also be applied to cases where three or more elements such as transistors are electrically connected. It is possible.

[0095] In this embodiment, a transistor having a silicon active region and a transistor having an oxide semiconductor active region are used. Although an example in which a transistor having a silicon layer is stacked on a conductive layer has been shown, the present invention is not limited to this. The present invention can also be applied to a case where a plurality of transistors are stacked. The present invention can also be applied to the case where a plurality of transistors are stacked.

[0096] Further, one embodiment of the present invention can also be applied to electrical connection of overlapping wirings.

[0097] FIG. 42 shows an example of an etching apparatus for etching a multilayer film having a plurality of film types. The etching apparatus shown in FIG. C, and the purpose is to temporarily hold the substrate while it is being moved to each etching chamber. A transfer chamber 820 for transferring etching gas to each etching chamber and a gas supply system 830 for supplying the gases. It has a supply system, a pump system, and a gas abatement system.

[0098] To form fine openings in a multilayer film containing multiple film types, a parallel plate etching device is required. In particular, it is preferable to use an etching device having a high density plasma source. Alternatively, it is preferable to use an appropriate etching gas for etching each layer. It is desirable to have a gas supply system that allows for a choice of gases, especially one that combines multiple gases. It is preferable to have a gas supply system that can

[0099] For example, the formation of a fine opening in a multilayer film having multiple film types can be achieved by using one etching chamber. This method can be performed by using an etching gas that is optimal for each layer. As shown in Figure 42, if the etching equipment has three etching chambers, multiple This allows multiple substrates to be processed simultaneously, improving production efficiency. Cut.

[0100] When etching a multilayer film having multiple film types in one etching chamber, In the etching chamber, the gas is switched to the optimum gas depending on the type of film to be etched. Various etching products can deposit on the walls of the etching chamber. The particles may peel off from the coating chamber wall and become particles. If it adheres to the surface, it may cause poor etching.

[0101] As a method for preventing the generation of such particles, it is necessary to separate the etching chamber for each film type. The etching method is as follows: Here, an example of etching a multilayer film having a plurality of film types will be shown. The object of the etching is a first insulating film, a second insulating film, a third insulating film, an oxide semiconductor film, and A conductive film, a fourth insulating film, an organic resin film, and a photoresist are formed on the substrate in this order. The photoresist is a laminated material that is formed into a predetermined shape through exposure and development. It has the following shape.

[0102] First, the substrate is placed in the etching chamber 810A, and the organic resin film and the fourth insulating film are Etching is then performed. The substrate is then transferred from the etching chamber 810A to the transfer chamber 810B. The substrate is then moved to the etching chamber 810B via the chamber 820, and the conductive film is etched. The substrate is then transferred from the etching chamber 810B to the transfer chamber 8 20 and moved to the etching chamber 810A, and the oxide semiconductor film, the third insulating film The film and the second insulating film are etched. The substrate is then removed from the etching chamber 810A. Then, the substrate is transferred to the etching chamber 810C via the transfer chamber 820. Then, by ashing, the products generated by the previous etching are removed. The etching chamber 810C is transferred to the transfer chamber 820. The substrate is then moved to an etching chamber 810A, where the first insulating film is etched. From the etching chamber 810A, the etching is carried out via the transfer chamber 820. The photoresist and organic The resin film is removed.

[0103] Even if the structure has a multi-layer film, the above procedure can be repeated to obtain a multi-layer film. This allows for the formation of minute openings.

[0104] In the above example, a plurality of etching processes are used to etch a multilayer film having a plurality of film types. A vacuum chamber is used, where the substrate is transferred under vacuum and exposed to the atmosphere. This allows for highly reproducible etching. In this case, the etching gas does not need to be switched for each film type, and the processing time is therefore shortened. This makes it possible to increase production efficiency.

[0105] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0106] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be made with reference to the drawings. For clarity, some elements may be enlarged, reduced, or omitted.

[0107] 10A and 10B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 10(A) is a top view, and a cross section taken along the dashed line B1-B2 shown in FIG. 10(A). corresponds to FIG. 10(B). Also, the cross section in the direction of the dashed line B3-B4 shown in FIG. 10(A) is 16(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is sometimes called the channel width direction.

[0108] The transistor 101 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 11 in contact with the conductive layer 150. 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, an insulating layer 190 (flattening film) that contacts the insulating layer 180 may be formed as needed. It may have.

[0109] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0110] 10B, a region 231 is a source region, a region 232 is a drain region, and a region 2 The region 33 can function as a channel forming region. The conductive layers 140 and 150 are in contact with each other, for example, the conductive layers 140 and 150. If a conductive material that easily bonds with oxygen is used as 150, the resistance of the region 231 and the region 232 can be reduced. It can be countered.

[0111] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The resistance becomes n-type.

[0112] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" are used interchangeably in this specification. The term "electrode layer" can also be used interchangeably with "wiring." can.

[0113] In addition, the conductive layer 170 is shown as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0114] Although the conductive layer 140 and the conductive layer 150 are shown as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may also be applied to other transistors described in this embodiment. can.

[0115] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 11A is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 11(B). The cross section in the direction of -C4 corresponds to FIG. 16(B). The direction of the dashed dotted line C3-C4 may be referred to as the channel length direction, and the direction of the dashed dotted line C3-C4 may be referred to as the channel width direction.

[0116] The transistor 102 has an insulating layer 160 acting as a gate insulating film and a gate electrode layer. Similar to transistor 101 except that the edges are not aligned with the active conductive layer 170. The structure of the transistor 102 is such that the conductive layer 140 and the conductive layer 150 are sandwiched between the insulating layer 16 0, the resistance between the conductive layer 140 and the conductive layer 150 and the conductive layer 170 is It has high resistance and low gate leakage current.

[0117] The transistor 101 and the transistor 102 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The top gate structure has a region where the gate electrode 150 overlaps the gate electrode 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. On the other hand, since no offset region is formed in the oxide semiconductor layer 130, a transistor with a high on-current is formed. It is easy to form a transistor.

[0118] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 12A is a top view of the transistor 103, and the dashed line D in FIG. The cross section in the 1-D2 direction corresponds to FIG. 12(B). The cross section in the -D4 direction corresponds to FIG. 16(A). The direction of the dashed dotted line D3-D4 may be referred to as the channel length direction, and the direction of the dashed dotted line D3-D4 may be referred to as the channel width direction.

[0119] The transistor 103 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. The edge layer 175, the insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and the insulating layer 180 a conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. If necessary, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer 190 (planarization film) in contact with 150 may also be provided.

[0120] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0121] 12B, a region 231 is a source region, a region 232 is a drain region, and a region 2 The region 33 can function as a channel forming region. The region 231 and the region 232 are insulating layers. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0122] Specifically, the insulating layer 175 is formed in the regions 231 and 232 by the steps up to the formation of the insulating layer 175. The oxygen vacancies caused by the ion implantation and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232 interact with each other. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0123] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 13A is a top view of the transistor 104, and the dashed line E in FIG. The cross section in the 1-E2 direction corresponds to FIG. 13(B). The cross section in the -E4 direction corresponds to FIG. 16(A). The direction of the dashed dotted line E3-E4 may be referred to as the channel length direction, and the direction of the dashed dotted line E3-E4 may be referred to as the channel width direction.

[0124] The transistor 104 is configured such that the conductive layer 140 and the conductive layer 150 are disposed at the edge of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103 except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0125] The regions 331 and 334 shown in FIG. 13B are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. Regions 331 and 332 correspond to regions 231 and 232 in transistor 101. The resistance can be reduced in the same way as in the case of the transistor 2. The resistance can be reduced in the same manner as in the region 231 and the region 232 in the capacitor 103. The width of the region 334 and the region 335 in the channel length direction is preferably 100 nm or less. When the gate thickness is 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. It is also possible to adopt a configuration in which the above-described resistance reduction is not performed.

[0126] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. Therefore, it is suitable for high-speed operation.

[0127] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 14A is a top view of the transistor 105, and the dashed line F in FIG. The cross section in the 1-F2 direction corresponds to Fig. 14(B). The cross section in the direction of -F4 corresponds to FIG. 16(A). The direction of the dashed dotted line F3-F4 may be referred to as the channel length direction, and the direction of the dashed dotted line F3-F4 may be referred to as the channel width direction.

[0128] The transistor 105 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151. the conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175; and an insulating layer 180 that is electrically conductive through openings in the insulating layers 175 and 180. Conductive layer 142 and conductive layer 151 are electrically connected to layer 141 and conductive layer 152, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer 190 (planarization film) may be provided.

[0129] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0130] The transistor 105 has a conductive layer 141 and a conductive layer 151, and an insulating layer 17. 5 and the insulating layer 180 through openings formed in the conductive layer 141 and the conductive layer 151 and the 1. The transistor has a conductive layer 142 and a conductive layer 152 electrically connecting the two. The conductive layer 140 (conductive layer 141 and conductive layer 142) has the same structure as the capacitor 101. The conductive layer 150 (conductive layer 151 and conductive layer 152) can act as a base electrode layer. 2) can act as a drain electrode layer.

[0131] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 15A is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 15(B). The cross section in the -G4 direction corresponds to FIG. 16(A). The direction of the dashed dotted line G3-G4 may be referred to as the channel length direction, and the direction of the dashed dotted line G3-G4 may be referred to as the channel width direction.

[0132] The transistor 106 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the insulating layer 160 in contact with the oxide semiconductor layer 130; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. , the conductive layer 141 and the conductive layer 142 are electrically connected to each other through openings provided in the insulating layer 175 and the insulating layer 180 . The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, an insulating layer 180, an insulating layer 190 (flat layer) in contact with the conductive layer 142 and the conductive layer 152, The substrate may have a protective film (a protective film) or the like.

[0133] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0134] Transistor 106 has the same structure as transistor 106 except that it has conductive layer 141 and conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has the same structure as the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 152) can act as a base electrode layer. 2) can act as a drain electrode layer.

[0135] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 50 is not in contact with the insulating layer 120, the oxygen in the insulating layer 120 is and the conductive layer 150 is less likely to take away the oxide from the insulating layer 120 into the oxide semiconductor layer 130. This makes it easier to supply the raw material.

[0136] Note that the regions 231 and 232 in the transistor 103, the transistor 104, In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed and the Impurities that increase the dielectric constant may be added. Examples of the elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, and nitrogen. , helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, One or more selected from the group consisting of titanium, zinc, and carbon can be used. The methods of adding impurities include plasma treatment, ion implantation, ion doping, and plasma Zumaion ion implantation and the like can be used.

[0137] When the above-described elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes the oxide The conductivity of the semiconductor layer can be increased.

[0138] When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of an impurity element, Hydrogen enters the oxygen vacancy site and a donor level is formed near the conduction band. Therefore, the oxide conductor has light-transmitting properties. An oxide semiconductor that has been made into a conductor is called an oxide conductor.

[0139] Oxide conductors are degenerate semiconductors, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a The contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer functioning as the drain electrode layer can be reduced.

[0140] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 18(A) and (B) are cross-sectional views in the channel length direction shown in (F) and (F), respectively. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows for an increase in on-current and control of the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive layer 170. It may be shorter than the width.

[0141] To increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and the double In addition, to control the threshold voltage, A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 18(B), 73 can be electrically connected via a contact hole.

[0142] In addition, in the transistors 101 to 106 in FIGS. Although the oxide semiconductor layer 130 is illustrated as a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 may be formed as shown in FIGS. Alternatively, it can be replaced with the oxide semiconductor layer 130 shown in FIG.

[0143] 19A, 19B, and 19C are top views of the oxide semiconductor layer 130 having a two-layer structure, and 19(A) is a top view, and is a cross-sectional view taken along the dashed line A1-A2 shown in FIG. 19(A) corresponds to the cross section in the direction of the dashed line A3-A4 shown in FIG. The cross section corresponds to FIG. 19(C).

[0144] 20A, 20B, and 20C are top views of the oxide semiconductor layer 130 having a three-layer structure. 20(A) is a top view, and the dashed line A1- The cross section in the A2 direction corresponds to Fig. 20(B). The cross sections in four directions correspond to FIG. 20(C).

[0145] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers or the like having different compositions can be used.

[0146] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 21A is a top view of the transistor 107, and the dashed line H The cross section in the 1-H2 direction corresponds to FIG. 21(B). The cross section in the -H4 direction corresponds to Fig. 27(A). The longitudinal direction, the direction of the dashed dotted line H3-H4, may be referred to as the channel width direction.

[0147] The transistor 107 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 140 and the conductive layer 150 that are connected, and the stacked layer, the conductive layer 140 and the conductive layer 15 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and a and an insulating layer 180 in contact with the insulating layer 180. (planarization film) or the like.

[0148] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 140 and the conductive layer 150 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has the same configuration as the transistor 101 .

[0149] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 22A is a top view of the transistor 108. The cross section in the direction of 1-I2 corresponds to FIG. 22(B). The cross section in the direction of -I4 corresponds to FIG. 27(B). The direction of the dashed dotted line I1-I2 corresponds to the channel The longitudinal direction, the direction of the dashed dotted line I3-I4, may be referred to as the channel width direction.

[0150] The transistor 108 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 140 and the conductive layer 150 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has a similar configuration to the transistor 102 .

[0151] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 23A is a top view of the transistor 109, and the dashed line J in FIG. The cross section in the 1-J2 direction corresponds to FIG. 23(B). The cross section in the -J4 direction corresponds to Fig. 27(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, may be referred to as the channel width direction.

[0152] The transistor 109 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. the oxide semiconductor layer 130c, the insulating layer 160 in contact with the oxide semiconductor layer 130c, and the insulating layer 16 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covering the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and and a conductive layer 14 electrically connected to the stack through an opening provided in the insulating layer 180. 0 and conductive layer 150. In addition, an insulating layer 180, a conductive layer 140 and An insulating layer 190 (planarizing film) in contact with the conductive layer 150 may be provided.

[0153] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 103 has the same configuration as the transistor 103 except that it is a compound semiconductor layer 130c.

[0154] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 24A is a top view of the transistor 110. The cross section in the direction of 1-K2 corresponds to FIG. 24(B). The cross section in the direction of -K4 corresponds to Fig. 27(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, may be referred to as the channel width direction.

[0155] The transistor 110 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 104 has the same configuration as the transistor 104 except that it is a compound semiconductor layer 130c.

[0156] The transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 25A is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 25(B). The cross section in the -L4 direction corresponds to Fig. 27(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, may be referred to as the channel width direction.

[0157] The transistor 111 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 141 and the conductive layer 151 that are connected, and the stacked layer, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the stacked conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the compound semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 is in contact with the insulating layer 175, and openings are formed in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 is also provided. If necessary, an insulating layer 180, a conductive layer 142, and a conductive layer 1 It may also have an insulating layer 190 (planarization film) in contact with 52.

[0158] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 141 and the conductive layer 151 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has the same configuration as the transistor 105 .

[0159] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 26A is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 26(B). The cross section in the direction of -M4 corresponds to Fig. 27(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, may be referred to as the channel width direction.

[0160] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c, oxide semiconductor layer 130d, oxide semiconductor layer 130e, oxide semiconductor layer 130f ...). The transistor 106 and the transistor 107 are the same except that the first and second layers are the organic semiconductor layer 130b and the oxide semiconductor layer 130c. They have a similar configuration.

[0161] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 29(A) and (B) are cross-sectional views of the channel length direction shown in FIG. 29(F) and FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows for an increase in on-current and control of the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive layer 170. It may be shorter than the width.

[0162] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is the oxide semiconductor layer 1 shown in the top view of FIG. 30, conductive layer 140, and conductive layer 150 are shown). (W OS) of the conductive layer 140 and the conductive layer 150. SD ) is formed long It may be formed short. OS ≧W SD (W SD is W OS (below) As a result, the gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electric field of the transistor The characteristics can be improved.

[0163] In the transistors of one embodiment of the present invention (transistors 101 to 112), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction through the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel This is called the (s-channel) structure.

[0164] In addition, a transistor having the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, etc. and oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c. In a transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By flowing current through the conductor layer 130b, the device is less susceptible to the influence of interface scattering and a high on-current can be obtained. It should be noted that increasing the thickness of the oxide semiconductor layer 130b can improve the on-state current. For example, when the thickness of the oxide semiconductor layer 130b is set to 100 nm to 200 nm, Good too.

[0165] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0166] Note that in this specification, the channel length refers to, for example, the length of a semiconductor device in a top view of a transistor. The conductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate The source (source region or This refers to the distance between the source electrode and the drain electrode. In one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions where the channel is formed. The value may be a maximum, minimum or average value.

[0167] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on state). The region where the gate electrode overlaps with the current-carrying part of the gate, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0168] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in a transistor with a fine, three-dimensional structure, The ratio of the channel region formed on the side of the semiconductor to the channel region formed In this case, the apparent channel width shown in the top view may be larger. The effective channel width where the channel is actually formed is larger than the actual channel width.

[0169] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0170] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The channel width is defined as the "surrounded channel width (SCW)". In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when simply referring to channel width, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. A value can be determined.

[0171] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0172] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0173] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0174] The substrate 115 is a silicon substrate 40, an insulating layer 81, an insulating layer 82, and an insulating film 115 shown in FIG. 1(A). This corresponds to a configuration including an insulating layer 83. Note that only p-channel transistors are formed on the silicon substrate. To form n - Preferably, a silicon substrate having a conductivity type of , n - The substrate may be an SOI substrate having a silicon layer of type or i-type. The surface of the silicon substrate on which the transistor is formed preferably has a (110) plane. A p-channel transistor is formed on a silicon substrate having a (110) surface. This can increase the mobility.

[0175] The insulating layer 120 corresponds to the insulating layer 84 in FIG. The oxygen supplying layer 130 serves to prevent impurities from diffusing from the oxide semiconductor layer 130. Therefore, the insulating layer 120 is an insulating film containing oxygen. It is preferable that the insulating film contains more oxygen than the stoichiometric composition. , Thermal Desorption Spectroscopy (TDS) The amount of oxygen released, converted to oxygen atoms, was 1.0 x 10 19 atom s / cm 3 The film surface temperature during the TDS analysis is The temperature range is preferably 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. As mentioned above, if the substrate 115 is a substrate on which other devices are formed, the insulating layer 120 may be It also functions as an interlayer insulating film. In that case, CMP (chemical mechanical polishing) is used to make the surface flat. Flattening treatment should be performed using methods such as mechanical polishing. is preferred.

[0176] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film may be a laminate of the above materials. It is also possible.

[0177] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are formed from the insulating layer 120 side. The details will be mainly explained for the case of a three-layer structure stacked in order.

[0178] When the oxide semiconductor layer 130 is a single layer, the layer corresponding to the oxide semiconductor layer 130b is Just use

[0179] In addition, when the oxide semiconductor layer 130 has two layers, the layer corresponding to the oxide semiconductor layer 130a and the and a layer corresponding to the oxide semiconductor layer 130b are stacked in this order from the insulating layer 120 side. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are interchanged. It is also possible to do so.

[0180] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is stacked on the oxide semiconductor layer 130 of the three-layer structure, or the three-layer structure Another oxide semiconductor layer may be inserted at any of the interfaces.

[0181] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band) than the oxide layer 130c. The electron affinity is determined by the energy difference between the vacuum level and the top of the valence band (ion The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the

[0182] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be formed of a thin oxide semiconductor.

[0183] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0184] The oxide semiconductor layer 130a contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface states may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a As a result, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0185] The oxide semiconductor layer 130c contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0186] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may contain, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf as an element having a higher conductivity than the oxide semiconductor layer 130b. Specifically, the atomic ratio is preferably 1.5 times or more. The amount is preferably two times or more, and more preferably three times or more. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from occurring in the oxide semiconductor layer. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0187] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least indium (In) or nickel. It is preferable that lead (Zn) is contained. Alternatively, it is preferable that both In and Zn are contained. In addition, in order to reduce variations in the electrical characteristics of transistors using the oxide semiconductor, Both preferably include a stabilizer.

[0188] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0189] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0190] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0191] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It refers to a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and A material expressed by the formula (n is an integer) may be used.

[0192] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, The oxide semiconductor layer 30a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c was In:M:Z If n=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 are y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1.0 times greater than y2 / x2. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, when y2 is equal to or greater than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more of x2, the field effect mobility of the transistor Therefore, it is preferable that y2 is less than three times x2.

[0193] When Zn and O are removed from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more for In and 75 atomic % or more for M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0194] The oxide semiconductor layer 130b is formed by multiplying the oxide semiconductor layer 130a and the oxide semiconductor layer 130b by the same amount. It is preferable to have a higher indium content than the c content. In oxide semiconductors, the s orbital of heavy metals is mainly The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the oxide semiconductor layer 130b has a higher mobility than the oxide semiconductor layer 130b. By using oxides with a high content of sodium, transistors with high field-effect mobility can be realized. It is possible.

[0195] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less. More preferably, the thickness of the oxide semiconductor layer 130c is 15 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. It is preferable that the thickness of the oxide semiconductor layer 30a is larger than that of the oxide semiconductor layer 130c.

[0196] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic (i-type) or It is effective to make the oxide semiconductor layer substantially intrinsic. Rear density is 1×10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 Not yet More preferably, it is less than 1×10 13 / cm 3 It means that it is less than.

[0197] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in the layer 130c and at the respective interfaces.

[0198] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary Induction Measuring Machine) is used. In the analysis of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 The hydrogen concentration is, for example, For example, at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. , 2 × 10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Below or less, more preferably 1 x 10 19 atoms / cm 3 Less than 5 × 10, more preferably1 8 atoms / cm 3 The nitrogen concentration is, for example, In the thickness or in a region of the oxide semiconductor layer, 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following do.

[0199] In addition, when the oxide semiconductor layer contains crystals, if silicon or carbon is contained at a high concentration, the oxide The crystallinity of the oxide semiconductor layer may be reduced. For example, at a certain depth in the oxide semiconductor layer or in a certain region in the oxide semiconductor layer. In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, or , in a region of the oxide semiconductor layer, the carbon concentration is set to 1×10 19 atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3It is sufficient that the part is less than the above.

[0200] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or about 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0201] Note that, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not come into contact with the gate insulating film, such as a gate electrode, is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field-effect mobility of the transistor. Therefore, it is preferable that the region of the oxide semiconductor layer that becomes the channel is separated from the gate insulating film. .

[0202] Therefore, the oxide semiconductor layer 130 is divided into the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b. This allows the formation of a transistor with high field-effect mobility and stable electrical characteristics. It is possible to form a

[0203] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers with different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0204] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, specifically, a U-shaped junction in which the energy of the bottom of the conduction band changes continuously between layers) The layers are fabricated so that a U-shaped well is formed. There are no impurities that form defect levels such as trap centers or recombination centers at the interface. If impurities are mixed between the stacked oxide semiconductor layers, When the energy band is not uniform, the continuity of the energy band is lost and carriers are trapped or recombined at the interface. It will disappear when combined.

[0205] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: 9:6 (atomic ratio), and the oxide semiconductor layer 130b has In:Ga:Zn=1:1:1, 2: In-Ga atomic ratios such as 1:3, 5:5:6, 3:1:2, or 4:2:4.1 The oxide semiconductor layer 130a may be formed of an oxide semiconductor such as Zn oxide. The atomic ratios of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c are calculated by subtracting the above-mentioned formula from the atomic ratios of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c. This includes a variation of plus or minus 40% in the child ratio.

[0206] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 becomes a well, and the oxide In the transistor using the semiconductor layer 130, the channel is formed in the oxide semiconductor layer 130b. The oxide semiconductor layer 130 has a conduction band minimum that changes continuously. Therefore, it can also be called a U-shaped well. can also be called a buried channel.

[0207] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a film such as a silicon oxide film. Trap levels due to impurities and defects can be formed near the interface with the insulating layer. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c allows the oxide semiconductor layer 13 This can keep 0b away from the trap level.

[0208] However, the energy of the conduction band minimum of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the bottom of the conduction band of the oxide semiconductor layer 130b and the energy of the bottom of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap level, a negative charge is generated at the interface of the insulating layer, and the transistor The threshold voltage of the transistor shifts in the positive direction.

[0209] Therefore, in order to reduce the fluctuation in the threshold voltage of the transistor, the oxide semiconductor layer 130 a and the oxide semiconductor layer 130c, and the energy of the conduction band minimum of the oxide semiconductor layer 130b It is necessary to provide a certain difference between the energy of the conduction band minimum and that of the The energy difference is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0210] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include: It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, it is possible to form a transistor. In addition, the c-axis oriented crystal is resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0211] Conductive layer 140 acts as a source electrode layer and conductive layer 1 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Typical examples include Ti, which is particularly susceptible to bonding with oxygen, and materials that can be processed at relatively high temperatures afterward. For these reasons, it is more preferable to use W, which has a high melting point. Also, low-resistance Cu and Cu-M A stack of an alloy such as n and the above material may be used. In the transistors 106, 111, and 112, for example, the conductive layer 14 The conductive layers 141 and 151 are made of W, and the conductive layers 142 and 152 are made of a laminated film of Ti and Al. etc. can be used.

[0212] The above material has a property of extracting oxygen from the oxide semiconductor film. In a part of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0213] When W is used for the conductive layer 140 and the conductive layer 150, nitrogen doping is also effective. By doping with nitrogen, the oxygen-pulling property can be weakened appropriately, and n-type The conductive layer can be prevented from expanding to the channel region. The n-type semiconductor layer is laminated with the oxide semiconductor layer, and the n-type semiconductor layer is brought into contact with the oxide semiconductor layer. Even if the n-type semiconductor is used, it is possible to prevent the n-type region from expanding into the channel region. The layers include nitrogen-doped In-Ga-Zn oxide, zinc oxide, indium oxide, and oxide. Tin oxide, indium tin oxide, etc. can be used.

[0214] The insulating layer 160, which acts as a gate insulating film, may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. ), nitrogen, zirconium (Zr), etc. may be contained as impurities.

[0215] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is made of, for example, oxygen. , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0216] Hafnium oxide and aluminum oxide are relatively The dielectric constant is high. Therefore, the physical film thickness can be made larger than the equivalent oxide film thickness. Even when the thickness of the valence oxide film is set to 10 nm or less or 5 nm or less, leakage due to tunnel current is That is, a transistor with a small off-state current can be realized. Furthermore, hafnium oxide having a crystalline structure can be used in combination with hafnium oxide having an amorphous structure. Therefore, in order to make a transistor with a small off-state current, For this purpose, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal system include monoclinic and cubic crystal systems. However, one embodiment of the present invention is not limited to these. I can't.

[0217] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When a conductor is in contact with the oxide semiconductor, the density of the nitrogen oxide level in the energy gap of the oxide semiconductor increases. The insulating layer 120 and the insulating layer 160 may be resistant to, for example, nitrogen oxide emissions. An oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film with a low leakage is used. It is possible.

[0218] In addition, silicon oxynitride films that release a small amount of nitrogen oxides have a low nitrogen oxide content in TDS. This is a membrane that releases more ammonia than the amount of ammonia released. 10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The results are as follows. The surface temperature of the film is 50°C or more and 650°C or less, or 50°C or more and 550°C or less. A range is preferred.

[0219] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0220] The conductive layer 170 acting as a gate electrode layer may be made of, for example, Al, Ti, Cr, Co, or Ni. Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W Furthermore, alloys of the above materials and conductive nitrides of the above materials may also be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are used. Typically, tungsten or a stack of tungsten and titanium nitride is used. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys, etc. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a silicon dioxide film.

[0221] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor transistor 106, transistor 109, transistor 110, and transistor 112 By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer becomes n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0222] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In transistors 107, 108, and 111, the insulating layer 175 is made of oxide. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Therefore, aluminum oxide has a high blocking effect, preventing the permeation of both water and oxygen. The aluminum film improves the electrical properties of the transistor during and after the transistor manufacturing process. to prevent impurities such as hydrogen and moisture, which are factors that cause fluctuations in the oxide semiconductor layer 130, from entering the oxide semiconductor layer 130; Preventing the release of oxygen, which is the main component material of the semiconductor layer 130, from the oxide semiconductor layer and insulating it It is suitable for use as a protective film having the effect of preventing unwanted release of oxygen from layer 120. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. can.

[0223] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0224] Here, the insulating layer 180 has a larger amount of oxygen than the stoichiometric composition, similar to the insulating layer 120. It is preferable that oxygen released from the insulating layer 180 travels through the insulating layer 160 to the oxide semiconductor. Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, which leads to the formation of a stable transistor. Electrical properties can be obtained.

[0225] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the value is reduced, the on-state current decreases.

[0226] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and reduces the on-state voltage of the transistor. The flow can be increased.

[0227] In addition, in the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side direction in addition to a gate electric field from the vertical direction. In other words, the gate electric field is applied to the entire channel forming layer. Since the effective channel width is increased, the on-current can be further increased.

[0228] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. In the first embodiment, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. This has the effect of making it difficult for an interface state to be formed. In a transistor having a three-layer oxide semiconductor layer 130, the oxide semiconductor layer 130b is located in the middle of the three-layer structure. By placing it in the layer above the ground, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor as described above, the threshold voltage is stabilized. Therefore, Icut (current when gate voltage VG is 0V) can be lowered, reducing power consumption. Furthermore, the threshold voltage of the transistor is stabilized, which improves the long-term reliability of the semiconductor device. Furthermore, the transistor of one embodiment of the present invention can be miniaturized. Since the deterioration of electrical characteristics can be suppressed, it is suitable for forming highly integrated semiconductor devices. Yes.

[0229] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0230] (Fourth embodiment) In this embodiment, the transistor 101, the transistor 107, and the transistor 108 described in Embodiment 2 are A method for manufacturing the transistor 111 will be described.

[0231] First, an example of a method for manufacturing a silicon transistor included in the substrate 115 will be described. As the substrate, - A single crystal silicon substrate is used, and an insulating layer (field oxide film) is formed on the surface. The element formation region is formed by the LOCOS method ( Local Oxidation of Silicon (STI) method and Shall Low Trench Isolation, etc. can be used.

[0232] The substrate is not limited to a single crystal silicon substrate, but can also be SOI (Silicon on Insulator) A substrate or the like can also be used.

[0233] Next, a gate insulating film is formed to cover the element formation region. The surface of the silicon oxide film is oxidized to form a silicon oxide film. After forming the silicon oxide film, the surface of the silicon oxide film may be nitrided by performing nitriding treatment.

[0234] Next, a conductive film is formed to cover the gate insulating film. , tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), Elements selected from copper (Cu), chromium (Cr), niobium (Nb), etc., or these elements It can be formed from an alloy material or compound material whose main component is It can also be formed from a metal nitride film made by nitriding silicon. It can also be formed from a semiconductor material such as polycrystalline silicon.

[0235] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film. Form.

[0236] Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed to cover the gate electrode layer. Then, sidewalls are formed on the side surfaces of the gate electrode layer by etching back.

[0237] Next, a resist mask is selectively formed so as to cover areas other than the element formation area. By introducing impurity elements using the mask and gate electrode layer, p + Type Impurity Here, to form a p-channel transistor, impurity elements and For this purpose, boron (B) or gallium (Ga), which are impurity elements that give p-type conductivity, can be used. This can be done.

[0238] This completes the fabrication of a p-channel transistor with an active region on the silicon substrate. A passivation film such as a silicon nitride film or an aluminum oxide film is formed on the transistor. It is preferable to form

[0239] Next, an interlayer insulating film is formed on the silicon substrate on which the transistors are formed, and various contact plates are Lugs and various wirings are formed. Also, as explained in the first embodiment, the diffusion of hydrogen is prevented. An insulating layer such as aluminum oxide is formed on the substrate 115. The present invention includes a silicon substrate on which a semiconductor device is formed, an interlayer insulating film formed on the silicon substrate, and the like.

[0240] Next, a manufacturing method of the transistor 101 will be described with reference to FIGS. The left side of the drawing shows a cross section of the transistor in the channel length direction, and the right side shows a cross section in the channel width direction. The cross section is shown. The drawing in the channel width direction is an enlarged view, so the apparent film thickness of each element is shown on the left. It is different in the drawing on the right.

[0241] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The oxide semiconductor layer 130 has a three-layer structure, and the oxide semiconductor layer 130c has a two-layer structure. In this case, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are two layers. When the conductor layer 130 has a single-layer structure, it may be formed as a single layer of the oxide semiconductor layer 130b.

[0242] First, an insulating layer 120 is formed on a substrate 115. The type of substrate 115 and the insulating layer 120 For the material, the explanation of the third embodiment can be referred to. The insulating layer 120 is formed by sputtering. , CVD method, MBE (Molecular Beam Epitaxy) method, etc. It can be formed.

[0243] The insulating layer 120 may be formed by ion implantation, ion doping, plasma immersion ion implantation, or the like. Oxygen may be added by implantation, plasma treatment, or the like. By adding oxygen, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 is further facilitated. It can be made easier.

[0244] Note that the surface of the substrate 115 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no influence of scattering, the insulating layer 120 may not be provided.

[0245] Next, an oxide semiconductor film 130A, which will become the oxide semiconductor layer 130a, is formed on the insulating layer 120. The oxide semiconductor film 130B that will become the semiconductor layer 130b and the oxide semiconductor film 130c that will become the oxide semiconductor layer 130c The oxide semiconductor film 130C is formed by sputtering, CVD, MBE, or the like (FIG. 3 1(A)).

[0246] When the oxide semiconductor layer 130 has a stacked structure, the oxide semiconductor film is Each layer is exposed to the atmosphere using a multi-chamber deposition device (e.g., a sputtering device). It is preferable to laminate the layers continuously without causing any damage to the film. In order to remove as much water as possible, which is an impurity for semiconductors, a cryopump is used. High vacuum evacuation (5×10) was performed using an adsorption type vacuum pump. -7 Pa~1×10 -4 Pa degree and the substrate on which the film is to be formed can be heated to 100°C or higher, preferably 500°C or higher. It is preferable to be able to heat the gas. Alternatively, a turbomolecular pump and a cold trap can be combined. This should prevent gas containing carbon components and moisture from flowing back into the chamber from the exhaust system. It is also preferable to use an exhaust system that combines a turbomolecular pump and a cryopump. Good too.

[0247] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of sputtering gases. Oxygen gas and argon gas used as sputtering gases are , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, it is possible to prevent moisture and the like from being taken into the oxide semiconductor film as much as possible. This can be prevented.

[0248] The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C are The materials described in Embodiment 3 can be used. For example, the oxide semiconductor film 130A In:Ga:Zn=1:3:6, 1:3:4, 1:3:3 or 1:3:2 [atomic ratio In:Ga:Zn=1:1:1 to the oxide semiconductor film 130B. In-Ga-Zn oxide with atomic ratios of 3:1:2, 5:5:6, or 4:2:4.1 The oxide semiconductor film 130C has a composition of In:Ga:Zn=1:3:6, 1:3:4, 1:3:3, or the like. Alternatively, an In-Ga-Zn oxide with an atomic ratio of 1:3:2 can be used. The nitride semiconductor film 130A and the oxide semiconductor film 130C contain an oxide such as gallium oxide. In addition, when a sputtering method is used for the film formation method, the above-mentioned material may be used as a target. The oxide semiconductor film 130A and the oxide semiconductor film 13 The atomic ratios of the oxide semiconductor film 130B and the oxide semiconductor film 130C are respectively calculated by subtracting the above atomic ratios from the atomic ratios of the oxide semiconductor film 130B and the oxide semiconductor film 130C. For example, the material In:Ga:Zn=4:2:4.1 The atomic ratio of the film formed by sputtering using the material as a target was In:Ga:Zn=4: Sometimes it can be 2:3.

[0249] However, as described in detail in the third embodiment, the oxide semiconductor film 130B contains an oxide semiconductor A material having a higher electron affinity than the oxide semiconductor film 130A and the oxide semiconductor film 130C is used.

[0250] Note that the oxide semiconductor film is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0251] After the oxide semiconductor film 130C is formed, first heat treatment may be performed. , at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, The reaction may be carried out in a gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. The atmosphere of the first heat treatment is an inert gas atmosphere, and then the desorbed oxygen is replenished. In order to achieve this, the first heat treatment may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C and the insulating layer 120, the oxide semiconductor film 130A, and the oxide semiconductor film 130 Impurities such as hydrogen and water can be removed from B and the oxide semiconductor film 130C. Note that the first heat treatment is performed on the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, The etching may be performed after the etching for forming the oxide semiconductor layer 130c.

[0252] Next, a conductive layer is formed on the oxide semiconductor film 130C. The conductive layer is formed, for example, by the following method. It can be formed by

[0253] First, a first conductive film is formed on the oxide semiconductor film 130C. l, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and related metallic materials A single layer or a laminate of materials selected from the alloys of the above can be used.

[0254] Next, a negative resist film is formed on the first conductive film, and an electron beam is applied to the resist film. The first layer is exposed to light using a method such as immersion exposure, EUV exposure, or the like, and then developed. A resist mask is formed. An organic layer is placed between the first conductive film and the resist film as an adhesive. It is preferable to form a coating film. A resist mask may be formed.

[0255] Next, the first conductive film is selectively etched using the first resist mask. The resist mask is then ashed to form a conductive layer.

[0256] Next, the conductive layer is used as a hard mask to form an oxide semiconductor film 130A. 130B and the oxide semiconductor film 130C are selectively etched to remove the conductive layer. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The oxide semiconductor layer 130 is formed by stacking the above-mentioned conductive films (see FIG. 31B). The oxide semiconductor layer 130 may be formed using a first resist mask without forming a layer. Here, oxygen ions may be implanted into the oxide semiconductor layer 130.

[0257] Next, a second conductive film is formed to cover the oxide semiconductor layer 130. is a material that can be used for the conductive layer 140 and the conductive layer 150 described in the third embodiment. The second conductive film can be formed by a method such as sputtering, CVD, or MBE. You can be there.

[0258] Next, a second resist mask is formed on the portions that will become the source and drain regions. Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150. (See Figure 31(C)).

[0259] Next, an insulating film 160A is formed on the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150. The insulating film 160A can be used for the insulating layer 160 described in the third embodiment. The insulating film 160A can be formed by a method such as sputtering, CVD, or MBE. etc. can be used.

[0260] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. By the second heat treatment, oxygen is removed from the insulating layer 120 and transferred to the oxide semiconductor layer 1. It is possible to diffuse the fluorine-containing compound into the entire surface of the substrate 30. The third heat treatment can be performed without performing the second heat treatment. The above effect may be obtained by the above theory.

[0261] Next, a third conductive film 171A and a fourth conductive film 171B, which will become the conductive layer 170, are formed on the insulating film 160A. The third conductive film 171A and the fourth conductive film 172A are formed as in the embodiment. The conductive layer 171 and the conductive layer 172 may be formed of a material that can be used for the conductive layer 171 and the conductive layer 172 described in 3. The third conductive film 171A and the fourth conductive film 172A can be formed by a sputtering method, a CVD method, or the like. The method, MBE, etc. can be used.

[0262] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 32(A) Then, using the resist mask, the third conductive film 171A and the fourth conductive film 171B are formed. 72A and the insulating film 160A are selectively etched to form the conductive layer 171 and the conductive layer 172. A conductive layer 170 and an insulating layer 160 are formed (see FIG. 32(B)). If the insulating film 160A is not etched, the transistor 102 can be fabricated. Cut.

[0263] Next, the oxide semiconductor layer 130, the conductive layer 140, the conductive layer 150, the insulating layer 160 and the conductive layer An insulating layer 175 is formed on the insulating layer 170. For the material of the insulating layer 175, see the description of the third embodiment. In the case of the transistor 101, an aluminum oxide film is preferably used. The insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, or the like. .

[0264] Next, the insulating layer 180 is formed on the insulating layer 175 (see FIG. 32(C)). For the material, the explanation of the third embodiment can be referred to. In addition, the insulating layer 180 is formed by sputtering. The method can be used for forming the thin film, such as a CVD method or an MBE method.

[0265] In addition, the insulating layer 175 and / or the insulating layer 180 may be subjected to ion implantation, ion doping, Oxygen is introduced using plasma immersion ion implantation, plasma treatment, etc. By adding oxygen, the insulating layer 175 and / or the insulating layer 1 This makes it easier to supply oxygen from 80 to the oxide semiconductor layer 130.

[0266] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be carried out by the insulating layer 120, the insulating layer 175, and the insulating layer 18. 0, excess oxygen is easily released, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. can be done.

[0267] Next, a method for manufacturing the transistor 107 will be described. Detailed explanation of the steps that overlap with the manufacturing method of 01 will be omitted.

[0268] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a and an oxide semiconductor layer 130b are formed on the insulating layer 120. and the oxide semiconductor film 130A which becomes the oxide semiconductor layer 130b. 0B is formed into a film by sputtering, CVD, MBE, or the like (see FIG. 33(A)).

[0269] Next, a first conductive film is formed on the oxide semiconductor film 130B, and the first conductive film is formed in the same manner as described above. A conductive layer is formed using a resist mask. Then, the conductive layer is subjected to an acid treatment using the resist mask as a hard mask. The conductive layer 130A and the oxide semiconductor layer 130B are selectively etched to form the conductive layer 130B. The layers are removed to form a stack of oxide semiconductor layers 130a and 130b. (See FIG. 33(B)). Note that a hard mask is not formed and the first resist mask is used. Here, the stack may be formed using the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. Oxygen ions may be implanted into the layer 130b.

[0270] Next, a second conductive film is formed to cover the stacked layer. A second resist mask is formed on the portion that will become the gate region, and the second resist mask is used to Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150 ( See Figure 33(C)).

[0271] Next, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are stacked, and the conductive layer 140 and the conductive layer 150, an oxide semiconductor film 130C which becomes the oxide semiconductor layer 130c is formed. Furthermore, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0272] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 34(A) Then, using the resist mask, the third conductive film 171A and the fourth conductive film 171B are formed. 72A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form conductive a conductive layer 170 consisting of a layer 171 and a conductive layer 172, an insulating layer 160, and an oxide semiconductor The insulating film 160A and the oxide semiconductor layer 130c are formed (see FIG. 34(B)). The film 130C is etched using a fourth resist mask to form the transistor 108. can be produced.

[0273] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 140, conductive layer 150, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed over the conductive layer 170 (see FIG. 34(C)).

[0274] Through the above steps, the transistor 107 can be manufactured.

[0275] Next, a method for manufacturing the transistor 111 will be described. Detailed explanation of the steps that overlap with the manufacturing method of 01 will be omitted.

[0276] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a and an oxide semiconductor layer 130b are formed on the insulating layer 120. and the oxide semiconductor film 130A which becomes the oxide semiconductor layer 130b. 0B is formed as a film by using a sputtering method, a CVD method, an MBE method, etc. Then, the first conductive film is formed as A conductive layer 141a is formed over the oxide semiconductor film 130B using a first resist mask. (See Figure 35(A)).

[0277] Then, the oxide semiconductor film 130A and the oxide semiconductor film 130B are removed using the conductive layer 141a as a hard mask. The oxide semiconductor layer 130B is selectively etched to remove the oxide semiconductor layer 130a and the oxide semiconductor layer 130 A stack of the oxide layer 141b and the conductive layer 141a is formed (see FIG. 35B). Oxygen ions may be implanted into the semiconductor layer 130a and the oxide semiconductor layer 130b.

[0278] Next, a second resist mask is formed on the portions that will become the source region and the drain region, Part of the conductive layer 141a is etched using the second resist mask, and the conductive layer 141 Then, a conductive layer 151 is formed (see FIG. 35(C)).

[0279] Next, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are stacked, and the conductive layer The oxide semiconductor film 130C that becomes the oxide semiconductor layer 130c is formed on the conductive layer 141 and the conductive layer 151. Furthermore, an insulating film 160A and a third conductive film 171A are formed on the oxide semiconductor film 130C. And the fourth conductive film 172A is formed.

[0280] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 36(A) Then, using the resist mask, the third conductive film 171A and the fourth conductive film 171B are formed. 72A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form conductive a conductive layer 170 consisting of a layer 171 and a conductive layer 172, an insulating layer 160, and an oxide semiconductor A layer 130c is formed (see FIG. 36(B)).

[0281] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 141, conductive layer 151, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed on the conductive layer 170 .

[0282] Next, openings are formed in the insulating layer 175 and the insulating layer 180, reaching the conductive layer 141 and the conductive layer 151. A fifth conductive film is formed so as to cover the opening. A fourth resist mask is provided, and the fifth conductive film is selectively etched using the resist mask. Then, etching is performed to form the conductive layer 142 and the conductive layer 152 (see FIG. 36(C)).

[0283] Through the above steps, the transistor 111 can be manufactured.

[0284] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are typically The film can be formed by sputtering or plasma CVD, but other methods, such as thermal The film may be formed by a CVD method. Examples of thermal CVD methods include MOCVD (Metal O Organic Chemical Vapor Deposition (ALD) and ALD There are also other methods such as the Atomic Layer Deposition (ALD) method.

[0285] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0286] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0287] In the ALD method, the chamber is kept at atmospheric or reduced pressure, and the source gases for the reaction are sequentially introduced. The film may be formed by repeating the gas introduction sequence. , by switching between the respective switching valves (also called high-speed valves), two or more types of raw materials can be The gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. At the same time as or after the second gas, an inert gas (argon, nitrogen, etc.) is introduced. If an inert gas is introduced at the same time, the inert gas acts as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. In addition, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later, forming a thin film. This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film can be adjusted by repeating the gas introduction sequence. The thickness can be precisely adjusted by changing the number of repetitions, and fine F It is suitable for producing ET.

[0288] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a Zn-O film, trimethylindium, trimethylgallium, and Dimethyl zinc can be used. The chemical formula of trimethyl indium is In(C The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is Zn(CH3)2. Instead of trimethylgallium, triethylgallium (chemical formula Ga(C2H5)3) Diethyl zinc (chemical formula Zn(C2H5)2) can also be used instead of dimethyl zinc. can also be used.

[0289] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis The raw material gas is vaporized trimethylsilyl dimethylamidohafnium (TDMAH) and oxidized Two types of gases are used: tetrakisdimethylamidohafnium (O3) and tetrakisdimethylamidohafnium (TDMHA). The chemical formula is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethoxy) Examples include (trimethylamido) hafnium.

[0290] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, the solvent and a liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) Two types of gases are used: a source gas containing methyltrimethylsilyl methyl ... The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris(diisopropyl alcohol). Methylamido) aluminum, triisobutylaluminum, aluminum tris(2, 2,6,6-tetramethyl-3,5-heptanedionate).

[0291] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0292] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing WF6 and B2H6 gases. The tungsten film is formed by simultaneously introducing B2H6 gas and H2 gas. Alternatively, SiH4 gas may be used.

[0293] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a Ga-O layer. Then, Zn(CH3)2 and O3 gas are introduced simultaneously to form a Zn-O layer. The order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an In-Zn-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed. Instead of O3 gas, H2O gas obtained by bubbling with an inert gas such as Ar was used. However, it is preferable to use O3 gas, which does not contain H. In(CH3)3 gas Alternatively, In(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Ga(C2H5)3 gas may be used. Zn(CH3)2 gas may also be used. stomach.

[0294] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0295] (Embodiment 5) <Structure of oxide semiconductors> The structure of an oxide semiconductor will be described below.

[0296] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0297] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0298] Oxide semiconductors are classified into, for example, non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Alternatively, oxide semiconductors can be divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. can be.

[0299] Note that as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, etc. The materials include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0300] First, let me explain about CAAC-OS.

[0301] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0302] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by the IR scope. By observing the high-resolution TEM image, multiple pellets can be identified. On the other hand, high-resolution TEM images also clearly show the boundaries between pellets, i.e., grain boundaries. Therefore, CAAC-OS cannot check the boundary. It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0303] For example, as shown in FIG. 43(A), a cross section of the CAAC-OS is taken from a direction approximately parallel to the sample surface. Here, a high-resolution TEM image of the sample is observed. The TEM image is observed using the spherical convergence corrector function. Hereafter, high-resolution TEM images using the differential correction function will be referred to as Cs-corrected high-resolution TEM images. Note that Cs-corrected high-resolution TEM images can be obtained using, for example, an atomic resolution TEM manufactured by JEOL Ltd. This can be done using an analytical electron microscope such as the JEM-ARM200F.

[0304] An enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 43(A) is shown in FIG. 43(B). From Figure 43(B), it can be seen that the metal atoms are arranged in layers in the pellet. Each layer of metal atoms is formed on the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). The shape reflects the unevenness of the surface, and is aligned parallel to the surface on which the CAAC-OS is formed or the top surface. .

[0305] In Figure 43(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines. From Figure 43(B) and Figure 43(C) The size of each pellet is about 1 nm to 3 nm, and the inclination between pellets is It can be seen that the size of the gap caused by the crack is about 0.8 nm. The nanocrystals can also be called nanocrystals (nc).

[0306] Here, from the Cs-corrected high-resolution TEM image, it is clear that the CAAC-OS pellet 5 on the substrate 5120 A schematic representation of the arrangement of 100 would resemble a stack of bricks or blocks. (See Figure 43(D)). The tilt between the pellets observed in Figure 43(C) The area where this occurs corresponds to the area 5161 shown in FIG.

[0307] Also, for example, as shown in FIG. 44(A), the CAAC-OS Observe the Cs-corrected high-resolution TEM image of the plane of area (1) and area (2) in Figure 44(A). The Cs-corrected high-resolution TEM images of the enlarged area (3) are shown in Fig. 4(B) and Fig. 4 4(C) and 44(D). The pellets are made by ensuring that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0308] For example, for CAAC-OS with InGaZnO4 crystals, X-ray diffraction (XRD) Construction by out-of-plane method using a Ray Diffraction (RF) device When structural analysis was performed, a peak appeared at a diffraction angle (2θ) of approximately 31°, as shown in Figure 45(A). This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. You can see that it is pointing in the right direction.

[0309] In addition, the out-of-plane method of CAAC-OS with InGaZnO4 crystals In the structural analysis, in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the c-axis orientation in some CAAC-OS. This indicates that the CAAC-OS contains crystals that do not have a peak at 2θ around 31°. It is preferable that the spectrum shows a peak at 2θ of around 36° and that the spectrum does not show a peak at 2θ of around 36°.

[0310] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 45(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in Figure 45(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0311] Next, the In-Ga-Zn oxide CAAC-OS was subjected to a process parallel to the sample surface. Diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident (selected area transmission electron diffraction) ) is shown in FIG. 46(A). From FIG. 46(A), for example, InGaZn The spots caused by the (009) plane of the O4 crystal are confirmed. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the On the other hand, for the same sample, the direction perpendicular to the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from the direction of the ) is shown. From Figure 46(B), a ring-shaped diffraction pattern is confirmed. Diffraction analysis also revealed that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. It can be seen that the first ring in Figure 46(B) is the InGaZnO4 crystal. This is thought to be due to the (010) and (100) planes. The second ring is thought to be due to the (110) plane.

[0312] In this way, the c-axis of each pellet (nanocrystal) is approximately perpendicular to the surface on which it is formed or the upper surface. Because of the direction, CAAC-OS is aligned with CANC (C-Axis Aligned It can also be called an oxide semiconductor having nanocrystals.

[0313] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are By removing oxygen from the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed, which causes a decrease in crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Because of their large radius, when they are contained inside an oxide semiconductor, they disrupt the atomic arrangement of the oxide semiconductor. Impurities contained in an oxide semiconductor can cause a decrease in crystallinity. This may be a source of loops or carriers.

[0314] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen vacancies in the body act as carrier traps or trap hydrogen, which can increase the carrier It can be a source of odor.

[0315] In addition, transistors using CAAC-OS show changes in their electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0316] Next, a microcrystalline oxide semiconductor will be described.

[0317] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region in which no clear crystal part can be identified. The crystal part contained in the crystal is 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often present. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline The nc-OS is also called a high-performance semiconductor. In high-resolution TEM images, the grain boundaries may not be clearly visible. It is possible that the pellets in AAC-OS have the same origin. The crystalline part of c-OS is sometimes called a pellet.

[0318] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD device that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peak is detected. Also, for nc-OS, the probe diameter (e.g., When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of, for example, 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size When nanobeam electron diffraction is performed on nc-OS, spots are observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. When nanobeam electron diffraction is performed on the OS, multiple spots are observed within the ring-shaped region. This may be the case.

[0319] In this way, the crystal orientation of each pellet (nanocrystal) is not regular. nc-OS has NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0320] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower defect state density than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. The defect level density is higher than that of AC-OS.

[0321] Next, the amorphous oxide semiconductor will be described.

[0322] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0323] In amorphous oxide semiconductors, no crystalline parts can be observed in high-resolution TEM images.

[0324] When structural analysis is performed on amorphous oxide semiconductors using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes are detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. However, when nanobeam electron diffraction is performed, no spots are observed, and a halo pattern is observed. can be.

[0325] There are various views on amorphous structures. For example, A structure that does not have a crystal structure is called a completely amorphous structure. Also, the distance between the nearest neighboring atoms or the second nearest neighboring atoms is called A structure that has order but no long-range order is sometimes called an amorphous structure. Therefore, according to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. Furthermore, at least oxides with long-range order cannot be called semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, CAAC-OS and nc-OS can be used as amorphous oxide semiconductors or completely amorphous oxides. It cannot be called a compound semiconductor.

[0326] Note that the oxide semiconductor has a structure exhibiting physical properties between those of the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. (a-like OS:amorphous-like Oxide Semiconductor It is called a uctor.

[0327] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portions can be identified.

[0328] The following describes how the influence of electron irradiation varies depending on the structure of the oxide semiconductor.

[0329] a-like OS, nc-OS, and CAAC-OS were prepared. -Ga-Zn oxide.

[0330] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0331] Furthermore, the size of the crystalline part of each sample is measured. Figure 47 shows the size of the crystalline part of each sample (from 22 points). This is an example of investigating the change in the average size of the 45 locations. It can be seen that the crystal part grows larger according to the cumulative amount of electron irradiation. As shown in (1) in 47, the size of the particles was about 1.2 nm in the initial stage of TEM observation. The crystal part (also called the initial nucleus) was exposed to a cumulative irradiation dose of 4.2 × 10 8 e - / nm 2 Smell On the other hand, the size of the nc-OS and C AAC-OS had a cumulative electron irradiation dose of 4.2 × 10 8 e - / nm 2 to It was found that the size of the crystals did not change regardless of the cumulative electron irradiation dose until the crystals reached the Specifically, as shown in (2) in Figure 47, regardless of the course of TEM observation, The size of the crystal part is about 1.4 nm. As shown above, the size of the crystals was approximately 2.1 nm regardless of the TEM observation process. You can see that.

[0332] In this way, a-like OS can be observed by irradiating it with a small amount of electrons, similar to the level observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, high-quality nc-OS and In the case of CAAC-OS, crystallization due to minute electron irradiation, such as that observed by TEM, is hardly observed. You can see that it cannot be seen.

[0333] The size of the crystalline parts of a-like OS and nc-OS was measured using high-resolution TEM. For example, InGaZnO4 crystals have a layered structure, and In The unit cell of the InGaZnO4 crystal is: It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers arranged in the c-axis direction. Therefore, the spacing between adjacent layers is determined by the lattice of the (009) plane. The value is approximately the same as the interplanar spacing (also called the d value), and is determined to be 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and investigated the In the area where the thickness is between 0.28 nm and 0.30 nm, each lattice fringe is InGaZ. It corresponds to the ab plane of the nO4 crystal.

[0334] In addition, the density of oxide semiconductors may differ depending on the structure. For example, If the composition of a material is known, the density of that material can be determined by comparing it with the density of a single crystal of the same composition. The structure of the oxide semiconductor can be estimated. For example, the density of a single crystal is The density of the OS is 78.6% or more and less than 92.3%. In contrast, the density of the nc-OS and CAAC-OS was 92.3% or more and less than 100%. Note that an oxide semiconductor having a density of less than 78% of the density of a single crystal can be formed by film formation. The body is difficult.

[0335] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In oxide semiconductors that satisfy the numerical ratio, single crystal InGaZnO4 with a rhombohedral crystal structure Density is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1[ In oxide semiconductors that satisfy the atomic ratio, the density of the a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1 [ In oxide semiconductors that satisfy the [number of atoms / atoms ratio], the density of the nc-OS and the density of the CAAC-OS are is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0336] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, it is possible to calculate the density corresponding to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate them in combination.

[0337] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film containing two or more of a compound semiconductor and a CAAC-OS.

[0338] Oxide semiconductors with low impurity concentrations and low defect state densities (few oxygen vacancies) have carrier Therefore, such an oxide semiconductor can be used as a high-purity intrinsic or The CAAC-OS and nc-OS are essentially high-purity intrinsic oxide semiconductors. The impurity concentration is lower than that of OS-like and amorphous oxide semiconductors, and the density of defect states is lower. That is, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor is likely to be obtained. The transistors using the CAAC-OS or nc-OS have a negative threshold voltage. In addition, the high purity intrinsic or In reality, high-purity intrinsic oxide semiconductors have few carrier traps. Transistors using C-OS or nc-OS have small fluctuations in electrical characteristics and high reliability. The charge trapped in the carrier traps in the oxide semiconductor is It takes a long time to release the charge, and it can behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect states has a low The electrical characteristics may become unstable.

[0339] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0340] FIG. 48(A) shows how a CAAC-OS film is formed by sputtering. FIG.

[0341] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnet. The magnetic field of the magnet is used to increase the deposition rate. The sputtering method is called magnetron sputtering.

[0342] The target 5130 has a polycrystalline structure, and each grain contains a cleavage plane.

[0343] As an example, the cleavage surface of a target 5130 having In-Ga-Zn oxide is described. FIG. 49(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In addition, in FIG. 49(A), the c-axis is directed upward, and the InGaZnO This is the structure of the crystal of 4.

[0344] As shown in Figure 49(A), in two adjacent Ga-Zn-O layers, the oxide It can be seen that the atoms are arranged close to each other. As a result, two adjacent Ga-Zn-O layers repel each other. The ZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0345] The substrate 5120 is disposed facing the target 5130, and the distance between them is d (target The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the film deposition chamber is set to 0.02m or more and 0.5m or less. Most of the film deposition gas (e.g., oxygen) It is filled with a gas mixture containing hydrogen, argon, or oxygen at a ratio of 5% by volume or more, and The pressure is controlled to be in the range of 0.1 Pa to 100 Pa, preferably in the range of 0.1 Pa to 10 Pa. By applying a voltage above a certain level to the target 5130, discharge begins and plasma is generated. It is noted that a high density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 The ions 5101 are, for example, positive ions of oxygen (O + ) and argon cations (A r + ) etc.

[0346] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually reach the target 5130. At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are separated and knocked out. 5100a and pellet 5100b are impacted by the impact of ions 5101 into the structure. Distortion may occur.

[0347] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, plane. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may be formed. In some cases, two squares (e.g., a diamond) are joined together to form a rectangle.

[0348] The thickness of the pellet 5100 is determined depending on the type of deposition gas, etc. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferable to thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The pellet 5100 is (1) in FIG. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the Ga-Zn-O layer 30, as shown in FIG. A pellet 5100 having three layers, an In-O layer, a Ga-Zn-O layer, and an In-O layer, emerges. FIG. 49(C) shows the structure of the pellet 5100 when observed from a direction parallel to the c-axis. Therefore, the pellet 5100 consists of two Ga-Zn-O layers (pans) and an In- It can also be called a nano-sized sandwich structure having a layer (filler) and a layer (filler).

[0349] The pellet 5100 receives an electrical charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 5100 has oxygen atoms on the side, and the oxygen atoms are negatively charged. In this way, the sides can be charged with the same polarity, The repulsion between the particles occurs, allowing the particles to maintain their flat shape. However, in the case of In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, an acid bonded to an indium atom, a gallium atom, or a zinc atom may The atoms may become negatively charged. Also, the pellet 5100 may become It grows by bonding with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. The difference in size between (2) and (1) in Figure 47 above is due to the growth in the plasma. Here, when the substrate 5120 is at room temperature, the pellet 5100 is heated for more than 1 minute. Since the film does not grow on the surface, it becomes nc-OS (see Figure 48(B)). The temperature at which film formation is possible is around room temperature. Therefore, even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow the pellet 5100 in plasma, Increasing the film formation power is effective. By increasing the film formation power, the pellet 5100 The structure can be stabilized.

[0350] As shown in Figures 48(A) and 48(B), for example, pellet 5100 is a plasma It flies through the air like a kite and flutters up onto the substrate 5120. Pellet 51 Because 00 is electrically charged, it approaches an area where other pellets 5100 have already accumulated. Here, on the upper surface of the substrate 5120, a repulsive force is generated. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120. The magnetic field and the electric current act on the object, creating a force (Lorentz force). This can be understood by the left-hand rule.

[0351] The pellet 5100 has a larger mass than a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of the field and the electric current. In order to increase the The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably It is preferable to provide an area where the resistance is 50 G or more. The magnetic field parallel to the top surface of the substrate 5120 is 1.5 times stronger than the magnetic field perpendicular to the top surface of the substrate 5120. times or more, preferably two times or more, more preferably three times or more, and even more preferably five times or more. It is a good idea to set up an area for this purpose.

[0352] At this time, the magnet and the substrate 5120 move or rotate relative to each other. Therefore, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. On the upper surface of 5120, the pellet 5100 is subjected to forces in various directions and It can be moved.

[0353] Also, when the substrate 5120 is heated as shown in FIG. 48(A), the pellet 5100 The resistance due to friction between the substrate 5120 and the pellets is small. The pellet 5100 glides over the top surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the particles reach the side of the pellet 5100, the sides are joined together. The oxygen atom on the side of 0 is released. The released oxygen atom Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. or 170° C. or more and less than 400° C. That is, when the substrate 5120 has a large area, In this case, it is possible to form a CAAC-OS film.

[0354] Furthermore, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, and the The structural distortion caused by the collision of the pellet 5101 is relaxed. Pellet 5100 becomes almost single crystal. Even if the 100 is heated after bonding, the pellet 5100 itself hardly expands or contracts. Therefore, the gaps between the pellets 5100 widen, causing defects such as grain boundaries. It does not form depressions or crevasse formation.

[0355] In addition, the CAAC-OS is not made of a single-crystal oxide semiconductor. The aggregates of pellet 5100 (nanocrystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between them. Even if deformation such as shrinkage occurs in CAAC-OS due to heating or bending, local stress Therefore, flexible semiconductors can be The structure of nc-OS is suitable for biomedical devices. The arrangement is like they are stacked in order.

[0356] When the target is sputtered with ions, not only pellets but also zinc oxide etc. fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And, 0.1 nm to 10 nm, 0.2 nm to 5 nm, or 0.5 A zinc oxide layer 5102 having a thickness of 2 nm or more is formed. A cross-sectional schematic diagram is shown in FIG.

[0357] As shown in FIG. 50(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the particles slide on pellet 5105b. In another aspect of 5a, a plurality of particles 510 ejected from the target along with zinc oxide. 3 is crystallized by heating the substrate 5120, forming a region 5105a1. The atoms 5103 may include oxygen, zinc, indium, and gallium, among others.

[0358] Then, as shown in FIG. 50(B), the region 5105a1 is assimilated with the pellet 5105a. 5105a2. The pellet 5105c has a side surface similar to that of the pellet 5105a. Place it so that it touches the other side of 05b.

[0359] Next, as shown in FIG. 50(C), a pellet 5105d is further added to the pellet 5105a2. and pellet 5105b, and then on pellet 5105a2 and pellet 51 It slides on the other side of the pellet 5105c. The pellet 5105e slides over the zinc oxide layer 5102.

[0360] As shown in FIG. 50(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is placed so that its side faces the pellet. Also, the other side of the pellet 5105d is arranged so as to be in contact with the other side of the pellet 5105c. In the process, a plurality of particles 5103 that fly out from the target together with zinc oxide are deposited on the substrate 512. 0, it crystallizes and forms a region 5105d1.

[0361] As described above, the piled pellets are arranged so that they come into contact with each other, and the particles are formed on the side surfaces of the pellets. As a result of this growth, a CAAC-OS is formed on the substrate 5120. The individual pellets of C-OS are larger than those of nc-OS. The difference in size between (1) and (2) corresponds to the growth after deposition.

[0362] In addition, the gaps between the pellets 5100 become extremely small, so that one large pellet is formed. The large pellets may have a single crystal structure. The size is 10 nm to 200 nm, 15 nm to 100 nm, or Therefore, the channel of the transistor may be When the formation region is smaller than a large pellet, it has a single crystal structure as the channel formation region. In addition, the pellet size is increased, so that the transistor chip size can be increased. Regions having a single crystal structure are used as the channel forming region, source region, and drain region. It may be possible.

[0363] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. This may improve the frequency characteristics of the transistor.

[0364] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. Therefore, unlike epitaxial growth, if the surface to be formed does not have a crystalline structure, For example, it is possible to form a CAAC-OS film on the substrate 5120. Even if the structure of the upper surface (surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a C-OS film.

[0365] In addition, even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven, the CAAC-OS For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed with the flat surface, which is parallel to the ab plane, facing downwards. When the thickness of the pellet 5100 is uniform, the thickness is uniform, flat, and high. A layer with high crystallinity is formed. Then, the layer is stacked in n stages (n is a natural number). CAAC-OS can be obtained by

[0366] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510 The structure is made up of n layers (n is a natural number) of layers in which 0s are arranged along the unevenness. Since the surface 20 has unevenness, gaps tend to occur between the pellets 5100. However, there is an intermolecular force between the pellets, so even if there are irregularities, the The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is maintained. It can be called CAAC-OS.

[0367] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if there is a problem, uniform film formation is possible.

[0368] Since the CAAC-OS film is formed using this model, the sputtered particles have a small thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0369] The film formation model shown above allows for the formation of highly crystalline films even on a surface with an amorphous structure. A CAAC-OS having the formula:

[0370] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0371] (Embodiment 6) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0372] FIG. 37 shows a CPU using the transistors described in the previous embodiments at least in part. FIG. 10 is a block diagram showing the configuration of an example.

[0373] The CPU shown in FIG. 37 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and ROM interface 1189 are Of course, the CPU shown in FIG. 37 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 37 is considered as one core, and a configuration including multiple such cores is considered as one core. It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be a bit or the like.

[0374] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0375] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0376] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to various circuits.

[0377] In the CPU shown in FIG. 37, a memory cell is provided in the register 1196. The transistors shown in the above embodiment can be used as the memory cells of 1196. do.

[0378] In the CPU shown in FIG. 37, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the power supply voltage is applied to the memory cells in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped. .

[0379] FIG. 38 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, a transistor 1210, The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a capacitor.

[0380] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 120 The first gate of the transistor 1209 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to a load such as a resistor. The structure is such that the terminal is grounded via the ground terminal.

[0381] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., traction) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0382] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 ​​is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0383] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0384] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no conduction between terminals 2.

[0385] In the transistor 1209 in FIG. 38, the second gate electrode (second gate electrode: back The first gate receives a control signal WE, and the second gate receives a control signal WE. The control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, the ground potential GND or the solenoid voltage of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the source potential of the transistor. This is a potential signal for controlling the threshold voltage of the transistor 1209. In addition, the control signal WE2 is the same potential signal as the control signal WE. The transistor 1209 may be a transistor without a second gate. A resistor can also be used.

[0386] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 38, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0387] In FIG. 38, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0388] In addition, in FIG. 38, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed by a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor with a channel formed in a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may be implemented by any other element than the transistor 1209. The other transistors may also include a transistor in which the channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. The transistor may also be a transistor that is

[0389] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0390] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0391] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, Even when the power supply voltage is not supplied to 200, the signal held in the capacitor element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0392] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0393] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal can be accurately read out.

[0394] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0395] In this embodiment, the storage element 1200 is used as a CPU. 200 is equipped with a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Devices), R Also applicable to F-ID (Radio Frequency Identification) It is possible.

[0396] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0397] (Embodiment 7) A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, portable data terminals, e-books, video cameras, digital cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) ), navigation systems, sound reproduction devices (car audio, digital audio players) Years, etc.), copiers, fax machines, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs, vending machines, etc. Specific examples of these electronic devices are shown in Figure 39.

[0398] FIG. 39(A) shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908 The portable game machine shown in FIG. 39A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0399] FIG. 39(B) shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input of information. .

[0400] FIG. 39(C) shows a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard, and a keyboard. The computer has a keyboard 923, a pointing device 924, and the like.

[0401] FIG. 39(D) shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, a wristband 9 33, etc. The display unit 932 may be a touch panel.

[0402] FIG. 39(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0403] FIG. 39(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a rear view mirror. It has Ito 954 etc.

[0404] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can. [Explanation of symbols]

[0405] 20 Through hole 21 Contact Hole 22 Contact Hole 23 Contact Hole 24 contact holes 25 Contact Hole 32 Source electrode layer 33 Drain electrode layer 35 Resist mask 40 Silicon substrate 51 Transistor 52 transistors 53 Transistor 54 transistors 55 Capacitor element 61 Contact plug 62 Contact plug 63 Contact plug 64 Contact plug 65 Contact plug 66 Contact plug 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 79 Wiring 81 Insulating layer 82 Insulating layer 83 Insulating layer 84 Insulating layer 85 Insulating layer 86 Insulating Layer 87 Insulating layer 90 Inverter circuit 91 circuits 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 108 transistors 109 Transistor 110 Transistor 111 Transistor 112 transistors 115 PCB 120 insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130A oxide semiconductor film 130b Oxide semiconductor layer 130B Oxide semiconductor film 130c Oxide semiconductor layer 130C oxide semiconductor film 140 Conductive layer 141 Conductive layer 141a Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 156 Resist mask 160 Insulating Layer 160A insulating film 170 Conductive Layer 171 Conductive layer 171A Conductive film 172 Conductive layer 172A Conductive film 173 Conductive Layer 175 Insulating Layer 180 insulating layer 190 Insulating Layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Display section 919 Camera 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Display section 933 Wristband 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 5100 pellets 5100a pellets 5100b pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellets 5105a1 area 5105a2 pellets 5105b Pellets 5105c Pellets 5105d Pellets 5105d1 area 5105e Pellets 5120 board 5130 Target 5161 area

Claims

1. a first transistor having a first channel formation region; a second transistor having a second channel formation region, a gate of the first transistor and a gate of the second transistor are electrically connected to a first conductive layer; the first channel formation region includes silicon; the second channel formation region includes an oxide semiconductor layer; a first gate insulating layer is provided on the first channel formation region; a first insulating layer is provided on the first gate insulating layer; the oxide semiconductor layer is provided on the first insulating layer; a second gate insulating layer is provided on the second channel formation region; a second insulating layer is provided on the second gate insulating layer; one of a source and a drain of the first transistor has a region in contact with the second conductive layer; the other of the source and the drain of the first transistor has a region in contact with a third conductive layer; one of a source and a drain of the second transistor has a region in contact with the second conductive layer; the other of the source and the drain of the second transistor has a region in contact with a fourth conductive layer; the second conductive layer is provided in the same layer as the third conductive layer, the third conductive layer is electrically connected to a fifth conductive layer provided on the third conductive layer; the fourth conductive layer is electrically connected to a sixth conductive layer provided on the fourth conductive layer; the first conductive layer has a region in contact with an upper surface of the second insulating layer; the sixth conductive layer has a region in contact with an upper surface of the second insulating layer, a high power supply potential is applied to the fifth conductive layer; A low power supply potential is applied to the sixth conductive layer.

2. a first transistor having a first channel formation region; a second transistor having a second channel formation region, a gate of the first transistor and a gate of the second transistor are electrically connected to a first conductive layer; the first channel formation region includes silicon; the second channel formation region includes an oxide semiconductor layer; a first gate insulating layer is provided on the first channel forming region; a first insulating layer is provided on the first gate insulating layer; the oxide semiconductor layer is provided on the first insulating layer; a second gate insulating layer is provided on the second channel formation region; a second insulating layer is provided on the second gate insulating layer; one of a source and a drain of the first transistor has a region in contact with the second conductive layer; the other of the source and the drain of the first transistor has a region in contact with a third conductive layer; one of a source and a drain of the second transistor has a region in contact with the second conductive layer; the other of the source and the drain of the second transistor has a region in contact with a fourth conductive layer; the second conductive layer is provided in the same layer as the third conductive layer, the third conductive layer is electrically connected to a fifth conductive layer provided on the third conductive layer; the fourth conductive layer is electrically connected to a sixth conductive layer provided on the fourth conductive layer; the first conductive layer has a region in contact with an upper surface of the second insulating layer; the sixth conductive layer has a region in contact with an upper surface of the second insulating layer, a high power supply potential is applied to the fifth conductive layer; a low power supply potential is applied to the sixth conductive layer; a channel length direction of the first transistor is provided along a first direction; a channel length direction of the second transistor is provided along the first direction.

3. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor layer contains In, Ga, and Zn.

4. In claim 1 or 2, The semiconductor device, wherein the oxide semiconductor layer contains indium oxide.

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