Semiconductor device

Abstract

To provide a storage device which does not require a complicated manufacturing process and can reduce power consumption; and provide a semiconductor device using the storage device.SOLUTION: A semiconductor device comprises: a phase inversion element such as an inverter or a clocked inverter which outputs an input signal by inverting a phase of the input signal; and a capacitive element for retaining data and a switching element for controlling accumulation and emission of charge in the capacitive element, which are provided in the storage element. As the switching element, a transistor including an oxide semiconductor in a channel formation region is used. When application of power supply voltage to the phase inversion element is stopped, data is retained by the capacitive element by storing data in the capacitive element even when supply of the power source voltage to the phase inversion element is stopped.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory device, and a semiconductor device and electronic equipment using the memory device. [Background technology]

[0002] A transistor using a semiconductor film formed on an insulating surface is indispensable for a semiconductor device. The manufacturing of transistors is limited by the heat resistance temperature of the substrate. Amorphous silicon, which can be formed at a relatively low temperature, and silicon, which is formed using laser light or catalytic elements. A transistor having an active layer made of polysilicon or the like obtained by crystallization is used in a semiconductor display device. It has become the mainstream transistor used in

[0003] In recent years, the high mobility achieved by polysilicon and microcrystalline silicon and the high mobility achieved by amorphous silicon have been Oxide is a new semiconductor material that combines the uniform device characteristics obtained with silicon. Metal oxides, which are called "metal semiconductors" and exhibit semiconducting properties, are attracting attention. It is used in a variety of applications, for example, indium oxide, a well-known metal oxide, They are used as transparent electrode materials in liquid crystal displays and other devices. Examples of the oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Transistors using metal oxides that exhibit such semiconducting properties in the channel formation region have already been developed. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0005] By the way, a register, which is one of the memory devices, is generally made up of inverters, clocked inverters, A logic circuit is made up of logic elements such as a memory and switching elements. Much faster than RAM (Random Access Memory) which is used as a Since registers can operate at high speeds, they are used in processors for arithmetic processing and It is used to temporarily store data, such as to store the execution status of a program.

[0006] FIG. 16A shows one of the memory elements that constitute a register using an inverter. The register 1300 shown in (A) includes an inverter 1301, an inverter 1302, a switch The inverter 1301 has a switching element 1303 and a switching element 1304. The input of the signal IN to the input terminal is controlled by a switching element 1303. The potential of the output terminal of the inverter 1301 is given to the subsequent circuit as a signal OUT. The output terminal of the inverter 1301 is connected to the input terminal of the inverter 1302. The output terminal of the inverter 1302 is connected to the inverter 1301 via the switching element 1304. is connected to the input terminal.

[0007] The potential of the signal IN input via the switching element 1303 is When the switching element 1303 is turned off and the switching element 1304 is turned on, the voltage is held in the register 1300. will be done.

[0008] A more specific circuit configuration of the register 1300 shown in FIG. 16(A) is shown in FIG. 16(B). The register 1300 shown in FIG. 16B includes an inverter 1301 and an inverter 1302. , switching element 1303, and switching element 1304. The connection configuration is the same as that shown in FIG.

[0009] The inverter 1301 includes p-channel transistors 131 whose gate electrodes are connected to each other. 0 and an n-channel transistor 1311. The node to which the power supply potential VDD is applied and the node to which the low-level power supply potential VSS is applied are Between the two nodes, a p-channel transistor 1310 and an n-channel transistor 131 1 is connected in series. Similarly, the inverter 1302 has gate electrodes A p-channel transistor 1312 and an n-channel transistor 131 3. A node to which a high-level power supply potential VDD is applied and a Between nodes to which the power supply potential VSS is applied, a p-channel transistor The capacitor 1312 and the n-channel transistor 1313 are connected in series.

[0010] The inverter 1301 shown in FIG. 16B has a gate of a p-channel transistor 1310. The potential applied to the electrode and the gate electrode of the n-channel transistor 1311 is Therefore, when the power supply potential VDD is given, Ideally, the current between a node that is connected to the power supply potential VSS is However, in reality, a small amount of off-state current flows in the transistor that should be off. Since the current between the nodes is still flowing, the current between the nodes will not be completely zero. The same phenomenon occurs in register 1300 even if data is written to it. Power consumption occurs even when the device is not being held.

[0011] For example, depending on the size of the transistor, In the case of a transistor, an off-state current of about 1 pA occurs when the voltage between nodes is about 3 V at room temperature. The memory element shown in FIG. 16(A) and FIG. 16(B) includes an inverter 1301 and an inverter Since two inverters 1302 are provided, an off-current of about 2 pA occurs. And the number of memory elements is about 10 7 In the case of a resistor with a total of about 1000 ohms, the off-state current is If the temperature of the IC chip where the resistor is installed rises, the power consumption will The force becomes even greater, and the off-state current of the resistor alone reaches several mA.

[0012] Therefore, one method to reduce power consumption is to stop the supply of power supply potential to the register. A register is a volatile memory that loses data if the supply of power potential is interrupted. Since it is a non-volatile storage device, the method requires that data be held in registers for a long time. If so, the data is temporarily transferred to a non-volatile storage device arranged around the register. However, these nonvolatile storage devices mainly use magnetic elements and ferroelectrics. , the manufacturing process is complicated.

[0013] In addition, when the power is turned off for an extended period of time, data will be lost on hard disks, flash memory, etc. You can transfer the data to a storage device and then shut down the power, but the data on those storage devices will be lost. It takes time to restore power, so it is not suitable for short-term power outages.

[0014] In view of the above-mentioned problems, the present invention is a semiconductor device that does not require a complicated manufacturing process and can reduce power consumption. It is another object of the present invention to provide a memory device that can perform the above-described operations, and a semiconductor device and an electronic device that use the memory device. In particular, a storage device that can reduce power consumption by stopping the power supply for a short period of time, One of the objects is to provide a semiconductor device and an electronic device using the same. [Means for solving the problem]

[0015] An inverter or clocked inverter that inverts the phase of the input signal and outputs it. In order to store data in a memory element using a logic element (hereinafter referred to as a phase inversion element), a capacitance element for storing and discharging electric charges, and a switching element for controlling the storage and release of electric charges in the capacitance element. The switching element includes an oxide semiconductor in a channel formation region. A transistor containing

[0016] Specifically, the memory element includes two phase inversion elements, a capacitance element, and a charge in the capacitance element. and a switching element for controlling the accumulation and release of the signal. The signal containing the data is applied to the input terminal of the first phase inversion element. The output terminal of the first phase inverter is connected to the input terminal of the second phase inverter. The output terminal of the first phase inversion element is connected to the input terminal of the first phase inversion element. The potential of the output terminal or the input terminal of the second phase inversion element is transmitted as a signal to a subsequent storage element or or output to other circuits.

[0017] The phase inversion element includes at least one p-channel transistor having gate electrodes connected to each other. and at least one n-channel transistor connected to the first node and the second node. The nodes are connected in series.

[0018] The capacitance element is configured to store the data of the signal input to the storage element as needed. is connected to a node to which the potential of the signal is applied via the switching element. do.

[0019] When a power supply voltage is applied between the first node and the second node, When a signal containing data is input to the input terminal of the phase inversion element, the first phase inversion element and the second phase inversion element The data is maintained by the phase inversion element between the first node and the second node. When the application of the power supply voltage is stopped, the switching element By turning on the capacitor, the signal data is stored in the capacitor. Even if the application of the power supply voltage is stopped, the data can be retained in the memory element.

[0020] The channel forming region of the transistor used in the switching element is made of high-purity silicon. Because it contains a fluorinated oxide semiconductor, it has the characteristic of having a significantly low off-state current. .

[0021] Oxide semiconductors have the advantages of high mobility provided by microcrystalline silicon or polycrystalline silicon, A metal that exhibits semiconducting properties and has the uniform device characteristics obtained with amorphous silicon. It is an oxide. And impurities such as water or hydrogen, which act as electron donors, are reduced. The highly purified oxide semiconductor (purified OS) is an i-type (intrinsic semiconductor). Or it is a semiconductor that is as close to i-type as possible (substantially i-type). Analysis method (SIMS: Secondary Ion Mass Spectrometry) The hydrogen concentration in the oxide semiconductor measured by 19 / cm 3 below, Preferably 5 x 10 18 / cm 3 Less than or equal to 5 × 10 17 / cm 3 Below, further Preferably 1 x 10 16 / cm 3 The moisture or The above configuration removes impurities such as hydrogen. The carrier density of the semiconductor film is 1×10 14 cm -3 Less than 1 x 10 12 cm -3 less than 1 × 10 11 cm -3 Can be less than That is, the carrier density of the oxide semiconductor film can be made as close to zero as possible. The band gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Therefore, the concentration of impurities such as water and hydrogen is sufficiently reduced and the material is highly purified. By using an oxide semiconductor film, the off-state current of a transistor can be reduced.

[0022] Here, analysis of the hydrogen concentration in the oxide semiconductor film and the conductive film will be described. The hydrogen concentration in semiconductor and conductive films is measured by secondary ion mass spectrometry (SIMS). SIMS analysis is performed using standard ion mass spectrometry (SIMS). In principle, it is possible to obtain accurate data near the sample surface and near the interface between layers of different materials. Therefore, we investigated the distribution of hydrogen concentration in the film in the thickness direction. When analyzing with SIMS, there should be no extreme fluctuations in the values ​​within the range where the target film exists. The average value in the region where a nearly constant value is obtained is adopted as the hydrogen concentration. When the thickness of the target film is small, it is affected by the hydrogen concentration in the adjacent film and remains almost constant. In this case, it may be impossible to find an area where the value of The maximum or minimum value of the hydrogen concentration is adopted as the hydrogen concentration in the film. In the region where the film exists, a mountain-shaped peak indicating a maximum value and a valley-shaped peak indicating a minimum value are formed. If not present, the value at the inflection point is taken as the hydrogen concentration.

[0023] Note that an oxide semiconductor film formed by sputtering or the like contains a large amount of moisture or hydrogen as impurities. It has been found that water or hydrogen easily forms donor levels. In view of this, in one embodiment of the present invention, In order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film, In an atmosphere of inert gas such as nitrogen or rare gas, oxygen gas, or ultra-dry air (C When measured using a RDS (cavity ring-down laser spectroscopy) dew point meter The moisture content is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, The heat treatment is carried out in an atmosphere of 500°C or higher (air) with a concentration of 10 ppb or less. 0°C or lower (or lower than the strain point of the glass substrate), preferably 550°C or higher and 750°C or lower It is desirable to carry out this heat treatment within the temperature range below which the substrate can withstand. The effect of desorption of moisture or hydrogen by heat treatment is measured by TDS (Therm Thermal Desorption Spectroscopy (TDA) confirmed this. It has been approved.

[0024] Heat treatment is performed using a furnace or rapid thermal annealing (RTA). The TA method uses a lamp light source, and the substrate is moved into a heated gas for a short time. The RTA method can reduce the time required for heat treatment to less than 0.1 hours. You can also do this.

[0025] Specifically, the oxide semiconductor film highly purified by the above-described heat treatment was used as an active layer. The transistor exhibits a very low off-state current. 1×10 6 Even if the device has a channel length (L) of 10 μm, the source electrode and drain The off-state current (gate electrode voltage) in the voltage between the electrodes (drain voltage) range of 1V to 10V The drain current when the voltage between the gate and source electrodes is set to 0 V or less is calculated using a semiconductor parameter analyzer. Below the riser measurement limit, i.e., 1×10 -13 A or less. The off-state current density, which corresponds to the off-state current divided by the transistor channel width, is 100 zA. Furthermore, as a switching element for holding the charge in the storage capacitor, A transistor having a highly purified oxide semiconductor film and a gate insulating film with a thickness of 100 nm. The off-state current of the transistor is calculated from the change in the charge amount per unit time of the storage capacitance using Measurements showed that when the voltage between the source and drain electrodes of the transistor was 3V, 1 It has been found that even lower off-state current densities of 0 zA / μm to 100 zA / μm can be obtained. Therefore, in a memory device according to one embodiment of the present invention, a highly purified oxide semiconductor The off-state current density of a transistor using the film as an active layer is 100 zA / μm or less, preferably It is possible to make the current flow rate at or below 10 zA / μm, and more preferably at or below 1 zA / μm. In the transistor using a highly purified oxide semiconductor film as an active layer, the off-state current is This is significantly lower than that of a transistor using crystalline silicon.

[0026] In addition, a transistor using a highly purified oxide semiconductor has almost no temperature dependence of its off-state current. One of the reasons for this is that there are many electron donors in oxide semiconductors. By removing impurities and purifying the oxide semiconductor, the conductivity type becomes as close to intrinsic as possible. The Fermi level is located in the center of the forbidden band. The energy gap of the compound semiconductor is 3 eV or more, and the number of thermally excited carriers is extremely small. Furthermore, the fact that the source electrode and the drain electrode are in a degenerated state also contributes to the This is the reason why the temperature dependence does not appear. The transistor operates by Most of the charge is due to carriers injected into the oxide semiconductor, and the carrier density varies depending on the temperature. Since there is no temperature dependency, it is thought that no temperature dependency of the off-current is observed.

[0027] The transistor having the above structure is used as a switch for holding the charge stored in the capacitor. By using it as a capacitance element, it is possible to prevent leakage current of electric charge from the capacitance element. Therefore, even when the power supply voltage is not applied, data can be retained without being lost. The period during which data is held in the capacitance element is the period during which the power supply voltage is supplied to the phase inversion element. Since there is no need to perform This reduces the wasteful power consumption of memory devices, and also reduces the This makes it possible to reduce the power consumption of the entire device.

[0028] Note that the transistor used in the phase inverter may be made of an amorphous or finely crystalline semiconductor other than an oxide semiconductor. Use semiconductors such as crystalline, polycrystalline, or single crystalline silicon or germanium. The transistor may be a thin semiconductor film or a bulk semiconductor film. A p-channel transistor using an oxide semiconductor film may be fabricated using a semiconductor substrate. If it is possible to manufacture such a memory element, it is possible to use an oxide semiconductor film in the active layer of all transistors in the memory element. can also be used to simplify the process.

[0029] In one embodiment of the present invention, a power supply voltage is supplied to a memory element through a gate electrode having an oxide semiconductor as a channel type. As described above, the control may be performed using a transistor including an oxide semiconductor in the transistor region. The transistors included in the channel formation region have an energy of 3.0 to 3.5 eV, which is about three times that of silicon. Therefore, the oxide semiconductor is included in the channel formation region. Since the transistor including the transistor has high voltage resistance, the supply of the power supply voltage to the memory element is By controlling the temperature with a motor, the reliability of the semiconductor device can be improved.

[0030] The oxide semiconductor is an In-Sn-Ga-Zn-O-based oxide semiconductor, which is a quaternary metal oxide. Conductors, ternary metal oxides such as In-Ga-Zn-O oxide semiconductors, In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors Conductors, binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxides semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors, In-O based oxide semiconductors, Sn-O based oxide semiconductors, Zn-O based oxide semiconductors, etc. In this specification, for example, an In—Sn—Ga—Zn—O system Oxide semiconductors are made of indium (In), tin (Sn), gallium (Ga), and zinc (Zn). The stoichiometric composition ratio is not particularly limited. The oxide semiconductor may contain silicon.

[0031] Alternatively, the oxide semiconductor may have the chemical formula InMO3(ZnO) m (m>0) Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. vinegar. [Effects of the Invention]

[0032] To provide a memory device capable of suppressing power consumption and a semiconductor device using the memory device This can be done. [Brief explanation of the drawings]

[0033] [Figure 1] Circuit diagram of a memory element. [Figure 2] Circuit diagram of a memory element. [Figure 3] Circuit diagram of a memory element. [Figure 4] Circuit diagram of a memory element. [Figure 5] Circuit diagram of a memory element. [Figure 6] Circuit diagram of a memory element. [Figure 7] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 8] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 9] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 10] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 11] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 12] FIG. [Figure 13] FIG. 1 is a diagram showing the configuration of a storage device. [Figure 14] 1A and 1B are a top view and a cross-sectional view of a transistor. [Figure 15] 1A to 1C illustrate a manufacturing method of a memory device. [Figure 16] FIG. 1 is a circuit diagram of a conventional memory element. [Figure 17] Block diagram of a CPU using a storage device. [Figure 18] FIG. 1 illustrates a configuration of an electronic device. [Figure 19] FIG. 10 is a cross-sectional view of a transistor including an oxide semiconductor. [Figure 20] 20 is an energy band diagram (schematic diagram) taken along the line AA' in FIG. 19. [Figure 21] (A) shows the state where a positive voltage (VG>0) is applied to the gate electrode (GE), and (B) shows the state where a negative voltage (VG<0) is applied to the gate electrode (GE). [Figure 22] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ). [Figure 23] FIG. [Figure 24] 4 is a timing chart showing the operation of the storage device. [Figure 25] 4 is a timing chart showing the operation of the storage device. [Figure 26] 4 is a timing chart showing the operation of the storage device. [Figure 27] 4 is a timing chart showing the operation of the storage device. [Figure 28] 4 is a timing chart showing the operation of the storage device. [Figure 29] 4 is a timing chart showing the operation of the storage device. DETAILED DESCRIPTION OF THE INVENTION

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and the embodiments and aspects thereof may be modified without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0035] In addition, the microprocessor, image processing circuit, DSP (Digital Signal Processor) processor), LSI (Large Scale Integrated Circuits) including microcontrollers Integrated circuits such as RFID tags and semiconductor display devices Any and all semiconductor devices that can be used as memory devices, such as In addition, semiconductor display devices include liquid crystal display devices and organic light emitting diode (OLED) devices. Light-emitting devices with light-emitting elements in each pixel, electronic paper, DMD (Digital Microscope) mirror device), PDP (Plasma Display Panel) ), FED (Field Emission Display), etc., which use semiconductor films This category includes semiconductor display devices that have circuit elements in their drive circuits.

[0036] (Embodiment 1) A memory device according to one embodiment of the present invention includes a memory element capable of storing 1-bit data. FIG. 1 shows an example of a circuit diagram of a memory element included in a memory device of the present invention. The storage element 100 shown in FIG. 1 is a first circuit that inverts the phase of an input signal and outputs the inverted signal. The first phase inverter 101, the second phase inverter 102, the switching element 103, and the The switching element 104, the capacitance element 105, and the capacitance switching element 106 are At least have.

[0037] A signal IN containing data input to the storage element 100 is input via a switching element 103. The signal is fed to the input terminal of the first phase inverter 101. The signal is fed to the output terminal of the first phase inverter 101. The terminal is connected to the input terminal of the second phase inverter 102. The output terminal of the second phase inverter 102 is connected to the input terminal of the first phase inverter 101 via the switching element 104. The output terminal of the first phase inverter 101 or the output terminal of the second phase inverter 102 is connected to the The potential of the input terminal of 02 is output as a signal OUT to a memory element in the subsequent stage or to another circuit. do.

[0038] In FIG. 1, inverters are used as the first phase inverter 101 and the second phase inverter 102. 101 or the second phase inversion element 102. As 02, in addition to an inverter, a clocked inverter can also be used.

[0039] The capacitance element 105 can store the data of the signal IN input to the storage element 100 as needed. The memory is connected via the switching element 103 and the capacitance switching element 106 so that the memory can be It is connected to the input terminal of the element 100, that is, the node to which the potential of the signal IN is applied. Specifically, the capacitance element 105 is a capacitor having a dielectric between a pair of electrodes. One electrode is connected to the input terminal of the first phase inverter 101 via the capacitance switching element 106. The other electrode is connected to a fixed potential such as a low-level power supply potential VSS or ground. is connected to the given node.

[0040] The capacitor-switching element 106 has a channel formation region made of a highly purified oxide semiconductor. The transistors used are in the range

[0041] The memory element 100 may include a diode, a resistor, an inductor, or the like as needed. Other circuit elements may also be included.

[0042] Next, a more specific example of a circuit diagram of the memory element shown in FIG. 1 is shown in FIG. The memory element 100 includes a first phase inverter 101, a second phase inverter 102, and a switch. A switching element 103, a switching element 104, a capacitance element 105, and a capacitance switch The connection configuration of these circuit elements is the same as in FIG.

[0043] In FIG. 2, the first phase inverter 101 is a p-channel inverter whose gate electrodes are connected to each other. The n-channel transistor 107 and the n-channel transistor 108 are connected to a high-level A first node is supplied with a power supply potential VDD, and a second node is supplied with a low-level power supply potential VSS. The two nodes are connected in series. The source electrode of the transistor 107 is connected to a first node to which a power supply potential VDD is applied, The source electrode of the n-channel transistor 108 is connected to a second node to which a power supply potential VSS is applied. The drain electrode of the p-channel transistor 107 and the The drain electrodes of the transistors 108 are connected to each other. The potential can be regarded as the potential of the output terminal of the first phase inverter 101. The gate electrode of the n-channel transistor 107 and the gate electrode of the n-channel transistor 108 The potential of the output electrode can be regarded as the potential of the input terminal of the first phase inverter 101 .

[0044] In addition, in FIG. 2, the second phase inversion element 102 has p-channel MOSFETs whose gate electrodes are connected to each other. A high-level power supply is connected between the n-channel transistor 109 and the n-channel transistor 110. A first node is supplied with a potential VDD, and a second node is supplied with a low-level power supply potential VSS. Specifically, the p-channel transistor has a configuration in which the nodes are connected in series. The source electrode of the transistor 109 is connected to a first node to which a power supply potential VDD is applied, and The source electrode of the channel type transistor 110 is connected to a second node to which a power supply potential VSS is applied. The drain electrode of the p-channel transistor 109 and the The drain electrodes of the transistors 110 and 111 are connected to each other. The potential can be regarded as the potential of the output terminal of the second phase inverter 102. The gate electrode of the n-channel transistor 109 and the gate of the n-channel transistor 110 The potential of the electrode can be regarded as the potential of the input terminal of the second phase inversion element 102 .

[0045] FIG. 2 illustrates a case where a transistor is used as the switching element 103. The transistor is switched on by a signal Sig1 applied to its gate electrode. In addition, when a transistor is used as the switching element 104, The transistor is switched on by a signal Sig2 applied to its gate electrode. The switching is controlled.

[0046] In FIG. 2, the switching element 103 and the switching element 104 are transistors. Although a configuration having only one transistor is shown, the present invention is not limited to this configuration. In one embodiment, the switching element 103 or the switching element 104 is a transistor. The switching element 103 or the switching element 104 may have a plurality of switching elements. In the case where a plurality of transistors functioning as switching elements are provided, the plurality of transistors The resistors may be connected in parallel, in series, or in both series and parallel. They may also be combined and connected.

[0047] 2, the capacitor-switching element 106 is formed by using an oxide semiconductor in a channel formation region. The transistor has a gate electrode provided with The switching is controlled by the signal Sig3. Since the transistor has a highly purified oxide semiconductor in a channel formation region, The current is significantly lower as mentioned above.

[0048] In FIG. 2, the capacitance switching element 106 has only one transistor. However, the present invention is not limited to this configuration. The switching element 106 may have a plurality of transistors. When the transistor 06 has a plurality of transistors functioning as switching elements, The transistors may be connected in parallel or in series. The parallel connection may be combined.

[0049] In this specification, the state in which transistors are connected in series means that the first transistor Only one of the source and drain electrodes of the first transistor is connected to the source of the second transistor. This means that the transistor is connected to only one of the two electrodes. The state in which the transistors are connected in parallel is when the source electrode and drain electrode of the first transistor are One of the electrodes is connected to either the source or drain electrode of the second transistor. the other of the source electrode and the drain electrode of the first transistor is connected to the second transistor This means that the other of the source electrode and drain electrode is connected to the other of the source electrode and drain electrode.

[0050] In one aspect of the present invention, at least the capacitance switching element 106 is switched. The transistor used as a switching element uses a highly purified oxide semiconductor as a channel Therefore, the first phase inverter 101 and the second phase inverter 102 are 02, the transistor used in the switching element 103 or the switching element 104 The material may be amorphous, microcrystalline, polycrystalline, or single-crystalline silicon other than an oxide semiconductor. A semiconductor such as germanium can be used for the transistor. A semiconductor film or a bulk semiconductor substrate may be used. If it is possible to fabricate p-channel transistors using a film, all of the memory elements The process can also be simplified by using an oxide semiconductor film for the active layer of the transistor.

[0051] In this specification, connection means electrical connection, and a current, a voltage, or a potential Therefore, the connected state corresponds to the state in which the signal is directly connected. It does not necessarily refer to the state of being connected, but rather to the state in which a current, voltage, or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes situations where the connection is indirectly made via a direct connection.

[0052] Also, when components that are independent on the circuit diagram are shown as being connected to each other, However, in reality, for example, when a part of the wiring also functions as an electrode, However, in some cases, a component simply combines the functions of multiple components. In this case, even when one conductive film has the functions of multiple components, it is still within the scope of the invention. Include in the category.

[0053] The source electrode and the drain electrode of the transistor are connected to each other. The name changes depending on the difference in potential applied to the electrodes. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the The electrode that is connected to the drain is called the drain electrode. The electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In this specification, for convenience, it is assumed that the source electrode and the drain electrode are fixed. However, in reality, the connection relationship of the transistors is explained in accordance with the above potential relationship. This means that the names of the source and drain electrodes are interchangeable.

[0054] Next, an example of the operation of the memory element shown in FIG. 1 will be described.

[0055] First, when writing data, the switching element 103 is turned on, and the switching element The switching element 104 is turned off, and the switching element 106 for capacitance is turned off. By applying a power supply potential VDD to the first node and a power supply potential VSS to the second node, the first node and the second node are connected to each other. A power supply voltage is applied between the nodes 2. The potential of the signal IN given to the memory element 100 is is supplied to the input terminal of the first phase inversion element 101 via the switching element 103. The output terminal of the first phase inverter 101 has a potential that is the inverse of the phase of the signal IN. Then, the switching element 104 is turned on, and the input terminal of the first phase inversion element 101 and the second By connecting the output terminal of the phase inverter 102 to the output terminal of the first phase inverter 101, the Data is written to the phase inverter 102.

[0056] Next, the input data is held by the first phase inverter 101 and the second phase inverter When the switching element 102 is used, the switching element 104 is turned on, and the capacitance switching element 10 The switching element 103 is turned off while the switching element 6 is kept off. By turning off 103, the input data is transmitted to the first phase inversion element 101 and the second phase inversion element 102. The phase is maintained by the phase inversion element 102. At this time, the power supply potential VDD is applied to the first node. By applying the power supply potential VSS to the second node, a voltage is applied between the first node and the second node. The source voltage remains applied.

[0057] The potential of the output terminal of the first phase inverter 101 is The data held by the second phase inverter 102 is reflected. By reading the potential, data can be read from the memory element 100.

[0058] In order to reduce power consumption when data is held, the input data is held as follows: When the capacitance element 105 is used, first, the switching element 103 is turned off, and then the switching element 104 is turned on. The element 104 is turned on, and the capacitance switching element 106 is turned on. The first phase inverter 101 and the second phase inverter 102 are connected via the switching element 106. As a result, an amount of charge corresponding to the value of the stored data is accumulated in the capacitor element 105. Then, data is written to the capacitor 105. When data is stored in the capacitor 105, After that, the capacitance switching element 106 is turned off, and the data stored in the capacitance element 105 is After the capacitance switching element 106 is turned off, the first node By applying, for example, a power supply potential VSS to the first node and the second node to make them equal potentials, The application of the power supply voltage between the first node and the second node is stopped. After this, the switching element 104 may be turned off.

[0059] In this way, when input data is held in the capacitor 105, the first node Since there is no need to apply a power supply voltage between the first node and the second node, the first phase inversion element 101 a p-channel transistor 107 and an n-channel transistor 108, or The second phase inversion element 102 has a p-channel transistor 109 and an n-channel transistor 108. The off-state current flowing between the first node and the second node through the transistor 110 is limited. Therefore, the off-state current of the memory element when data is held can be reduced to almost 0. This can significantly reduce the power consumption caused by the memory device, and further, the semiconductor device using the memory device. This makes it possible to keep the power consumption of the entire device low.

[0060] The transistor used in the capacitance switching element 106 is a highly purified Since an oxide semiconductor is used in the channel formation region, the off-state current density is 100 zA / μm or less, preferably 10 zA / μm or less, and more preferably 1 zA / μm or less. Therefore, a transistor using a highly purified oxide semiconductor film as an active layer can be The off-state current is significantly lower than that of a transistor using crystalline silicon. As a result, when the capacitance switching element 106 using the transistor is turned off, the capacitance element The charge stored in 105 is hardly discharged, so the data is retained.

[0061] When reading out data stored in the capacitance element 105, the switching element 10 Then, the power supply potential VDD is again applied to the first node, and the second node is By providing a power supply potential VSS, a power supply voltage is applied between the first node and the second node. Then, by turning on the capacitance switching element 106, the potential reflecting the data is The signal OUT having the value .theta.

[0062] Next, in the circuit shown in FIG. 2, the timing when the supply of the power supply potential VDD is not stopped is An example of the timing chart is shown in Figure 24. When the signal Sig1 goes low, the signal Sig2 goes high. When the signal IN is turned off, a feedback loop is created and the state is maintained. When the signal Sig1 goes high again and the signal Sig2 goes low, the signal I N is input and output via the first phase inversion element 101. At this time, the signal Sig3 is -level.

[0063] FIG. 25 is a timing chart showing a case where the supply of the power supply potential VDD of the circuit of FIG. 2 is stopped. This is an example. When the signal Sig1 goes low and the signal Sig2 goes high, This cuts off the signal IN, creating a feedback loop and maintaining the state. By setting the signal 3 to a high level, storage is performed in the capacitance element 105 (high level in FIG. 25). After that, even if the supply of the power supply potential VDD is stopped, the potential of the capacitance element 105 is maintained. After that, when the power supply potential VDD is supplied and the signal Sig3 becomes high level again, the capacitance The potential of the element 105 is output via the first phase inversion element 101 (low level in FIG. 25). (L).

[0064] (Embodiment 2) In this embodiment mode, another example of a memory element included in a memory device of the present invention will be described. FIG. 3 shows an example of a circuit diagram of a memory element of this embodiment.

[0065] The storage element 200 shown in FIG. 3 is a first phase inverting element that inverts the phase of an input signal and outputs it. a switching element 201, a second phase inversion element 202, and a third phase inversion element 207; A switching element 203, a switching element 204, a switching element 208, and a switching element The capacitor element 209, the capacitor element 205, and the capacitor switching element 206 are included. do.

[0066] A signal IN containing data input to the storage element 200 is input via a switching element 203. The signal is fed to the input terminal of the first phase inverter 201. The signal is fed to the output terminal of the first phase inverter 201. The terminal is connected to the input terminal of the second phase inverter 202. The output terminal of the second phase inverter 202 is connected to the input terminal of the first phase inverter 201 via a switching element 204. The output terminal of the first phase inverter 201 or the output terminal of the second phase inverter 202 is connected to the The potential of the input terminal of 02 is transmitted to the subsequent storage stage as a signal OUT via a switching element 208. The signal is output to a memory element or other circuit.

[0067] The capacitance element 205 can store the data of the signal IN input to the storage element 200 as needed. The input terminal of the storage element 200, i.e., That is, it is connected to a node to which the potential of the signal IN is applied. , a capacitor having a dielectric between a pair of electrodes, one of which is a capacitance switch The other electrode is connected to a node to which the potential of the signal IN is applied via a switching element 206. Connect to a node that has a fixed potential such as a low-level power supply potential VSS or ground. It has been done.

[0068] The one electrode of the capacitance element 205 is connected to the input terminal of the third phase inversion element 207. The potential of the output terminal of the third phase inverter 207 is changed via the switching element 209. The signal is then output as a signal OUT to a subsequent storage element or other circuit.

[0069] In FIG. 3, the first phase inverter 201, the second phase inverter 202, and the third phase inverter 203 are shown. Although an example in which an inverter is used as the inverting element 207 is shown, the first phase inverting element 201 , the second phase inversion element 202 or the third phase inversion element 207 may be an inverter. , a clocked inverter can also be used.

[0070] The capacitor-switching element 206 has a channel formation region made of a highly purified oxide semiconductor. The transistors used are in the range

[0071] The storage element 200 may include a diode, a resistor, an inductor, or the like, as needed. Other circuit elements may also be included.

[0072] Next, a more specific example of a circuit diagram of the memory element shown in FIG. 3 is shown in FIG. The memory element 200 includes a first phase inverter 201, a second phase inverter 202, a third phase inverter 203, and a Phase reversal element 207, switching element 203, switching element 204, switching element element 208, switching element 209, capacitance element 205, and capacitance switching element 206. The connection configuration of these circuit elements is the same as that shown in FIG.

[0073] In FIG. 4, the first phase inversion element 201 is a p-channel element whose gate electrodes are connected to each other. A high-level voltage is applied to the n-channel transistor 210 and the n-channel transistor 211. A first node is supplied with a power supply potential VDD, and a second node is supplied with a low-level power supply potential VSS. The two nodes are connected in series. The source electrode of the transistor 210 is connected to a first node to which a power supply potential VDD is applied, The source electrode of the n-channel transistor 211 is connected to a second node to which a power supply potential VSS is applied. The drain electrode of the p-channel transistor 210 and the The drain electrodes of the transistors 211 and 212 are connected to each other. The potential can be regarded as the potential of the output terminal of the first phase inverter 201. The gate electrode of the n-channel transistor 210 and the gate electrode of the n-channel transistor 211 The potential of the output electrode can be regarded as the potential of the input terminal of the first phase inverter 201 .

[0074] In addition, in FIG. 4, the second phase inversion element 202 has p-channel MOSFETs whose gate electrodes are connected to each other. A high-level power supply is connected between the n-channel transistor 212 and the n-channel transistor 213. A first node is supplied with a potential VDD, and a second node is supplied with a low-level power supply potential VSS. Specifically, the p-channel transistor has a configuration in which the nodes are connected in series. The source electrode of the transistor 212 is connected to a first node to which a power supply potential VDD is applied, and The source electrode of the channel type transistor 213 is connected to the second node to which the power supply potential VSS is applied. Also, the drain electrode of the p-channel transistor 212 and the The drain electrodes of the two drain electrodes are connected to each other. The potential can be regarded as the potential of the output terminal of the second phase inversion element 202. The gate electrode of the n-channel transistor 212 and the gate of the n-channel transistor 213 The potential of the electrode can be regarded as the potential of the input terminal of the second phase inversion element 202 .

[0075] In addition, in FIG. 4, the third phase inversion element 207 has p-channel MOSFETs whose gate electrodes are connected to each other. A high-level power supply is connected between the n-channel transistor 214 and the n-channel transistor 215. A third node is supplied with a potential VDD, and a fourth node is supplied with a low-level power supply potential VSS. Specifically, the p-channel transistor has a configuration in which the nodes are connected in series. The source electrode of the transistor 214 is connected to a third node to which a power supply potential VDD is applied, and The source electrode of the channel type transistor 215 is connected to a fourth node to which a power supply potential VSS is applied. The drain electrode of the p-channel transistor 214 and the drain electrode of the n-channel transistor 215 are connected to each other. The drain electrodes of the two drain electrodes are connected to each other. The potential can be regarded as the potential of the output terminal of the third phase inverter 207. The gate electrode of the n-channel transistor 214 and the gate of the n-channel transistor 215 The potential of the electrode can be regarded as the potential of the input terminal of the third phase inversion element 207 .

[0076] The first node and the third node may be electrically connected to each other. The second node and the fourth node may also be electrically connected to each other. That's fine.

[0077] FIG. 4 illustrates a case where a transistor is used as the switching element 203. The transistor is switched on by a signal Sig1 applied to its gate electrode. In addition, when a transistor is used as the switching element 204, The transistor is switched on by a signal Sig2 applied to its gate electrode. In addition, a transistor is used as the switching element 209. The transistor is turned on by a signal Sig4 applied to its gate electrode. The switching is controlled by the

[0078] In FIG. 4, the switching element 203, the switching element 204, the switching element 209 shows a configuration having only one transistor each, but the present invention does not use this configuration. In one embodiment of the present invention, the switching element 203 and the switching element 2 04 or the switching element 209 may have a plurality of transistors. The switching element 203, the switching element 204, or the switching element 209 is When a plurality of transistors functioning as a switching element are provided, the plurality of transistors may be connected in parallel, in series, or in a combination of series and parallel. It may be connected to the network.

[0079] 4, the capacitor-switching element 206 is formed by using an oxide semiconductor as a channel forming region. The transistor has a gate electrode provided with The switching is controlled by the signal Sig3. Since the transistor has a highly purified oxide semiconductor in a channel formation region, The current is significantly lower as mentioned above.

[0080] In FIG. 4, the capacitance switching element 206 has only one transistor. However, the present invention is not limited to this configuration. The switching element 206 may have a plurality of transistors. When the transistor 06 has a plurality of transistors functioning as switching elements, The transistors may be connected in parallel or in series. The parallel connection may be combined.

[0081] In one aspect of the present invention, at least the capacitance switching element 206 is switched. The transistor used as a switching element uses a highly purified oxide semiconductor as a channel Therefore, the first phase inverter 201 and the second phase inverter 202 are 02, a third phase inversion element 207, a switching element 203, a switching element 204, The transistors used for the switching elements 208 and 209 are made of oxide Non-semiconductors, amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or germanium The transistor may be formed using a thin semiconductor film. A p-type semiconductor substrate using an oxide semiconductor film may be used. If it is possible to fabricate a channel type transistor, all the transistors in the memory element can be fabricated. The process can be simplified by using an oxide semiconductor film for the active layer of the capacitor.

[0082] Next, an example of the operation of the memory element shown in FIG. 3 will be described.

[0083] First, when writing data, the switching element 203 is turned on, and the switching element 204 is off, switching element 208 is off, switching element 209 is off, for capacitance The switching element 206 is turned on. Then, the power supply potential VDD is applied to the first node. By applying the power supply potential VSS to the second node, a power supply voltage is applied between the first node and the second node. The potential of the signal IN given to the memory element 200 is 3 to the input terminal of the first phase inverter 201. The output terminal of 201 has a potential that is the inverse of the phase of the signal IN. 204 is turned on, and the input terminal of the first phase inverter 201 and the input terminal of the second phase inverter 202 are connected. By connecting the output terminals, the first phase inverter 201 and the second phase inverter 202 Data is written to

[0084] When writing data, the capacitance switching element 206 is used to When the amount of charge corresponding to the value of the data is accumulated in the capacitance element 205, the capacitance element 205 also The data is written.

[0085] When writing data, a power supply voltage is applied between the third node and the fourth node. Therefore, for example, the third node and the fourth node do not need to be connected to a power supply potential VS Give S and make it an equipotential.

[0086] Next, the input data is held by the first phase inverter 201 and the second phase inverter When the switching element 202 is used, the switching element 204 is turned on and the switching element 208 is turned off. With the switching element 209 turned off, the switching element 203 is turned off, and the capacitance By turning off the switching element 203, The input data is converted into a phase by a first phase inverter 201 and a second phase inverter 202. At this time, the power supply potential VDD is applied to the first node, and the power supply potential VDD is applied to the second node. By applying VSS, the power supply voltage is applied between the first node and the second node. Maintain.

[0087] Moreover, by turning off the capacitance switching element 206, the data written to the capacitance element 205 is The data will also be retained.

[0088] The potential of the output terminal of the first phase inverter 201 is and the data held by the second phase inverter 202 are reflected. By turning on the switching element 208 and reading the potential, the data is stored in the memory element 20 It can be read from 0.

[0089] In order to reduce power consumption when data is held, the input data is held as follows: When the capacitance element 205 is used alone, a power supply, for example, is connected to the first node and the second node. By applying the potential VSS to make them equal potentials, the power supply voltage between the first node and the second node is applied. When the application of the power supply voltage between the first node and the second node is stopped, the first position The data held in the phase inversion element 201 and the second phase inversion element 202 is erased. However, the data written in the capacitor element 205 is retained as is.

[0090] In this way, when input data is held in the capacitor element 205, the first node Since there is no need to apply a power supply voltage between the first node and the second node, the first phase inversion element 201 a p-channel transistor 210 and an n-channel transistor 211, or The second phase inversion element 202 has a p-channel transistor 212 and an n-channel transistor 213. The off-state current flowing between the first node and the second node through the transistor 213 is limited to Therefore, the current flowing through the memory element during data retention can be reduced to 0. The power consumption can be significantly reduced, and the memory device and the semiconductor device using the memory device This makes it possible to reduce the overall power consumption.

[0091] When input data is stored in the capacitor 205, the third node and the fourth node Therefore, it is not necessary to apply a power supply voltage between the nodes of the third phase inversion element 207. The third transistor 214 is connected to the third power supply 211 via a p-channel transistor 214 and an n-channel transistor 215. The off-state current flowing between the first node and the fourth node can be reduced to as close to zero as possible. As a result, power consumption due to the off-state current of the storage element during data retention can be significantly reduced. Therefore, the power consumption of the memory device, and in turn of the entire semiconductor device using the memory device, can be reduced. This becomes possible.

[0092] The transistor used in the capacitance switching element 206 is a highly purified Since an oxide semiconductor is used in the channel formation region, the off-state current density is 100 zA / μm or less, preferably 10 zA / μm or less, and more preferably 1 zA / μm or less. Therefore, a transistor using a highly purified oxide semiconductor film as an active layer can be The off-state current is significantly lower than that of a transistor using crystalline silicon. As a result, when the capacitance switching element 206 using the transistor is turned off, the capacitance element The charge stored in the element 205 is hardly discharged, so the data is retained.

[0093] When reading out data stored in the capacitor element 205, the power supply voltage is applied to the third node. By applying a power supply potential VDD to the third node and a power supply potential VSS to the fourth node, A power supply voltage is applied between the nodes. A power supply voltage is applied between the third node and the fourth node. The output terminal of the third phase inverter 207 receives a potential whose phase is inverted from the potential at the input terminal. The input terminal of the third phase inverter 207 is supplied with the voltage stored in the capacitor 205. The potential at the output terminal is given a value that corresponds to the amount of charge stored in the Therefore, by turning on the switching element 209, the data is reflected. The signal OUT having the potential can be read out from the storage element 200.

[0094] FIG. 26 is a timing chart showing the case where the supply of the power supply potential VDD to the circuit of FIG. 4 is not stopped. For example, when the signal Sig1 goes low and the signal Sig2 goes high, Therefore, the signal IN is blocked, a feedback loop is created, and the state can be maintained. When signal Sig1 goes high and signal Sig2 goes low, signal IN is input and the first phase The signal is output via the inverter 201. At this time, the signals Sig3 and Sig4 are at a low level. and the signal Sig5 is at a high level.

[0095] FIG. 27 is a timing chart showing a case where the supply of the power supply potential VDD of the circuit of FIG. 4 is stopped. This is an example. When the signal Sig1 goes low and the signal Sig2 goes high, This cuts off the signal IN, creating a feedback loop and maintaining the state. By setting the level to high, the capacitance element 205 stores the signal (low level in FIG. 27). After that, even if the supply of the power supply potential VDD is stopped, the potential of the capacitive element 205 is maintained. Thereafter, the power supply potential VDD is supplied, the signal Sig5 is at a low level, and the signal Sig3 is at a low level. When the signal Sig4 goes high, the potential of the capacitor 205 goes high. 27. The signal is output via 207 (high level in FIG. 27).

[0096] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0097] (Embodiment 3) In this embodiment mode, another example of a memory element included in a memory device of the present invention will be described. FIG. 5 shows an example of a circuit diagram of a memory element of this embodiment.

[0098] The storage element 300 shown in FIG. 5 is a first phase inverting element that inverts the phase of an input signal and outputs it. A phase inversion element 301, a second phase inversion element 302, a switching element 303, and a switching a switching element 304, a capacitance element 305, a capacitance switching element 306, and a capacitance element 307 and a capacitance switching element 308.

[0099] A signal IN containing data input to the storage element 300 is input via a switching element 303. The signal is fed to the input terminal of the first phase inverter 301. The signal is fed to the output terminal of the first phase inverter 301. The terminal is connected to the input terminal of the second phase inverter 302. The output terminal of the second phase inverter 302 is connected to the input terminal of the first phase inverter 301 via the switching element 304. The output terminal of the first phase inverter 301 or the output terminal of the second phase inverter 302 is connected to the The potential of the input terminal of 02 is output as a signal OUT to a memory element in the subsequent stage or to another circuit. do.

[0100] The capacitance element 305 can store the data of the signal IN input to the storage element 300 as needed. The memory is connected via the switching element 303 and the capacitance switching element 306 so that the memory can be It is connected to the input terminal of the element 300, that is, the node to which the potential of the signal IN is applied. Specifically, the capacitance element 305 is a capacitor having a dielectric between a pair of electrodes. One electrode is connected to the input terminal of the first phase inverter 301 via the capacitance switching element 306. The other electrode is connected to a fixed potential such as a low-level power supply potential VSS or ground. is connected to the given node.

[0101] The capacitor 307, like the capacitor 305, decodes the signal IN input to the storage element 300. The switching element 303, the first phase inversion element 304, and the 01 and the capacitance switching element 308, the input terminal of the storage element 300, i.e. The capacitor 307 is connected to a node to which the potential of the signal IN is applied. A capacitor having a dielectric between a pair of electrodes, one of which is a capacitance switching The other electrode is connected to the output terminal of the first phase inversion element 301 via the element 308. connected to a node to which a fixed potential such as a negative-level power supply potential VSS or ground is applied. It is being done.

[0102] In FIG. 5, the first phase inverter 301 and the second phase inverter 302 are inverters. Although an example using a phase inverter 301 or a phase inverter 302 is shown, As 2, in addition to an inverter, a clocked inverter can also be used.

[0103] The capacitance switching element 306 and the capacitance switching element 308 are made of highly purified silicon. The present invention uses a transistor having a channel formation region made of an oxide semiconductor.

[0104] The storage element 300 may include a diode, a resistor, an inductor, or the like, as needed. Other circuit elements may also be included.

[0105] Next, a more specific example of a circuit diagram of the memory element shown in FIG. 5 is shown in FIG. The storage element 300 includes a first phase inverter 301, a second phase inverter 302, a switch a switching element 303, a switching element 304, a capacitance element 305, and a capacitance switching element 3 306, a capacitance element 307, and a capacitance switching element 308. The connection configuration of the circuit elements is the same as in FIG.

[0106] 6, the first phase inverter 301 is a p-channel inverter whose gate electrodes are connected to each other. n-channel transistor 309 and n-channel transistor 310 are connected to a high level A first node is supplied with a power supply potential VDD, and a second node is supplied with a low-level power supply potential VSS. The two nodes are connected in series. The source electrode of the transistor 309 is connected to a first node to which a power supply potential VDD is applied, The source electrode of the n-channel transistor 310 is connected to a second node to which a power supply potential VSS is applied. Also, the drain electrode of the p-channel transistor 309 and the The drain electrodes of the transistors 310 are connected to each other. The potential can be regarded as the potential of the output terminal of the first phase inverter 301. The gate electrode of the n-channel transistor 309 and the gate electrode of the n-channel transistor 310 The potential of the output electrode can be regarded as the potential of the input terminal of first phase inverter 301 .

[0107] 6, the second phase inversion element 302 has p-channel MOSFETs whose gate electrodes are connected to each other. A high-level power supply is connected between the n-channel transistor 311 and the n-channel transistor 312. A first node is supplied with a potential VDD, and a second node is supplied with a low-level power supply potential VSS. Specifically, the p-channel transistor has a configuration in which the nodes are connected in series. The source electrode of the transistor 311 is connected to a first node to which a power supply potential VDD is applied, and The source electrode of the channel type transistor 312 is connected to a second node to which a power supply potential VSS is applied. The drain electrode of the p-channel transistor 311 is connected to the The drain electrodes of the two drain electrodes are connected to each other. The potential can be regarded as the potential of the output terminal of the second phase inverter 302. The gate electrode of the n-channel transistor 311 and the gate of the n-channel transistor 312 The potential of the electrode can be regarded as the potential of the input terminal of the second phase inversion element 302 .

[0108] FIG. 6 illustrates a case where a transistor is used as the switching element 303. The transistor is switched on by a signal Sig1 applied to its gate electrode. In addition, when a transistor is used as the switching element 304, The transistor is switched on by a signal Sig2 applied to its gate electrode. The switching is controlled.

[0109] In FIG. 6, the switching element 303 and the switching element 304 are transistors. Although a configuration having only one register is shown, the present invention is not limited to this configuration. In one embodiment, the switching element 303 or the switching element 304 is a transistor The switching element 303 or the switching element 304 may be a switching element. When a plurality of transistors functioning as switching elements are provided, the plurality of transistors The power supplies may be connected in parallel, in series, or in a combination of series and parallel. They may be combined and connected.

[0110] 6, the capacitor-switching element 306 is formed by using an oxide semiconductor in a channel formation region. The transistor has a gate electrode provided with The switching is controlled by the signal Sig3. Since the transistor has a highly purified oxide semiconductor in a channel formation region, The current is significantly lower as mentioned above.

[0111] 6, the capacitor-switching element 308 is formed by using an oxide semiconductor as a channel forming region. The transistor has a gate electrode provided with The switching is controlled by the signal Sig4. Since the transistor has a highly purified oxide semiconductor in a channel formation region, The current is significantly lower as mentioned above.

[0112] 6, the capacitance switching element 306 or the capacitance switching element 308 Although the present invention is not limited to a single transistor, In one embodiment of the present invention, the capacitance switching element 306 or the capacitance switching element 3 The capacitor switching element 306 or the capacitor The switching element 308 has a plurality of transistors that function as switching elements. In this case, the plurality of transistors may be connected in parallel or in series. Alternatively, the circuits may be connected in series and parallel in combination.

[0113] In one embodiment of the present invention, at least the capacitance switching element 306 or the capacitance switching element In the switching element 308, a transistor used as a switching element is It is sufficient that the channel formation region contains a purified oxide semiconductor. An inverting element 301, a second phase inverting element 302, a switching element 303, a switching element The transistor used for the element 304 may be made of an amorphous, microcrystalline, polycrystalline, or Alternatively, a semiconductor such as single crystal silicon or germanium can be used. The transistor may be made of a thin semiconductor film or a bulk semiconductor substrate. A p-channel transistor can be manufactured using an oxide semiconductor film. If possible, use oxide semiconductor films for the active layers of all transistors in the memory element, and The process can also be simplified.

[0114] Next, an example of the operation of the memory element shown in FIG. 5 or FIG. 6 will be described.

[0115] First, when writing data, the switching element 303 is turned on, and the switching element 304 is off, the capacitance switching element 306 is off, and the capacitance switching element 308 is Then, the power supply potential VDD is applied to the first node, and the power supply potential V By applying SS, the power supply voltage is applied between the first node and the second node. The potential of the signal IN given to 300 is inverted through a switching element 303. is applied to the input terminal of the first phase inverter 301, the output terminal of the first phase inverter 301 is the signal Then, the switching element 304 is turned on, and the first The input terminal of the phase inverter 301 is connected to the output terminal of the second phase inverter 302. Then, data is written to the first phase inverter 301 and the second phase inverter 302 .

[0116] Next, the input data is held by the first phase inverter 301 and the second phase inverter When the switching element 302 is used, the switching element 304 is turned on, and the capacitance switching element 30 6 is turned off, and the capacitance switching element 308 is turned off. By turning off the switching element 303, the input data , is held by the first phase inverter 301 and the second phase inverter 302. A power supply potential VDD is applied to the first node, and a power supply potential VSS is applied to the second node. The state in which the power supply voltage is applied between the first node and the second node is maintained.

[0117] The potential of the output terminal of the first phase inverter 301 is and the data held by the second phase inverter 302 are reflected. By reading the potential, data can be read from the memory element 300.

[0118] In order to reduce power consumption when data is held, the input data is held as follows: When the capacitance element 305 and the capacitance element 307 are used, the switching element 303 is turned off. The switching element 304 is turned on, the capacitance switching element 306 is turned on, and the capacitance switch Then, the first switching element 308 is turned on via the capacitance switching element 306. The phase inverter 301 and the second phase inverter 302 are connected to each other. The amount of charge stored in the capacitor 305 is used to write data to the capacitor 305. Also, the first phase inverter 30 The amount of charge corresponding to the data value held in the first and second phase inversion elements 302 is By storing the charge in the capacitor 307, data is written to the capacitor 307. The voltage between the pair of electrodes of the capacitor 305 and the voltage between the pair of electrodes of the capacitor 307 are The voltage between them has the opposite polarity.

[0119] After the data is stored in the capacitor element 305, the capacitor switching element 306 is turned off. In this way, the data stored in the capacitor 305 is held. After the value is stored, the capacitance switching element 308 is turned off, and the capacitance element 307 The stored data is retained. After the node 308 is turned off, the first node and the second node are connected to, for example, the power supply potential VSS. By applying this voltage to the first node and the second node to create an equipotential, the application of the power supply voltage between the first node and the second node is stopped. .

[0120] In this way, input data is held in the capacitors 305 and 307. In this case, there is no need to apply a power supply voltage between the first node and the second node. The phase inversion element 301 has a p-channel transistor 309 and an n-channel transistor The p-channel transistor 310 of the second phase inversion element 302 or the p-channel transistor 311 of the second phase inversion element 302 and a current flows between the first node and the second node through an n-channel transistor 312. Therefore, the off-state current of the memory element during data retention can be reduced to as close to zero as possible. The power consumption caused by the off-state current can be significantly reduced, and the memory device, It is possible to reduce the power consumption of the entire semiconductor device using the above.

[0121] In addition, the capacitor switching element 306 and the capacitor switching element 308 are used The transistor uses a highly purified oxide semiconductor for a channel formation region, The off-state current density is 100 zA / μm or less, preferably 10 zA / μm or less, and more preferably Therefore, the highly purified oxide semiconductor film can be obtained. The transistor used as the active layer has an off-state current of crystalline silicon. As a result, the capacitance switching When the element 306 is off, the charge stored in the capacitance element 305 is hardly discharged. The capacitance switching element 308 using the transistor is turned on. When the voltage is off, the charge stored in the capacitor element 307 is hardly discharged, and the data is retained. do.

[0122] When reading out data stored in the capacitors 305 and 307, By applying a power supply potential VDD to the first node and a power supply potential VSS to the second node, A power supply voltage is applied between the first node and the second node. When a power supply voltage is applied between the first node and the second node, The output terminal of the phase inversion element 301 is supplied with a potential whose phase is inverted from that of the input terminal. The input terminal of the first phase inverter 301 is connected to the capacitor 305. Since a potential corresponding to the amount of charge is given, the potential of the output terminal reflects the data. Moreover, by turning on the capacitance switching element 308, the charge stored in the capacitance element 305 is A potential corresponding to the amount of charge stored in the first phase inverter 301 is applied to the output terminal of the first phase inverter 301. Therefore, the signal OUT having a potential reflecting the data is read from the storage element 300. It can be seen.

[0123] FIG. 28 is a timing chart showing the case where the supply of the power supply potential VDD to the circuit of FIG. 6 is not stopped. For example, when the signal Sig1 goes low and the signal Sig2 goes high, Therefore, the signal IN is blocked, a feedback loop is created, and the state can be maintained. When signal Sig1 goes high and signal Sig2 goes low, signal IN is input and the first phase The signal is output via the inverter 301. At this time, the signals Sig3 and Sig4 are at a low level. Let's say.

[0124] FIG. 29 is a timing chart showing a case where the supply of the power supply potential VDD of the circuit of FIG. 6 is stopped. This is an example. When the signal Sig1 goes low and the signal Sig2 goes high, This cuts off the signal IN, creating a feedback loop and maintaining the state. 3. By setting the signal Sig4 to a high level, the capacitance elements 305 and 307 are written After that, even if the supply of the power supply potential VDD is stopped, the capacitance elements 305 and 306 remain unchanged. The potential of the capacitor 307 is maintained (in FIG. 29, the capacitor 305 is at a high level and the capacitor 307 is at a low level). After that, the power supply potential VDD is supplied, and the signals Sig3 and Sig4 are again high level. When the potential of the capacitor 305 reaches a low level, the potential of the capacitor 305 is output via the first phase inverter 301. , the potential of the capacitor element 307 is output (both are at low level in FIG. 29).

[0125] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0126] (Fourth embodiment) A semiconductor device according to one embodiment of the present invention includes a silicon transistor and an oxide semiconductor The silicon-based transistor is made of silicon wafer, S OI (Silicon on Insulator) substrate, silicon thin film on insulating surface, etc. It can be formed using the following.

[0127] The SOI substrate is, for example, a UNIBOND (registered trademark) substrate, represented by Smart Cut (registered trademark). trademark), ELTRAN (Epitaxial Layer Transfer) (registered trademark Marker), Dielectric Separation Method, PACE (Plasma Assisted Chemical Etching method, SIMOX (Separation by Impl It can be prepared by using the stimulated oxygen method or the like.

[0128] A silicon semiconductor film formed on a substrate having an insulating surface is crystallized by known techniques. Known crystallization methods include laser crystallization using laser light, and crystallization using a catalytic element. Alternatively, a crystallization method using a catalyst element and a laser crystallization method may be combined. In addition, when a substrate with excellent heat resistance such as quartz is used, Thermal crystallization using a thermal furnace, lamp annealing crystallization using infrared light, and catalytic element crystallization A crystallization method that combines a crystallization method using a high-temperature annealing method at about 950° C. and a crystallization method using a high-temperature annealing method at about 950° C. may also be used.

[0129] Furthermore, the semiconductor element manufactured by the above method can be mounted on a flexible substrate such as plastic. The semiconductor device may be formed by transferring the semiconductor device onto a substrate. For example, a metal oxide film is provided between the substrate and the semiconductor element, and the metal oxide film is crystallized. a method for separating and transferring a semiconductor element by weakening the substrate, and a method for forming an amorphous material containing hydrogen between a substrate and a semiconductor element; A silicon film is provided, and the amorphous silicon film is removed by irradiation with laser light or etching. A method for separating and transferring a semiconductor element from a substrate, a method for mechanically removing a substrate on which a semiconductor element is formed, The semiconductor element is then separated from the substrate and transferred by etching with a solution or gas. Methods etc.

[0130] In this embodiment, an SOI (Silicon on Insulator) substrate is used. After a transistor including silicon is manufactured, a transistor including an oxide semiconductor is manufactured. The structure of a semiconductor device and a manufacturing method thereof will be described using an example in which a semiconductor device is manufactured.

[0131] First, as shown in FIG. 7(A), the bond substrate 500 is cleaned, and then the surface of the bond substrate 500 is An insulating film 501 is formed on the surface.

[0132] A silicon single crystal semiconductor substrate can be used as the bond substrate 500. The bond substrate 500 is made of silicon having a strain in the crystal lattice, germanium with respect to silicon, and A semiconductor substrate such as silicon germanium doped with fluorine may also be used.

[0133] Note that the single crystal semiconductor substrate used for the bond substrate 500 has a crystal axis direction that is perpendicular to the substrate. It is desirable that the lattice defects are uniform, but it is also necessary to completely eliminate lattice defects such as point defects, line defects, and planar defects. It is not necessary for the crystal to be a perfect crystal.

[0134] The shape of the bond substrate 500 is not limited to a circular shape, and it may be processed into a shape other than a circular shape. For example, the shape of the base substrate 503 to be bonded later is generally rectangular, and Considering that the exposure area of ​​an exposure device such as a small projection exposure device is rectangular, the bond substrate 5 The shape of the bond substrate 500 may be processed so that it becomes rectangular. This can be done by cutting a commercially available circular single crystal semiconductor substrate.

[0135] The insulating film 501 may be a single insulating film or a laminate of multiple insulating films. The thickness of the insulating film 501 is determined by the thickness of the insulating film 501, so that the region containing impurities will be removed later. Taking this into consideration, it is preferable to set the thickness to 15 nm or more and 500 nm or less.

[0136] The insulating film 501 may be made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Bare film, germanium oxide, germanium nitride film, germanium oxynitride film, nitrided germanium oxide An insulating film containing silicon or germanium in its composition, such as a germanium film, can be used. Also, insulating films made of metal oxides such as aluminum oxide, tantalum oxide, and hafnium oxide. , insulating films made of metal nitrides such as aluminum nitride, and metal oxide films such as aluminum nitride films. insulating films made of metal oxynitrides, such as aluminum nitride oxide films; A velum may also be used.

[0137] In this embodiment, silicon oxide formed by thermally oxidizing the bond substrate 500 is An example is shown in which the insulating film 501 is used. Note that in FIG. 7A, the insulating film 501 is a bond substrate. The insulating film 501 is formed to cover the entire surface of the bond substrate 500. It is sufficient that the surface is formed on at least one side.

[0138] In this specification, an oxynitride is a compound having a composition in which oxygen is contained more than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It refers to a substance.

[0139] In addition, when the insulating film 501 is formed by thermally oxidizing the surface of the bond substrate 500, Oxidation is carried out using dry oxidation, which uses oxygen with a low moisture content, or using halide oxidation such as hydrogen chloride in an oxygen atmosphere. Thermal oxidation, which involves adding a gas containing hydrogen, can also be used. Pyrogenic oxidation produces water by heating high-purity water to over 100 degrees. The insulating film 501 may be formed by wet oxidation such as steam oxidation, which performs oxidation using a silicon dioxide gas.

[0140] The base substrate 503 is made of an alkali metal or alkaline earth metal, etc., to improve the reliability of the semiconductor device. When a substrate containing impurities that reduce the impurities is used, the substrate is formed after separation from the base substrate 503. At least a barrier film that can prevent the impurities from diffusing into the semiconductor film to be formed is provided. It is preferable that the insulating film 501 has at least one layer. The insulating film may be a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film. The insulating film used as the barrier film has a thickness of, for example, 15 nm to 30 nm. It is preferable that the barrier film is formed with a thickness of 0 nm. An insulating film with a lower nitrogen content than the barrier film, such as a silicon oxide film or a silicon oxynitride film, is formed. The thickness of the insulating film with a low nitrogen content may be set to 5 nm or more and 200 nm or less.

[0141] When silicon oxide is used as the insulating film 501, the insulating film 501 is made of silane and oxygen, TEOS (Tetra-Oxygen Sulfide). Using a mixture of tetraethoxysilane and oxygen, thermal CVD, plasma CVD, and atmospheric CV In this case, the insulating layer can be formed by a vapor deposition method such as bias ECRCVD. The surface of the insulating film 501 may be densified by oxygen plasma treatment. When used as 1, a mixture of silane and ammonia gas is used, and gas phase deposition such as plasma CVD is performed. It can be formed by the long method.

[0142] Silicon oxide, which is produced by chemical vapor deposition using organic silane gas, is used as the insulating film 50 As the organic silane gas, ethyl silicate (TEOS: chemical formula Si( OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylsilane Tylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (O MCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. A fluorine-containing compound can be used.

[0143] By using organic silane as the source gas, a smooth surface can be obtained at a process temperature of 350°C or less. In addition, a silicon oxide film having the above properties can be formed by the thermal CVD method at a heating temperature of 200°C or higher. LTO (low temperature oxide) is formed at temperatures below 500°C. For LTO formation, monosilane is used as the silicon source gas. (SiH4) or disilane (Si2H6), etc., are used as the oxygen source gas, and nitrogen dioxide ( NO2) can be used.

[0144] For example, the insulating film 501 made of a silicon oxide film is formed by using TEOS and O2 as source gases. In this case, the flow rate of TEOS is 15 sccm, the flow rate of O2 is 750 sccm, and the deposition pressure is 100 Pa. The film formation temperature is set to 300°C, the RF output is set to 300W, and the power supply frequency is set to 13.56MHz.

[0145] Note that a silicon oxide film formed using organic silane or a silicon nitride oxide film formed at low temperature is used. Insulating films formed at relatively low temperatures, such as those made of silicon dioxide, have many OH groups on their surfaces. By hydrogen bonding with the base substrate, silanol groups are formed, bonding the base substrate and insulating film at low temperatures. Finally, a covalent siloxane bond is formed between the base substrate and the insulating film. Therefore, the silicon oxide film formed using the above organic silane or the silicon oxide film formed at a relatively low temperature The insulating film such as LTO formed by the method has OH groups, which are used in Smart Cut etc. It can be said that this is more suitable for bonding at low temperatures than a thermal oxide film that does not exist or is very small.

[0146] The insulating film 501 is a film for forming a smooth and hydrophilic bonding surface on the surface of the bond substrate 500. Therefore, the average roughness Ra of the insulating film 501 is 0.7 nm or less, and more preferably 0. The thickness of the insulating film 501 is preferably 5 nm or more and 500 nm or less. More preferably, it should be 10 nm or more and 200 nm or less.

[0147] Next, as shown in FIG. 7(B), ions made of ions accelerated by an electric field are applied to the bond substrate 500. The beam is irradiated onto the bond substrate 500 through the insulating film 501 as shown by the arrows. An embrittlement layer 502 having microvoids is formed in a region at a certain depth from the surface of the substrate 500. For example, the embrittlement layer refers to a layer that is locally weakened by the disruption of the crystal structure. The state of the embrittlement layer differs depending on the means for forming the embrittlement layer. The area may also be weakened to some extent, but the weakened layer is the area that will be separated later and the surrounding layers. Refers to...

[0148] The depth of the region where the embrittlement layer 502 is formed depends on the acceleration energy of the ion beam and the ion beam The incident angle can be adjusted by adjusting the incident angle. A weakened layer 502 is formed. At the depth of the ion implantation, the bond substrate 500 is separated from the bond substrate 500. The thickness of the semiconductor film 504 to be formed is determined. The thickness can be from 50 nm to 500 nm, preferably from 50 nm to 200 nm. That's good.

[0149] Ions are implanted into the bond substrate 500 by an ion doping method that does not involve mass separation. However, the present invention is based on the ion separation method involving mass separation. An injection method may also be used.

[0150] When hydrogen (H2) is used as the source gas, the hydrogen gas is excited to generate H +, H2 + , H3 + to produce The ratio of ion species generated from the source gas varies depending on the plasma excitation method. The pressure of the atmosphere in which the plasma is generated and the amount of source gas supplied can be adjusted to change the When ion implantation is performed by the ion doping method, the ion beam is + , H2 + , H3 + H3 + It contains 50% or more, more preferably 80% or more. It is preferable that H3 + By making the ratio of ions to 80% or more, the amount of ions contained in the ion beam can be reduced. H2 + The proportion of ions becomes relatively small, so the hydrogen ions contained in the ion beam The variation in the average penetration depth of the ions is reduced, improving the ion implantation efficiency and shortening the tact time. can be shortened.

[0151] Also, H3 + is H + , H2 + Therefore, in an ion beam, H3 + When the ratio of H is high, + , H2 + The doping process differs depending on whether the ratio is high or low. Even if the fast voltage is the same, the former case implants hydrogen into a shallow region of the bond substrate 500. In the former case, the hydrogen implanted into the bond substrate 500 is Since the concentration distribution in the embrittlement layer 502 becomes steep, the thickness of the embrittlement layer 502 itself can be made thin.

[0152] When ion implantation is performed using hydrogen gas by ion doping, the acceleration voltage must be 10 kV or higher. 200kV or less, dose 1×10 16 ions / cm2 More than 6 x 10 16 ions / c m 2 By setting the following, the ion species and their ratios contained in the ion beam, the thickness of the insulating film 501, Depending on the film thickness, the embrittlement layer 502 is formed at a depth of 50 nm to 500 nm in the bond substrate 500. It can be formed in an area.

[0153] For example, the bond substrate 500 is a single crystal silicon substrate, and the insulating film 501 is 100 nm thick. When the thermal oxide film is formed, the flow rate of the source gas, 100% hydrogen gas, is 50 sc cm, beam current density 5 μA / cm 2 , acceleration voltage 50 kV, dose 2.0 × 10 16 a toms / cm 2 Under these conditions, a semiconductor film with a thickness of about 146 nm was separated from the bond substrate 500. It should be noted that the conditions for adding hydrogen to the bond substrate 500 are the same. In addition, by increasing the thickness of the insulating film 501, the thickness of the semiconductor film can be reduced. can be done.

[0154] Helium (He) can also be used as the source gas for the ion beam. The ion species generated is He + Therefore, ion doping without mass separation is Even in the guage method, + can be implanted into the bond substrate 500 as the main ions. Therefore, minute voids can be efficiently formed in the embrittlement layer 502 by ion doping. When ion implantation is performed by ion doping using helium, the acceleration voltage is 10 kV. or more than 200 kV, dose 1 × 10 16 ions / cm 2 More than 6 x 10 16 ions / cm2 It can be as follows:

[0155] The source gas is a halogen gas such as chlorine gas (Cl2 gas) or fluorine gas (F2 gas). You can also be there.

[0156] When ions are implanted into the bond substrate 500 by an ion doping method, the ion doping Since impurities present in the processing device are injected into the object to be processed together with ions, the surface of the insulating film 501 There is a possibility that impurities such as S, Ca, Fe, and Mo may exist near the surface of the insulating film 50. The area near the surface of 1 that is thought to have the most impurities is removed by etching or polishing. Specifically, the insulating film 501 may be removed from the surface thereof by 10 nm to 100 nm, or more preferably by It is desirable to remove the area to a depth of about 30 to 70 nm. and reactive ion etching (RIE) method. For example, ICP (Inductively Coupled Plasma) etching etching, ECR (Electron Cyclotron Resonance) etching ing method, parallel plate (capacitively coupled) etching method, magnetron plasma etching method, 2 High frequency plasma etching or helicon wave plasma etching can be used. For example, when removing the surface of a silicon nitride oxide film by ICP etching, The flow rate of the reaction gas CHF3 was 7.5 sccm, the flow rate of He was 100 sccm, and the reaction pressure was The pressure was 5.5 Pa, the temperature of the lower electrode was 70°C, and RF (13.56 MH z) Power 475 W, power input to the lower electrode (bias side) 300 W, etching time 1 By setting the time to about 0 seconds, it is possible to remove the area from the surface to a depth of about 50 nm. Cut.

[0157] In addition to the fluorine-based gas CHF3, other etching gases include Cl2, BCl3, and SiC Chlorine gases such as l4, CCl4, fluorine gases such as CF4, SF6, NF3, and O2 It can be used appropriately. In addition, an inert gas other than He can be added to the etching gas used. For example, the inert element to be added may be one selected from Ne, Ar, Kr, and Xe. Alternatively, a plurality of elements can be used. When removing by etching, use an aqueous solution containing ammonium hydrogen fluoride, ammonium fluoride, etc. The polishing can be performed by chemical mechanical polishing (CMP). Mechanical Polishing) or Liquid Jet Polishing This can be done by:

[0158] After the formation of the embrittlement layer 502, the heavily contaminated area near the surface of the insulating film 501 is etched. The semiconductor film 503 is formed on the base substrate 503 by removing the insulating film 504 by etching or polishing. The amount of impurities mixed into the semiconductor device 04 can be reduced. In the case of semiconductors, the influence of impurities can cause transistor problems such as fluctuations in threshold voltage and increases in leakage current. This can prevent the occurrence of deterioration in electrical characteristics and reliability.

[0159] The removal of the impurities can be achieved by atomic beam or ion beam irradiation, plasma treatment, or It can be done by radical treatment. When an atomic beam or an ion beam is used, In this case, an inert gas neutral atom beam or an inert gas ion beam such as argon is used. It is possible.

[0160] Next, as shown in FIG. 7(C), the bond substrate 500 and the base substrate 501 are placed together with an insulating film 501 sandwiched therebetween. A base substrate 503 is attached to the substrate.

[0161] Before bonding the base substrate 503 and the bond substrate 500 together, In this embodiment, the insulating film 501 formed on the bond substrate 500 and the bond substrate 501 are On the surface of the base substrate 503, in order to improve the bonding strength between the insulating film 501 and the base substrate 503, It is preferable to perform the following surface treatment.

[0162] Surface treatment can be wet treatment, dry treatment, or a combination of wet and dry treatments. Combinations of different wet or dry processes are also possible. Wet treatments include ozone treatment using ozone water (ozone water cleaning), Ultrasonic cleaning such as megasonic cleaning or two-fluid cleaning (using functional water such as pure water or hydrogen-added water) spraying with a carrier gas such as nitrogen), cleaning with hydrochloric acid and hydrogen peroxide, etc. Dry processing includes inert gas neutral atom beam processing, inert gas ion processing, etc. Beam treatment, UV treatment, ozone treatment, plasma treatment, biased plasma treatment, or By performing the surface treatment as described above, it is possible to improve the bonding performance. This increases the hydrophilicity and cleanliness of the surface to be bonded, thereby improving the bonding strength.

[0163] The bonding was performed by closely adhering the base substrate 503 to the insulating film 501 on the bond substrate 500. Thereafter, a pressure of 1 N / cm was applied to a part of the overlapped base substrate 503 and bond substrate 500. 2 Over 50 0N / cm 2 Less than 11N / cm, preferably2 More than 20N / cm 2 Apply pressure of the following amount When pressure is applied, the base substrate 503 and the insulating film 501 begin to bond from that point, Eventually, the bond extends to the entire contact surface.

[0164] The bonding is achieved using van der Waals forces and hydrogen bonds, resulting in a strong bond even at room temperature. Since the above bonding can be performed at low temperature, the base substrate 503 Various materials can be used. For example, the base substrate 503 is an aluminosilicate Cate glass, barium borosilicate glass, aluminoborosilicate glass, etc. for the electronics industry In addition to various glass substrates used in the Furthermore, the base substrate 503 can be made of silicon, gallium arsenide, insulator, or the like. A semiconductor substrate such as aluminum phosphide can be used. Alternatively, a stainless steel substrate can be used. A metal substrate may be used as the base substrate 503. The glass substrate has a thermal expansion coefficient of 25 x 10 -7 / ℃ or more 50×10 -7 / ℃ or less (preferably is 30 x 10 -7 / ℃ or more 40×10 -7 / ℃ or less), and the strain point is 580℃ or more and It is preferable to use a substrate whose temperature is 80°C or less (preferably, 600°C or more and 680°C or less). In addition, if an alkali-free glass substrate is used as the glass substrate, the semiconductor device can be prevented from being damaged by impurities. This can reduce pollution.

[0165] The glass substrate used can be a mother glass substrate developed for the manufacture of liquid crystal panels. Mother glass is available in sizes such as 3rd generation (550mm x 650mm), 3rd generation (550mm x 650mm), and 4th generation (550mm x 650mm). 5th generation (600mm x 720mm), 4th generation (680mm x 880mm or 730 mm×920mm), 5th generation (1100mm×1300mm), 6th generation (1500m m×1850mm), 7th generation (1870mm×2200mm), 8th generation (2200m Substrates with sizes such as 2400 x 2400 mm are known. By using it as a base substrate 503 to manufacture an SOI substrate, the area of ​​the SOI substrate can be increased. By using a large substrate such as a mother glass substrate as the base substrate 503, Larger SOI substrates can be realized. If larger SOI substrates are realized, it will be possible to manufacture a large number of devices from a single substrate. As the number of IC, LSI, and other chips manufactured from this increases, productivity can be dramatically improved. This can be done.

[0166] There is no significant limitation on the substrate that can be used as the base substrate 503, but at least It is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. A glass substrate manufactured by the float method or the annealing method can be used. If the temperature of the subsequent heat treatment is high, it is advisable to use a material with a strain point of 730°C or higher. The glass substrate may be made of, for example, aluminosilicate glass, aluminoborosilicate glass, Glass materials such as barium borosilicate glass are used. By containing more barium oxide (BaO) than the original glass, more practical heat-resistant glass can be obtained. For this reason, it is preferable to use a glass substrate containing more BaO than B2O3. In order to avoid bonding defects caused by shrinkage, the base The base substrate 503 may be subjected to a heat treatment in advance.

[0167] An insulating film may be formed on the base substrate 503. Although an insulating film does not necessarily have to be formed on the surface, it is preferable to form an insulating film on the surface of the base substrate 503. By forming the above-mentioned layer, alkali metal or aluminum can be easily transferred from the base substrate 503 to the bond substrate 500. This can prevent impurities such as potassium earth metals from entering. When an insulating film is formed on the surface, the insulating film on the base substrate 503 is bonded to the insulating film 501. Therefore, the types of substrates that can be used as the base substrate 503 are further expanded. Generally, substrates made of flexible synthetic resins such as plastic tend to have low heat resistance. If the substrate can withstand the processing temperature in the subsequent manufacturing process of the semiconductor device, When an insulating film is formed on the substrate, the substrate can be used as a base substrate 503. As a plastic substrate, polyester, typified by polyethylene terephthalate (PET), Polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate Polycarbonate (PC), Polyetheretherketone (PEEK), Polysulfone (PSF) , polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate Polyvinyl chloride (PBT), polyimide, acrylonitrile butadiene styrene resin Examples of the material include polyethylene, polypropylene, polyvinyl acetate, and acrylic resin. When forming an insulating film on the insulating film 3, the surface of the insulating film is subjected to a surface treatment in the same manner as the insulating film 501. Then, it is advisable to perform lamination.

[0168] After the bond substrate 500 is attached to the base substrate 503, the base substrate 503 and the insulating film 50 It is preferable to perform a heat treatment to increase the bonding strength at the bonding interface with 1. The temperature is set to a temperature that does not cause cracks in the embrittlement layer 502, and is set to a temperature of 200°C or higher and 400°C or lower. The base substrate 503 can be treated in this temperature range. By attaching the bond substrate 500, the insulating film 501 is formed between the base substrate 503 and the insulating film 501. The bonding strength of the joint can be strengthened.

[0169] When the bond substrate 500 and the base substrate 503 are attached to each other, the bonding surface may be contaminated with dust or the like. If the surface is contaminated with , the contaminated part will not be bonded. The bond substrate 500 and the base substrate 503 are preferably bonded to each other in an airtight processing chamber. When the bond substrate 500 and the base substrate 503 are bonded to each other, the processing chamber is 5.0×10 -3 The pressure is reduced to about Pa to purify the atmosphere during the bonding process. good.

[0170] Next, by performing a heat treatment, adjacent microvoids in the embrittlement layer 502 are bonded to each other. As a result, the volume of the microvoids increases. As a result, as shown in FIG. 7(D), the embrittlement layer 502 In this step, the semiconductor film 504, which is a part of the bond substrate 500, is separated from the bond substrate 500. Since the insulating film 501 is bonded to the base substrate 503, the bond is not formed on the base substrate 503. The semiconductor film 504 separated from the bond substrate 500 is fixed. The temperature of the heat treatment for separating from the base substrate 500 is set to a temperature that does not exceed the distortion point of the base substrate 503. Let's say.

[0171] This heat treatment is carried out using an RTA (Rapid Thermal Anneal) device, a resistance heating device, A thermal furnace or microwave heating device can be used. The RTA device is a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid When using a GRTA device, The heating temperature should be between 550°C and 650°C, and the treatment time should be between 0.5 and 60 minutes. When using a resistance heating device, the heating temperature should be between 200°C and 650°C, and the treatment time should be 2 The period can be more than 1 hour and less than 4 hours.

[0172] The heat treatment may be performed using dielectric heating using high frequency waves such as microwaves. Heat treatment by dielectric heating is performed using a high frequency generator with a frequency of 300 MHz or This can be done by irradiating the bond substrate 500 with a high frequency of 3 THz. For example, by irradiating 2.45 GHz microwaves at 900 W for 14 minutes, Adjacent microvoids are bonded together, and the bond substrate 500 is finally separated at the embrittlement layer. It can be done.

[0173] A specific method of heat treatment using a vertical furnace with resistance heating will be described. The base substrate 503 with the 00 attached thereto is placed on a boat in a vertical furnace. In order to prevent the bond substrate 500 from being oxidized, the chamber is first Evacuate the chamber to create a vacuum. The vacuum level is 5 x 10 -3 After creating a vacuum, Nitrogen is supplied into the chamber to create a nitrogen atmosphere at atmospheric pressure. Increase heat temperature to 200°C.

[0174] After the chamber is filled with nitrogen at atmospheric pressure, it is heated at 200°C for 2 hours. Increase the temperature to 400°C over 1 hour. Once the heating temperature of 400°C is stable, let it cool for 1 hour. Once the heating temperature has stabilized at 600°C, After that, reduce the heating temperature to 400°C over 1 hour, and then heat for 10 to 30 minutes. After a while, the boat is removed from the chamber. The bond substrate 500 and the base substrate 503 to which the semiconductor film 504 is attached are cooled.

[0175] The heat treatment using the resistance heating furnace strengthens the bonding strength between the insulating film 501 and the base substrate 503. The heat treatment for decomposing the embrittlement layer 502 and the heat treatment for dividing the embrittlement layer 502 are performed successively. When the two heat treatments are performed in different equipment, for example, in a resistance heating furnace, the treatment temperature is 20 After performing a heat treatment at 0° C. for 2 hours, the bonded base substrate 503 and the bond The substrate 500 is then removed from the furnace. Then, the substrate 500 is heated in an RTA apparatus at a processing temperature of 600° C. or higher and 700° C. or higher. Then, a heat treatment is performed for a treatment time of about 1 minute to several hours to form the bond substrate 500 into the embrittlement layer 50 Divide it into 2.

[0176] Note that the periphery of the bond substrate 500 may not be bonded to the base substrate 503. This is because the peripheral portion of the bond substrate 500 is chamfered or has a curvature. Therefore, the base substrate 503 and the insulating film 501 are not in close contact with each other, or the periphery of the bond substrate 500 is This is thought to be because the embrittlement layer 502 is difficult to split at the edges. The reason for this is that polishing such as CMP performed when manufacturing the bond substrate 500 may damage the bond substrate. The peripheral portion of the plate 500 is insufficient, and the surface of the peripheral portion is rougher than that of the central portion. In addition, when the bond substrate 500 is transported, the periphery of the bond substrate 500 is moved by a carrier or the like. If scratches are made on the edges, the scratches also make it difficult for the peripheral area to be bonded to the base substrate 503. Therefore, the base substrate 503 has a size larger than that of the bond substrate 500. A semiconductor film 504 having a small size is attached.

[0177] Note that before separating the bond substrate 500, hydrogenation treatment is performed on the bond substrate 500. The hydrogenation treatment is carried out, for example, in a hydrogen atmosphere at 350° C. for about 2 hours.

[0178] When the base substrate 503 and the plurality of bond substrates 500 are bonded to each other, The semiconductor substrate 500 may have different crystal plane orientations. Mobility varies depending on the crystal plane orientation. Therefore, it is necessary to select a crystal plane orientation suitable for the semiconductor device to be formed. The semiconductor film 504 may be formed by appropriately selecting a bond substrate 500 having the above structure. If an n-type semiconductor element is formed using the conductor film 504, a semiconductor having a {100} plane By forming the film 504, it is possible to increase the mobility of majority carriers in the semiconductor device. For example, if a p-type semiconductor element is formed using the semiconductor film 504, By forming the semiconductor film 504 having a {10} plane, the majority carriers in the semiconductor element If a transistor is formed as a semiconductor element, For example, the bonding direction of the semiconductor film 504 is determined in consideration of the channel direction and the crystal plane orientation. Make sure that

[0179] Next, the surface of the semiconductor film 504 may be planarized by polishing. Planarization is not necessarily essential. However, by performing the planarization, the semiconductor film 506 and the semiconductor film 507 to be formed later can be formed. The interface characteristics of the insulating film can be improved. The thickness of the semiconductor film 504 can be reduced by the above-mentioned planarization. The above-mentioned planarization may be performed on the semiconductor film 504 before etching, but it may be performed after etching. The same may be applied to the semiconductor film 506 and the semiconductor film 507 formed by etching.

[0180] Alternatively, the surface of the semiconductor film 504 may be etched instead of polished. The surface can be flattened. Reactive ion etching (RIE) is used for etching. reactive ion etching, e.g., ICP (Inductively Coupled Plasma) Coupled Plasma Etching, ECR (Electron Cyclic Neutron Resonance etching method, parallel plate (capacitively coupled) etching method, magnetron plasma etching method, dual frequency plasma etching method or helicon wave A dry etching method such as plasma etching may be used.

[0181] For example, when using ICP etching, the flow rate of the etching gas, chlorine, is 40 sccm. ~100sccm, power input to the coil-type electrode 100W~200W, lower electrode (by The power input to the gas side should be 40W to 100W, and the reaction pressure should be 0.5Pa to 1.0Pa. For example, the flow rate of chlorine, which is an etching gas, is 100 sccm, the reaction pressure is 1.0 Pa, and The temperature of the electrode was 70°C, and the RF (13.56MHz) power input to the coil-type electrode was 150W. The power input to the lower electrode (bias side) is 40 W, and the etching time is 25 to 27 seconds. By using the method c, the semiconductor film 504 can be thinned to about 50 nm to 60 nm. Etching gases include chlorine, boron chloride, silicon chloride, and chlorine-based gases such as carbon tetrachloride. Fluorine-based gases such as carbon tetrafluoride, sulfur fluoride or nitrogen fluoride, oxygen, etc. may be used appropriately. This can be done.

[0182] By the etching, the semiconductor film is thinned to a thickness that is optimal for the semiconductor element to be formed later. Not only can the semiconductor film 504 be thinned, but the surface of the semiconductor film 504 can be flattened.

[0183] The semiconductor film 504 in close contact with the base substrate 503 is formed after the formation of the embrittlement layer 502 and the embrittlement layer 503. The separation at 02 may cause crystal defects or damage the flatness of the surface. Therefore, in one aspect of the present invention, a method for reducing crystal defects and improving flatness is provided. In order to do this, a process of removing oxide films such as native oxide films formed on the surface of the semiconductor film 504 is performed. After this, the semiconductor film 504 is irradiated with laser light.

[0184] In this embodiment of the present invention, the semiconductor film 504 is immersed in DHF containing 0.5 wt % hydrogen fluoride. The oxide film is removed by exposing it for 10 seconds.

[0185] The laser light irradiation can be performed with an energy density sufficient to partially melt the semiconductor film 504. If the semiconductor film 504 is completely melted, random nucleation occurs in the liquid phase. Therefore, when the semiconductor film 504 is recrystallized, microcrystals are generated, and the crystallinity is reduced. By partially melting the semiconductor film 504, crystal growth occurs from the unmelted solid phase portion. The vertical growth causes the semiconductor film 50 to grow. The crystal defects in the semiconductor film 504 are reduced and the crystallinity is restored. The semiconductor film 504 is melted up to the interface with the insulating film 501 and is in a liquid state. On the other hand, the semiconductor film 504 being in a partially molten state means that the upper layer is molten and in a liquid phase. This refers to a state in which the lower layer is a solid phase.

[0186] The laser beam is irradiated by pulse oscillation in order to melt the semiconductor film 504 partially. For example, in the case of pulse oscillation, the repetition frequency is 1 MHz. z or less, and the pulse width is 10 ns or more and 500 ns or less. For example, the repetition frequency is 10 Hz. A XeCl excimer laser with a frequency of 300 Hz, a pulse width of 25 ns, and a wavelength of 308 nm was used. This can be done.

[0187] The laser light is the fundamental wave or second harmonic of a solid-state laser that is selectively absorbed by the semiconductor. Specifically, for example, a laser having a wavelength in the range of 250 nm to 700 nm is preferable. The energy of the laser beam can be determined by the wavelength of the laser beam, The thickness of the semiconductor film 504 can be determined by taking into consideration the skin depth of the semiconductor film 504. The thickness of the membrane 504 is about 120 nm, and the wavelength of the laser light is 308 nm. When using a laser beam with an energy density of 600 mJ / cm 2 ~700mJ / cm 2 That's all we need to do.

[0188] Pulse oscillation lasers include Ar lasers, Kr lasers, excimer lasers, and CO2 lasers. Laser, YAG laser, Y2O3 laser, YVO4 laser, YLF laser, YAlO3 laser The, glass laser, ruby ​​laser, alexandrite laser, Ti: sapphire laser , copper vapor lasers or gold vapor lasers can be used.

[0189] In this embodiment, when the thickness of the semiconductor film 504 is about 146 nm, the laser light irradiation is performed as follows. This can be done as follows: A XeCl excimer laser is used as the laser oscillator for the laser light. (Wavelength: 308 nm, pulse width: 20 ns, repetition frequency: 30 Hz) is used. The cross section of the laser beam is shaped into a line of 0.4 mm x 120 mm. The laser beam is irradiated onto the semiconductor film 504 at a speed of 0.5 mm / sec. As a result, a semiconductor film 505 in which the crystal defects have been repaired is formed, as shown in FIG. 7(E).

[0190] The laser beam irradiation is carried out in an inert atmosphere such as a rare gas or nitrogen atmosphere, or in a reduced pressure atmosphere. To irradiate the laser beam in the above atmosphere, an airtight chamber is required. The laser beam is irradiated into the chamber, and the atmosphere inside the chamber is controlled. If no inert gas is used, it can be removed by spraying an inert gas such as nitrogen gas onto the surface to be irradiated with the laser light. Laser light irradiation can be achieved in an active atmosphere, an inert atmosphere, or a reduced pressure atmosphere. By irradiating the laser beam in the atmosphere, the generation of natural oxide film is reduced compared to when irradiating in the air. The semiconductor film 505 formed after the laser light irradiation is prevented from cracking or cracking. The occurrence of etch stripes can be suppressed, the flatness of the semiconductor film 505 can be improved, and the laser beam This can widen the usable energy range.

[0191] The optical system makes the energy distribution of the laser light uniform and makes the cross section linear. This makes it possible to achieve high throughput and uniform irradiation of the laser light. By making the beam length of the laser light longer than one side of the base substrate 503, By this scanning, the entire semiconductor film 504 attached to the base substrate 503 is irradiated with the laser light. When the beam length of the laser light is shorter than one side of the base substrate 503, the laser light can be irradiated multiple times. By this scanning, the entire semiconductor film 504 attached to the base substrate 503 is irradiated with the laser light. The length should be such that it can be

[0192] Laser light is irradiated in an inert atmosphere such as a rare gas or nitrogen atmosphere, or in a reduced pressure atmosphere. To do this, a laser beam is irradiated in an airtight chamber, and the atmosphere in this chamber is If a chamber is not used, the surface to be irradiated with the laser beam should be inert gas such as nitrogen gas. By spraying an inert gas onto the target, it is possible to irradiate the target with laser light in an inert atmosphere. By irradiating the laser beam in an activated atmosphere or a reduced pressure atmosphere, it is possible to The generation of a natural oxide film is more suppressed than in the case of the oxidized silicon dioxide film, and the semiconductor film 505 formed after the laser light irradiation is The occurrence of cracks or pitch stripes is suppressed, and the flatness of the semiconductor film 505 is improved. This allows the usable energy range of the laser beam to be widened.

[0193] Before the laser beam irradiation, the surface of the semiconductor film 504 is planarized by dry etching. In this case, damage such as crystal defects occurs near the surface of the semiconductor film 504 due to dry etching. However, the damage caused by dry etching can be reduced by the irradiation of the laser beam. It is also possible to repair scratches.

[0194] Next, after the laser light irradiation, the surface of the semiconductor film 505 may be etched. When the surface of the semiconductor film 505 is etched after the irradiation with laser light, the irradiation with laser light is not necessarily performed. It is not necessary to etch the surface of the semiconductor film 504 before the irradiation of laser light. If the surface of the semiconductor film 504 is etched before the laser irradiation, the semiconductor film 504 is not necessarily etched after the laser irradiation. There is no need to etch the surface of the film 505. Alternatively, after the irradiation of the laser light, Before the irradiation, the surface of the semiconductor film 505 may be etched.

[0195] By the etching, the semiconductor film is thinned to a thickness that is optimal for the semiconductor element to be formed later. Not only can the semiconductor film 505 be thinned, but the surface of the semiconductor film 505 can be flattened.

[0196] After the laser light irradiation, the semiconductor film 505 is subjected to a heat treatment at 500° C. or more and 650° C. or less. By this heat treatment, the semiconductor film 5 that was not recovered by the irradiation of the laser light is removed. This heat treatment can eliminate defects in the semiconductor film 505 and relax the distortion of the semiconductor film 505. , RTA (Rapid Thermal Anneal) equipment, resistance heating furnace, microwave A heating device can be used. The RTA device is a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) For example, when a resistance heating furnace is used, the temperature is 600 Heat at ℃ for 4 hours.

[0197] Next, as shown in FIG. 8(A), the semiconductor film 505 is partially etched to form a semiconductor film. The semiconductor film 505 is formed into island-shaped semiconductor films 506 and 507. Further etching removes the area where the bonding strength is insufficient at the edge of the semiconductor film 505. In this embodiment, one semiconductor film 505 is etched. The semiconductor films 506 and 507 are formed by etching. The number is not limited to this.

[0198] After the semiconductor film 505 is separated, the surface of the bond substrate 500 is planarized. Then, the semiconductor film 505 can be separated again.

[0199] Specifically, the insulating film 501 remaining mainly at the edge of the bond substrate 500 is removed by etching or the like. The insulating film 501 is formed of silicon oxide, silicon oxynitride, or silicon nitride oxide. If the film is not thick enough, wet etching using hydrofluoric acid can be used.

[0200] Next, the protrusions formed at the edge of the bond substrate 500 by separating the semiconductor film 505 and the hydrogen The remaining embrittlement layer containing excess silicon is removed. It is preferable to use wet etching, and the etching solution is tetramethylammonium hydroxide. tetramethylammonium hydroxide (TM) AH) solution can be used.

[0201] Next, the surface of the bond substrate 500 is polished. The polishing can be performed by CMP. In order to smooth the surface of the board substrate 500, it is desirable to polish it by about 1 μm to 10 μm. After polishing, polishing particles remain on the surface of the bond substrate 500, so RCA using hydrofluoric acid, etc. Perform cleaning.

[0202] By reusing the bond substrate 500, the material cost of the semiconductor substrate can be reduced. .

[0203] The semiconductor film 506 and the semiconductor film 507 are doped with boron, aluminum, or the like to control the threshold voltage. A p-type impurity such as gallium or an n-type impurity such as phosphorus or arsenic may be added. The addition of impurities to control the threshold voltage is performed on the semiconductor film before patterning. Alternatively, the semiconductor film 506 and the semiconductor film 507 formed after patterning may be subjected to the etching treatment. Also, impurities for controlling the threshold voltage may be added to the bond substrate. Alternatively, the doping of impurities can be performed on the bond substrate to roughly adjust the threshold voltage. After this, in order to fine-tune the threshold voltage, the semiconductor film before patterning is The same is also applied to the semiconductor film 506 and the semiconductor film 507 formed by patterning. is also good.

[0204] Next, as shown in FIG. 8(B), a gate insulating film is formed to cover the semiconductor film 506 and the semiconductor film 507. The gate insulating film 508 is formed by performing high density plasma treatment. It can be formed by oxidizing or nitriding the surfaces of the conductive film 506 and the semiconductor film 507. High-density plasma treatment is a process in which rare gases such as He, Ar, Kr, and Xe are mixed with oxygen and nitrogen oxides. The plasma is excited by a mixture of gases such as ammonia, nitrogen, and hydrogen. By introducing microwaves, it is possible to generate high density plasma with low electron temperature. Oxygen radicals (including OH radicals) generated in such high-density plasma The surface of the semiconductor film is oxidized by nitrogen radicals (which may contain NH radicals) and nitrogen radicals (which may contain NH radicals). By nitriding or oxidizing the insulating film, a thickness of 1 to 20 nm, preferably 5 to 10 nm, is formed. This insulating film of 5 to 10 nm is used as a gate insulating film 508. For example, nitrous oxide (N2O) is diluted 1 to 3 times (flow ratio) with Ar, and A microwave (2.45 GHz) power of 3 to 5 kW was applied at a pressure of 0 Pa to form the semiconductor film 5 The surfaces of the semiconductor film 506 and the semiconductor film 507 are oxidized or nitrided. An insulating film of 2 nm (preferably 2 nm to 6 nm) is formed. The reactor was heated to 10-30 Pa with 3-5 kW microwaves (2.4 5GHz) power is applied to form a silicon oxynitride film by vapor deposition, and the gate insulating film is formed. By combining solid-state reactions and reactions by vapor phase growth, the interface state density is It is possible to form a gate insulating film with low and excellent dielectric strength.

[0205] The oxidation or nitridation of the semiconductor film by the high-density plasma treatment described above proceeds as a solid-phase reaction. The interface state density between the gate insulating film 508 and the semiconductor film 506 and the semiconductor film 507 is extremely low. In addition, the semiconductor film 506 and the semiconductor film 507 can be formed by high-density plasma treatment. By directly oxidizing or nitriding the insulating film, it is possible to reduce variations in the thickness of the insulating film that is formed. In addition, when the semiconductor film has crystallinity, the surface of the semiconductor film is etched by high-density plasma treatment. By oxidizing through a solid-state reaction, oxidation is prevented from progressing too quickly only at the grain boundaries. Therefore, it is possible to form a gate insulating film with good uniformity and low interface state density. The insulating film formed by plasma treatment is included in part or all of the gate insulating film. Such a transistor can suppress variations in characteristics.

[0206] Alternatively, the semiconductor film 506 and the semiconductor film 507 are thermally oxidized to form a gate insulating film 508. Alternatively, the film may be formed by using a plasma CVD method or a sputtering method. , silicon oxide, silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide The gate insulating film 50 is formed by using a film containing tantalum oxide or tantalum oxide as a single layer or by laminating the film. 8 may be formed.

[0207] Next, as shown in FIG. 8(C), a conductive film is formed on the gate insulating film 508, and then the conductive film The semiconductor film 506 and the semiconductor film 507 are patterned into a predetermined shape. An electrode 509 is formed on the other side. The conductive film is formed by using a CVD method, a sputtering method, or the like. The conductive film can be made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), and Buten (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb) Furthermore, alloys containing the above metals as the main components may be used. Alternatively, a compound containing an impurity element such as phosphorus that provides conductivity to the semiconductor film may be used. Alternatively, the insulating film 12 may be formed using a semiconductor such as polycrystalline silicon doped with .

[0208] The combination of two conductive films is tantalum nitride or tantalum for the first layer and tantalum for the second layer. In addition to the above examples, tungsten nitride and tungsten, nitride can be used. Examples include molybdenum chloride and molybdenum, aluminum and tantalum, and aluminum and titanium. Tungsten and tantalum nitride have high heat resistance, so after forming the two-layer conductive film, In the process, a heat treatment for the purpose of thermal activation can be performed. As a combination of, for example, silicon doped with impurities that give n-type conductivity and nickel Silicide, silicon doped with impurities to give n-type conductivity, tungsten silicide, etc. can also be used.

[0209] In this embodiment, the electrode 509 is formed of a single layer of conductive film. The electrode 509 may be formed of a plurality of stacked conductive films. In the case of a three-layer structure in which three or more conductive films are stacked, a molybdenum film, an aluminum film, and a molybdenum film are stacked. It is advisable to adopt a laminated structure of a dielectric film.

[0210] When forming the electrode 509, the electrode 509 is selectively formed by using a droplet discharge method without using a mask. 09 may also be formed.

[0211] The droplet ejection method is a method of ejecting or spraying droplets containing a predetermined composition from a fine hole to produce a predetermined This refers to a method for forming a pattern, and inkjet methods are included in this category.

[0212] The electrode 509 is formed by forming a conductive film and then using an ICP (Inductively Coupled Plasma) Plasma: Inductively coupled plasma etching method was used, and etching conditions (coil type the amount of power applied to the electrode layer on the substrate side, the amount of power applied to the electrode layer on the substrate side, the electrode temperature on the substrate side, etc. ) can be appropriately adjusted to etch the desired tapered shape. The angle of the tapered shape can also be controlled by changing the shape of the mask. The etching gas may be chlorine, boron chloride, silicon chloride, carbon tetrachloride, or the like. Chlorine-based gases, fluorine-based gases such as carbon tetrafluoride, sulfur fluoride or nitrogen fluoride, or oxygen are used appropriately. It can be used as appropriate.

[0213] Next, as shown in FIG. 8(D), an impurity element that imparts one conductivity type is introduced using the electrode 509 as a mask. is added to the semiconductor film 506 and the semiconductor film 507. In this embodiment mode, n A type-imparting impurity element (for example, phosphorus or arsenic) is added to impart p-type conductivity to the semiconductor film 507. An impurity element (for example, boron) is added. When doping the semiconductor film 506 with n-type impurities, the semiconductor film 506 is covered with a mask or the like, and the p-type On the other hand, the impurity element that gives n-type conductivity is selectively added. When doping the semiconductor film 506 with p-type impurities, the semiconductor film 507 to which p-type impurities are to be doped is covered with a mask or the like. The doping of the impurity element that gives the n-type conductivity is selectively performed. Impurities that give either p-type or n-type conductivity to the semiconductor films 506 and 507 After adding the elements, a p-type or n-type pore is selectively formed in only one of the semiconductor films at a higher concentration. It is also possible to add one of the impurity elements that provides the other of the two. By adding the impurity, an impurity region 510 is formed in the semiconductor film 506, and an impurity region 511 is formed in the semiconductor film 507. is formed.

[0214] Next, as shown in FIG. 9(A), sidewalls 512 are formed on the side surfaces of the electrode 509 . The sidewall 512 is formed by, for example, forming a new layer so as to cover the gate insulating film 508 and the electrode 509. An insulating film is formed on the surface, and the newly formed This can be achieved by partially etching the insulating film. As a result, the newly formed insulating film is partially etched, forming a size on the side of the electrode 509. The gate insulating film 508 is also formed by the anisotropic etching. The insulating film for forming the sidewall 512 may be etched completely or partially. Silicon film, silicon oxide film, oxide film, etc. are produced by PCVD method, plasma CVD method, sputtering method, etc. Silicon nitride film, silicon nitride oxide film, and films containing organic materials such as organic resins are used as single layers or laminated layers. In this embodiment, a silicon oxide film having a thickness of 100 nm is formed by plasma C It is formed by the VD method. The etching gas is a mixture of CHF3 and helium. The process for forming the sidewalls 512 is not limited to these. It is not something that can be done.

[0215] Next, as shown in FIG. 9(B), using the electrode 509 and the sidewall 512 as a mask, An impurity element that imparts one conductivity type is added to the semiconductor film 506 and the semiconductor film 507. The conductive film 506 and the semiconductor film 507 are formed by adding the same conductive impurity element as that added in the previous step. The impurity element that gives p-type conductivity is added at a higher concentration. When doping 507, the semiconductor film 506 to be doped with n-type impurities is covered with a mask or the like, and p-type On the other hand, the doping of impurity elements that give n-type conductivity is selective. When the element is added to the semiconductor film 506, the semiconductor film 507 to which the p-type impurity is added is masked. or the like, so that the addition of an impurity element that imparts n-type conductivity is selectively carried out.

[0216] By adding the impurity element, a pair of high concentration impurity regions 513 and a pair of high concentration impurity regions 514 are formed in the semiconductor film 506. A pair of low concentration impurity regions 514 and a channel forming region 515 are formed. By adding the pure element, a pair of high concentration impurity regions 516 and a pair of low concentration impurity regions 517 are formed in the semiconductor film 507. A high concentration impurity region 517 and a channel forming region 518 are formed. 13. The high concentration impurity region 516 functions as a source region or a drain region, and the low concentration impurity region The impurity region 514 and the low concentration impurity region 517 are LDD (Lightly Doped Dra). The LDD region does not necessarily have to be provided, and it functions as a source region. Alternatively, only the impurity region that functions as the drain region may be formed. The LDD region may be formed on only one side of the drain region.

[0217] In the case of a silicon transistor, the source and drain regions are It functions as a source electrode and a drain electrode.

[0218] A sidewall 512 formed on the semiconductor film 507 and a semiconductor film 506 formed on the semiconductor film 506 The sidewalls 512 are formed so that the width in the direction in which the carriers move is the same. The width may be different from that of the semiconductor film 50 that will become a p-type transistor. The width of the sidewall 512 on the semiconductor film 506 that will become the n-type transistor is It is preferable that the width of the wall 512 is longer than that of the source in a p-type transistor. The boron implanted to form the source and drain regions is highly diffusive and has a short channel In the p-type transistor, the width of the sidewall 512 is By making it longer, it is possible to dope the source and drain regions with a high concentration of boron. This allows the source and drain regions to have low resistance.

[0219] Next, in order to further reduce the resistance of the source and drain regions, a semiconductor film 506 and a semiconductor The silicide layer may be formed by silicidating the film 507. The semiconductor film is brought into contact with a metal, and then subjected to heat treatment, GRTA method, LRTA method, etc., to form a metal layer in the semiconductor film. The silicide layer is formed by reacting silicon with a metal. Nickel silicide may be used. When the thickness of the semiconductor film 506 and the semiconductor film 507 is thin, Even if the silicide reaction is advanced to the bottom of the semiconductor film 506 and the semiconductor film 507 in this region, The metal materials used for silicidation are titanium (Ti), nickel (Ni), W, Molybdenum (Mo), Cobalt (Co), Zirconium (Zr), Hf, tantalum (Ta), vanadium (V), neodymium (Nd), chromium ( Cr), platinum (Pt), palladium (Pd), etc. can be used. Alternatively, silicide may be formed by irradiation with light from a lamp or the like.

[0220] By the above-described series of steps, an n-channel transistor 520 and a p-channel transistor A star 521 is formed.

[0221] After the process shown in FIG. 9B is completed, the n-channel transistor 520 and the p-channel A transistor using an oxide semiconductor is formed over the channel transistor 521.

[0222] First, as shown in FIG. 10A, an n-channel transistor 520 and a p-channel transistor An insulating film 530 is formed to cover the transistor 521. By providing the insulating film 530, This can prevent the surface of the electrode 509 from being oxidized during the heat treatment. 0, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum oxide In this embodiment, a nitride oxide film having a thickness of about 50 nm is used. A silicon dioxide film is used as the insulating film 530 .

[0223] Next, as shown in FIG. 10B, an n-channel transistor 520 and a p-channel transistor An insulating film 531 and an insulating film 532 are formed on the insulating film 530 so as to cover the transistor 521. The insulating films 531 and 532 are made of a material that can withstand the temperature of heat treatment in a subsequent manufacturing process. Specifically, the insulating film 531 and the insulating film 532 are formed of, for example, silicon oxide, silicon nitride, or nitride. Inorganic insulating materials such as silicon oxide, silicon oxynitride, aluminum nitride, and aluminum oxide nitride A membrane can be used.

[0224] In this embodiment, insulating films 531 and 532 are stacked on the insulating film 530. However, the insulating film formed on the insulating film 530 may be a single layer insulating film, or may be a three or more layer insulating film. The films may be laminated.

[0225] The surface of the insulating film 532 may be flattened by a CMP method or the like.

[0226] Next, as shown in FIG. 10(B), a gate electrode 601 and an electrode 602 are formed on the insulating film 532. Form.

[0227] The materials of the gate electrode 601 and the electrode 602 are molybdenum, titanium, chromium, tantalum, and titanium. Metallic materials such as tin, neodymium, scandium, etc., and alloys containing these metallic materials as the main components A conductive film using a material or a nitride of these metals can be used as a single layer or a laminated layer. In addition, if the metal material can withstand the temperature of the heat treatment to be performed in the subsequent process, Aluminum and copper can also be used as the material. Aluminum and copper are heat-resistant and corrosion-resistant. To avoid problems with thermal conductivity, it is recommended to use it in combination with a high melting point metal material. Materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium. Sodium, etc. can be used.

[0228] For example, the gate electrode 601 and the electrode 602 each having a two-layer laminated structure may be formed of an aluminum film. Two-layer structure with a molybdenum film laminated on top, and two-layer structure with a molybdenum film laminated on top of a copper film A two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film, or a titanium nitride film It is preferable to use a two-layer structure in which a titanium film and a molybdenum film are laminated. The gate electrode 601 and the electrode 602 are made of an aluminum film, an aluminum film and a silicon film. alloy film, aluminum and titanium alloy film, or aluminum and neodymium alloy film a tungsten film, a tungsten nitride film, a titanium nitride film, or a titanium film as an upper and lower layer; It is preferable to have a laminated structure.

[0229] The gate electrode 601 and the electrode 602 are made of indium oxide, indium tin oxide, or indium oxide. zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, Alternatively, a light-transmitting conductive oxide film such as zinc gallium oxide can be used.

[0230] The thickness of the gate electrode 601 and the electrode 602 is 10 nm to 400 nm, preferably 100 nm. In this embodiment, a sputtering method using a tungsten target is used. After forming a conductive film for the gate electrode of 150 nm, the conductive film is etched to the desired thickness. By processing (patterning) the film into the above shapes, a gate electrode 601 and an electrode 602 are formed. If the end of the formed gate electrode is tapered, the gate insulating film laminated thereon may It is preferable that the resist mask is formed by an ink jet method. If the resist mask is formed by the inkjet method, no photomask is required. , and manufacturing costs can be reduced.

[0231] Next, as shown in FIG. 10(C), a gate insulating film is formed on the gate electrode 601 and the electrode 602. The gate insulating film 603 is formed by plasma CVD or sputtering. Silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film, aluminum oxynitride film, oxide haf The gate insulating film can be formed of a tantalum oxide film or a tantalum oxide film in a single layer or a laminated layer. It is desirable that the insulating film 603 contains as little impurities as possible, such as moisture and hydrogen. When forming a silicon oxide film by the annealing method, a silicon target or a quartz target is used as the target. A quartz target was used, and oxygen or a mixture of oxygen and argon was used as the sputtering gas. do.

[0232] By removing impurities, an oxide semiconductor that has been made i-type or substantially i-type (highly purified) Since the oxide semiconductor is extremely sensitive to the interface state and the interface charge, The interface between the oxide semiconductor and the gate insulating film 603 is important. The gate insulating film (GI) in contact with the nitride semiconductor is required to be of high quality.

[0233] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. This is preferable because it allows the formation of a high-quality insulating film. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0234] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other film formation methods such as the plasma CVD method and the like can also be applied. This improves the quality of the gate insulating film and the interface characteristics between the gate insulating film and the oxide semiconductor. In any case, it is important that the film quality as a gate insulating film is good. In other words, it is possible to reduce the interface state density between the gate insulating film and the oxide semiconductor and form a good interface. As long as it's possible, that's fine.

[0235] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 603 having a structure in which an insulating film such as a silicon dioxide film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films are used as insulating films with high barrier properties and oxide semiconductors. As an insulating film with high barrier properties, for example, a silicon nitride film or a silicon nitride oxide film is used. , aluminum nitride film, or aluminum nitride oxide film. By using a thin insulating film, impurities in the atmosphere such as moisture or hydrogen, or impurities contained in the substrate, Impurities such as alkali metals and heavy metals are present in the oxide semiconductor film, the gate insulating film 603, Alternatively, the intrusion of the oxide semiconductor film into the interface between the oxide semiconductor film and another insulating film and its vicinity can be prevented. In addition, a silicon oxide film or a silicon oxynitride film having a low nitrogen content that is in contact with the oxide semiconductor film may be used. By forming an insulating film such as a film, the insulating film with high barrier properties is in direct contact with the oxide semiconductor film. This can prevent this.

[0236] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0)), and a second gate insulating film is formed on the first gate insulating film. As the insulating film, a silicon oxide film (SiO x (x>0) The gate insulating film 603 may be formed by layering the gate insulating film 603 with a thickness of 100 nm. can be set appropriately depending on the characteristics required for the transistor, and is in the range of 350 nm to 400 nm. It can be about m.

[0237] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. A gate insulating film 60 having a structure in which a silicon oxide film having a thickness of 100 nm formed by Form 3.

[0238] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the gate insulating film 603 as much as possible, As a pre-treatment for film formation, the gate electrode 601 and the electrode The base substrate 503 on which the 602 is formed is preheated, and the moisture adsorbed on the base substrate 503 is removed. It is preferable to desorb and exhaust impurities such as hydrogen. The temperature is 0°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The exhaust means provided in the vacuum chamber is preferably a cryopump. It can also be done as follows.

[0239] Next, a film having a thickness of 2 nm to 200 nm, preferably 3 nm, is deposited on the gate insulating film 603. and forming an oxide semiconductor film with a thickness of 3 nm to 20 nm, more preferably 50 nm to 100 nm. The oxide semiconductor film is formed by sputtering using an oxide semiconductor as a target. The oxide semiconductor film is formed under a rare gas (for example, argon) atmosphere, an oxygen atmosphere, or Alternatively, it is formed by sputtering in a mixed atmosphere of rare gas (e.g., argon) and oxygen. It is possible.

[0240] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating film 603 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. The treatment may be carried out in an atmosphere containing argon to which chlorine, carbon tetrafluoride, etc. have been added.

[0241] The oxide semiconductor film can be formed using any of the above-described oxide semiconductors.

[0242] In this embodiment, gold containing In (indium), Ga (gallium), and Zn (zinc) is used. In-Ga-Zn with a film thickness of 30 nm obtained by sputtering using a metal oxide target The —O-based non-single-crystal film is used as the oxide semiconductor film. The metal composition ratio is In:Ga:Zn=1:1:0.5, In:Ga:Zn=1:1:1, or Alternatively, a metal oxide target having In:Ga:Zn=1:1:2 can be used. Alternatively, the film may be formed using a target containing 2% by weight or more and 10% by weight or less of SiO2. In addition, the filling rate of the metal oxide target containing In, Ga, and Zn is 90% or more. The filling rate is 0% or less, preferably 95% to 99.9%. By using the above, the formed oxide semiconductor film becomes a dense film.

[0243] In this embodiment, the substrate is held in a processing chamber maintained in a reduced pressure state, and the remaining moisture in the processing chamber is removed. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. An oxide semiconductor film is formed over a base substrate 503. During the film formation, the substrate temperature is set to 100° C. or higher. The temperature may be set to 00°C or less, preferably 200°C or more and 400°C or less. By forming the oxide semiconductor film, the concentration of impurities contained in the formed oxide semiconductor film can be reduced. In addition, damage caused by sputtering is reduced. For example, a cryopump or an ion pump is preferably used. It is preferable to use a pump or a titanium sublimation pump. Alternatively, a turbo pump with a cold trap may be used. When the processing chamber is evacuated, hydrogen atoms and compounds containing hydrogen atoms such as water (H2O) are released. Preferably, compounds containing carbon atoms are also exhausted, so that oxide films formed in the processing chamber can be The concentration of impurities contained in the compound semiconductor film can be reduced.

[0244] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. When a pulsed direct current (DC) power supply is used, particles that are generated during film formation are This is preferable because it reduces dust particles that are generated and makes the film thickness distribution uniform.

[0245] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pre-treatment for film formation, up to the gate insulating film 603 is formed in the pre-heating chamber of the sputtering equipment. The base substrate 503 is preheated to remove moisture or hydrogen adsorbed on the base substrate 503. It is preferable to desorb and exhaust the impurities. The temperature is 0°C or lower, preferably 150°C to 300°C. The means is preferably a cryopump, but this preheating process can be omitted. This preheating is also performed before the insulating film 612 is formed on the source electrode 607 and the drain electrode 60 8. The same process may be carried out on the base substrate 503 on which the wirings 609 to 611 have been formed.

[0246] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and D There is also the pulsed DC sputtering method, which applies a bias in a pulsed manner. The RF sputtering method is mainly used to form insulating films, while the DC sputtering method The tarring method is mainly used when forming a metal film.

[0247] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0248] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0249] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0250] The gate insulating film 603 and the oxide semiconductor film can be successively formed without exposure to air. By continuously forming films without exposing them to the atmosphere, the interface is free from water and hydrocarbons. The interface between each layer is formed without being contaminated by atmospheric components or impurity elements floating in the air. Therefore, variations in transistor characteristics can be reduced.

[0251] Next, as shown in FIG. 10C, the oxide semiconductor film is etched to have a desired shape. The gate insulating film 603 is patterned at a position overlapping the gate electrode 601. An island-shaped oxide semiconductor film 605 is formed.

[0252] A resist mask for forming the island-shaped oxide semiconductor film 605 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0253] Note that the etching for forming the island-shaped oxide semiconductor film 605 is dry etching. Dry etching can be performed by wet etching, or both can be used. The gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron chloride (B Cl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4), etc.) are preferred. Fluorine-containing gases (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) , nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr) , oxygen (O2), and these gases are added with rare gases such as helium (He) and argon (Ar). A gas containing a gas added thereto can be used.

[0254] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were determined as follows: The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0255] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) ITO-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. After wet etching, the etching solution is removed by washing together with the etched material. The waste etching solution containing the removed material is purified and the contained material is reused. Materials such as indium contained in the oxide semiconductor film may be extracted from the waste liquid after the etching. By collecting and reusing materials, resources can be used effectively and costs can be reduced.

[0256] Note that reverse sputtering is performed before forming a conductive film in the next step, and the island-shaped oxide semiconductor film 605 and It is also preferable to remove resist residues adhering to the surface of the gate insulating film 603. .

[0257] Next, the mixture is heated under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or The dew point was measured using an ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy)) dew point meter. The moisture content measured by the method is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm The oxide semiconductor film 605 is heated in an air atmosphere (preferably 10 ppb or less). By performing heat treatment on the oxide semiconductor film 605, Specifically, the temperature is 300°C or higher and 850°C or lower ( or a temperature below the distortion point of the glass substrate), preferably 550°C or higher and 750°C or lower. For example, the heat treatment can be performed at 600°C for 3 to 6 minutes. If the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so distortion of the glass substrate can be reduced. It is also possible to process at temperatures above 450°C. The heat treatment may be carried out for about one hour.

[0258] In this embodiment, an electric furnace, which is a type of heat treatment apparatus, is used to heat the oxide semiconductor film 605. Then, heat treatment was performed for 6 minutes in a nitrogen atmosphere with the substrate temperature reaching 600°C. After that, it is kept away from the atmosphere to prevent the re-introduction of moisture or hydrogen.

[0259] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0260] For example, the substrate is transferred into an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, the substrate is removed from the inert gas heated to a high temperature. GRTA can be used to perform high-temperature heat treatment in a short time.

[0261] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain oxygen or hydrogen. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0262] When impurities such as moisture or hydrogen are added to an oxide semiconductor, the gate bias and thermal stress Test conditions are, for example, 85°C, 2 x 10 6 V / cm, 12 hours) In this case, the bonds between the impurities and the main component of the oxide semiconductor are formed by a strong electric field (B: bias) and high temperature ( T: temperature), the dangling bonds generated by the dangling bonds cause the drift of the threshold voltage (Vth). However, as described above, the interface between the gate insulating film and the oxide semiconductor film The characteristics are improved and impurities, particularly moisture or hydrogen, in the oxide semiconductor film are removed as much as possible. By removing the SiO 2 layer, a transistor that is stable even in the BT test can be obtained.

[0263] Through the above steps, the hydrogen concentration in the oxide semiconductor film 605 can be reduced and the oxide semiconductor film 605 can be highly purified. This makes it possible to stabilize the oxide semiconductor film. The heat treatment below produces an oxide semiconductor film with extremely low carrier density and a wide band gap. Therefore, a transistor can be manufactured using a large-area substrate. This allows for increased mass production. By using an oxide semiconductor film, the breakdown voltage is high, the short channel effect is low, and the on / off It is possible to fabricate transistors with high ratios.

[0264] When the oxide semiconductor film is heated, the temperature may vary depending on the material of the oxide semiconductor film and heating conditions. Plate-like crystals may be formed on the surface of the oxide semiconductor film. It is preferable that the crystal is a single crystal with the c-axis oriented substantially perpendicular to the crystal. The crystal is preferably a polycrystalline substance with the c-axis oriented substantially perpendicular to the surface of the oxide semiconductor film. In addition to the c-axis orientation, the polycrystalline body has ab planes that match each other. It is preferable that the a-axis or the b-axis of the oxide semiconductor film be the same. If the substrate surface is uneven, the plate crystals will become polycrystalline. It is desirable that the surface be relatively flat.

[0265] Next, the insulating film 530, the insulating film 531, the insulating film 532, and the gate insulating film 603 are partially etched. By this, the high concentration impurity region 513 of the n-channel transistor 520 , a high concentration impurity region 516 of a p-channel transistor 521 and a region that reaches an electrode 602 Then, a contact hole is formed over the oxide semiconductor film 605. The conductive film used as the drain electrode (including the wiring formed in the same layer) is formed by sputtering. After forming the conductive film by a deposition method or a vacuum deposition method, the conductive film is patterned by etching or the like. As shown in FIG. 11A, the source electrode 607 and the drain electrode 608 are formed on the oxide semiconductor film 605. a wiring 609 in contact with the electrode 602 and the high-concentration impurity region 513; The wiring 610 in contact with the impurity region 516, the high-concentration impurity region 513, and the high-concentration impurity region Wiring 611 contacting 516 is formed.

[0266] Material of the conductive film that will become the source and drain electrodes (including wiring formed in the same layer as these) The material is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or Examples of the film include an alloy containing the above elements as a component, or an alloy film made of a combination of the above elements. In addition, high-temperature materials such as Cr, Ta, Ti, Mo, and W are used on the upper or lower side of metal films such as Al and Cu. It may also be configured by laminating high melting point metal films. Elements such as Nd, Sc, and Y are added to prevent the occurrence of hillocks and whiskers that occur in Al films. By using Al materials that are known to be heat resistant, it is possible to improve heat resistance.

[0267] The conductive film may have a single layer structure or a stacked structure of two or more layers. a single-layer structure of an aluminum film containing titanium; a two-layer structure of a titanium film laminated on an aluminum film; A film is then laminated on top of the Ti film, an aluminum film is then laminated on top of that, and a Ti film is then formed on top of that. Examples include a three-layer structure.

[0268] Also, the conductive layer that becomes the source electrode and the drain electrode (including the wiring formed in the same layer as these) The film may be formed of a conductive metal oxide. Indium (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy (In2 O3-ZnO) or the above metal oxide material containing silicon or silicon oxide can be used.

[0269] When a heat treatment is performed after the conductive film is formed, the conductive film must have heat resistance to withstand this heat treatment. It is preferable that

[0270] Note that the conductive film is etched so as not to remove the oxide semiconductor film 605 as much as possible. The materials and etching conditions are adjusted appropriately. Depending on the etching conditions, island-like The exposed portion of the oxide semiconductor film 605 is partially etched, whereby a groove (a depression) is formed. It may also be achieved.

[0271] In this embodiment, a titanium film is used as the conductive film, so that the ammonia hydrogen peroxide (31% by weight) The conductive film was selectively wetted using hydrogen water: 28% by weight ammonia water: water = 5:2:2. However, the oxide semiconductor film 605 may also be partly etched. Alternatively, a gas containing chlorine (Cl2), boron chloride (BCl3), etc. may be used to form a conductive film. may be dry etched.

[0272] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives the applied light multiple levels of intensity is used. The resist mask formed using the multi-tone mask may be formed by etching a plurality of resist masks. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A single multi-tone mask can be used to create a register that corresponds to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding The photolithography process can also be eliminated, which simplifies the process.

[0273] Next, plasma treatment is performed using gases such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor film. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0274] After the plasma treatment, as shown in FIG. 11(B), the source electrode 607 and the drain electrode The insulating film 604 is formed so as to cover the inner electrode 608, the wirings 609 to 611, and the oxide semiconductor film 605. An insulating film 612 is formed. The insulating film 612 is made to contain as little impurities as possible, such as moisture and hydrogen. It is preferable that the insulating film is a single layer insulating film or a laminate of multiple insulating films. When hydrogen is contained in the insulating film 612, the hydrogen may enter the oxide semiconductor film or Hydrogen extracts oxygen from the oxide semiconductor film, and the back channel of the oxide semiconductor film becomes low-resistance. Therefore, the insulating film 61 may be turned into n-type. 2) It is important not to use hydrogen in the film formation method so that the film contains as little hydrogen as possible. It is desirable to use a material with high barrier properties for the insulating film 612. As a highly elastic insulating film, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or a nitride film When a plurality of insulating films are stacked, an aluminum oxide film or the like can be used. The insulating film such as a silicon oxide film or a silicon oxynitride film having a low nitrogen content is The insulating film is formed closer to the oxide semiconductor film 605 than the insulating film having a low nitrogen content. A source electrode 607, a drain electrode 608, and an oxide semiconductor film are formed with a thin insulating film sandwiched therebetween. An insulating film with high barrier properties is formed so as to overlap with 605. By this, the oxide semiconductor film 605, the gate insulating film 603, or the oxide semiconductor film 6 Prevents impurities such as moisture or hydrogen from entering the interface between 05 and other insulating films and its vicinity. In addition, a silicon oxide film having a low nitrogen ratio that is in contact with the oxide semiconductor film 605 can be formed. By forming an insulating film such as a silicon oxynitride film, an insulating film using a material with high barrier properties can be obtained. Direct contact with the oxide semiconductor film 605 can be prevented.

[0275] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 612 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. Set the temperature to 100°C.

[0276] Note that heat treatment may be performed after the insulating film 612 is formed. In an inert gas atmosphere such as nitrogen or rare gas, an oxygen gas atmosphere, or ultra-dry air (CR Water when measured using a DS (cavity ring-down laser spectroscopy) dew point meter The amount should be 20 ppm or less (-55°C in dew point equivalent), preferably 1 ppm or less, 0 ppb or less air), preferably at 200°C or more and 400°C or less, for example The heating is performed at 250° C. or more and 350° C. or less. In this embodiment, for example, the heating is performed at 250° C. or more in a nitrogen atmosphere. Alternatively, the source electrode 607 and the drain electrode 608 are connected to the wiring. Before forming the wirings 609 to 611, the oxide semiconductor film is subjected to the same heat treatment as that performed on the oxide semiconductor film. Similarly, RTA treatment may be performed at high temperature for a short time. Even if oxygen vacancies occur in the oxide semiconductor film 605 due to the treatment, the source electrode 60 The oxide semiconductor film 605 is provided between the drain electrode 608 and the oxide semiconductor film 605. After the insulating film 612 containing silicon is provided, heat treatment is performed, whereby an oxide semiconductor Therefore, oxygen is supplied to the oxide semiconductor film 605 at a portion where the oxide semiconductor film 605 is in contact with the insulating film 612. By providing oxygen to the region where oxygen is present, the oxygen vacancies that act as donors are reduced, and the stoichiometric composition ratio is satisfied. As a result, the oxide semiconductor film 605 can be made i-type or substantially i-type. This can improve the electrical characteristics of the transistor and reduce the variations in the electrical characteristics. The timing of this heat treatment can be determined as long as it is performed after the insulating film 612 is formed. It is not limited to this, and other processes, such as heat treatment during resin film formation and processes for reducing the resistance of the transparent conductive film, may be used. By performing the heat treatment for the oxide semiconductor film 605 at the same time as the heat treatment for the oxide semiconductor film 605, the oxide semiconductor film 605 can be formed into an i-type oxide semiconductor film without increasing the number of steps. It can be made into an i-type or substantially i-type.

[0277] Next, a conductive film is formed over the insulating film 612 and then patterned. A back gate electrode may be formed at a position overlapping the nitride semiconductor film 605. When forming a back gate electrode, an insulating film is formed so as to cover the back gate electrode. The gate electrode 601, the electrode 602, or the source electrode 607 and the drain electrode 608, The wirings 609 to 611 can be formed using the same material and structure.

[0278] The thickness of the back gate electrode is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a structure in which a titanium film, an aluminum film, and a titanium film are stacked is used. After forming the conductive film, a resist mask is formed by photolithography or the like, and Unnecessary portions are removed by etching, and the conductive film is processed (patterned) into a desired shape. By this, a back gate electrode is formed.

[0279] The insulating film prevents moisture, hydrogen, oxygen, etc. in the atmosphere from affecting the characteristics of the transistor. It is desirable to use a material with high barrier properties that can prevent the The insulating film may be a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film. A single layer or laminated layer of aluminum film is formed by plasma CVD or sputtering. To obtain a barrier effect, the insulating film can be formed to a thickness of, for example, 15 nm to 4 It is preferable to form the film with a thickness of 00 nm.

[0280] In this embodiment, a 300 nm insulating film is formed by plasma CVD. The film formation conditions are as follows: The flow rate of silane gas was set to 4 sccm, and the flow rate of nitrous oxide (NO) was set to 800 sccm. The substrate temperature is set to 400°C.

[0281] Through the above steps, a transistor 620 functioning as a switching element and a phase inversion element are formed. An n-channel transistor 520 and a p-channel transistor 521 that constitute the capacitor The capacitor element 623 is formed by connecting the electrode 602 and the source electrode 607. are formed in the overlapping region with the gate insulating film 603 sandwiched therebetween. The transistor 623 does not necessarily have to be formed on the same layer as the transistor 620; for example, The p-channel transistor 520 and the p-channel transistor 521 are formed on the same layer. is also good.

[0282] The transistor 620 includes a gate electrode 601 and a gate insulating film 603 on the gate electrode 601. and an oxide semiconductor film 601 overlapping the gate electrode 601 on the gate insulating film 603. 5 and a pair of source and drain electrodes 607 and 608 formed on the oxide semiconductor film 605. Further, the transistor 620 is formed over the oxide semiconductor film 605. The insulating film 612 may be included as a component of the transistor 62 shown in FIG. 0 is a portion of the oxide semiconductor film 605 between the source electrode 607 and the drain electrode 608. The channel etch structure has an exposed portion.

[0283] Although the transistor 620 has been described as a single-gate transistor, If necessary, a plurality of electrically connected gate electrodes 601 may be provided to form a channel. A transistor having a multi-gate structure having multiple regions can also be formed.

[0284] The band gap of oxide semiconductors is 3.0 to 3.5 eV. The band gap of gallium nitride is 3.39 eV, and Both have a band gap approximately three times larger than that of silicon. Compound semiconductors such as silicon and gallium nitride are wide-gap semiconductors. The characteristic of a large band gap, which is common to oxide semiconductors, is a factor that contributes to the breakdown voltage of semiconductor devices. Furthermore, it is advantageous in reducing power loss.

[0285] However, compound semiconductors such as silicon carbide and gallium nitride have higher proton density than oxide semiconductors. The process temperature for silicon carbide is approximately 1500°C, and the process temperature for gas nitride is approximately 1500°C. The process temperature for lithium is about 1100°C, and both are easily available silicon wafers and low-temperature gallium. Therefore, it is not possible to use inexpensive substrates and the size of the substrate is large. Therefore, semiconductors using compound semiconductors such as silicon carbide and gallium nitride are used. On the other hand, oxide semiconductors are formed by heat treatment at temperatures between 300°C and 850°C. It is possible to form a film on a glass substrate. In this way, semiconductor elements made of oxide semiconductors are stacked on an integrated circuit made of ordinary semiconductor materials. It is also possible to make it so.

[0286] Next, as in this embodiment, impurities such as moisture or hydrogen contained in the oxide semiconductor film are removed. How removing as much as possible and purifying the oxide semiconductor film affects the characteristics of transistors The impact will be explained below.

[0287] FIG. 19 is a cross-sectional view of a transistor using an oxide semiconductor. An oxide semiconductor film (OS) is provided via a gate insulating film (GI), and a source electrode is formed on top of it. (S) and drain electrode (D) are provided, and on the source electrode (S) and drain electrode (D) An insulating film is provided on the

[0288] FIG. 20 shows an energy band diagram (schematic diagram) in the cross section A-A' shown in FIG. In FIG. 20, black circles (●) represent electrons, white circles (○) represent holes, and each represents a charge. When a positive voltage (VD>0) is applied to the drain electrode (D), The dashed line indicates when no voltage is applied to the gate electrode (GE) (VG=0), and the solid line indicates when the gate electrode This shows the case where a positive voltage (VG>0) is applied to the gate electrode (GE). When no voltage is applied, the high potential barrier causes the source electrode (S) to flow through the oxide semiconductor film (O S) side, no carriers (electrons) are injected, and no current flows. When a positive voltage is applied to the electrode (GE), the potential barrier decreases, and the oxide semiconductor film (OS ) indicates the ON state where current flows.

[0289] FIG. 21 is an energy band diagram (schematic diagram) in the cross section taken along line B-B' in FIG. Figure 21(A) shows the state where a positive voltage (VG>0) is applied to the gate electrode (GE), This shows the on-state where carriers (electrons) flow between the source electrode and the drain electrode. FIG. 21(B) shows a state in which a negative voltage (VG<0) is applied to the gate electrode (GE). This shows the case where the power is off.

[0290] Figure 22 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor Shows.

[0291] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are generally n-type, and in this case the Fermi level (Ef) is Located away from the intrinsic Fermi level (Ei) in the center of the gap and closer to the conduction band (Ec) In the oxide semiconductor, some of the hydrogen acts as a donor, and the oxide semiconductor becomes an n-type It is known that oxygen vacancies are one of the factors that cause n-type It is known that there is.

[0292] In contrast, one embodiment of the present invention is a method for forming an oxide semiconductor by removing hydrogen, which is an n-type impurity, from an oxide semiconductor. The semiconductor is highly purified to minimize the amount of impurities other than the main component of the compound semiconductor, and oxygen deficiency is eliminated. By removing the oxide semiconductor, the oxide semiconductor becomes intrinsic (i-type) or as close to intrinsic as possible. That is, instead of adding impurities to make the oxide semiconductor i-type, moisture or hydrogen is added. By removing impurities such as oxygen vacancies and purifying the material as much as possible, it is possible to obtain an i-type (intrinsic semiconductor) or The feature of this method is that an oxide semiconductor that is as close as possible to an i-type (intrinsic semiconductor) is obtained. As a result, the Fermi level (Ef) is at the same level as the intrinsic Fermi level (Ei), as shown by the arrow. You can get as close as possible to the bell.

[0293] The band gap (Eg) of the oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4.3 V. When the material constituting the source electrode and the drain electrode is titanium (Ti), The work function of the metal-oxide semiconductor is approximately equal to the electron affinity (χ) of the oxide semiconductor. At the semiconductor interface, no Schottky barrier is formed for electrons. There are materials that meet this condition.

[0294] At this time, the electrons are transferred to the gate insulating film and the highly purified oxide semiconductor as shown in FIG. The electrons move through the lowest energetically stable part on the oxide semiconductor side at the interface with the oxide semiconductor.

[0295] In addition, in FIG. 21(B), when a negative voltage is applied to the gate electrode (GE), the minority capacitance Since the rear hole is substantially zero, the current is close to zero.

[0296] For example, if the channel width (W) is 1×10 6 The device had a channel length (L) of 10 μm. However, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -1 3A characteristic of less than A can be obtained. As a gate insulating film having a highly purified oxide semiconductor film, a thickness of 100 nm transistor, the charge amount per unit time of the storage capacitance is monitored. When measuring the off-state current of the transistor, the voltage between the source and drain electrodes is 3 For V, even lower off-state current densities of 10 zA / μm to 100 zA / μm are obtained. That is, a transistor using a highly purified oxide semiconductor film as an active layer has the following characteristics: The off-state current density is 100 zA / μm or less, preferably 10 zA / μm or less, and more preferably Or it can be made 1zA / μm or less.

[0297] In this way, impurities such as moisture or hydrogen other than the main components of the oxide semiconductor are contained as little as possible. Thus, by purifying the oxide semiconductor film, the operation of the transistor can be improved. It is possible.

[0298] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0299] (Embodiment 5) In this embodiment, the structure of a transistor including an oxide semiconductor film is different from that in Embodiment 4. The structure of the transistor will be described.

[0300] The memory device shown in FIG. 12(A) is an n-channel memory device using crystalline silicon, similar to the fourth embodiment. The transistor 520 includes a p-channel transistor 521. In FIG. 12A, an n-channel transistor 520 and a p-channel transistor 5 21, a bottom-gate transistor having a channel protection structure using an oxide semiconductor film 630 is formed.

[0301] The transistor 630 includes a gate electrode 631 formed on an insulating film 532 and a gate electrode 632. 31, and a gate insulating film 632 overlapping with the gate electrode 631 on the gate insulating film 632. The oxide semiconductor film 633 is formed on the gate electrode 631. The oxide semiconductor film 633 is formed on the gate electrode 631. A channel protective film 634 formed on the semiconductor film 633 and a The transistor 63 further includes a source electrode 635 and a drain electrode 636. The insulating film 637 formed over the oxide semiconductor film 633 may be included as a component of the insulating film 637. stomach.

[0302] By providing the channel protective film 634, the channel formation region of the oxide semiconductor film 633 Damage to the part that will be damaged during subsequent processes (such as plasma during etching or etching) This prevents film thinning caused by adhesives, thus improving the reliability of the transistor. It is possible.

[0303] The channel protection film 634 is made of an inorganic material containing oxygen (silicon oxide, silicon nitride oxide, silicon oxynitride, etc.). Aluminum oxide, aluminum oxynitride, etc.) can be used. The protective film 634 is formed by vapor deposition such as plasma CVD or thermal CVD, or by sputtering. The channel protection film 634 can be formed by etching after the film formation. Here, a silicon oxide film is formed by sputtering, and then photolithography is performed. The channel protective film 634 is formed by etching using a mask made of the above material.

[0304] By using an inorganic material containing oxygen for the channel protective film 634, moisture or hydrogen is reduced. Even if oxygen vacancies are generated in the oxide semiconductor film 633 by the heat treatment for the oxidation, the oxygen Oxygen is supplied to at least the regions of the compound semiconductor film 633 that are in contact with the channel protection film 634. It is possible to provide oxygen to reduce the oxygen vacancies that act as donors and achieve a structure that satisfies the stoichiometric composition ratio. Therefore, the channel forming region can be made i-type or substantially i-type. This reduces the variation in the electrical characteristics of transistors due to element deficiency, thereby improving the electrical characteristics. This can be done.

[0305] The transistor 630 further includes a back gate electrode over the insulating film 637. The back gate electrode may be formed so as to overlap with a channel formation region of the oxide semiconductor film 633. The back gate electrode can be formed even in an electrically insulated floating state. In the latter case, the back gate electrode may be in a state where a potential is applied. The potential may be the same as that of the port electrode 631, or may be a fixed potential such as ground. By controlling the level of the potential applied to the back gate electrode, The threshold voltage of the transistor 630 can be controlled.

[0306] The memory device shown in FIG. 12B is an n-channel memory device using crystalline silicon, similar to the fourth embodiment. The transistor 520 includes a p-channel transistor 521. In FIG. 12B, an n-channel transistor 520 and a p-channel transistor 52 A bottom-contact transistor 640 using an oxide semiconductor film is formed on the semiconductor substrate 1. There are.

[0307] The transistor 640 includes a gate electrode 641 formed on the insulating film 532 and a gate electrode 642. A gate insulating film 642 on the gate insulating film 642, a source electrode 643 on the gate insulating film 642, a drain electrode The gate electrode 641 has an oxide semiconductor film 645 overlapping with the electrode 644 and the gate electrode 641. The transistor 640 has an insulating film 646 formed over an oxide semiconductor film 645. It may be included in the composition element.

[0308] In the case of a bottom contact type transistor 640 of the type shown in FIG. 12(B), the source The thicknesses of the electrode 643 and the drain electrode 644 are determined so that the oxide semiconductor film 645 to be formed later will be stepped. In order to prevent leakage, it is necessary to make it thinner than the bottom gate type shown in the fourth embodiment. Specifically, it is 10 nm to 200 nm, preferably 50 nm to 75 nm.

[0309] The transistor 640 further includes a back gate electrode on the insulating film 646. The back gate electrode may be formed so as to overlap with a channel formation region of the oxide semiconductor film 645. The back gate electrode can be formed even in an electrically insulated floating state. In the latter case, the back gate electrode may be in a state where a potential is applied. The potential may be the same as that of the port electrode 641, or may be a fixed potential such as ground. By controlling the level of the potential applied to the back gate electrode, The threshold voltage of the transistor 640 can be controlled.

[0310] The memory device shown in FIG. 12C is an n-channel memory device using crystalline silicon, similar to the fourth embodiment. The transistor 520 includes a p-channel transistor 521. In FIG. 12C, an n-channel transistor 520 and a p-channel transistor 52 A top-gate transistor 650 using an oxide semiconductor film is formed on the semiconductor substrate 1. .

[0311] The transistor 650 has a source electrode 651 and a drain electrode 652 formed on the insulating film 532. 52, an oxide semiconductor film 653 formed on the source electrode 651 and the drain electrode 652, , a gate insulating film 654 on the oxide semiconductor film 653, and an oxide film on the gate insulating film 654. The gate electrode 655 overlaps the semiconductor film 653. 50 may include an insulating film 656 formed on a gate electrode 655 as a component thereof. .

[0312] In the case of the top-gate transistor 650 of FIG. 12(C), the source electrode The thickness of the drain electrode 652 is set to prevent the oxide semiconductor film 653 to be formed later from being broken. To prevent this, it is desirable to make it thinner than the bottom gate type shown in the fourth embodiment. Specifically, the thickness is set to 10 nm to 200 nm, preferably 50 nm to 75 nm.

[0313] Furthermore, a memory device according to one embodiment of the present invention is manufactured using a bulk single-crystal semiconductor substrate. The transistors may be used to fabricate phase inversion elements, switching elements, etc. A transistor using an oxide semiconductor is formed on a transistor formed using a bulk single-crystal semiconductor substrate. 1 is a cross-sectional view of a memory device in which a transistor having a thickness of 100 nm is formed, as an example.

[0314] The memory device shown in FIG. 23 includes an n-channel transistor 66 formed on a semiconductor substrate 660. 1 and p-channel transistor 662, and n-channel transistor 661 and p-channel transistor A capacitive switching element formed on an insulating film 663 covering a panel transistor 662. The image sensor includes a transistor 664 and a capacitor 665 used as a switching element.

[0315] The transistor 664 is a transistor whose channel formation region is formed using an oxide semiconductor. 12. It may have the following structure.

[0316] The semiconductor substrate 660 may be, for example, a single crystal silicon substrate having n-type or p-type conductivity, Compound semiconductor substrates (GaAs substrates, InP substrates, GaN substrates, SiC substrates, sapphire substrates) In FIG. 23, a single crystal having n-type conductivity can be used. A case where a silicon substrate is used is shown as an example.

[0317] The n-channel transistor 661 and the p-channel transistor 662 are element division transistors. The insulating film 666 is electrically isolated from the insulating film 666. , selective oxidation method (LOCOS (Local Oxidation of Silicon) method) or trench isolation method, etc. can be used.

[0318] The region where the p-channel transistor 662 is formed is doped with an impurity that imparts p-type conductivity. By selectively introducing elements, a region called a p-well 667 is formed. When a semiconductor substrate having p-type conductivity is used, an n-channel transistor 661 is formed. By selectively introducing impurity elements that give n-type conductivity into the region where n-type conductivity is to be formed, All that is required is to form a well.

[0319] This embodiment mode can be implemented in combination with the above embodiment modes.

[0320] (Sixth embodiment) In this embodiment mode, a high-purity silicon nitride film is used as a switching element for controlling the supply of a power supply potential to a memory element. One embodiment of the present invention uses a transistor having a channel formation region made of a gate-doped oxide semiconductor. The configuration of the storage device according to the present invention will be described below.

[0321] FIG. 13A illustrates an example of the configuration of a memory device according to this embodiment. The memory device shown in FIG. 1 includes a switching element 401 and a memory element group having a plurality of memory elements 402. Specifically, each storage element 402 has the same structure as in the first embodiment to the second embodiment. 5 can be used. A high-level power supply potential V Furthermore, each memory element 402 included in the memory element group 403 is supplied with a signal DD. The potential of IN and the potential of the low-level power supply potential VSS are given.

[0322] In FIG. 13A, a switching element 401 is formed by using an oxide semiconductor in a channel formation region. The transistor has a gate electrode to which a signal The switching is controlled by SigA. Since the transistor has a highly purified oxide semiconductor in a channel formation region, the off-state current of the transistor is As mentioned above, it is significantly low.

[0323] In FIG. 13A, the switching element 401 has only one transistor. However, the present invention is not limited to this configuration. The element 401 may have a plurality of transistors. When a plurality of transistors functioning as switching elements are provided, the plurality of transistors The capacitors may be connected in parallel, in series, or in a combination of series and parallel. They may be joined and connected.

[0324] In FIG. 13A, the switching element 401 controls each of the memory element groups 403. The supply of a high-level power supply potential VDD to the storage element 402 is controlled. The supply of the low-level power supply potential VSS may be controlled by the switching element 401. 13(B), each memory element 402 included in the memory element group 403 is provided with a switching element 401. 1 shows an example of a memory device to which a low-level power supply potential VSS is supplied via a switch. The switching element 401 transmits low-level signals to each memory element 402 in the memory element group 403. The supply of the power supply potential VSS of the filter can be controlled.

[0325] Next, the oxide semiconductor layer described in Embodiment 4 or 5 is formed in the channel formation region. A power device that can control higher voltages or currents than the transistors used The structure of a transistor having the above structure will be described below. By using it for the switching element 401, the reliability of the memory device can be further improved. Note that the same parts as those in the fourth or fifth embodiment or parts having similar functions and processes are The process can be performed in the same manner as in the fourth or fifth embodiment, so repeated explanation is not necessary. is omitted.

[0326] FIG. 14A is a cross-sectional view of a transistor 420 described in this embodiment. 14B is a top view of the transistor 420, and is a diagram showing the structure of the transistor 420 along the dashed line B1-B2 in FIG. The cross-sectional view corresponds to FIG.

[0327] The transistor 420 has a first electrode 421 on an insulating surface.

[0328] The first electrode 421 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. a metal element selected from the group consisting of tungsten and yttrium, or a compound containing the above-mentioned metal elements It is made of gold, an alloy combining the above metal elements, etc. The metal element is selected from one or more of aluminum, zirconium, and beryllium. The first electrode 421 can have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, or a layer of an aluminum film Two-layer structure with titanium film stacked, two-layer structure with titanium film stacked on tungsten film, titanium A titanium film is then formed on top of the aluminum film. Also, aluminum can be combined with titanium, tantalum, and tungsten. One or more elements selected from the group consisting of silicon, molybdenum, chromium, neodymium, and scandium Combination films, alloy films, or nitride films may also be used.

[0329] The first electrode 421 is made of indium tin oxide or indium containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the conductive material having light-transmitting properties and the metal element may be laminated together.

[0330] The first electrode 421 is formed by depositing a conductive film on an insulating surface by sputtering, CVD, or vacuum evaporation. a resist mask is formed over the conductive film by a photolithography process; The conductive film can be formed by etching using the resist mask. The first electrode 421 is formed by a printing method or an ink-jet method without using a photolithography process. By doing so, the number of steps can be reduced. This is preferable because it improves the coverage of the gate insulating film that will be formed later. The angle between the end of the first electrode 421 and the insulating surface on which the first electrode 421 is formed is set to 30° or more. By setting the angle to 0° or less, preferably 40° to 50°, the gate insulating film to be formed later can be This can improve the coverage of the surface.

[0331] In this embodiment, a conductive film to be the first electrode 421 is formed by a sputtering method. A 50 nm titanium film is formed, a 100 nm aluminum film is formed, and a 50 nm Next, a resist mask formed by a photolithography process is used to form a titanium film. The first electrode 421 is formed by etching using a photolithography process. Instead of a resist mask formed by a method using a photoresist, a resist mask was formed by an ink-jet method. By manufacturing the product in this manner, the number of steps can be reduced.

[0332] The transistor 420 includes an island-shaped oxide semiconductor film 422 over a first electrode 421. The oxide semiconductor film 422 can be formed by a sputtering method, a coating method, a printing method, or the like. In this embodiment, an oxide semiconductor is formed on the first electrode 421 by sputtering. After forming the oxide semiconductor film, the oxide semiconductor film is processed into a desired shape by etching or the like. The island-shaped oxide semiconductor film 422 is formed by oxidizing a rare gas (e.g., argon), oxygen, or a rare gas (e.g., argon) and oxygen atmosphere The film can be formed by sputtering.

[0333] Note that the etching for forming the island-shaped oxide semiconductor film 422 is the same as that described in Embodiment 4. In addition, the etching of the oxide semiconductor film may be performed by referring to the description of the etching of the oxide semiconductor film. The edge of the island-shaped oxide semiconductor film 422 formed by etching and the first electrode 421 are The angle is set to 30° or more and 60° or less, preferably 40° or more and 50° or less, so that the This is preferable because it can improve the coverage of the gate insulating film to be formed.

[0334] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Inverse sputtering is performed to generate a smear, and dust adhering to the surface of the first electrode 421 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply below, forming plasma near the substrate and modifying the surface. It is to be noted that nitrogen, helium, etc. may be used instead of the argon atmosphere. Alternatively, the heating may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. Alternatively, the treatment may be carried out in an atmosphere containing chlorine, carbon tetrafluoride, or the like added to the fluorine atmosphere.

[0335] The oxide semiconductor film 422 can be formed using any of the above oxide semiconductors.

[0336] In this embodiment, an acid containing In (indium), Ga (gallium), and Zn (zinc) is used. 30 nm thick In-Ga-Z obtained by sputtering using an In-Ga-Zr nitride semiconductor target An nO-based non-single-crystal film is used as the oxide semiconductor film 422. For example, the atomic ratio of each metal is In:Ga:Zn=1:1:0.5, In:Ga:Zn= Use a metal oxide target with a ratio of 1:1:1 or In:Ga:Zn=1:1:2 The oxide semiconductor film can be formed by heating under a rare gas (typically, argon) atmosphere with oxygen. Sputtering in an atmosphere or in an atmosphere of rare gas (typically argon) and oxygen When the sputtering method is used, the SiO2 layer can be formed by doubling the The film may be formed using a target containing In, Ga in an amount of 10% by weight or more. and the filling rate of the metal oxide target containing Zn is 90% or more and 100% or less, preferably The filling rate is 95% or more and 99.9%. By using a metal oxide target with a high filling rate, The formed oxide semiconductor film becomes a dense film.

[0337] The substrate is held in a processing chamber maintained in a reduced pressure state, and hydrogen and The sputtering gas from which the moisture and oxygen have been removed is introduced, and the metal oxide is used as the target to deposit oxide on the substrate. During the film formation, the substrate temperature is preferably set to 100° C. or higher and 600° C. or lower. The temperature may be 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump. As an exhaust means, a turbo pump with a A cryopump may be used to evacuate the processing chamber. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon atoms Since the exhaust gas contains the oxide semiconductor film formed in the treatment chamber, The concentration of impurities can be reduced.

[0338] In this embodiment, as an example of the film formation conditions for the oxide semiconductor film, the substrate temperature is room temperature, and the substrate and the substrate are heated. The distance between the getter and the target was 110 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and oxygen and argon (oxygen flow rate 15 sccm: argon flow rate 30 sccm) atmosphere conditions are suitable. When a pulsed direct current (DC) power supply is used, the particles generated during film formation are This is preferable because it can reduce dust particles, which are called oxide semiconductor films, and the film thickness distribution is uniform. is 1 μm or more, preferably 3 μm or more, and more preferably 10 μm or more. The appropriate thickness varies depending on the oxide semiconductor film material used, and the thickness should be selected appropriately depending on the material. That's fine.

[0339] Note that in order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film 422 as much as possible, Therefore, as a pre-treatment for film formation, the first electrode 421 is formed in the pre-heating chamber of the sputtering device. The formed substrate is preheated, and impurities such as hydrogen and moisture adsorbed on the substrate are desorbed and exhausted. The preheating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 150°C or lower. The temperature is preferably 300°C or higher. The exhaust means provided in the preheating chamber is preferably a cryopump. This preheating process can be omitted. Before the formation of the film, the same process may be carried out on a substrate on which a gate electrode has already been formed.

[0340] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and D There is also the pulsed DC sputtering method, which applies a bias in a pulsed manner. The RF sputtering method is mainly used to form insulating films, while the DC sputtering method The tarring method is mainly used when forming a metal film.

[0341] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0342] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0343] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0344] The oxide semiconductor film 422 is heated in an inert gas atmosphere such as nitrogen or a rare gas under a reduced pressure atmosphere. under an oxygen gas atmosphere or ultra-dry air (CRDS (cavity ring down laser separation) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). In an atmosphere of 1 ppm or less, preferably 10 ppb or less (air), By performing heat treatment on the oxide semiconductor film 422, moisture and hydrogen are removed. Specifically, the oxide semiconductor film 422 is formed at a temperature higher than or equal to 300° C. and lower than or equal to 850° C. (at least The RTA method can be used to heat the glass substrate at a temperature below the strain point. Dehydration or dehydrogenation can be achieved in a short time, so processing can be performed even at temperatures exceeding the strain point of the glass substrate. In this embodiment, an electric furnace, which is one of the heat treatment devices, is used to heat an oxide semiconductor. The substrate film 422 is heated to 450° C. in a nitrogen atmosphere for 1 hour. After the heat treatment, the oxide semiconductor is prevented from coming into contact with the air and from being recontaminated with water or hydrogen. The film 422 becomes an i-type (intrinsic semiconductor) or i-type due to the desorption of impurities such as moisture and hydrogen. Since the impurities mentioned above cause the threshold voltage to shift, the characteristics of the transistor This can prevent the deterioration of the device's properties from being accelerated and reduce the off-state current.

[0345] For a detailed description of the heat treatment device used in the heat treatment, see the embodiment. This has already been mentioned in 4, so it will be omitted here.

[0346] In addition, in the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable that the concentration is 0.1 ppm or less.

[0347] In addition, the gate bias thermal stress test (BT test, test conditions are, for example, 85°C, 2×1 0 6 V / cm, 12 hours), when impurities are added to the oxide semiconductor, the impurities The bonds between the material and the main component of the oxide semiconductor are formed by a strong electric field (B: bias) and high temperature (T: temperature). The resulting dangling bonds induce a drift in the threshold voltage (Vth). However, as described above, in order to improve the interface characteristics between the gate insulating film and the oxide semiconductor film, Furthermore, impurities, particularly hydrogen and water, in the oxide semiconductor film are removed as much as possible. A stable transistor is obtained even in the BT test.

[0348] Through the above steps, the concentration of hydrogen in the oxide semiconductor film can be reduced and the oxide semiconductor film can be highly purified. This makes it possible to stabilize the oxide semiconductor film. By heat treatment, an oxide semiconductor film with extremely low carrier density and a wide band gap is formed. Therefore, a transistor can be fabricated using a large-area substrate. Therefore, mass productivity can be improved. By using a semiconductor film, it is possible to achieve high voltage resistance, low short channel effect, and high on-off ratio. Therefore, it is possible to fabricate a high-performance transistor.

[0349] The transistor 420 further includes a second electrode 423 over the oxide semiconductor film 422. The material and structure of the conductive film used for the second electrode 423 are the same as those of the first electrode 421. The second electrode 423 can be formed by the same method as that of the first electrode 423. It can be implemented in the same manner as electrode 421.

[0350] In this embodiment, a photolithography process is performed to form a pattern on a conductive film that is to be the second electrode 423. A resist mask is formed, and the conductive film is etched using the resist mask to form a second conductive film. Here, a conductive film having a thickness of 50 nm is used as the second electrode 423. A titanium film, an aluminum film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm are stacked in this order. The angle between the edge of the second electrode 423 and the oxide semiconductor film 422 is set to be greater than or equal to 30° and greater than or equal to 60°. 50° or less, preferably 40° to 50°, This is preferable because it can improve coverage. The second electrode 421 is formed at a position spaced apart from the first electrode 421 without contacting the first electrode 421 .

[0351] One of the first electrode 421 and the second electrode 423 is a source electrode of the transistor, and the other is a The other electrode functions as the drain electrode.

[0352] After the second electrode 423 is formed, heat treatment may be performed. The temperature is set to 850° C. or lower, preferably 400° C. or higher but lower than the strain point of the substrate. The substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and nitrogen is applied to the oxide semiconductor film 422. The heat treatment was carried out at 450°C for 1 hour under an inert gas atmosphere such as a rare gas. After that, by not exposing the oxide semiconductor film to the air, hydrogen, water, a hydroxyl group, hydride, or the like is prevented from being added to the oxide semiconductor film. By preventing re-entry of hydrogen, the hydrogen concentration is further reduced and the hydrogen is highly purified, resulting in i-type or substantially Therefore, an i-type oxide semiconductor film can be obtained.

[0353] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that hydrogen, water, hydroxyl groups, hydrides, etc. are not contained in the additive. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment equipment is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., non- It is preferable to keep the concentration of impurities at 1 ppm or less, preferably 0.1 ppm or less.

[0354] The transistor 420 includes a first electrode 421, an oxide semiconductor film 422, a second electrode 4 23, a gate insulating film 424 is formed to cover the gate insulating film 424. The gate insulating film 424 is formed by plasma CVD or sputtering. Using the ring method, silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, oxide Aluminum film, aluminum nitride film, aluminum oxynitride film, aluminum nitride oxide film The film, hafnium oxide film or tantalum oxide film can be formed as a single layer or a laminate. do.

[0355] The gate insulating film 424 is made of hafnium silicate (HfSiO x ), N is added HfSi x O y , nitrogen-doped hafnium aluminate (HfAlO x ), oxidation Leakage current is reduced by using high-k materials such as hafnium and yttrium oxide Furthermore, high-k materials and silicon oxide films, silicon nitride films, silicon oxynitride films, A laminated structure of one or more of a silicon film, a silicon nitride oxide film, or an aluminum oxide film The thickness of the gate insulating film 424 is set to 50 nm or more and 500 nm or less. By increasing the thickness of the gate insulating film 424, leakage current can be reduced. Cut.

[0356] It is desirable that the gate insulating film 424 contains as little impurities as possible, such as moisture and hydrogen. When forming a silicon oxide film by the tar- ping method, a silicon target is used as the target. A quartz or silica target is used, and oxygen or a mixture of oxygen and argon is used as the sputtering gas. This is done using a

[0357] By removing impurities, an oxide semiconductor that has been made i-type or substantially i-type (highly purified) Since the gate insulating film (oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface with the gate insulating film 424 is important. The membrane (GI) is required to be of high quality.

[0358] For example, high density plasma CVD using microwaves (2.45 GHz) produces dense, high dielectric strength films. This is preferable because it allows the formation of a high-quality insulating film. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0359] Of course, if a good insulating film can be formed as the gate insulating film 424, sputtering is also possible. Other film formation methods such as the ring method and plasma CVD method can be applied. The insulating film 424 and the interface characteristics with the oxide semiconductor are modified by the heat treatment. In any case, it is of course important that the film quality as a gate insulating film is good. If the interface state density with the oxide semiconductor can be reduced and a good interface can be formed, good.

[0360] Insulating films made of materials with high barrier properties, silicon oxide films with a low nitrogen content, and oxynitride films A gate insulating film 424 having a structure in which an insulating film such as a silicon film is laminated may be formed. In this case, the insulating film such as a silicon oxide film or a silicon oxynitride film has a barrier property and an oxidizing property. The insulating film with high barrier properties is formed between the semiconductor film, for example, silicon nitride film, nitride oxide film, etc. Examples of the barrier include a silicon film, an aluminum nitride film, and an aluminum nitride oxide film. By using an insulating film with this property, impurities in the atmosphere such as moisture or hydrogen, or Impurities such as alkali metals and heavy metals contained in the oxide semiconductor film and the gate insulating film 42 4, or the interface between the oxide semiconductor film and other insulating films and its vicinity. In addition, a silicon oxide film or a silicon oxynitride film having a low nitrogen ratio that is in contact with the oxide semiconductor film can be used. By forming an insulating film such as a bare film, the insulating film made of a material with high barrier properties is directly formed on the oxide semiconductor. This can prevent contact with the conductive film.

[0361] For example, a silicon oxide film (S) having a thickness of 5 nm to 300 nm is used as the first gate insulating film. iO x (x>0)) is formed on the first gate insulating film, and a second gate insulating film is sputtered on the first gate insulating film. Silicon nitride film (SiN) with a thickness of 50 nm to 200 nm is formed by the deposition method. y (y>0 )) may be stacked to form a gate insulating film with a thickness of 100 nm. 0.4 Pa, high frequency power supply 1.5 kW, oxygen and argon (oxygen flow rate 25 sccm: argon A 100 nm thick film was deposited by RF sputtering under an atmosphere with a flow rate of 25 sccm (1:1). A silicon oxide film is formed.

[0362] In order to prevent hydrogen, hydroxyl groups, and moisture from being contained in the gate insulating film 424 as much as possible, As a pretreatment for film formation, the first electrode 421, the oxide The substrate on which the semiconductor film 422 and the second electrode 423 are formed is preheated to remove the water adsorbed on the substrate. It is preferable to desorb and exhaust impurities such as oxygen and moisture. The temperature is 0°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The exhaust means to be provided is preferably a cryopump. Note that this preheating process may be omitted. It is also possible.

[0363] Note that heat treatment may be performed after the gate insulating film 424 is formed. In an atmosphere or inert gas atmosphere (nitrogen, helium, neon, argon, etc.) The heating temperature is preferably 200° C. or higher and 400° C. or lower, for example 250° C. or higher and 350° C. or lower. In this embodiment, for example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. By the heat treatment, the oxide semiconductor film 422 comes into contact with silicon oxide which forms the gate insulating film 424. The heat treatment for desorbing moisture and hydrogen as described above will result in the oxidation of the material. Even if an oxygen deficiency occurs, oxygen is supplied from silicon oxide, and the donor oxygen is The oxide semiconductor film can have a structure in which the element vacancy is reduced and the stoichiometric composition ratio is satisfied. 422 can be made into i-type or substantially i-type. The step is not particularly limited as long as it is performed after the formation of the gate insulating film 424, and may be performed in other steps, for example, after the formation of the gate insulating film 424. The gate electrode 425, the insulating film 426, or the wiring 434, the wiring 435, and the wiring 436 are The heat treatment for reducing the resistance of the transparent conductive film may be performed after forming either one of the above. By combining this with other heat treatments such as heating, the number of steps can be reduced.

[0364] The material of the gate electrode 425 is molybdenum, titanium, chromium, tantalum, tungsten, nickel, or the like. Conductors made of metal materials such as chromium and scandium, and alloy materials whose main components are these metal materials. The conductive film or nitride of these metals can be used as a single layer or a laminate. If it can withstand the temperature of the heat treatment performed in the process, aluminum is used as the metal material. Aluminum or copper can be used. Aluminum or copper can avoid the problems of heat resistance and corrosion. To avoid this, it is recommended to use it in combination with high melting point metal materials. Molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. You can be there.

[0365] For example, a gate electrode 425 having a two-layer stack structure may be formed by depositing molybdenum on an aluminum film. a two-layer structure with a molybdenum film laminated on a copper film, or a two-layer structure with a molybdenum film laminated on a copper film, or a two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film; It is preferable to have a two-layer structure in which a molybdenum film is laminated. The electrode 425 may be an aluminum film, an aluminum-silicon alloy film, or an aluminum The intermediate layer is an alloy film of aluminum and titanium or an alloy film of aluminum and neodymium, and the The structure is a laminate of a tungsten nitride film, a titanium nitride film, or a titanium film as upper and lower layers. It is preferable that

[0366] In addition, the gate electrode 425 may be made of indium oxide, indium tin oxide, indium oxide zinc oxide, or the like. Lead alloys, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, or zinc oxide gas By using a light-transmitting conductive oxide film such as silicon as the gate electrode 425, the opening of the pixel portion can be The rate of speech can be improved.

[0367] The thickness of the gate electrode 425 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a 150 nm film is formed by sputtering using a tungsten target. After forming a conductive film for the gate electrode of m, the conductive film is etched into a desired shape. The gate electrode 425 is formed by patterning. At least, the gate insulating film 424 is provided between the oxide semiconductor film 422 and the oxide semiconductor film 422. The gate insulating film 424 is formed at the edge of the oxide semiconductor film 422. A channel forming region is formed in the portion where the gate electrode 425 overlaps with the insulating film 424. If the end of the formed gate electrode 425 is tapered, the insulating film 42 laminated thereon may be formed in a tapered shape. It is preferable because the coating property of 6 is improved. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0368] The transistor 420 includes a first electrode 421, an oxide semiconductor film 422, a second electrode 4 23, an insulating film 426 is provided to cover the gate insulating film 424 and the gate electrode 425. The insulating film 426 preferably contains as little impurities as possible, such as moisture and hydrogen. The insulating film 42 may be an insulating film, or may be composed of a plurality of laminated insulating films. 6 is, for example, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film. oxide insulating films such as aluminum films, silicon nitride films, silicon nitride oxide films, aluminum nitride films, Alternatively, an oxide insulating film and a nitride insulating film such as an aluminum nitride oxide film are used. The insulating film 426 may be a laminate of an insulating film having a high barrier property, e.g., a silicon dioxide insulating film. For example, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film. By using a film or the like, it is possible to form a thin film in the oxide semiconductor film 422, the gate insulating film 424, or the oxide semiconductor film 423. Impurities such as moisture or hydrogen enter the interface between the compound semiconductor film 422 and other insulating films and the vicinity thereof. It can prevent it from getting in.

[0369] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 426 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. When the insulating film 426 is formed by sputtering, the substrate is heated at 100° C. to 4 High-purity nitrogen is heated to a temperature of 00°C and hydrogen, water, hydroxyl groups, hydrides, etc. are removed. A sputtering gas containing silicon is introduced and an insulating film 426 is formed using a silicon semiconductor target. In this case, hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the processing chamber may also be removed. It is preferable to form the insulating film while removing the insulating film.

[0370] Note that heat treatment may be performed after the insulating film 426 is formed. In an atmosphere (nitrogen, helium, neon, argon, etc.), preferably at 200°C The heating is carried out at a temperature of 250°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower.

[0371] The contact holes 431, 432, and 433 are photoresist holes. A resist mask is formed by a lithography process, and the gate insulating film 424 and the insulating film 426 The contact hole 431 can be formed by selectively removing a part of the This exposes a portion of the gate electrode 425. The contact hole 432 allows A part of the electrode 423 is exposed. When these contact holes are formed, the gate electrode of the first electrode 421 is exposed. In the area not covered by the electrode 425, the first electrode 421 is exposed. A hole may be formed.

[0372] Then, contact holes 431 and 432 are formed in the insulating film 426. The gate electrode 425, the second electrode 423, and the gate electrode 4 25, wiring 434, wiring 435, and wiring 436 are connected to the When forming the wiring, the wiring connected to the first electrode 421 through the contact hole is formed. That's fine.

[0373] The wiring 434, the wiring 435, and the wiring 436 have the same structure and material as the first electrode 421. The conductive film can be used to form the insulating film by a similar manufacturing method.

[0374] In FIG. 14B, the wiring 440 is formed simultaneously with the wiring 434, the wiring 435, and the wiring 436. The wiring is connected to the first electrode 421 via the contact hole 441. do.

[0375] As described above, the concentration of hydrogen in the oxide semiconductor film can be reduced, and the oxide semiconductor film can be highly purified. The oxide semiconductor film can be stabilized by the heat treatment at a temperature equal to or lower than the glass transition temperature. This makes it possible to form an oxide semiconductor film with a very low carrier density and a wide band gap. Therefore, a transistor can be manufactured using a large-area substrate. In addition, the hydrogen concentration is reduced and the oxide semiconductor is highly purified. By using a thin film, the transistor has high voltage resistance, low short channel effect, and high on-off ratio. A transistor can be fabricated.

[0376] In this embodiment, a region of the oxide semiconductor film 422 that is different from the second electrode 423 is The entire portion formed in the region is covered with the gate electrode 425. The second electrode 423 may be formed in a region of the oxide semiconductor film 422 different from the region of the second electrode 423. At least a part of the exposed portion may be covered by the gate electrode 425.

[0377] Here, the drain resistance of the transistor described in this embodiment will be described.

[0378] When the electric field in the semiconductor reaches a certain threshold, impact ionization occurs, and the high electric field causes electrons to be generated in the depletion layer. The carriers accelerated by this force collide with the crystal lattice, generating electron-hole pairs. As the electron-hole pairs generated by impact ionization are further accelerated by the electric field, Repeated collision ionization leads to an avalanche breakdown, where the current increases exponentially. Ionization occurs when carriers (electrons, holes) gain kinetic energy greater than the band gap of a semiconductor. Therefore, the larger the band gap, the more likely it is that impact ionization will occur. The electric field required to generate this is high.

[0379] The band gap of oxide semiconductor is 3.15 eV, which is the same as that of amorphous silicon. Since this is larger than the 1.74 eV of the MOSFET, avalanche breakdown is unlikely to occur. Transistors using oxide semiconductors have a high drain breakdown voltage and can withstand high electric fields. This makes it difficult for an exponential rise in the on-state current to occur.

[0380] Next, hot carrier degradation of a transistor including an oxide semiconductor will be described.

[0381] Hot carrier degradation occurs when electrons accelerated to high speeds penetrate the gate insulating film near the drain in the channel. The charge is injected into the insulating film and becomes a fixed charge, or a trap level is formed at the gate insulating film interface. This leads to the deterioration of transistor characteristics such as threshold voltage fluctuation and leakage current. The cause of hot carrier degradation is channel hot electron injection (CHEE). Drain avalanche hot carrier injection (DAHC injection) and drain avalanche hot carrier injection (DAHC injection).

[0382] Since silicon has a narrow band gap, electrons are generated in an avalanche manner due to avalanche breakdown. The number of electrons accelerated to a high enough speed to overcome the barrier to the gate insulating film increases. However, since the oxide semiconductor described in this embodiment has a wide band gap, it is possible to form an avalanche It is less likely to experience shear breakdown and has higher resistance to hot carrier degradation than silicon. The band gap of silicon carbide, which is one of the piezoelectric materials, and the band gap of oxide semiconductors Although the electron mobility is similar, the oxide semiconductor has a mobility that is about two orders of magnitude smaller, so electrons are accelerated more easily. In particular, hot carrier degradation is less likely to occur than with silicon carbide, and the drain breakdown voltage is higher. I can say.

[0383] From the above, a transistor using an oxide semiconductor has a high drain breakdown voltage. A drain breakdown voltage of 100V or more, preferably 500V, and more preferably 1kV or more is possible.

[0384] Here, we compare silicon carbide, a typical example of a transistor, with oxide semiconductors. The following shows how 4H-SiC is used as silicon carbide.

[0385] Oxide semiconductors and 4H-SiC have several things in common. The intrinsic carrier density is For example, according to the Fermi-Dirac distribution, the intrinsic carrier density of an oxide semiconductor is 1 0 -7 cm -3 This is estimated to be about 6.7 × 10 in 4H-SiC. -1 1 cm -3 Similarly, this is an extremely low value.

[0386] The energy band gap of oxide semiconductors is 3.0 to 3.5 eV, and 4H-S The energy band gap of iC is 3.26 eV, so it is called a wide-gap semiconductor. Oxide semiconductors and silicon carbide have this in common as well.

[0387] However, the process temperatures for oxide semiconductors and silicon carbide are significantly different. Silicon carbide generally requires heat treatment at 1500 to 2000°C. Semiconductors can be fabricated by heat treatment at 300 to 850°C, and transistors can be formed on large-area substrates. This allows for the fabrication of transistors, and also increases throughput.

[0388] In addition, silicon carbide transistors use PN junctions, so donor or Because a doping process of impurities (phosphorus, boron, etc.) that can act as acceptors is required, On the other hand, a transistor using an oxide semiconductor does not have a PN junction. This allows for a reduction in manufacturing processes and an improvement in throughput, and also makes it possible to manufacture large-area substrates. It is possible to use.

[0389] In an oxide semiconductor, the DOS (density of scattering) in the band gap Although many studies have been conducted on the physical properties of the DOS, these studies have not fully investigated the DOS itself. In this embodiment, the idea of ​​oxidizing water and hydrogen, which can be the cause of DOS, is not included. By removing the oxide from the semiconductor, a highly purified oxide semiconductor is produced. This is based on the idea of ​​reducing the amount of waste as much as possible. This enables the production of industrial products that meet these requirements.

[0390] Furthermore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and oxygen vacancies are eliminated. By reducing the DOS, a more highly purified (i-type) oxide semiconductor can be obtained. For example, an oxide film containing excess oxygen is formed in close contact with the channel forming region, By supplying oxygen from the oxide film, it is possible to reduce DOS due to oxygen defects.

[0391] Defects in oxide semiconductors are caused by excess hydrogen at shallow levels 0.1 to 0.2 eV below the conduction band, or by oxide These defects are thought to be caused by deep levels due to a lack of elements. The technical idea of ​​thoroughly removing hydrogen and providing sufficient oxygen is correct. cormorant.

[0392] In addition, although oxide semiconductors are generally n-type, in this embodiment, impurities, particularly water and By removing hydrogen, the i-type structure is realized. In this respect, it is similar to semiconductors such as silicon. Compared to the conventional technological concept of adding impurities to create i-type, the technological concept of this invention is new. is.

[0393] In addition, by making the oxide semiconductor i-type, the temperature characteristics of the transistor are good. Generally speaking, the current-voltage characteristics of a transistor in the temperature range from -25°C to 150°C In this case, the on-current, off-current, field-effect mobility, S value, and threshold voltage fluctuate little. There is almost no deterioration in the current-voltage characteristics due to temperature.

[0394] Note that the transistor including an oxide semiconductor described in this embodiment is a transistor including an oxide semiconductor. Although the mobility is about two orders of magnitude lower than that of the transistors used, the Increasing the channel width (W) increases the transistor current value and improves device characteristics. It can be done.

[0395] The technical idea of ​​this embodiment is to provide a method for forming a semiconductor layer without adding any other substance to the oxide semiconductor. On the other hand, by intentionally removing impurities such as water and hydrogen that are unintentionally present, oxide semiconductors can be obtained. The purpose is to purify the conductor. In other words, to remove water or hydrogen that constitutes the donor level. Furthermore, by reducing oxygen vacancies and supplying sufficient oxygen to form the oxide semiconductor, The object is to highly purify the oxide semiconductor.

[0396] 10 at the time of oxide semiconductor film formation 20 cm -3 The hydrogen level is measured by SIMS (Secondary Ion Mass Spectroscopy) The water or hydrogen that causes this donor level is intentionally removed, and The oxygen (one of the components of oxide semiconductors) that is simultaneously reduced when water or hydrogen is removed is removed. By adding it to an oxide semiconductor, the oxide semiconductor is highly purified and electrically becomes an i-type (intrinsic) semiconductor. Conductor.

[0397] In this embodiment, the smaller the amount of water and hydrogen in the oxide semiconductor, the better. It is preferable that the carrier density is 1×10 14 cm -3 Less than 1 x 10 12 cm -3 less than, more preferably less than the measurement limit Bottom 1×10 11 cm -3 It is desirable to reduce carriers in the oxide semiconductor and By eliminating the intrinsic semiconductor, the The function of the oxide semiconductor is to act as a path for carriers to pass through. When the capacitor is in the off state, Ioff can be made extremely low. .

[0398] In addition, the oxide semiconductor functions as a path for carriers, and the oxide semiconductor itself It is an i-type (intrinsic) that has been highly purified to have no or very little carrier. The current is supplied by the source electrode and the drain electrode.

[0399] Note that the transistor having the structure described in this embodiment can be used in the same manner as in Embodiment 4. In contrast to a lateral transistor in which the channel is formed approximately parallel to the substrate, The occupied area can be reduced, which allows for miniaturization of transistors.

[0400] In this way, impurities other than the main components, typically hydrogen, water, hydroxyl groups, or hydrides, are extremely By purifying the oxide semiconductor film so that it does not contain any oxide, the operation of the transistor can be improved. In particular, it is possible to improve the breakdown voltage, reduce the short channel effect, and The turn-off ratio can be increased.

[0401] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0402] (Embodiment 7) In this embodiment, a method for forming an oxide semiconductor film, which is different from that in Embodiment 4, is described with reference to FIGS. This will be explained using:

[0403] First, gate electrodes 701 and 702 are formed on an insulating surface, and then gate electrodes 70 1. A gate insulating film 703 is formed on a gate electrode 702 (see FIG. 15(A)). The materials, structures, and film thicknesses of the electrode 701, gate electrode 702, and gate insulating film 703 are as follows: Since this has already been explained in the fourth embodiment, the details will be omitted in this embodiment. Abbreviated.

[0404] Next, as shown in FIG. 15(A), a film having a thickness of 2 nm to 15 nm is formed on the gate insulating film 703. The following first oxide semiconductor film 730 is formed. (typically argon) atmosphere, oxygen atmosphere, or a rare gas (e.g., argon) and an oxygen atmosphere It can be formed by sputtering in a nitrogen-mixed atmosphere.

[0405] Note that before the first oxide semiconductor film 730 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating film 703 to generate plasma. It is preferable to remove dust particles that may be present on the target. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is a method to modify the surface by using nitrogen or helium instead of argon atmosphere. Alternatively, the treatment may be carried out in an argon atmosphere to which oxygen, nitrous oxide, etc. have been added. Alternatively, the treatment may be carried out in an argon atmosphere to which chlorine, carbon tetrafluoride, or the like has been added.

[0406] The first oxide semiconductor film 730 can be formed using any of the above oxide semiconductors.

[0407] In this embodiment, gold containing In (indium), Ga (gallium), and Zn (zinc) is used. In-Ga-Zn- with a thickness of 5 nm obtained by sputtering using a metal oxide target An O-based non-single-crystal film is used as the first oxide semiconductor film 730. For example, if the atomic ratio of each metal is In:Ga:Zn=1:1:0.5, In:Ga:Zn A metal oxide target with In:Ga:Zn=1:1:1 or In:Ga:Zn=1:1:2 was used. In this embodiment, the crystallization is intentionally performed by performing heat treatment later. It is preferable to use a metal oxide target that is prone to crystallization. The filling rate of the metal oxide target containing Zn is 90% or more and 100% or less, preferably 95% or less. % or more and 99.9% or less. By using a metal oxide target with a high filling rate, The impurity concentration in the oxide semiconductor film to be formed can be reduced, and the electrical characteristics or reliability can be improved. Therefore, a transistor with high performance can be obtained.

[0408] The substrate is held in a processing chamber under reduced pressure, and hydrogen and moisture are removed while removing residual moisture in the processing chamber. The sputtering gas is introduced and the first oxide is deposited on the insulating surface using the metal oxide as a target. During the film formation, the substrate temperature is preferably set to 100° C. or higher and 600° C. or lower. The temperature may be 200°C or higher and 400°C or lower. The concentration of impurities contained in the sputtered oxide semiconductor film can be reduced. To remove residual moisture in the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump. As an exhaust means, a turbo pump with a A cryopump may be used to evacuate the processing chamber. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon atoms Since the exhaust gas contains the oxide semiconductor film formed in the treatment chamber, The concentration of impurities can be reduced.

[0409] As an example of the film formation conditions, the distance between the substrate and the target is 170 mm, and the pressure is 0.4 Pa. The conditions were: DC power 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. When a pulsed direct current (DC) power supply is used, particles that are generated during film formation are The oxide semiconductor film is preferable because it can reduce dust particles and make the film thickness distribution uniform. The thickness is set to 5 nm or more and 30 nm or less. The appropriate thickness depends on the oxide semiconductor material used. The thickness may be selected appropriately depending on the material.

[0410] Note that hydrogen, a hydroxyl group, and moisture should be prevented from being contained in the first oxide semiconductor film 730 as much as possible. In order to do this, as a pre-treatment for film formation, the gate insulating film 70 is formed in the pre-heating chamber of the sputtering device. The substrate on which the above steps 3 have been formed is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate. It is preferable to evacuate the air. The preheating temperature is preferably 100°C or higher and 600°C or lower. The temperature is between 150 and 300°C. The exhaust means provided in the preheating chamber is a cryopump. However, this preheating step may be omitted.

[0411] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and D There is also the pulsed DC sputtering method, which applies a bias in a pulsed manner. The RF sputtering method is mainly used to form insulating films, while the DC sputtering method The tarring method is mainly used when forming a metal film.

[0412] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0413] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the sputtering method.

[0414] In addition, as a film formation method using a sputtering method, a target material and a sputtering gas are mixed during film formation. Reactive sputtering method to form compound thin films by chemically reacting the silicon dioxide and silicon dioxide components. There is also a bias sputtering method in which a voltage is applied to the substrate during film formation.

[0415] The gate insulating film 703 and the first oxide semiconductor film 730 are continuously formed without being exposed to the air. By continuously forming the film without exposing it to the atmosphere, the interface is free from water and high Each volume is free from contamination by atmospheric components and impurities floating in the air, such as hydrocarbons. Since a layer interface can be formed, variations in transistor characteristics can be reduced. do.

[0416] Next, first heat treatment is performed, and the first oxide semiconductor film 73 is formed as shown in FIG. By growing crystals from the surface of 0, at least a part of the crystal is crystallized or becomes a single crystal. The first heat treatment is performed at a temperature of 450° C. or higher for 8 hours. The temperature is set to 50°C or lower, preferably 600°C or higher and 700°C or lower. The heating time is set to 1 minute or higher and 2 minutes or lower. The single crystal layer grows from the surface to the inside, and the thickness is 2 nm to 10 nm. The crystal layer formed on the surface is a plate-like crystal having an average thickness of 1000 m or less. The ab plane is located at the center of the surface, and the c axis is oriented perpendicular to the surface. The entire first oxide semiconductor film 731 is crystallized (CO-growth) by the heat treatment in step 1. Here is an example of a crystal (also called a crystallization).

[0417] In the first heat treatment, nitrogen, oxygen, helium, neon, argon, or the like is used. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is 6N (99.99%). 99%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1pp It is preferable that the concentration of H2O is 20 ppm or less, preferably 0.1 ppm or less. The first heat treatment may be performed in a dry air atmosphere of 0.1 m or less.

[0418] In this embodiment, the first heat treatment is performed at 700° C. for 1 hour in a dry air atmosphere. Perform processing.

[0419] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0420] For example, the substrate is transferred into an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, the substrate is removed from the inert gas heated to a high temperature. GRTA can be used to perform high-temperature heat treatment in a short time.

[0421] Next, as shown in FIG. 15C, a first oxide semiconductor film 731 which is a flat single crystal is formed. The thickness of the second oxide semiconductor film 731 is at least larger than that of the first oxide semiconductor film 731 and is in the range of 10 μm or less. The second oxide semiconductor film 732 is formed as follows. The thickness of the film can be determined by the operator depending on the device to be fabricated. In the case of manufacturing a multi-gate transistor, the first oxide semiconductor film 731 and the second oxide semiconductor film 732 are The total thickness of the semiconductor film 732 is set to 10 nm or more and 200 nm or less. When a transistor is manufactured, the first oxide semiconductor film 731 and the second oxide semiconductor film 732 The total thickness of the second oxide semiconductor film 732 is greater than or equal to 10 nm and less than or equal to 50 nm. In a gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon ) and can be formed by sputtering in an oxygen atmosphere.

[0422] The second oxide semiconductor film 732 can be formed using any of the above oxide semiconductors. do.

[0423] The first oxide semiconductor film 731 and the second oxide semiconductor film 732 are made of materials containing the same components. Use materials with the same crystal structure and close lattice constants (with a mismatch of 1% or less). When materials containing the same components are used, it is preferable that the This facilitates crystal growth from the single crystal layer of the first oxide semiconductor film 731. When the materials contain the same components, the interface properties such as adhesion and electrical properties are also good. Note that the second oxide semiconductor film 732 has higher crystallinity than the first oxide semiconductor film 731. When the electrons are ionized, some electrical properties (e.g., mobility, threshold voltage, band gap, etc.) It is best to choose the one that is most preferable.

[0424] Next, second heat treatment is performed to convert the first oxide semiconductor film 731 into the second oxide semiconductor film 732. The temperature of the second heat treatment is 450°C or higher and 850°C or higher. The heating temperature is preferably 550°C or higher and 650°C or lower. The heating time is 1 minute or longer and 24 hours or longer. By the second heat treatment, the crystallized first acid is formed as shown in FIG. 7, an oxide semiconductor film having a first oxide semiconductor film 731 and a second oxide semiconductor film 735 that has been crystallized. A conductive film 733 can be obtained.

[0425] The oxide semiconductors used for the first oxide semiconductor film 731 and the second oxide semiconductor film 735 When the materials for the first oxide semiconductor film 731 and the second oxide semiconductor film 732 contain the same components, The second oxide semiconductor film 735 has the same crystal structure as the first oxide semiconductor film 735. It is formed by axial growth or epitaxial growth from the solid film 731. Therefore, in practice, the first oxide semiconductor film 733 has a c-axis. The boundary between the oxide semiconductor film 731 and the second oxide semiconductor film 735 becomes unclear.

[0426] Note that the oxide semiconductor film 733 has a rough surface in a region overlapping with the uneven portion of the gate insulating film. Since the oxide semiconductor film 73 contains polycrystals, it may have grain boundaries. 3, the region that will become the channel formation region overlaps at least the flat portion of the gate insulating film. Therefore, the first oxide semiconductor film 731 and the second oxide semiconductor film 735 are c-axis oriented. The first oxide semiconductor film 731 and the second oxide semiconductor film 732 may be single crystal. When the conductive film 735 is c-axis oriented, the first oxide semiconductor film 731 and the second oxide semiconductor film 732 are It is further desirable that the ab planes of the conductor films 735 coincide with each other, and that the a-axis or b-axis coincide with each other. It is preferable to use ab axes, but the ab axis direction may be misaligned.

[0427] In the second heat treatment, nitrogen, oxygen, helium, neon, argon, etc. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon is preferably 6N or higher. or 7N or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). It is also preferable to carry out the second heat treatment in ultra-dry air with an H2O concentration of 20 ppm or less. In addition, the inside of the furnace may be in a nitrogen atmosphere during the temperature rise of the second heat treatment, and in a nitrogen atmosphere during the cooling of the furnace. The atmosphere inside may be changed to an oxygen atmosphere.

[0428] The heat treatment device used for the second heat treatment is not particularly limited, and may be a heat treatment device using a heat source such as a resistance heat source. The apparatus may be provided with a device for heating the object to be treated by thermal conduction or thermal radiation from the apparatus. An electric furnace or an RTA device such as a GRTA device or an LRTA device can be used.

[0429] Next, the oxide semiconductor film 733 is processed into a shape by photolithography. The island-shaped oxide semiconductor film 73 is formed at a position overlapping with the gate electrode 701 and the gate electrode 702. 4 and an oxide semiconductor film 736 are formed. A resist mask for this purpose may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0430] Hereinafter, the steps after the step of fabricating the source electrode and the drain electrode shown in FIG. 11(A) of the fourth embodiment will be described. By referring to the above, a transistor that functions as a switching element of a memory cell can be fabricated. This can be done.

[0431] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0432] (Embodiment 8) In this embodiment, a configuration of a CPU, which is one of the semiconductor devices according to one embodiment of the present invention, will be described. I will explain.

[0433] 17 shows the configuration of the CPU of this embodiment. The CPU shown in FIG. 17 is provided on a board 900. , Arithmetic logic unit (ALU)901, ALU Controller902, Instruction Decoder903, Int errupt Controller904, Timing Controller90 5, Register 906, Register Controller 907, Bus Interface (Bus I / F) 908, rewritable ROM 909, ROM interface The main components are the ROM 909 and the ROM I / F 920. F920 may be provided on a separate chip. Of course, the CPU shown in FIG. 17 can be simplified in its configuration. This is just an example, and actual CPUs have a wide variety of configurations depending on their applications. .

[0434] The instruction input to the CPU via Bus I / F 908 is Instruction D After being input to ecoder903 and decoded, it is sent to ALU Controller90 2, Interrupt Controller904, Register Contr The signal is input to the oller 907 and timing controller 905.

[0435] ALU Controller902, Interrupt Controller90 4, Register Controller907, Timing Controll er905 performs various controls based on the decoded instructions. The controller 902 generates a signal to control the operation of the ALU 901. The interrupt controller 904 performs the following operations while the CPU is executing a program: Interrupt requests from external I / O devices and peripheral circuits are judged based on their priority and mask status. The Register Controller 907 processes the Generates the address of Register 906 and reads or writes to Register 906 depending on the CPU state. Perform the writing.

[0436] The Timing Controller 905 also controls the ALU 901 and ALU Controller oller902, Instruction Decoder903, Interrup Operation of the t Controller 904 and Register Controller 907 It generates signals to control the timing of operations, for example, Timing Controller 905 is an internal clock signal that generates an internal clock signal CLK2 based on a reference clock signal CLK1. It is equipped with a clock generating unit, which supplies a clock signal CLK2 to the various circuits mentioned above.

[0437] In the CPU of this embodiment, the configuration shown in the above embodiment is stored in the register 906. The register controller 907 is provided with a memory element having the following functions: Selects the hold operation in Register 906 according to the instruction from ALU 901. That is, in the storage element of the register 906, the data is stored by the phase inversion element. The phase inversion element selects whether to hold the data by the phase inversion element or by the capacitance element. When data retention by the register 906 is selected, When data retention in the capacitor element is selected, the capacitor The data is rewritten to the element, and the power supply voltage to the memory element in Register 906 is As for power supply shutdown, as shown in FIG. and a node to which the power supply potential VDD or VSS is applied. This can be achieved by providing a child.

[0438] In this way, when the CPU operation is temporarily stopped and the supply of power voltage is stopped, It is possible to retain data even when the power is low, and power consumption can be reduced. For example, a user of a personal computer inputs information into an input device such as a keyboard. Even when input is stopped, the CPU can be stopped, thereby reducing power consumption. can be reduced.

[0439] In this embodiment, a CPU has been described as an example, but the semiconductor device of the present invention is not limited to a CPU. DSP, custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as gate arrays.

[0440] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. [Example]

[0441] By using a semiconductor device according to one embodiment of the present invention, highly reliable electronic devices and low power consumption devices can be realized. It is possible to provide electronic devices that can withstand high power consumption, especially mobile phones that are difficult to receive a constant supply of power. In the case of an electronic device for use, a semiconductor device with low power consumption according to one embodiment of the present invention may be used as a component thereof. By adding this, you can get the benefit of longer continuous use time. Redundant circuitry to compensate for high off-state current by using low-current transistors Since design is no longer necessary, the degree of integration of integrated circuits used in semiconductor devices can be increased. This allows the semiconductor device to have higher performance.

[0442] A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, personal digital assistants, e-books, video cameras, digital cameras, still camera, goggle-type display (head-mounted display), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (AT) M), vending machines, etc. Specific examples of these electronic devices are shown in Figure 18.

[0443] FIG. 18A shows an electronic book having a housing 7001, a display portion 7002, and the like. The semiconductor device according to the embodiment can be used in an integrated circuit for controlling the operation of an electronic book. The semiconductor device according to one embodiment of the present invention is used in an integrated circuit for controlling the driving of an electronic book. This makes it possible to provide highly reliable e-books that consume less power. In addition, by using a flexible substrate, the semiconductor device and the semiconductor display device can be made flexible. This allows us to provide flexible, lightweight, and user-friendly e-books. can.

[0444] FIG. 18B shows a display device, which includes a housing 7011, a display portion 7012, a support base 7013, and the like. The semiconductor device according to one aspect of the present invention is an integrated circuit for controlling the driving of a display device. The present invention can be applied to an integrated circuit for controlling the driving of a display device. By using a semiconductor device, a highly reliable display device and a display device with low power consumption are provided. The display device can be used for personal computers, TV broadcast reception, advertising, etc. This includes all display devices for displaying information, such as displays.

[0445] FIG. 18C shows a display device, which includes a housing 7021, a display portion 7022, and the like. The semiconductor device according to the embodiment can be used in an integrated circuit for controlling the driving of a display device. The semiconductor device according to one embodiment of the present invention is used in an integrated circuit for controlling driving of a display device. This makes it possible to provide a highly reliable display device and a display device with low power consumption. In addition, by using a flexible substrate, the semiconductor device and the semiconductor display device can be made flexible. This makes it possible to provide a flexible, lightweight, and user-friendly display device. Therefore, as shown in FIG. 18(C), the display device can be used by fixing it to a fabric or the like. This allows the display device to be used in a wider range of applications.

[0446] FIG. 18D shows a portable game machine, which includes a housing 7031, a housing 7032, a display portion 7033, Display unit 7034, microphone 7035, speaker 7036, operation keys 7037, The semiconductor device according to one embodiment of the present invention is a driving circuit for a portable game machine. It can be used in an integrated circuit for controlling the operation of a portable game console. By using a semiconductor device according to one embodiment of the present invention for an integrated circuit, a highly reliable portable game device can be realized. It is possible to provide a portable game machine with low power consumption. The portable game machine has two display units 7033 and 7034. The number of display units that the game machine has is not limited to this.

[0447] FIG. 18(E) shows a mobile phone, which includes a housing 7041, a display portion 7042, an audio input portion 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. A semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the driving of a mobile phone. The semiconductor device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using this device, it is possible to provide highly reliable mobile phones with low power consumption. Cut.

[0448] FIG. 18(F) shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 18(F) has a modem built in a housing 7051. A semiconductor device according to one embodiment of the present invention may be a semiconductor device for controlling the driving of a portable information terminal. The present invention can be applied to an integrated circuit for controlling the operation of a portable information terminal. By using the semiconductor device according to one embodiment, a highly reliable portable information terminal and a low-power portable information terminal can be provided. A portable information terminal can be provided.

[0449] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0450] 100 memory element 101 Phase inversion element 102 Phase inversion element 103 Switching element 104 Switching element 105 Capacitive element 106 Capacitive switching element 107 p-channel transistor 108 n-channel transistors 109 p-channel transistor 110 n-channel transistor 200 memory elements 201 Phase Inversion Element 202 Phase Inversion Element 203 Switching element 204 Switching element 205 Capacitor 206 Capacitive switching element 207 Phase Inversion Element 208 Switching element 209 Switching element 210 p-channel transistor 211 n-channel transistor 212 p-channel transistor 213 n-channel transistor 214 p-channel transistor 215 n-channel transistor 300 memory elements 301 Phase Inversion Element 302 Phase Inversion Element 303 Switching element 304 Switching element 305 Capacitor 306 Capacitive switching element 307 Capacitor 308 Capacitive switching element 309 p-channel transistor 310 n-channel transistor 311 p-channel transistor 312 n-channel transistor 401 Switching element 402 Memory element 403 Memory Element Group 420 transistors 421 First electrode 422 Oxide semiconductor film 423 Second electrode 424 Gate insulating film 425 gate electrode 426 Insulating Film 431 Contact Hole 432 Contact Hole 433 Contact Hole 434 Wiring 435 Wiring 436 Wiring 440 Wiring 441 Contact Hole 500 bonded substrate 501 insulating film 502 Embrittlement layer 503 base board 504 Semiconductor film 505 Semiconductor film 506 Semiconductor Film 507 Semiconductor Film 508 Gate insulating film 509 Electrode 510 Impurity region 511 Impurity region 512 Sidewall 513 High concentration impurity region 514 Low concentration impurity region 515 Channel formation region 516 High concentration impurity region 517 Low concentration impurity region 518 Channel formation region 520 n-channel transistor 521 p-channel transistor 530 insulating film 531 Insulating film 532 insulating film 601 Gate electrode 602 Electrode 603 Gate insulating film 605 Oxide semiconductor film 607 Source electrode 608 Drain electrode 609 Wiring 610 Wiring 611 Wiring 612 insulating film 620 Transistor 623 Capacitor 630 Transistor 631 Gate electrode 632 Gate insulating film 633 Oxide Semiconductor Film 634 Channel protection film 635 Source Electrode 636 Drain electrode 637 Insulating Film 640 transistors 641 Gate electrode 642 Gate insulating film 643 Source Electrode 644 Drain electrode 645 Oxide Semiconductor Film 646 Insulating Film 650 transistors 651 Source electrode 652 Drain electrode 653 Oxide semiconductor film 654 Gate insulating film 655 gate electrode 656 Insulating film 660 Semiconductor Substrate 661 n-channel transistor 662 p-channel transistor 663 Insulating Film 664 Transistor 665 Capacitor 666 Element isolation insulating film 701 Gate electrode 702 gate electrode 703 Gate insulating film 730 Oxide semiconductor film 731 Oxide semiconductor film 732 Oxide semiconductor film 733 Oxide semiconductor film 734 Oxide semiconductor film 735 Oxide semiconductor film 736 Oxide semiconductor film 900 boards 901 ALU 902 ALU Controller 903 Instruction Decoder 904 Interrupt Controller 905 Timing Controller 906 Register 907 Register Controller 908 Bus I / F 909 ROM 920 ROM interface 1300 Registers 1301 Inverter 1302 inverter 1303 Switching element 1304 Switching element 1310 p-channel transistor 1311 n-channel transistor 1312 p-channel transistor 1313 n-channel transistor 7001 Case 7002 Display section 7011 Case 7012 Display section 7013 Support stand 7021 Housing 7022 Display section 7031 Housing 7032 chassis 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Housing 7042 Display section 7043 Audio Input Unit 7044 Audio output section 7045 Operation Key 7046 Light receiving section 7051 Housing 7052 Display section 7053 Operation Key

Claims

1. a first transistor, a second transistor, a first insulating film, and a first conductive film; the first transistor has a channel formation region in a silicon film; the second transistor has a channel formation region in an oxide semiconductor film, the first insulating film has a region located above a gate electrode of the first transistor, a second insulating film having a region in contact with an upper surface of the first insulating film; a second conductive film that functions as one of a source electrode and a drain electrode of the first transistor and has a region in contact with an upper surface of the second insulating film; the second conductive film has a region in contact with an upper surface of the second insulating film and is made of the same material as a third conductive film that functions as one of a source electrode and a drain electrode of the second transistor; a fourth conductive film having a function as a gate electrode of the second transistor has a region in contact with an upper surface of the first insulating film; the first conductive film has a region in contact with an upper surface of the first insulating film and has the same material as the fourth conductive film; the first conductive film has a region in contact with the second conductive film, A semiconductor device in which a channel formation region of the first transistor does not overlap with the oxide semiconductor film in a cross-sectional view.

2. In claim 1, The fourth conductive film comprises molybdenum.

3. In claim 1 or claim 2, The oxide semiconductor film contains In, Ga, and Zn.

4. In claim 1 or claim 2, The semiconductor device is such that the oxide semiconductor film is In—O.

Images