Semiconductor device

Abstract

To provide a semiconductor device which can suppress positional deviation of a joint part between a plurality of electrodes of a semiconductor element, and a plurality of wires.SOLUTION: A semiconductor device A10 includes a first insulation layer 11, a plurality of first wires 21 each having a first re-wiring part 212, a semiconductor element having a plurality of electrodes, a sealing resin 41 covering the semiconductor element, and a plurality of terminals. The first insulation layer 11 has a plurality of first grooves 111 recessed from a second surface 11B. The first re-wiring part 212 has a substrate layer 21A in contact with any one of the plurality of first grooves 111, and a plating layer 21B covering the substrate layer 21A. The plating layer 21B has a recess 212A, and projects from the second surface 11B. The first re-wiring part 212 has two end edges which are separated from each other in a direction perpendicular to an extension direction of itself. The recess 212A is separated from the two end edges. The two end edges are positioned outside of the substrate layer 21A when viewed in a thickness direction z.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] As electronic devices have become smaller in recent years, semiconductor devices used in those electronic devices have also become smaller. In response to this trend, so-called fan-out semiconductor devices have become known. The semiconductor device includes a semiconductor element having multiple electrodes, an insulating layer in contact with the semiconductor element, multiple wirings disposed on the insulating layer and connected to the multiple electrodes, and a sealing resin in contact with the insulating layer and covering a portion of the semiconductor element. When viewed in the thickness direction, the multiple wirings include portions located outward from the semiconductor element. This has the advantage of allowing for miniaturization of the semiconductor device while also being able to flexibly accommodate the shape of the wiring pattern of the wiring board on which the semiconductor device is mounted.

[0003] Patent Document 1 discloses an example of a method for manufacturing a fan-out type semiconductor device. The manufacturing method includes the steps of embedding a semiconductor element having multiple electrodes in an encapsulating resin (a cured body in Patent Document 1), forming an insulating layer (a buffer coating film in Patent Document 1) that contacts both the semiconductor element and the encapsulating resin, and forming multiple wirings connected to the multiple electrodes. In the step of embedding the semiconductor element in the encapsulating resin, the multiple electrodes are exposed from the encapsulating resin. In the step of forming the insulating layer, multiple openings are formed in the insulating layer by photolithography patterning using a mask so that the multiple electrodes are exposed. In the step of forming the multiple wirings, a plating layer is formed in the multiple openings in the insulating layer and on the insulating layer.

[0004] During the process of embedding a semiconductor element in a sealing resin, the sealing resin hardens and shrinks, causing displacement of the semiconductor element. If multiple openings are formed in the insulating layer in this state, misalignment occurs between the multiple openings and the multiple electrodes. If multiple wirings are formed in this case, misalignment occurs at the junctions between the multiple electrodes and the multiple wirings. Therefore, it is desirable to suppress this misalignment in order to further improve the reliability of semiconductor devices. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-89081 Summary of the Invention [Problem to be solved by the invention]

[0006] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can suppress misalignment at joints between a plurality of electrodes of a semiconductor element and a plurality of wirings. [Means for solving the problem]

[0007] A semiconductor device provided by a first aspect of the present disclosure includes a first insulating layer having a first surface and a second surface facing opposite to each other in a thickness direction, a plurality of first wirings each having a first buried portion at least partially embedded in the first insulating layer and a first rewiring portion disposed on the second surface and connected to the first buried portion, a semiconductor element provided near the first surface and having a plurality of electrodes connected to at least a portion of the first buried portions of the plurality of first wirings and in contact with the first surface, and a sealing resin in contact with the first surface and covering a portion of the semiconductor element, wherein, as viewed in the thickness direction, the first rewiring portions of the plurality of first wirings include portions located outward from the semiconductor element, the first insulating layer has a plurality of first grooves recessed from the second surface in the thickness direction, and the first rewiring portions of the plurality of first wirings are The first groove is in contact with the first grooves.

[0008] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: embedding a semiconductor element having a plurality of electrodes provided on either side in a thickness direction in a sealing resin so that the plurality of electrodes are exposed; forming an insulating layer laminated on the sealing resin and covering the plurality of electrodes; and forming a plurality of wirings having an embedded portion that is embedded in the insulating layer and connected to one of the plurality of electrodes, and a rewiring portion that is disposed on the insulating layer and connected to the embedded portion, wherein the insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a portion of the plurality of wirings; and forming the plurality of wirings includes the steps of: forming a plurality of holes that expose the plurality of electrodes and a plurality of grooves that are recessed from the surface of the insulating layer and connect to the plurality of holes in the insulating layer by using a laser while image-recognizing the positions of the plurality of electrodes, thereby depositing an underlayer that covers the wall surfaces that define each of the plurality of holes and the plurality of grooves; and forming a plating layer that covers the underlayer.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure, seen through a sealing resin. [Figure 2] 2 is a plan view showing the semiconductor element in a more transparent manner than in FIG. 1. [Figure 3] FIG. 2 is a bottom view of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a bottom view corresponding to FIG. 3, showing the protective layer and a plurality of terminals. [Figure 5] FIG. 2 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 2 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 6 is a partially enlarged view of FIG. 5. [Figure 8] FIG. 6 is a partially enlarged view of FIG. 5. [Figure 9] FIG. 9 is a partially enlarged cross-sectional view taken along line IX-IX in FIG. [Figure 10] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 11] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 12] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a partially enlarged view of FIG. [Figure 14] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 15] FIG. 15 is a partially enlarged view of FIG. [Figure 16] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 17] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 18] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device shown in FIG. [Figure 19] 10 is a plan view of a semiconductor device according to a second embodiment of the present disclosure, seen through a sealing resin. FIG. [Figure 20] FIG. 20 is a plan view corresponding to FIG. 19, further showing the first insulating layer and the semiconductor element. [Figure 21] FIG. 20 is a bottom view of the semiconductor device shown in FIG. [Figure 22] 22 is a bottom view corresponding to FIG. 21, showing the protective layer and a plurality of terminals. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 20. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 20. [Figure 25] FIG. 24 is a partially enlarged view of FIG. 23. [Figure 26] FIG. 26 is a partially enlarged cross-sectional view taken along line XXVI-XXVI in FIG. 20. [Figure 27]FIG. 10 is a plan view of a semiconductor device according to a third embodiment of the present disclosure, showing a heat dissipation member, a bonding layer, and a sealing resin. [Figure 28] FIG. 28 is a bottom view of the semiconductor device shown in FIG. 27. [Figure 29] FIG. 29 is a bottom view corresponding to FIG. 28, showing the first insulating layer, the protective layer, and the plurality of terminals in a transparent manner. [Figure 30] FIG. 28 is a cross-sectional view taken along the line XXX-XXX in FIG. 27. [Figure 31] FIG. 28 is a cross-sectional view taken along line XXXI-XXXI in FIG. 27. [Figure 32] FIG. 31 is a partially enlarged view of FIG. 30. [Figure 33] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure, seen through a light-transmitting resin. [Figure 34] FIG. 34 is a plan view corresponding to FIG. 33, further showing the first insulating layer and the plurality of first wirings. [Figure 35] FIG. 34 is a cross-sectional view taken along line XXXV-XXXV in FIG. 33. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0012] [First embodiment] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 9. The semiconductor device A10 includes a first insulating layer 11, a plurality of first wirings 21, a semiconductor element 30, a sealing resin 41, a protective layer 42, and a plurality of terminals 50. The semiconductor device A10 is a fan-out type package that is surface-mounted on a wiring board. For ease of understanding, FIG. 1 shows the sealing resin 41 in a see-through manner. For ease of understanding, FIG. 2 shows the semiconductor element 30 in a see-through manner compared to FIG. 1. For ease of understanding, FIG. 4 shows the protective layer 42 and the plurality of terminals 50 in a see-through manner. Note that the outline of the semiconductor element 30 in FIG. 2 is shown by an imaginary line (double-dashed line).

[0013] In the description of the semiconductor device A10, the thickness direction of the first insulating layer 11 is referred to as the "thickness direction z." The direction perpendicular to the thickness direction z is referred to as the "first direction x." The direction perpendicular to both the thickness direction z and the first direction x is referred to as the "second direction y." As shown in FIG. 1, the outer shape of the semiconductor device A10 is rectangular when viewed in the thickness direction z. The first direction x corresponds to the longitudinal direction of the semiconductor device A10. The second direction y corresponds to the lateral direction of the semiconductor device A10. The thickness direction z, the first direction x, and the second direction y also apply to the description of the semiconductor devices A20 to A40 described later.

[0014] As shown in FIGS. 5 and 6 , the first insulating layer 11 faces the semiconductor element 30 in the thickness direction z. The first insulating layer 11 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes part of the multiple first wirings 21. The synthetic resin is, for example, an epoxy resin or a polyimide resin. The first insulating layer 11 has a first surface 11A, a second surface 11B, and multiple end surfaces 11C. The first surface 11A and the second surface 11B face opposite each other in the thickness direction z. The first surface 11A faces the semiconductor element 30. In the semiconductor device A10, the second surface 11B faces the wiring board when the semiconductor device A10 is mounted on the wiring board. The multiple end surfaces 11C are connected to both the first surface 11A and the second surface 11B. Each of the multiple end surfaces 11C faces either the first direction x or the second direction y.

[0015] As shown in FIGS. 7 to 9, the first insulating layer 11 has a plurality of first grooves 111. The plurality of first grooves 111 are recessed from the second surface 11B in the thickness direction z. As shown in FIG. 9, the side surface of each of the plurality of first grooves 111 is tapered in the thickness direction z from the bottom surface of the first groove 111 to the second surface 11B. In each of the plurality of first grooves 111, the dimension c1 in the first direction x of the bottom surface of the first groove 111 is equal to the dimension c2 of the first groove 111 and the second groove 111 that are spaced apart from each other in the first direction x. It is smaller than the dimension c2 between the two boundaries with the second surface 11B.

[0016] As shown in FIGS. 5 and 6 , the multiple first wirings 21 are disposed in the first insulating layer 11. The multiple first wirings 21 form conductive paths for supplying power to the semiconductor element 30 and for inputting and outputting signals. Each of the multiple first wirings 21 has a first embedded portion 211 and a first rewiring portion 212. At least a portion (in the semiconductor device A10, the entire portion) of the first embedded portion 211 is embedded in the first insulating layer 11. As shown in FIG. 7 , the side surface of the first embedded portion 211 is tapered in the thickness direction z from the first surface 11A to the second surface 11B of the first insulating layer 11. The dimension b1 of the end face of the first embedded portion 211 closest to the first surface 11A in a direction perpendicular to the thickness direction z is smaller than the dimension b2 of the end face of the first embedded portion 211 closest to the second surface 11B in a direction perpendicular to the thickness direction z. The first rewiring portions 212 are disposed on the second surface 11B of the first insulating layer 11. The first rewiring portions 212 are connected to the first embedded portions 211. As shown in FIGS. 1 to 4 , the first rewiring portions 212 of the multiple first wirings 21 include portions that are located outward from the semiconductor element 30 when viewed in the thickness direction z. The first rewiring portions 212 of the multiple first wirings 21 are in contact with the multiple first grooves 111 of the first insulating layer 11. Therefore, the first rewiring portions 212 of the multiple first wirings 21 are configured such that portions thereof are embedded in the multiple first grooves 111.

[0017] As shown in FIGS. 7 and 8 , each of the first embedded portions 211 of the multiple first wirings 21 and the first rewiring portions 212 of the multiple first wirings 21 has an underlayer 21A and a plating layer 21B. The underlayer 21A is composed of metal elements contained in an additive contained in the first insulating layer 11. The plating layer 21B is made of a material containing, for example, copper (Cu). The underlayer 21A of the first embedded portion 211 is in contact with the first insulating layer 11. The plating layer 21B of the first embedded portion 211 is surrounded by the underlayer 21A of the first embedded portion 211 around the thickness direction z. The underlayer 21A of the first rewiring portion 212 is in contact with one of the multiple first grooves 111 of the first insulating layer 11. The plating layer 21B of the first rewiring portion 212 covers the underlayer 21A of the first rewiring portion 212. 9, the plating layer 21B of the first rewiring portion 212 has a recess 212A recessed in the thickness direction z. The recess 212A extends in the same direction as one of the first rewiring portions 212 of the multiple first wirings 21 extends.

[0018] As shown in FIGS. 5 and 6, the semiconductor element 30 is connected to a plurality of first wirings 21. The semiconductor element 30 is in contact with the first surface 11A of the first insulating layer 11. In the semiconductor device A10, the semiconductor element 30 is an LSI (Large Scale Integration) including, for example, a voltage control circuit such as an LDO (Low Drop Out) and an amplifier circuit such as an operational amplifier. 1, 5, and 6, the semiconductor element 30 has a plurality of electrodes 31. The plurality of electrodes 31 are provided near the first surface 11A. The plurality of electrodes 31 are electrically connected to a circuit configured in the semiconductor element 30. The plurality of electrodes 31 include, for example, aluminum (Al). The plurality of electrodes 31 are directly connected to at least some (all in the case of the semiconductor device A10) of the first embedded portions 211 of the plurality of first wirings 21. This allows the semiconductor element 30 to be electrically connected to the plurality of first wirings 21.

[0019] As shown in FIGS. 5 and 6 , the sealing resin 41 covers a portion of the semiconductor element 30. The sealing resin 41 contacts the first surface 11A of the first insulating layer 11. The sealing resin 41 is made of a material containing, for example, black epoxy resin. The sealing resin 41 has a plurality of side surfaces 411. Each of the plurality of side surfaces 411 faces either the first direction x or the second direction y. Each of the plurality of side surfaces 411 is flush with one of the plurality of end surfaces 11C of the first insulating layer 11.

[0020] 5 and 6, the protective layer 42 is in contact with the second surface 11B of the first insulating layer 11. The first rewiring portions 212 of the plurality of first wirings 21 are covered with the protective layer 42. Protective layer 42 has electrical insulation properties. The protective layer 42 is made of a material containing, for example, polyimide. As shown in FIGS. 3 and 8, the protective layer 42 has a plurality of openings 421. The plurality of openings 421 penetrate the protective layer 42 in the thickness direction z. Parts of the first rewiring portions 212 of the plurality of first wirings 21 are exposed from the plurality of openings 421.

[0021] As shown in FIGS. 3 and 8 , the terminals 50 are individually bonded to portions of the first rewiring portions 212 of the first wirings 21 exposed through the openings 421 in the protective layer 42. The terminals 50 are used to mount the semiconductor device A10 on a wiring board. The terminals 50 protrude from the protective layer 42 in the thickness direction z. As shown in FIG. 8 , in the example of the semiconductor device A10, each of the terminals 50 has a base 51 and a bump 52. The base 51 contacts a portion of one of the first rewiring portions 212 of the first wirings 21. The base 51 is made of multiple metal layers, including a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer, stacked in this order in a direction away from the second surface 11B of the first insulating layer 11 in the thickness direction z. Note that the palladium layer may not be included among these metal layers. The bump 52 contacts both the base 51 and the protective layer 42. The bump portion 52 includes a portion that protrudes in the thickness direction z from the protective layer 42. The bump portion 52 is made of a material containing tin (Sn).

[0022] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 11 to 18. The cross-sectional positions in Figures 11 to 18 (excluding Figures 13 and 15) are the same as the cross-sectional position in Figure 5.

[0023] First, as shown in FIG. 10 , the semiconductor element 30 is embedded in the sealing resin 81. The sealing resin 81 is made of a material containing black epoxy resin. The semiconductor element 30 has a plurality of electrodes 31 provided on either side in the thickness direction z. In this process, the material of the sealing resin 81 and the semiconductor element 30 are placed in a mold, and then compression molding is performed. As a result, the semiconductor element 30 is embedded in the sealing resin 81. At this time, the plurality of electrodes 31 are exposed from the sealing resin 81.

[0024] Next, as shown in FIG. 11, an insulating layer 82 is formed so as to be laminated on the sealing resin 81 and cover the plurality of electrodes 31 of the semiconductor element 30. The insulating layer 82 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes part of the plurality of wirings 83 (details will be described later). The synthetic resin is, for example, an epoxy resin or a polyimide resin. The insulating layer 82 is formed by compression molding.

[0025] Next, as shown in FIGS. 12 to 15, a plurality of wirings 83 connected to a plurality of electrodes 31 of the semiconductor element 30 are formed. The plurality of wirings 83 correspond to a plurality of first wirings 21 of the semiconductor device A10. As shown in FIG. 14, each of the plurality of wirings 83 has an embedded portion 831 and a rewiring portion 832. The embedded portion 831 is embedded in the wiring 83 and connected to one of the plurality of electrodes 31. The rewiring portion 832 is disposed on the insulating layer 82 and connected to the embedded portion 831. As shown in FIG. 15, each of the embedded portions 831 of the plurality of wirings 83 and the rewiring portions 832 of the plurality of wirings 83 has an underlayer 83A and a plating layer 83B. The process of forming the plurality of wirings 83 includes a process of depositing an underlayer 83A that covers the surface of the insulating layer 82 and a process of forming a plating layer 83B that covers the underlayer 83A.

[0026] First, as shown in FIG. 13, a base layer 83A is deposited to cover the surface of the insulating layer 82. In this step, as shown in FIG. 12, a plurality of holes 821 and a plurality of grooves 822 are formed in the insulating layer 82 by a laser. The plurality of holes 821 penetrate the insulating layer 82 in the thickness direction z. The plurality of electrodes 31 of the semiconductor element 30 are individually exposed from the plurality of holes 821. The positions of the plurality of electrodes 31 are image-recognized by an infrared camera or the like, and the plurality of electrodes 31 are individually exposed from the plurality of holes 821. The insulating layer 82 is formed by irradiating the insulating layer 82 with a laser until the electrodes 31 are exposed. The position of the laser irradiation is corrected as needed based on the positional information of the electrodes 31 obtained by image recognition. The grooves 822 are recessed from the surface of the insulating layer 82 and connect to the holes 821. The grooves 822 are formed by irradiating the surface of the insulating layer 82 with a laser. The laser is, for example, an ultraviolet laser with a wavelength of 355 nm and a beam diameter of 17 μm. By forming the holes 821 and the grooves 822 in the insulating layer 82, a base layer 83A is deposited, covering the wall surfaces defining each of the holes 821 and the grooves 822, as shown in FIG. 13 . The base layer 83A is composed of a metal element contained in an additive contained in the insulating layer 82. The metal element contained in the additive is excited by the laser irradiation. As a result, a metal layer containing the metal element is deposited as the base layer 83A.

[0027] Next, as shown in FIG. 15, a plating layer 83B is formed to cover the base layer 83A. The plating layer 83B is made of a material containing copper. The plating layer 83B is formed by electroless plating. As a result, as shown in FIG. 14, a buried portion 831 is formed in each of the plurality of holes 821. In addition, a rewiring portion 832 is formed in each of the plurality of grooves 822. In this way, a plurality of wirings 83 is formed.

[0028] Next, as shown in FIG. 16 , a protective layer 84 is formed on the insulating layer 82, covering portions of the multiple wirings 83. The protective layer 84 has multiple openings 841 that penetrate in the thickness direction z. First, a spin coater is used to apply photosensitive polyimide to the surface of the insulating layer 82 and the surfaces of the multiple wirings 83. Next, photolithography patterning is used to form the multiple openings 841 in the photosensitive polyimide. At this time, portions of the rewiring portions 832 of the multiple wirings 83 are exposed from the multiple openings 841. In this manner, the protective layer 84 is formed.

[0029] Next, as shown in FIG. 17, a plurality of terminals 50 are formed, each individually bonded to the rewiring portions 832 of the plurality of wirings 83 exposed from the plurality of openings 841 of the protective layer 84. First, the base portions 51 of the plurality of terminals 50 shown in FIG. 8 are formed. The base portions 51 are formed by electroless plating. Next, the bump portions 52 of the plurality of terminals 50 shown in FIG. 8 are formed. The bump portions 52 are formed by melting a conductive material containing tin, such as solder, by reflow and then solidifying it by cooling. In this manner, a plurality of terminals 50 are formed.

[0030] 18, the sealing resin 81, insulating layer 82, and protective layer 84 are cut along cutting lines CL with a dicing blade or the like to separate them into a plurality of individual pieces. Each individual piece includes one semiconductor element 30 and a plurality of wirings 83 connected thereto. The sealing resin 81, insulating layer 82, and protective layer 84 separated by this process correspond to the sealing resin 41, first insulating layer 11, and protective layer 42 of the semiconductor device A10. The semiconductor device A10 is manufactured through the above processes.

[0031] Next, the effects of the semiconductor device A10 and the method for manufacturing the semiconductor device A10 will be described.

[0032] The semiconductor device A10 includes a first insulating layer 11 having a second surface 11B and a plurality of first wirings 21 having first embedded portions 211 and first rewiring portions 212. The first rewiring portions 212 of the plurality of first wirings 21 are disposed on the second surface 11B and are connected to the first embedded portions 211 of the plurality of first wirings 21 that are connected to a plurality of electrodes 31 of the semiconductor element 30. The first insulating layer 11 has a plurality of first grooves 111 recessed from the second surface 11B in the thickness direction z. The first rewiring portions 212 of the plurality of first wirings 21 are in contact with the plurality of first grooves 111. The plurality of first grooves 111 correspond to a plurality of grooves 822 formed in the insulating layer 82 by a laser in a process for forming a plurality of wirings 83 in the manufacture of the semiconductor device A10.

[0033] The process for forming the plurality of wirings 83 in the manufacturing method of the semiconductor device A10 includes the steps of depositing a base layer 83A on the surface of an insulating layer 82 and forming a plating layer 83B covering the base layer 83A. The plurality of wirings 83 correspond to the plurality of first wirings 21 of the semiconductor device A10. The insulating layer 82 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes part of the plurality of wirings 83 (the base layer 83A). The step of depositing the base layer 83A involves forming a plurality of holes 821 and a plurality of grooves 822 in the insulating layer 82 using a laser, thereby depositing the base layer 83A that covers the wall surfaces defining each of the plurality of holes 821 and the plurality of grooves 822. The plurality of holes 821 are formed by exposing the plurality of electrodes 31 of the semiconductor element 30 while image-recognizing the positions of the plurality of electrodes 31. As a result, even if displacement occurs in the semiconductor element 30 due to cure shrinkage of the sealing resin 81, position correction corresponding to the displacement of the plurality of electrodes 31 is performed by image recognition during laser irradiation, so that the plurality of holes 821 exposing the plurality of electrodes 31 can be formed with high precision. That is, the plurality of wirings 83 can be formed with high precision to match the positions of the plurality of electrodes 31. Therefore, according to the semiconductor device A10 and the manufacture of the semiconductor device A10, it is possible to suppress misalignment at the joints between the plurality of electrodes 31 of the semiconductor element 30 and the plurality of wirings 83 (the plurality of first wirings 21).

[0034] In the process of forming the plurality of wirings 83 according to the manufacturing method of the semiconductor device A10, the plating layer 83B is formed by electroless plating, which eliminates the need to deposit the base layer 83A that serves as a conductive path for forming the plating, and therefore allows the plurality of wirings 83 to be formed more efficiently than in the case of electrolytic plating.

[0035] Each of the first rewiring portions 212 of the multiple first wirings 21 has an underlayer 21A in contact with one of the multiple first grooves 111 and a plating layer 21B covering the underlayer 21A. The plating layer 21B has a recess 212A recessed in the thickness direction z. The recess 212A is a trace left by forming the plating layer 83B on the underlayer 83A covering the multiple grooves 822 in the step of forming the multiple wirings 83 according to the manufacturing method of the semiconductor device A10. Therefore, the recess 212A is configured to extend in the direction in which one of the first rewiring portions 212 of the multiple first wirings 21 extends.

[0036] The semiconductor device A10 further includes a protective layer 42 in contact with the second surface 11B of the first insulating layer 11, and a plurality of terminals 50. The plurality of terminals 50 are individually bonded to parts of the first rewiring portions 212 of the plurality of first wirings 21 exposed from the plurality of openings 421 in the protective layer 42. The plurality of terminals 50 protrude from the protective layer 42 in the thickness direction z. The plurality of terminals 50 are made of a material containing tin. This makes it easier to mount the semiconductor device A10 on a wiring board.

[0037] Second Embodiment A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 19 to 26. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted.

[0038] The semiconductor device A20 differs from the previously described semiconductor device A10 in that it further includes a second insulating layer 12 and a plurality of second wirings 22, and in the configuration of the protective layer 42 and the plurality of terminals 50. Here, FIG. 19 shows a perspective view of the sealing resin 41 for ease of understanding. FIG. 20 shows a perspective view of the first insulating layer 11 and the semiconductor element 30 in comparison to FIG. 19 for ease of understanding. FIG. 22 shows a perspective view of the protective layer 42 and the plurality of terminals 50 for ease of understanding. Note that the outline of the semiconductor element 30 shown through the perspective view in FIG. 20 is shown by imaginary lines.

[0039] As shown in FIGS. 23 and 24 , the second insulating layer 12 contacts the second surface 11B of the first insulating layer 11. Therefore, the first insulating layer 11 is sandwiched between the second insulating layer 12 and the sealing resin 41. The second insulating layer 12 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes part of the second wirings 22. The synthetic resin is, for example, an epoxy resin or a polyimide resin. The second insulating layer 12 has a third surface 12A, a fourth surface 12B, and multiple end surfaces 12C. The third surface 12A and the fourth surface 12B face opposite each other in the thickness direction z. The third surface 12A contacts the second surface 11B. The fourth surface 12B faces the wiring board when the semiconductor device A20 is mounted on the wiring board. The multiple end surfaces 12C are connected to both the third surface 12A and the fourth surface 12B. Each of the multiple end faces 12C faces either the first direction x or the second direction y. Each of the multiple end faces 12C is flush with both one of the multiple end faces 11C of the first insulating layer 11 and one of the multiple side faces 411 of the sealing resin 41.

[0040] 25 and 26, the second insulating layer 12 has a plurality of second grooves 121. The plurality of second grooves 121 are recessed from the fourth surface 12B in the thickness direction z. As shown in FIG. 26, the side surface of each of the plurality of second grooves 121 is tapered in the thickness direction z from the bottom surface of the second groove 121 to the fourth surface 12B. In each of the plurality of second grooves 121, the dimension c3 in the first direction x of the bottom surface of the second groove 121 is smaller than the dimension c4 between two boundaries between the second groove 121 and the fourth surface 12B that are spaced apart from each other in the first direction x.

[0041] As shown in FIGS. 23 and 24 , the multiple second wirings 22 are disposed in the second insulating layer 12. The multiple second wirings 22, together with the multiple first wirings 21, form a conductive path across the semiconductor element 30. Each of the multiple second wirings 22 has a second embedded portion 221 and a second rewiring portion 222. The second embedded portion 221 is embedded in the second insulating layer 12. As shown in FIG. 25 , the side surface of the second embedded portion 221 tapers in the thickness direction z from the third surface 12A to the fourth surface 12B of the second insulating layer 12. The dimension b3 of the end face of the second embedded portion 221 closest to the third surface 12A in a direction perpendicular to the thickness direction z is smaller than the dimension b4 of the end face of the second embedded portion 221 closest to the fourth surface 12B in a direction perpendicular to the thickness direction z. The second rewiring portion 222 is disposed on the fourth surface 12B of the second insulating layer 12. The second rewiring portion 222 is connected to the first rewiring portion 212. The second rewiring portions 222 of the multiple second wirings 22 are in contact with the second grooves 121 of the second insulating layer 12. Therefore, the second rewiring portions 222 of the multiple second wirings 22 are configured such that parts of them are embedded in the multiple second grooves 121.

[0042] 23 and 24 , the second embedded portions 221 of the plurality of second wirings 22 are connected to the first rewiring portions 212 of the plurality of first wirings 21. As a result, the semiconductor element 30 is electrically connected to the plurality of second wirings 22 via the plurality of first wirings 21. The second embedded portions 221 of the plurality of second wirings 22 are covered with the second insulating layer 12. As shown in FIGS. 20 and 22 , the second rewiring portions 222 of the plurality of second wirings 22 include portions that overlap with the first rewiring portions 212 of the plurality of first wirings 21 when viewed in the thickness direction z.

[0043] As shown in FIG. 25 , each of the second embedded portions 221 of the multiple second wirings 22 and the second rewiring portions 222 of the multiple second wirings 22 has an underlayer 22A and a plating layer 22B. The underlayer 22A is composed of metal elements contained in an additive contained in the second insulating layer 12. The plating layer 22B is made of a material containing, for example, copper. The underlayer 22A of the second embedded portion 221 is in contact with the second insulating layer 12. The plating layer 22B of the second embedded portion 221 is surrounded by the underlayer 22A of the second embedded portion 221 around the thickness direction z. The underlayer 22A of the second rewiring portion 222 is in contact with one of the multiple second grooves 121 of the second insulating layer 12. The plating layer 22B of the second rewiring portion 222 covers the underlayer 22A of the second rewiring portion 222. As shown in FIG. 26, the plating layer 22B of the second wiring portion 222 has a recess 222A recessed in the thickness direction z. The recess 222A extends in the direction in which any one of the second rewiring portions 222 of the plurality of second wirings 22 extends.

[0044] 23 and 24, the protective layer 42 is in contact with the fourth surface 12B of the second insulating layer 12. The second re-wiring portions 222 of the multiple second wirings 22 are covered with the protective layer 42. Portions of the second re-wiring portions 222 of the multiple second wirings 22 are exposed from the multiple openings 421 of the protective layer 42. As shown in FIGS. 21 and 25, the multiple terminals 50 are individually bonded to portions of the second re-wiring portions 222 of the multiple second wirings 22 that are exposed from the multiple openings 421.

[0045] Next, the effects of the semiconductor device A20 will be described.

[0046] The semiconductor device A20 includes a first insulating layer 11 having a second surface 11B and a plurality of first wirings 21 each having a first embedded portion 211 and a first rewiring portion 212. The first rewiring portions 212 of the plurality of first wirings 21 are disposed on the second surface 11B and are connected to the first embedded portions 211 of the plurality of first wirings 21, which are connected to a plurality of electrodes 31 of a semiconductor element 30. The first insulating layer 11 has a plurality of first grooves 111 recessed from the second surface 11B in the thickness direction z. The first rewiring portions 212 of the plurality of first wirings 21 are in contact with the plurality of first grooves 111. Therefore, the semiconductor device A20 also suppresses misalignment at the joints between the plurality of electrodes 31 of the semiconductor element 30 and the plurality of first wirings 21.

[0047] The semiconductor device A20 further includes a second insulating layer 12 having a third surface 12A and a fourth surface 12B, and a plurality of second wirings 22 having second embedded portions 221 and second rewiring portions 222. The third surface 12A is in contact with the second surface 11B of the first insulating layer 11. The second rewiring portions 222 of the plurality of second wirings 22 are disposed on the fourth surface 12B and connected to the second embedded portions 221 of the plurality of second wirings 22 embedded in the second insulating layer 12. The first rewiring portions 212 of the plurality of first wirings 21 are connected to the second embedded portions 221 of the plurality of second wirings 22 and are covered by the second insulating layer 12. This allows the plurality of first wirings 21 and the plurality of second wirings 22 to be arranged in a multilayer configuration in the thickness direction z in the semiconductor device A20. Therefore, when viewed in the thickness direction z, the second rewiring portions 222 of the multiple second wirings 22 can be arranged to overlap the first rewiring portions 212 of the multiple first wirings 21. Therefore, the semiconductor device A20 can have a more complex wiring pattern than the semiconductor device A10.

[0048] Third Embodiment A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to Figures 27 to 32. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted.

[0049] The semiconductor device A30 differs from the previously described semiconductor device A10 in that it further includes a heat dissipation member 23 and a bonding layer 39, and in the configurations of the first embedded portions 211 of the plurality of first wirings 21 and the semiconductor element 30. Here, for ease of understanding, FIG. 27 shows the heat dissipation member 23, bonding layer 39, and sealing resin 41 in a see-through manner. For ease of understanding, FIG. 29 shows the first insulating layer 11, protective layer 42, and plurality of terminals 50 in a see-through manner. Note that the outlines of the heat dissipation member 23 and bonding layer 39 shown in FIG. 27 are shown by imaginary lines.

[0050] In the semiconductor device A30, the semiconductor element 30 is a switching element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The device A30 is used in DC / DC converters and inverters for various electrical appliances.

[0051] 30 and 31 , the heat dissipation member 23 is located on the opposite side of the semiconductor element 30 from the first insulating layer 11 in the thickness direction z. At least a portion of the heat dissipation member 23 is covered with a sealing resin 41. The heat dissipation member 23 is a metal plate containing, for example, copper. The heat dissipation member 23 not only dissipates heat generated from the semiconductor element 30 to the outside when the semiconductor device A30 is in use, but also forms, together with the multiple first wirings 21, a conductive path to the semiconductor element 30.

[0052] In the semiconductor device A30, the semiconductor element 30 is, for example, a MOSFET made of a semiconductor material mainly composed of silicon carbide (SiC). Note that the semiconductor element 30 is not limited to a MOSFET and may be a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) or a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor). The description of the semiconductor device A30 will be directed to a case where the semiconductor element 30 is an n-channel MOSFET.

[0053] 27 and 29 to 32, the multiple electrodes 31 of the semiconductor element 30 include a principal surface electrode 311 and a gate electrode 312. As viewed in the thickness direction z, the area of ​​the principal surface electrode 311 is larger than the area of ​​the gate electrode 312. A source current flows through the principal surface electrode 311 from inside the semiconductor element 30. A gate voltage for driving the semiconductor element 30 is applied to the gate electrode 312.

[0054] 32, the semiconductor element 30 has a back surface electrode 32 and an insulating film 33. As shown in FIGS. 30 to 32, the back surface electrode 32 is located farther from the first surface 11A of the first insulating layer 11 in the thickness direction z than the main surface electrode 311 and the gate electrode 312 are. The back surface electrode 32 faces the heat dissipation member 23. The back surface electrode 32 is provided over the entire surface of the semiconductor element 30 facing the heat dissipation member 23. A drain current flows through the back surface electrode 32 toward the inside of the semiconductor element 30.

[0055] 32, the insulating film 33 is provided near the first surface 11A of the first insulating layer 11, similar to the principal surface electrode 311 and the gate electrode 312. As shown in FIG. 29, the insulating film 33 surrounds each of the principal surface electrode 311 and the gate electrode 312 when viewed in the thickness direction z. The insulating film 33 is formed of, for example, a silicon dioxide (SiO2) layer, a silicon nitride (Si3N4) layer, a polybenzoxazole (PBO) layer, or the like, in the thickness direction z toward the first surface 11A. ) layer is laminated in this order. Note that the insulating film 33 may be a polyimide layer instead of the polybenzoxazole layer.

[0056] As shown in Figures 30 to 32, the bonding layer 39 is interposed between the back electrode 32 of the semiconductor element 30 and the heat dissipation member 23. The bonding layer 39 is, for example, a lead-free solder containing tin as its main component, or baked silver. This bonds the back electrode 32 to the heat dissipation member 23. In addition, the heat dissipation member 23 is electrically connected to the back electrode 32 via the bonding layer 39.

[0057] 30 , the first embedded portions 211 of the multiple first wirings 21 include those embedded in the first insulating layer 11 and those embedded in both the first insulating layer 11 and the sealing resin 41. The first embedded portions 211 of the multiple first wirings 21 embedded in the first insulating layer 11 are connected to the multiple electrodes 31 (main surface electrodes 311 and gate electrodes 312) of the semiconductor element 30. The first embedded portions 211 of the multiple first wirings 21 embedded in both the first insulating layer 11 and the sealing resin 41 are joined to the heat dissipation member 23.

[0058] Next, the effects of the semiconductor device A30 will be described.

[0059] The semiconductor device A30 includes a first insulating layer 11 having a second surface 11B, a first embedded portion 211, and a The semiconductor device A30 also includes a plurality of first wirings 21 having first rewiring portions 212. The first rewiring portions 212 of the plurality of first wirings 21 are arranged on the second surface 11B and connected to first embedded portions 211 of the plurality of first wirings 21 that are connected to a plurality of electrodes 31 of the semiconductor element 30. The first insulating layer 11 has a plurality of first grooves 111 recessed from the second surface 11B in the thickness direction z. The first rewiring portions 212 of the plurality of first wirings 21 are in contact with the plurality of first grooves 111. Therefore, the semiconductor device A30 also suppresses misalignment at the joints between the plurality of electrodes 31 of the semiconductor element 30 and the plurality of first wirings 21.

[0060] The semiconductor device A30 further includes a heat dissipation member 23 located on the opposite side of the semiconductor element 30 from the first insulating layer 11. A back electrode 32 of the semiconductor element 30 and a part of the first embedded portions 211 of the plurality of first wirings 21 are joined to the heat dissipation member 23. As a result, when the semiconductor element 30 is an n-channel MOSFET, the heat dissipation member 23 serves as a conductive path of the semiconductor element 30 through which a drain current flows. Additionally, when the semiconductor device A30 is in use, heat generated from the semiconductor element 30 can be efficiently dissipated to the outside.

[0061] [Fourth embodiment] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 33 to 35. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated descriptions will be omitted.

[0062] The semiconductor device A40 differs from the semiconductor device A10 described above in that it further includes a plurality of through-hole wirings 24 and a light-transmitting resin 43, and in the configurations of the first insulating layer 11, the semiconductor element 30, and the plurality of terminals 50. The semiconductor device A40 also does not include a protective layer 42. For ease of understanding, FIG. 33 shows the light-transmitting resin 43 in a transparent manner. For ease of understanding, FIG. 34 shows the first insulating layer 11 and the plurality of first wirings 21 in a transparent manner, as compared to FIG. 33. Note that the outline of the first insulating layer 11 through which light is transmitted is shown by an imaginary line in FIG. 34.

[0063] 33 to 35, the first insulating layer 11 includes portions that are spaced apart from each other in the first direction x. As a result, the semiconductor element 30 includes portions that are not covered by the first insulating layer 11. In the semiconductor device A40, the semiconductor element 30 is an optical element that emits light from these portions. In the example shown in the semiconductor device A40, the optical element is an LED. When a voltage is applied to the multiple electrodes 31 of the semiconductor element 30, light is emitted from these portions in the thickness direction z.

[0064] 33 and 34, the plurality of through wirings 24 are located outward from the semiconductor element 30 when viewed in the thickness direction z. As shown in FIG. 35, the plurality of through wirings 24 are connected to the first rewiring portions 212 of the plurality of first wirings 21. The plurality of through wirings 24 extend in the thickness direction z from the first rewiring portions 212 of the plurality of first wirings 21 and penetrate the sealing resin 41. The plurality of through wirings 24 are made of a material containing, for example, copper.

[0065] 35, the light-transmitting resin 43 is in contact with the sealing resin 41. The light-transmitting resin 43 covers the first insulating layer 11, the semiconductor element 30, and a portion of each of the first rewiring portions 212 of the plurality of first wirings 21. Light emitted from the semiconductor element 30 passes through the light-transmitting resin 43. The light-transmitting resin 43 is made of a material including, for example, a transparent epoxy resin or a synthetic resin containing silicone.

[0066] 35, the terminals 50 are individually joined to parts of the through wires 24 exposed from the sealing resin 41. The terminals 50 protrude from the sealing resin 41 in the thickness direction z.

[0067] Next, the effects of the semiconductor device A40 will be described.

[0068] The semiconductor device A40 includes a first insulating layer 11 having a second surface 11B and a plurality of first wirings 21 each having a first embedded portion 211 and a first rewiring portion 212. The first rewiring portions 212 of the plurality of first wirings 21 are disposed on the second surface 11B and are connected to the first embedded portions 211 of the plurality of first wirings 21, which are connected to a plurality of electrodes 31 of the semiconductor element 30. The first insulating layer 11 has a plurality of first grooves 111 recessed from the second surface 11B in the thickness direction z. The first rewiring portions 212 of the plurality of first wirings 21 are in contact with the plurality of first grooves 111. Therefore, the semiconductor device A40 also suppresses misalignment at the joints between the plurality of electrodes 31 of the semiconductor element 30 and the plurality of first wirings 21.

[0069] In the semiconductor device A40, the semiconductor element 30 is an optical element that emits light from a portion not covered by the first insulating layer 11. The semiconductor device A40 further includes a plurality of through-wirings 24 that are located outward of the semiconductor element 30 in the thickness direction z and that are connected to the first rewiring portions 212 of the plurality of first wirings 21. The plurality of through-wirings 24 extend in the thickness direction z from the first rewiring portions 212 of the plurality of first wirings 21 and penetrate the sealing resin 41. This allows the semiconductor device A40 to be mounted on the wiring board so as to face the wiring board in the thickness direction z in a direction opposite to the direction in which light is emitted from the semiconductor element 30.

[0070] The present disclosure is not limited to the above-described embodiments. For example, while the above-described embodiments each include a single semiconductor element 30, multiple semiconductor elements may be used. Furthermore, while the above-described embodiments each have a rectangular outer shape when viewed in the thickness direction z, the outer shape is not limited to a rectangular shape and may be, for example, a circular or hexagonal shape. The specific configuration of each part of the present disclosure can be freely designed in various ways.

[0071] The present disclosure includes the embodiments described in the appendix below.

[0072] Supplementary Note 1: A first insulating layer having a first surface and a second surface facing opposite to each other in a thickness direction; a plurality of first wirings each having a first buried portion at least partially buried in the first insulating layer, and a first rewiring portion disposed on the second surface and connected to the first buried portion; a semiconductor element provided near the first surface, having a plurality of electrodes connected to at least a portion of the first embedded portions of the plurality of first wirings, and in contact with the first surface; a sealing resin in contact with the first surface and covering a portion of the semiconductor element, When viewed in the thickness direction, the first rewiring portions of the plurality of first wirings include portions positioned outward from the semiconductor element, the first insulating layer has a plurality of first grooves recessed from the second surface in the thickness direction, The semiconductor device, wherein the first rewiring portions of the plurality of first wirings are in contact with the plurality of first grooves.

[0073] Appendix 2: The semiconductor device according to Appendix 1, wherein the first insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a portion of the plurality of first wirings.

[0074] Supplementary Note 3: Each of the first rewiring portions of the plurality of first wirings has an underlayer in contact with any one of the plurality of first grooves and a plating layer covering the underlayer; the underlayer is composed of the metal element contained in the additive, 3. The semiconductor device according to claim 2, wherein the plating layer has a recess that is recessed in the thickness direction.

[0075] Supplementary Note 4: The recessed portion is formed in a direction in which any one of the first rewiring portions of the plurality of first wirings extends. 4. The semiconductor device of claim 3, wherein the semiconductor device extends along the

[0076] Appendix 5. Further comprising a protective layer in contact with the second surface, the protective layer has a plurality of openings penetrating in the thickness direction, 5. The semiconductor device according to claim 4, wherein a portion of the first rewiring portions of the plurality of first wirings is exposed from the plurality of openings.

[0077] Appendix 6. Further comprising a plurality of terminals, the plurality of terminals are individually joined to parts of the first rewiring portions of the plurality of first wirings exposed from the plurality of openings; 6. The semiconductor device according to claim 5, wherein the terminals protrude from the protective layer in the thickness direction.

[0078] Appendix 7. The semiconductor device according to Appendix 6, wherein the plurality of terminals are made of a material containing tin.

[0079] Supplementary Note 8: A second insulating layer having a third surface and a fourth surface facing opposite to each other in a thickness direction, the third surface being in contact with the second surface; a second buried portion buried in the second insulating layer, and a plurality of second wirings disposed on the fourth surface and having second rewiring portions connected to the second buried portion; 5. The semiconductor device according to claim 1, wherein the first rewiring portions of the plurality of first wirings are connected to the second buried portions of the plurality of second wirings and are covered by the second insulating layer.

[0080] Appendix 9. The semiconductor device according to Appendix 8, wherein, when viewed in the thickness direction, the second rewiring portions of the plurality of second wirings include portions that overlap the first rewiring portions of the plurality of first wirings.

[0081] Addendum 10. The second insulating layer has a plurality of second grooves recessed from the fourth surface toward the thickness direction, 10. The semiconductor device according to claim 9, wherein the second rewiring portions of the second wirings are in contact with the second grooves.

[0082] Appendix 11. The semiconductor device according to Appendix 10, wherein the second insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a portion of the plurality of second wirings.

[0083] Addendum 12. The semiconductor device further includes a heat dissipation member located on the opposite side of the first insulating layer with respect to the semiconductor element, the plurality of electrodes include a principal surface electrode and a gate electrode; the semiconductor element has a back surface electrode located farther from the first surface in the thickness direction than the main surface electrode and the gate electrode; the back surface electrode and a part of the first embedded portions of the plurality of first wirings are joined to the heat dissipation member; 12. The semiconductor device according to claim 1, wherein at least a portion of the heat dissipation component is covered with the sealing resin.

[0084] Supplementary Note 13: The semiconductor element is an optical element in which a portion not covered with the first insulating layer emits light; Further, the semiconductor device includes a plurality of through wirings located outward from the semiconductor element as viewed in the thickness direction and connected to the first rewiring portions of the plurality of first wirings, The plurality of through wirings extend from the first rewiring portions of the plurality of first wirings in the thickness direction. 5. The semiconductor device according to claim 1, wherein the insulating film is formed on the insulating film and penetrates the sealing resin.

[0085] Supplementary Note 14: Further comprising a light-transmitting resin in contact with the sealing resin; 14. The semiconductor device according to claim 13, wherein the translucent resin covers a portion of each of the first insulating layer, the semiconductor element, and the first rewiring portions of the plurality of first wirings.

[0086] Appendix 15. Further comprising a plurality of terminals, the plurality of terminals are individually joined to portions of the plurality of through-wires exposed from the sealing resin, 15. The semiconductor device according to claim 13, wherein the plurality of terminals protrude from the sealing resin in the thickness direction.

[0087] Addendum 16. A process of embedding a semiconductor element having a plurality of electrodes provided on either side in a thickness direction in a sealing resin so that the plurality of electrodes are exposed; forming an insulating layer laminated on the sealing resin and covering the plurality of electrodes; forming a plurality of wirings each having a buried portion that is buried in the insulating layer and connected to any one of the plurality of electrodes, and a rewiring portion that is disposed on the insulating layer and connected to the buried portion; the insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of the plurality of wirings; The step of forming the plurality of wirings includes a step of forming, in the insulating layer using a laser, a plurality of holes exposing the plurality of electrodes and a plurality of grooves recessed from the surface of the insulating layer and connected to the plurality of holes while image-recognizing the positions of the plurality of electrodes, thereby depositing an underlayer covering wall surfaces defining each of the plurality of holes and the plurality of grooves; and forming a plating layer that covers the underlayer.

[0088] Appendix 17. The method for manufacturing a semiconductor device according to Appendix 16, wherein in the step of forming the plating layer, the plating layer is formed by electroless plating.

Claims

1. a semiconductor element having a main surface and a rear surface facing opposite to each other in a first direction, a first electrode and a control electrode formed on the main surface, and a second electrode formed on the rear surface; a first insulating layer having a first surface facing the main surface of the element; a first wiring including a first buried portion electrically connected to the first electrode and at least a portion of which is buried in the first insulating layer, and a first rewiring portion connected to the first buried portion; a second wiring including a second buried portion electrically connected to the control electrode and at least a portion of which is buried in the first insulating layer, and a second rewiring portion connected to the second buried portion; a third wiring including a third buried portion that is electrically connected to the second electrode and at least a portion of which is buried in the first insulating layer, and a third rewiring portion that is connected to the third buried portion; In a cross section in which the first direction and a second direction perpendicular to the first direction are in-plane directions, the dimension of the third rewiring portion in the second direction is larger than the dimension of the second rewiring portion in the second direction.

2. 2 . The semiconductor device according to claim 1 , wherein at least one of the first rewiring section and the third rewiring section includes a portion located outward from the semiconductor element when viewed in the first direction.

3. a heat dissipation member located on the opposite side of the semiconductor element from the first insulating layer in the first direction, The semiconductor device according to claim 2 , wherein said second electrode is electrically connected to said third embedded portion via said heat dissipation member.

4. The semiconductor device according to claim 3 , wherein the dimension of said heat dissipation member in said first direction is larger than the dimension of said semiconductor element in said first direction.

5. The semiconductor device according to claim 3 , further comprising a second insulating layer laminated on said first surface.

6. At least a portion of the heat dissipation member is covered with the second insulating layer, The semiconductor device according to claim 5 , wherein the second insulating layer includes a portion located outward from each of the semiconductor element and the heat dissipation component when viewed in the first direction.

7. the heat dissipation member has an exposed surface facing the same side as the back surface of the element in the first direction, the exposed surface is exposed from the second insulating layer, The semiconductor device according to claim 6 , wherein the semiconductor element entirely overlaps the exposed surface when viewed in the first direction.

8. 8 . The semiconductor device according to claim 7 , wherein, when viewed in the first direction, each of the first rewiring portion and the third rewiring portion includes a portion located outward from the heat dissipation member.

9. 9. The semiconductor device according to claim 1, wherein in a cross section in which the first direction and the second direction are in-plane directions, a dimension of the first electrode in the second direction is larger than a dimension of the control electrode in the second direction.

10. the first insulating layer has a second surface facing the opposite side to the first surface in the first direction, and a plurality of grooves recessed from the second surface; each of the first rewiring portion, the second rewiring portion, and the third rewiring portion has a first portion individually accommodated in the plurality of grooves and a second portion connected to the first portion and protruding from the second surface; The semiconductor device according to claim 1 , wherein the second portion is in contact with the second surface.

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