Semiconductor device

Abstract

To provide a thin semiconductor device.SOLUTION: A semiconductor device includes a semiconductor element having an element main surface and an element back surface facing opposite each other in the thickness direction (z direction), a wiring layer 21 electrically connected to the semiconductor element, and a sealing resin 6 covering a portion of the wiring layer 21 and the semiconductor element. The wiring layer 21 has a wiring layer main surface 211 facing the element back surface and electrically connected to the semiconductor element, and a wiring layer back surface 212 facing the opposite side of the wiring layer main surface 211 in the z direction. The wiring layer back surface 212 includes a protruding portion 214 protruding in the z direction. The protruding portion 214 has a tapered cross-sectional shape when viewed in a direction perpendicular to the z direction.SELECTED DRAWING: Figure 33

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device equipped with a semiconductor element and a manufacturing method thereof. [Background technology]

[0002] In recent years, there have been leadless package semiconductor devices such as SON packages (Small Outline Non-leaded packages) and QFN packages (Quad Flat Non-leaded packages). Leadless package semiconductor devices have terminals for external connection that do not protrude from the sealing resin that seals the semiconductor element, which is advantageous for making the semiconductor device smaller and thinner. For example, Patent Document 1 discloses such a leadless package semiconductor device.

[0003] The semiconductor device described in Patent Document 1 includes a semiconductor element, a lead frame, multiple wires, and a sealing resin. The lead frame is made of, for example, copper. The lead frame has a die pad portion and multiple lead portions. The die pad portion supports the semiconductor element. Each of the multiple lead portions is electrically connected to the semiconductor element via a wire. The multiple lead portions are terminals for the external connection when the semiconductor device is mounted on a circuit board of an electronic device or the like. The sealing resin covers the semiconductor element. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-18846 Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional semiconductor devices, the lead frame is formed by processing a metal plate (copper plate). Semiconductor devices with such a lead frame structure have room for improvement in terms of making them thinner.

[0006] The present disclosure has been made in view of the above-mentioned problems, and has as its object to provide a semiconductor device that is thinned and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0007] A semiconductor device provided by a first aspect of the present disclosure comprises a semiconductor element having an element main surface and an element back surface facing opposite each other in a thickness direction, an internal electrode conductive to the semiconductor element, a sealing resin covering the semiconductor element and a portion of the internal electrode, and an external electrode exposed from the sealing resin and conductive to the internal electrode, wherein the internal electrode includes a wiring layer having a wiring layer main surface facing the element back surface and a wiring layer back surface facing opposite the wiring layer main surface in the thickness direction, and a columnar portion protruding in the thickness direction from the wiring layer main surface, wherein the columnar portion faces a first direction perpendicular to the thickness direction and has an exposed side surface exposed from the sealing resin, and the external electrode includes a first covering portion covering the exposed side surface.

[0008] In a preferred embodiment of the semiconductor device, the columnar portion has a top surface facing in the same direction as the main surface of the element, and the top surface is covered with the sealing resin.

[0009] In a preferred embodiment of the semiconductor device, the columnar section includes a first seed layer and a first plating layer stacked on top of each other, and the first seed layer is in contact with the main surface of the wiring layer.

[0010] In a preferred embodiment of the semiconductor device, the wiring layer includes a second seed layer and a second plating layer stacked on top of each other, and the columnar portion is in contact with the second plating layer.

[0011] In a preferred embodiment of the semiconductor device, the first seed layer and the second seed layer are made of the same material, and the first plating layer and the second plating layer are made of the same material.

[0012] In a preferred embodiment of the semiconductor device, the wiring layer has an end face that faces the same direction as the exposed side face and is connected to the exposed side face, and the external electrode further includes a second covering portion that covers the end face and is connected to the first covering portion.

[0013] In a preferred embodiment of the semiconductor device, the external electrode further includes a third covering portion that covers a part of the rear surface of the wiring layer and is connected to the second covering portion.

[0014] In a preferred embodiment of the semiconductor device, the semiconductor device further comprises a first insulating film made of an insulating resin material, and the rear surface of the wiring layer has an electrode-covered region covered by the external electrode and an insulating film-covered region covered by the first insulating film.

[0015] In a preferred embodiment of the semiconductor device, the first insulating film has an insulating film main surface facing the same direction as the element main surface and an insulating film back surface facing the opposite side to the insulating film main surface, and includes an opening that connects from the insulating film main surface to the insulating film back surface in the thickness direction, and the internal electrode includes a filling portion that fills the opening.

[0016] In a preferred embodiment of the semiconductor device, the semiconductor device further comprises a metal layer that overlaps the opening when viewed in the thickness direction and is connected to the filling portion.

[0017] In a preferred embodiment of the semiconductor device, the main surface of the wiring layer is rougher than the rear surface of the wiring layer.

[0018] In a preferred embodiment of the semiconductor device, the exposed side surface is rougher than the main surface of the wiring layer.

[0019] In a preferred embodiment of the semiconductor device, the external electrodes are made of a Ni layer, a Pd layer, and an Au layer stacked one on top of the other.

[0020] In a preferred embodiment of the semiconductor device, the semiconductor device further comprises a conductive bonding material interposed between the semiconductor element and the wiring layer to electrically bond them together.

[0021] In a preferred embodiment of the semiconductor device, the semiconductor device further comprises a second insulating film interposed between the sealing resin and the internal electrode, and the second insulating film has a through hole filled with the conductive bonding material.

[0022] In a preferred embodiment of the semiconductor device, the columnar portion has a resin abutment side surface that faces a direction perpendicular to the thickness direction and abuts the sealing resin, and the columnar portion includes a protrusion that protrudes from the resin abutment side surface when viewed in the thickness direction, and the protrusion has an engagement surface that is connected to the resin abutment side surface and abuts the sealing resin.

[0023] In a preferred embodiment of the semiconductor device, the locking surface faces in the same direction as the exposed side surface.

[0024] In a preferred embodiment of the semiconductor device, the locking surface faces the main surface of the wiring layer.

[0025] A method for manufacturing a semiconductor device provided by a second aspect of the present disclosure is characterized by including the steps of: preparing a support substrate; forming an internal electrode; forming an internal electrode including a wiring layer having a wiring layer main surface and a wiring layer back surface facing opposite each other in a thickness direction, with the wiring layer back surface facing the support substrate, and a columnar portion protruding from the wiring layer main surface; conductively joining a semiconductor element onto the wiring layer; forming a sealing resin covering the semiconductor element and the wiring layer main surface; removing the support substrate; forming an exposed side surface on the columnar portion facing a first direction perpendicular to the thickness direction and exposed from the sealing resin; and forming an external electrode covering the exposed side surface.

[0026] In a preferred embodiment of the method for manufacturing a semiconductor device, the internal electrode forming step is performed by electrolytic plating.

[0027] In a preferred embodiment of the method for manufacturing a semiconductor device, the external electrode forming step is performed by electroless plating. [Effects of the Invention]

[0028] According to the semiconductor device of the present disclosure, the semiconductor device can be made thinner. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 3] FIG. 1 is a side view showing a semiconductor device according to a first embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] 5 is an enlarged cross-sectional view of a main part of the cross section shown in FIG. 4. FIG. [Figure 6] 5 is an enlarged cross-sectional view of a main part of the cross section shown in FIG. 4. FIG. [Figure 7] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 8] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 9] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 10] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 11] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 12] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 13] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 14] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 15] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 16] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 17] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 18] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 19] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 20] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 21] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 22] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 23] 2 is a plan view showing a process according to a method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 24] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 25] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 26] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 27] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 28] 2 is a bottom view showing a step in the method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 29] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 30] 2 is a bottom view showing a step in the method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 31] 2A to 2C are cross-sectional views showing steps in a method for manufacturing the semiconductor device of FIG. [Figure 32] 2 is a bottom view showing a step in the method for manufacturing the semiconductor device of FIG. 1. FIG. [Figure 33] FIG. 10 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modified example of the first embodiment. [Figure 34] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 35] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 36] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 37] 37A to 37C are cross-sectional views showing steps in the manufacturing method of the semiconductor device of FIG. 36. [Figure 38] 37A to 37C are cross-sectional views showing steps in the manufacturing method of the semiconductor device of FIG. 36. [Figure 39] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modified example of the fourth embodiment. [Figure 40] FIG. 10 is a plan view showing a semiconductor device according to a fifth embodiment. [Figure 41] FIG. 41 is a cross-sectional view taken along line FF in FIG. 40. [Figure 42] FIG. 10 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. [Figure 43] 43A to 43C are cross-sectional views showing steps in the manufacturing method of the semiconductor device of FIG. 42. [Figure 44] FIG. 10 is a plan view showing a semiconductor device according to a modified example. [Figure 45] FIG. 10 is a plan view showing a semiconductor device according to a modified example. [Figure 46] FIG. 10 is a plan view showing a semiconductor device according to a modified example. [Figure 47] FIG. 10 is a plan view showing a semiconductor device according to a modified example. [Figure 48] FIG. 48 is a cross-sectional view taken along line GG in FIG. 47. DETAILED DESCRIPTION OF THE INVENTION

[0030] Preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device of the present disclosure will be described below with reference to the drawings.

[0031] [First embodiment] 1 to 6 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a semiconductor element 1, internal electrodes 2, external electrodes 3, an insulating film 41, a conductive bonding material 5, and a sealing resin 6.

[0032] FIG. 1 is a plan view showing the semiconductor device A1. In FIG. 1, the sealing resin 6 is omitted. FIG. 2 is a bottom view showing the semiconductor device A1. FIG. 3 is a side view showing the semiconductor device A1. FIG. 3 shows the side of the semiconductor device A1 when viewed in the x direction, which will be described later. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. 1. FIG. 5 is an enlarged cross-sectional view of a main part of FIG. 4. FIG. 6 is an enlarged cross-sectional view of a main part of FIG. 4. For convenience of explanation, three mutually orthogonal directions are defined as the x direction, y direction, and z direction. The z direction is the thickness direction of the semiconductor device A1. The x direction is the left-right direction in the plan view of the semiconductor device A1. The y direction is the up-down direction in the plan view of the semiconductor device A1. The x direction and z direction correspond to the "first direction" and "thickness direction," respectively, described in the claims.

[0033] The semiconductor device A1 is a resin package that is surface-mounted on circuit boards of various electronic devices, etc. As shown in Figures 1 and 2, the semiconductor device A1 has a rectangular shape when viewed in the z direction (hereinafter also referred to as "plan view"). The semiconductor device A1 in this embodiment is a so-called SON package type.

[0034] The semiconductor element 1 is an element that is the functional core of the semiconductor device A1. The semiconductor element 1 is, for example, an integrated circuit (IC) such as an LSI (Large Scale Integration). The semiconductor element 1 may also be a voltage control element such as an LDO (Low Drop Out), an amplifying element such as an operational amplifier, or a discrete semiconductor element such as a diode. The semiconductor element 1 is rectangular in plan view. The semiconductor element 1 is mounted on internal electrodes 2. The semiconductor element 1 overlaps an insulating film 41 in plan view. The semiconductor element 1 is mounted by flip-chip bonding.

[0035] The semiconductor element 1 has an element main surface 11 and an element back surface 12. The element main surface 11 and the element back surface 12 are spaced apart from each other in the z direction and face opposite directions. In this embodiment, both the element main surface 11 and the element back surface 12 are flat.

[0036] A plurality of electrode pads 13 and a passivation film 14 are formed on the rear surface 12 of the device. Each of the plurality of electrode pads 13 has a rectangular shape in a plan view. As shown in FIG. 6, each electrode pad 13 is bonded to a conductive bonding material 5. Each electrode pad 13 includes a first conductive portion 131 and a second conductive portion 132.

[0037] The first conductive portion 131 is made of, for example, Al (aluminum). The second conductive portion 132 is made of a Ni (nickel) layer, a Pd (palladium) layer, and an Au (gold) layer stacked one on top of the other. In the second conductive portion 132, the Ni layer abuts the first conductive portion 131. By providing the second conductive portion 132 in the electrode pad 13, it is possible to prevent the first conductive portion 131 made of Al from penetrating into the conductive bonding material 5.

[0038] The passivation film 14 is a protective film for the semiconductor element 1 formed to cover the element rear surface 12. The passivation film 14 is formed by laminating a SiN layer formed by, for example, a plasma CVD method and a polyimide resin layer formed by coating. The passivation film 14 has openings in multiple locations (four locations in this embodiment), and the electrode pads 13 are exposed from each of the openings.

[0039] The internal electrode 2 is a conductor disposed inside the semiconductor device A1. The internal electrode 2 is electrically connected to the semiconductor element 1. The internal electrode 2 includes a wiring layer 21 and a columnar portion 22.

[0040] The wiring layer 21 is composed of a seed layer 210a and a plating layer 210b stacked on top of each other. The seed layer 210a is composed of, for example, a first layer whose main component is Ti (titanium) and a second layer whose main component is Cu (copper). The seed layer 210a has a thickness of approximately 200 to 800 nm. The plating layer 210b is mainly composed of Cu. The z-direction dimension (hereinafter also referred to as "thickness") of the plating layer 210b is approximately 20 to 50 μm. Note that the materials and thicknesses of the seed layer 210a and the plating layer 210b are not limited to those described above. The seed layer 210a and the plating layer 210b correspond to the "second seed layer" and the "second plating layer" respectively in the claims. The wiring layer 21 has a wiring layer main surface 211, a wiring layer back surface 212, and an end surface 213.

[0041] The wiring layer main surface 211 faces the z direction and faces the element back surface 12 of the semiconductor element 1. The semiconductor element 1 is mounted on the wiring layer main surface 211 via a conductive bonding material 5. A portion of the wiring layer main surface 211 is covered with a sealing resin 6. The wiring layer back surface 212 faces the z direction and faces the opposite side to the wiring layer main surface 211. The wiring layer back surface 212 has an electrode-covered region 212a and an insulating film-covered region 212b. The electrode-covered region 212a is a region of the wiring layer back surface 212 that is covered with the external electrode 3. The insulating film-covered region 212b is a region of the wiring layer back surface 212 that is covered with the insulating film 41. In this embodiment, the electrode-covered region 212a is a region of the wiring layer back surface 212 other than the insulating film-covered region 212b. In this embodiment, the electrode-covered region 212a is disposed outward in the z direction from the insulating film-covered region 212b. Therefore, there is a step on the rear surface 212 of the wiring layer.

[0042] The end face 213 intersects the wiring layer rear surface 212 and faces outward in the x-direction. In this embodiment, the end face 213 also intersects the wiring layer main surface 211. The end face 213 is covered with the external electrode 3. Therefore, the end face 213 is not visible from outside the semiconductor device A1.

[0043] Each of the multiple columnar portions 22 protrudes in the z direction from the wiring layer 21 (wiring layer main surface 211). In this embodiment, the internal electrode 2 has four columnar portions 22. Each columnar portion 22 is a prism having a rectangular cross section in the xy plane. The shape of each columnar portion 22 is not limited and may be, for example, a cylinder or a polygonal prism. Each columnar portion 22 has a larger dimension in the z direction than the wiring layer 21. Each columnar portion 22 is composed of a seed layer 220a and a plating layer 220b stacked on top of each other. The seed layer 220a is composed of, for example, a first layer whose main component is Ti and a second layer whose main component is Cu. Therefore, the seed layer 210a and the seed layer 220a are made of the same material. The seed layer 220a has a thickness of approximately 200 to 800 nm. The plating layer 220b is mainly made of Cu. Therefore, the plating layer 210b and the plating layer 220b are made of the same material. The thickness of plating layer 220b is approximately 50 to 100 μm. Note that the materials and thicknesses of seed layer 220a and plating layer 220b are not limited to those described above. Seed layer 220a and plating layer 220b correspond to the "first seed layer" and "first plating layer" respectively in the claims.

[0044] As shown in FIG. 4 , each columnar portion 22 has a base end surface 221, a top surface 222, an exposed side surface 223, and a resin-contacting side surface 224. The base end surface 221 is a surface that contacts the wiring layer 21. The base end surface 221 is flat. The top surface 222 is a surface that faces the opposite side to the base end surface 221 in the z direction. In this embodiment, the top surface 222 is flat. The top surface 222 is covered with the sealing resin 6. In this embodiment, the top surface 222 overlaps the semiconductor element 1 when viewed in the x direction. In other words, the top surface 222 is disposed between the element main surface 11 and the element back surface 12 in the z direction. In each columnar portion 22, the exposed side surface 223 and the resin-contacting side surface 224 face either the x direction or the y direction, which are perpendicular to the z direction. In this embodiment, the exposed side surface 223 faces outward in the x direction. The exposed side surface 223 is exposed from the sealing resin 6. In this embodiment, the exposed side surface 223 is flush with the end surface 213. The resin abutment side surface 224 is in contact with the sealing resin 6. Therefore, the resin abutment side surface 224 is covered with the sealing resin 6.

[0045] In this embodiment, the internal electrode 2 has a z-direction dimension d1 shown in FIG. 5 of 100 μm or more. Alternatively, the z-direction dimension d1 may be approximately 100 to 150 μm. Furthermore, the surfaces of the internal electrode 2 that come into contact with the sealing resin 6 (the wiring layer main surface 211, the top surface 222, and the resin-contacting side surface 224) are roughened to a roughness of, for example, approximately 2 to 3 μm by a roughening treatment in the manufacturing method described below. In this embodiment, each surface that comes into contact with the sealing resin 6 is rougher than the wiring layer back surface 212. Furthermore, each surface that comes into contact with the sealing resin 6 is smoother than the exposed side surface 223. In other words, the exposed side surface 223 is rougher than the surface that comes into contact with the sealing resin 6.

[0046] The external electrodes 3 are conductors that are electrically connected to the internal electrodes 2 and are exposed to the outside of the semiconductor device A1. The external electrodes 3 are terminals used when mounting the semiconductor device A1 on a circuit board. The external electrodes 3 are formed by electroless plating. In this embodiment, the external electrodes 3 are made of a Ni layer, a Pd layer, and an Au layer that are stacked one on top of the other. The Ni layer is in contact with the internal electrode 2 and has a thickness of about 5 μm. The Au layer is exposed to the outside and has a thickness of about 0.01 to 0.02 μm. The Pd layer is interposed between the Ni layer and the Au layer and has a thickness of about 0.01 to 0.02 μm. The number, thickness, material, and formation method of the external electrodes 3 are not limited.

[0047] As shown in FIGS. 3 and 4 , each of the multiple external electrodes 3 includes a first covering portion 31, a second covering portion 32, and a third covering portion 33. The first covering portion 31 is a portion of the external electrode 3 that covers the exposed side surface 223 of the columnar portion 22. The second covering portion 32 is a portion of the external electrode 3 that covers the end surface 213 of the wiring layer 21. The third covering portion 33 is a portion that covers a part (electrode covered region 212a) of the wiring layer rear surface 212 of the wiring layer 21. In this embodiment, two external electrodes 3 are visible on each of the two side surfaces facing the x direction of the semiconductor device A1, and four external electrodes 3 are visible from the bottom surface of the semiconductor device A1. The first covering portion 31, the second covering portion 32, and the third covering portion 33 are integrally formed. The multiple external electrodes 3 are insulated from each other by an insulating film 41.

[0048] The insulating film 41 is made of an insulating material, such as polyimide resin or phenol resin. The insulating film 41 is provided on the bottom side of the semiconductor device A1. In this embodiment, the insulating film 41 is arranged lower in the z-direction than the sealing resin 6. In this embodiment, the insulating film 41 has a rectangular shape in a plan view, as shown in FIG. 1. The shape of the insulating film 41 in a plan view is not limited. The insulating film 41 corresponds to a "first insulating film" recited in the claims. The insulating film 41 has an insulating film main surface 411 and an insulating film back surface 412 facing opposite to each other in the z-direction.

[0049] The insulating film main surface 411 faces the same direction as the element main surface 11 of the semiconductor element 1 and faces the element back surface 12 of the semiconductor element 1. The insulating film back surface 412 faces the same direction as the element back surface 12. The insulating film main surface 411 contacts a part (insulating film covered region 212b) of the wiring layer back surface 212 of the wiring layer 21. The insulating film back surface 412 is flush with a part (electrode covered region 212a) of the wiring layer back surface 212 of the wiring layer 21.

[0050] As shown in FIGS. 4 and 6, the conductive bonding material 5 is a conductive member interposed between the wiring layer 21 of the internal electrode 2 and the electrode pad 13 of the semiconductor element 1. In this embodiment, the conductive bonding material 5 is made of a Ni layer in contact with the wiring layer 21 and a solder layer in contact with the Ni layer. The solder layer is made of an alloy containing Sn (tin). Examples of such alloys include lead-free solder such as an Sn—Sb alloy or an Sn—Ag alloy, and a solder containing Pb (lead). The semiconductor element 1 is fixed to the wiring layer 21 (internal electrode 2) by the conductive bonding material 5.

[0051] The sealing resin 6 is a synthetic resin whose main component is, for example, a black epoxy resin. As shown in Fig. 4, the sealing resin 6 covers the semiconductor element 1, a portion of the internal electrodes 2, and the conductive bonding material 5. The sealing resin 6 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 63.

[0052] The resin main surface 61 faces the same direction as the element main surface 11. As shown in FIG. 3, the resin back surface 62 faces the same direction as the element back surface 12. The resin back surface 62 contacts the internal electrode 2 and the insulating film 41. Each resin side surface 63 is perpendicular to the resin main surface 61 and the resin back surface 62. In this embodiment, the sealing resin 6 has two resin side surfaces 63 facing opposite each other in the x direction and two resin side surfaces 63 facing opposite each other in the y direction. In this embodiment, as shown in FIG. 3, two external electrodes 3 are exposed from each of the two resin side surfaces 63 facing in the x direction. Furthermore, the external electrodes 3 are located outward of the semiconductor device A1 from each of the two resin side surfaces 63 facing in the x direction in a plan view.

[0053] Next, an example of a method for manufacturing the semiconductor device A1 will be described with reference to Figs. 7 to 32. Of Figs. 7 to 32, Figs. 9, 12, 14, 17, 19, 21, and 23 are plan views showing steps in the method for manufacturing the semiconductor device A1, and Figs. 28, 30, and 32 are bottom views showing steps in the method for manufacturing the semiconductor device A1. The other drawings are cross-sectional views showing steps in the method for manufacturing the semiconductor device A1. The cross-sections are the same as the cross-section shown in Fig. 4. For ease of understanding, the cross-sectional views shown in Figs. 25 to 27, 29, and 31 are shown upside down in the z direction relative to the other cross-sectional views.

[0054] First, as shown in FIG. 7 , a support substrate 800 having a main surface 800a and a back surface 800b facing the z direction is prepared. The support substrate 800 is, for example, a glass substrate or a Si (silicon) substrate. In this embodiment, in the step of preparing the support substrate 800 (support substrate preparation step), a light-transmitting glass substrate is used as the support substrate 800. The thickness of the support substrate 800 is approximately 0.5 μm. Next, as shown in FIG. 7 , a temporary fixing material 801 is formed on the support substrate 800. In the step of forming the temporary fixing material 801 (temporary fixing material formation step), the temporary fixing material 801 is formed so as to cover the entire main surface 800a. Then, as shown in FIG. 7 , a sputtered film 802 is formed on the temporary fixing material 801. In the step of forming the sputtered film 802 (sputtered film formation step), the sputtered film 802 is formed so as to cover the entire surface of the temporary fixing material 801. The sputtered film 802 is a metal film whose main component is Ti.

[0055] Next, as shown in FIGS. 8 and 9, an insulating film 841 is formed. The insulating film 841 corresponds to the insulating film 41 of the semiconductor device A1. The insulating film 841 is made of a photosensitive resin material, such as polyimide resin or phenol resin. In the step of forming the insulating film 841 (insulating film forming step), the insulating film 841 is applied onto the sputtered film 802 using, for example, a spin coater (spin coating device), as shown in FIG. 8. Note that a film-like photosensitive resin material may also be applied. The photosensitive resin material is then exposed and developed to perform patterning. This forms the insulating film 841 shown in FIGS. 8 and 9. By forming the insulating film 841, the sputtered film 802 has a portion covered with the insulating film 841 and a portion exposed from the insulating film 841, as shown in FIG. 9. The portion of the sputtered film 802 exposed from the insulating film 841 will later become a portion corresponding to the electrode-covered region 212a of the wiring layer 21 of the semiconductor device A1.

[0056] Next, as shown in FIG. 10, a seed layer 820a is formed. A portion of the seed layer 820a will later correspond to a portion of the internal electrode 2 of the semiconductor device A1 (specifically, the seed layer 210a of the wiring layer 21). The seed layer 820a is formed by sputtering. The seed layer 820a is formed over the entire surface of the main surface 800a of the support substrate 800. The seed layer 820a in this embodiment is composed of a Ti layer and a Cu layer stacked on top of each other. In the step of forming the seed layer 820a (preceding seed layer formation step), a Ti layer in contact with the insulating film 841 and the sputtered film 802 is formed, and then a Cu layer in contact with the Ti layer is formed.

[0057] Next, as shown in FIGS. 11 and 12, a plating layer 820b is formed. The plating layer 820b corresponds to a portion of the internal electrode 2 of the semiconductor device A1 (specifically, the plating layer 210b of the wiring layer 21). The plating layer 820b is formed by patterning using photolithography and electroplating. In the step of forming the plating layer 820b (pre-plating layer forming step), a resist layer (not shown) for forming the plating layer 820b is first formed by photolithography. In forming the resist layer, a photosensitive resist is applied so as to cover the entire surface of the seed layer 820a, and the photosensitive resist is patterned by exposure and development. This patterning exposes a portion of the seed layer 820a (the portion where the plating layer 820b is to be formed). Then, the plating layer 820b is formed on the exposed seed layer 820a by electroplating using the seed layer 820a as a conductive path. Thereafter, the resist layer is removed, thereby forming the plating layer 820b shown in FIGS. 11 and 12.

[0058] Next, as shown in FIGS. 13 and 14, all unnecessary seed layer 820a that is not covered with plating layer 820b is removed. This unnecessary seed layer 820a is removed by wet etching. For example, a mixed solution of H2SO4 (sulfuric acid) and H2O2 (hydrogen peroxide) is used for this wet etching. By the step of removing the unnecessary seed layer 820a (previous seed layer removal step), as shown in FIGS. 13 and 14, the insulating film 841 is exposed from the portion where the seed layer 820a has been removed. Furthermore, by removing the unnecessary seed layer 820a, a wiring layer 821 made of the seed layer 820a and plating layer 820b is formed. This wiring layer 821 corresponds to the wiring layer 21 of the internal electrode 2 of the semiconductor device A1. Therefore, the wiring layer 821 is formed by a wiring layer formation step including a previous seed layer formation step, a previous plating layer formation step, and a previous seed layer removal step.

[0059] Next, as shown in FIG. 15, a seed layer 820c is formed. A portion of the seed layer 820c will later correspond to a portion of the internal electrode 2 of the semiconductor device A1 (specifically, the seed layer 220a of the columnar portion 22). The seed layer 820c is formed by a sputtering method. The seed layer 820c is formed over the entire surface of the main surface 800a side of the support substrate 800. The seed layer 820c according to this embodiment is composed of a Ti layer and a Cu layer stacked on top of each other. In the step of forming the seed layer 820c (subsequent seed layer formation step), a Ti layer is formed in contact with either the insulating film 841 or the plating layer 820b, and then a Cu layer is formed in contact with the Ti layer.

[0060] Next, as shown in FIGS. 16 and 17, a plating layer 820d is formed. The plating layer 820d corresponds to a portion of the internal electrode 2 of the semiconductor device A1 (specifically, the plating layer 220b of the columnar portion 22). The plating layer 820d is formed by pattern formation using photolithography and electrolytic plating. In the step of forming the plating layer 820d (the subsequent plating layer formation step), a resist layer (not shown) for forming the plating layer 820d is first formed by photolithography. In forming the resist layer, a photosensitive resist is applied so as to cover the entire surface of the seed layer 820c, and the photosensitive resist is patterned by exposure and development. This patterning exposes a portion of the seed layer 820c (the portion where the plating layer 820d is to be formed). Then, the plating layer 820d is formed on the exposed seed layer 820c by electrolytic plating using the seed layer 820c as a conductive path. Thereafter, the resist layer is removed to form the plating layer 820d shown in FIGS.

[0061] Next, as shown in FIGS. 18 and 19, a conductive bonding material 85 is formed. The conductive bonding material 85 corresponds to the conductive bonding material 5 of the semiconductor device A1. The conductive bonding material 85 is formed by patterning using photolithography and electrolytic plating. In the process of forming the conductive bonding material 85 (conductive bonding material forming process), a resist layer (not shown) for forming the conductive bonding material 85 is first formed on the seed layer 820c, and the resist layer is patterned. This patterning exposes a portion of the seed layer 820c (the portion where the conductive bonding material 85 is to be formed) from the resist layer. Then, electrolytic plating using the seed layer 820c as a conductive path forms the conductive bonding material 85 on the exposed portion. At this time, a first conductive layer in contact with the seed layer 820c and a second conductive layer in contact with the first conductive layer are sequentially stacked. In this embodiment, the first conductive layer is mainly composed of Ni, and the second conductive layer is mainly composed of lead-free solder such as a Sn—Ag alloy or a Sn—Sb alloy. The resist layer is then removed.

[0062] Next, as shown in FIGS. 20 and 21, all unnecessary seed layer 820c that is not covered by plating layer 820d and conductive bonding material 85 is removed. This unnecessary seed layer 820c is removed in the same manner as in the first seed layer removal process. That is, it is removed by wet etching using a mixed solution of H2SO4 (sulfuric acid) and H2O2 (hydrogen peroxide), for example. By the process of removing the unnecessary seed layer 820c (subsequent seed layer removal process), as shown in FIGS. 20 and 21, the wiring layer 821, the insulating film 841, and the sputtered film 802 are exposed from the portion where the seed layer 820c has been removed. Furthermore, by removing the unnecessary seed layer 820c, a columnar portion 822 made of the seed layer 820c and plating layer 820d is formed. The columnar portion 822 corresponds to the columnar portion 22 of the internal electrode 2 of the semiconductor device A1. Therefore, the columnar portion 822 is formed by a columnar portion forming process including a subsequent seed layer forming process, a subsequent plating layer forming process, and a subsequent seed layer removing process. In addition, since the internal electrode 82 includes the wiring layer 821 and the columnar portion 822, the process of forming the internal electrode 82 (internal electrode forming process) includes the wiring layer forming process and the columnar portion forming process.

[0063] Next, a roughening treatment is performed. The chemical used in the roughening treatment is not particularly limited as long as it reacts with the material (Cu) of the internal electrode 82 (the wiring layer 821 and the columnar portion 822). The roughening treatment roughens the surfaces of the wiring layer 821 and the columnar portion 822. This roughness is, for example, about 2 to 3 μm.

[0064] Next, as shown in FIGS. 22 and 23, a semiconductor element 81 is mounted. Note that in the following figures, including FIG. 22, the seed layer 820a and the plating layer 820b are referred to as the wiring layer 821 without distinction. Similarly, the seed layer 820c and the plating layer 820d are referred to as the columnar portion 822 without distinction. The semiconductor element 81 corresponds to the semiconductor element 1 of the semiconductor device A1. The process of mounting the semiconductor element 81 (semiconductor element mounting process) is performed by FCB (Flip Chip Bonding). After applying flux to the electrode pads (not shown) of the semiconductor element 81, the semiconductor element 81 is temporarily attached to a conductive bonding material 85 in a position facing the wiring layer 821 using a flip chip bonder. At this time, the conductive bonding material 85 is sandwiched between both the wiring layer 821 and the semiconductor element 81. Next, the conductive bonding material 85 is melted by reflow and then solidified by cooling, thereby completing the mounting of the semiconductor element 81.

[0065] Next, as shown in FIG. 24, a sealing resin 86 is formed to cover the semiconductor element 81. The sealing resin 86 corresponds to the sealing resin 6 of the semiconductor device A1. In this embodiment, the sealing resin 86 is a synthetic resin having electrical insulation properties, for example, a black epoxy resin as a main component. In the step of forming the sealing resin 86 (sealing resin forming step), the sealing resin 86 is formed on the support substrate 800 so as to cover the semiconductor element 81 without exposing it. The sealing resin 86 formed in the sealing resin forming step has a resin main surface 861. As shown in FIG. 24, the wiring layer 821 and the columnar portion 822 are covered with the sealing resin 86. After the sealing resin forming step, the sealing resin 86 may be ground from the resin main surface 861 side to reduce the thickness of the sealing resin 86. At this time, the grinding may be performed until the top surface of the semiconductor element 81 is exposed from the sealing resin 86.

[0066] Next, as shown in FIGS. 25 and 26, the support substrate 800 is peeled off. In the step of peeling off the support substrate 800 (support substrate peeling step), first, as shown in FIG. 25, a dicing tape 804 is attached to the resin main surface 861. Thereafter, for example, a laser is irradiated from the back surface 800b of the support substrate 800. At this time, the laser light passes through the support substrate 800 and is irradiated onto the temporary fixing material 801. This reduces the adhesion of the temporary fixing material 801, allowing the support substrate 800 to be peeled off. If the temporary fixing material 801 remains partially (for example, as soot) after the support substrate 800 is peeled off, this partially remaining temporary fixing material 801 is removed, for example, by plasma. By the above process, the support substrate 800 and the temporary fixing material 801 are removed, as shown in FIG. 26. It should be noted that the support substrate peeling step is not limited to laser irradiation. For example, the support substrate 800 and the like may be peeled off by blowing air from the x direction (the left-right direction in FIG. 25), or the temporary fixing material 801 may be softened by heating and then the support substrate 800 and the like may be peeled off. In the case of peeling off by laser irradiation, the support substrate 800 needs to be made of a material with appropriate light transmissivity to transmit laser light. On the other hand, in the case of peeling off by blowing air or peeling off by heating, a Si substrate, for example, may be used as the support substrate 800 instead of a glass substrate.

[0067] 27 and 28, the sputtered film 802 is removed. By the step of removing the sputtered film 802 (sputtered film removing step), an insulating film rear surface 841b of the insulating film 841 and a wiring layer rear surface 821b of the wiring layer 821 are exposed, as shown in FIG.

[0068] Next, as shown in FIGS. 29 and 30 , the sealing resin 86 is cut along the x and y directions, respectively, to separate it into individual pieces for each semiconductor element 81. The step of cutting the sealing resin 86 (cutting step) is performed by blade dicing. In this embodiment, the sealing resin 86 is separated into individual pieces for each semiconductor element 81 by cutting along cutting lines CL shown in FIGS. 27 and 28 . Note that the width in the short direction of the cutting lines CL shown in FIGS. 27 and 28 is the thickness of the dicing blade. In the cutting step of this embodiment, the dicing tape 804 is not completely cut in the z direction (it is cut a little), as shown by the cutting lines CL in FIG. 28 . As a result, even when the sealing resin 86 is separated into individual pieces for each semiconductor element 81, the pieces do not fall apart because they are connected by the dicing tape 804. As a result of the cutting step, as shown in FIG. 29 , a resin side surface 863 of the sealing resin 86, an end face 821c of the wiring layer 821, and an exposed side surface 822c of the columnar portion 822 are formed. These surfaces are exposed to the outside.

[0069] Next, as shown in FIGS. 31 and 32, an external electrode 83 is formed. The external electrode 83 corresponds to the external electrode 3 of the semiconductor device A1. The process of forming the external electrode 83 (external electrode forming process) is performed by electroless plating. In this embodiment, a Ni layer, a Pd layer, and an Au layer are deposited in this order by electroless plating. At this time, the Ni layer is formed so as to contact and cover the surfaces of the wiring layer 821 and the columnar portion 822 exposed from the insulating film 841 and the sealing resin 86. Then, a Pd layer is formed on the Ni layer, and an Au layer is formed on the Pd layer. Note that the external electrode 83 is not deposited on the insulating film 841. In this way, the external electrode 83 shown in FIGS. 31 and 32 is formed.

[0070] Next, peel off the dicing tape 804. Through the above steps, the semiconductor device A1 shown in FIGS.

[0071] Next, the effects of the semiconductor device A1 and the manufacturing method thereof according to the first embodiment will be described.

[0072] According to this embodiment, the semiconductor device A1 includes internal electrodes 2 formed by electrolytic plating and external electrodes 3 formed by electroless plating. Therefore, the semiconductor device A1 is wired by plating and does not use a lead frame formed from a metal plate. Wiring formed by plating can be thinner than when a lead frame structure is adopted. Therefore, the semiconductor device A1 can be made thinner. Furthermore, with the increasing integration of ICs and LSIs, the number of terminals has increased, necessitating the miniaturization of internal electrodes, etc. However, when using a lead frame, there is a limit to the miniaturization possible due to the need to process a metal plate. On the other hand, the semiconductor device A1 can accommodate miniaturization because the internal electrodes 2 are formed by plating. Therefore, it is possible to manufacture semiconductor devices with a larger number of terminals.

[0073] According to this embodiment, the internal electrode 2 includes a wiring layer 21 having an end face 213 exposed from the resin side face 63 and a columnar portion 22 having an exposed side face 223 exposed from the resin side face 63. The external electrode 3 also includes a second covering portion 32 covering the end face 213 and a first covering portion 31 covering the exposed side face 223. This configuration allows the z-direction dimension of the external electrode 3 formed on the side face of the semiconductor device A1 (the side face facing the x-direction in this embodiment) to be larger than when the columnar portion 22 is not included. Solder is used to mount the semiconductor device A1 on a circuit board or the like. If the internal electrode 2 were composed only of the wiring layer 21 without including the columnar portion 22, the external electrode 3 formed on the side face of the semiconductor device A1 would only be the second covering portion 32. In this case, the z-direction dimension of the second covering portion 32 alone would be too small, making it difficult to form a solder fillet when mounting the semiconductor device A1 on a circuit board. However, in this embodiment, the z-direction dimension of the external electrodes 3 formed on the side surfaces of the semiconductor device A1 can be increased, so that solder fillets can be formed when the semiconductor device A1 is mounted on a circuit board or the like. This increases the mounting strength of the semiconductor device A1 on the circuit board. In addition, the solder connection state can be visually confirmed from the side surfaces of the semiconductor device A1.

[0074] According to this embodiment, a roughening treatment is performed in the manufacturing process of the semiconductor device A1. This roughening treatment roughens the wiring layer main surface 211, the top surface 222, and the resin abutting side surface 224. This configuration improves the adhesion between the internal electrode 2 and the sealing resin 6.

[0075] In the first embodiment, the angle between the wiring layer rear surface 212 and the end surface 213 is approximately a right angle. However, during the cutting process, a protrusion may occur at the portion where the wiring layer rear surface 212 and the end surface 213 connect. FIG. 33 shows an enlarged cross-sectional view of a main portion when such a protrusion occurs. FIG. 33 corresponds to the enlarged cross-sectional view of a main portion in FIG. 5. FIG. 33 shows a case where a protrusion 214 protrudes in the z direction from the wiring layer rear surface 212 of the wiring layer 21. In this case, the external electrode 3 is formed so as to cover the protrusion 214. Note that the shape of the protrusion 214 shown in FIG. 33 is an example and is not limited to this. For example, the protrusion 214 may protrude in other directions, such as the x direction or the y direction, instead of the z direction.

[0076] In the first embodiment, when the semiconductor device A1 is viewed from the bottom side (see Figure 2), only the external electrode 3 is exposed from the insulating film 41, but this is not limited to this, and for example, a portion of the resin back surface 62 of the sealing resin 6 may be exposed from the insulating film 41.

[0077] Other embodiments of the semiconductor device and the method for manufacturing the semiconductor device of the present disclosure will be described below. In the other embodiments described below, elements that are the same as or similar to those in the first embodiment will be denoted by the same reference numerals and will not be described again.

[0078] Second Embodiment 34 shows a semiconductor device according to Embodiment 2. The semiconductor device A2 of this embodiment differs from the semiconductor device A1 (first embodiment) in that it further includes a metal layer 7.

[0079] Fig. 34 is a cross-sectional view showing the semiconductor device A2, which corresponds to the cross section shown in Fig. 4 of the first embodiment.

[0080] In this embodiment, the insulating film 41 has an opening 413. The opening 413 is connected in the z-direction from the insulating film main surface 411 to the insulating film rear surface 412. The shape of the opening 413 in a plan view is not particularly limited, but in this embodiment, it is rectangular. The opening 413 is formed by patterning during the insulating film formation step.

[0081] In this embodiment, the internal electrode 2 further includes a filling portion 23. The filling portion 23 is a portion of the internal electrode 2 that fills the opening 413 of the insulating film 41. The filling portion 23 is formed by the above-mentioned wiring layer forming step.

[0082] The metal layer 7 is made of a conductive metal material. In this embodiment, the metal layer 7 is formed by electroless plating, similar to the external electrodes 3. Therefore, the metal layer 7 is made of a Ni layer, a Pd layer, and an Au layer stacked one on top of the other. Note that the material and the method of forming the metal layer 7 are not limited to those described above. The metal layer 7 is connected to the filling portion 23 and exposed to the outside of the semiconductor device A2.

[0083] In the semiconductor device A2, wiring is performed by plating, so that the same effect as in the first embodiment can be achieved, that is, the semiconductor device A2 can be made thinner.

[0084] According to this embodiment, the semiconductor device A2 includes a metal layer 7. When the semiconductor device A2 is energized, the semiconductor element 1 generates heat. The heat generated from the semiconductor element 1 is transferred to the metal layer 7 and dissipated to the outside. Therefore, the metal layer 7 functions as a heat dissipation portion of the semiconductor device A2. With this configuration, the heat dissipation performance of the semiconductor device A2 can be improved. Furthermore, the metal layer 7 is made of metal and has conductivity. Therefore, the metal layer 7 can also be used as a terminal for external connection.

[0085] According to this embodiment, the metal layer 7 is formed by electroless plating in the same manner as the external electrodes 3. Therefore, the external electrodes 3 and the metal layer 7 can be formed at the same time.

[0086] Third Embodiment 35 shows a semiconductor device according to Embodiment 3. The semiconductor device A3 of this embodiment differs from the semiconductor device A1 (first embodiment) in that it further includes an insulating film .

[0087] Fig. 35 is a cross-sectional view showing the semiconductor device A3, which corresponds to the cross section shown in Fig. 4 of the first embodiment.

[0088] The insulating film 42 is made of an insulating material, such as polyimide resin. The insulating film 42 is sandwiched between the internal electrode 2 and the sealing resin 6. The insulating film 42 is formed, for example, by photolithography. The insulating film 42 is formed after the roughening treatment and before the semiconductor element mounting process. Therefore, since the insulating film 42 is formed after the conductive bonding material 5 (85) is formed, the insulating film 42 has through holes 421, and the through holes 421 are filled with the conductive bonding material 5. The insulating film 42 corresponds to the "second insulating film" recited in the claims.

[0089] In the semiconductor device A3, wiring is performed by plating, so that the same effect as in the first embodiment can be achieved, that is, the semiconductor device A3 can be made thinner.

[0090] In this embodiment, the insulating film 42 has a through hole 421, and the conductive bonding material 5 is formed so as to partially fill the through hole 421. The conductive bonding material 85 is softened by reflow during the semiconductor element mounting process. At this time, the softened conductive bonding material 85 may diffuse along the wiring layer main surface 211. However, in this embodiment, since the wiring layer main surface 211 is covered with the insulating film 42, the conductive bonding material 5 (85) can be prevented from diffusing along the wiring layer main surface 211.

[0091] [Fourth embodiment] 36 shows a semiconductor device according to the fourth embodiment. The semiconductor device A4 of this embodiment differs from the semiconductor device A1 (first embodiment) in that the resin side surface 63 of the sealing resin 6 has a step.

[0092] Fig. 36 is a cross-sectional view showing the semiconductor device A4, which corresponds to the cross section shown in Fig. 4 of the first embodiment.

[0093] 36 , each of the multiple resin side surfaces 63 includes a resin side surface first portion 631 and a resin side surface second portion 632. Both the resin side surface first portion 631 and the resin side surface second portion 632 are flat. The resin side surface first portion 631 is disposed outward from the resin side surface second portion 632 in a plan view. The resin side surface second portion 632 is flush with the exposed side surface 223 of the columnar portion 22 and the end face 213 of the wiring layer 21.

[0094] An example of a method for manufacturing the semiconductor device A4 will be described with reference to Fig. 37 and Fig. 38. Note that a description of parts common to the method for manufacturing the semiconductor device A1 according to the first embodiment will be omitted. Fig. 37 and Fig. 38 are cross-sectional views showing the manufacturing process of the semiconductor device A4.

[0095] In the manufacturing method of the semiconductor device A4, the steps from the support substrate preparation step (see FIG. 7) to the sputtered film removal step (see FIGS. 27 and 28) are performed in the same manner as in the first embodiment. However, in this embodiment, the dicing tape 804 does not need to be attached in the support substrate peeling step. Thereafter, as shown in FIG. 37, grooves 89 are formed. The step of forming the grooves 89 is performed, for example, by half-cut dicing using a dicing blade. In half-cut dicing, the grooves 89 are formed by not completely cutting the sealing resin 86 in the z direction. The depth of the grooves 89 is determined by the amount of cutting during the half-cut dicing, and the width of the grooves 89 is determined by the thickness of the dicing blade used. By half-cut dicing, an end face 821c of the wiring layer 821 and an exposed side face 822c of the columnar portion 822 are formed, exposed from the sealing resin 86, as shown in FIG. 37.

[0096] Next, as shown in FIG. 38, external electrodes 83 are formed. The external electrode formation process in this embodiment is performed by electroless plating, as in the first embodiment. As a result, external electrodes 83 are formed so as to cover the surfaces of the wiring layer 821 and the columnar portions 822 exposed from the sealing resin 86. Thereafter, the semiconductor device is cut along cutting lines CL2 shown in FIG. 38 to separate into individual pieces for each semiconductor element 81. The thickness of the dicing blade used when cutting along cutting lines CL2 is smaller than the thickness of the dicing blade used in the half-cut dicing. By performing the above steps, the semiconductor device A4 shown in FIG. 36 is manufactured. That is, a semiconductor device A4 having a step on the resin side surface 63 of the sealing resin 6 is manufactured.

[0097] In the semiconductor device A4 as well, wiring is performed by plating, so that the same effect as in the first embodiment can be achieved, that is, the semiconductor device A4 can be made thinner.

[0098] According to this embodiment, the dicing tape 804 is not applied in the support substrate peeling step. In the first embodiment, the sealing resin 86 is completely cut along the z direction in the cutting step. Therefore, it was necessary to fix the resin with the dicing tape 804 to prevent it from falling apart when the external electrode forming step (electroless plating) is performed. On the other hand, in this embodiment, the sealing resin 86 is continuous when the external electrode forming step is performed, so it will not fall apart even without the dicing tape 804. Therefore, there is no need to apply the dicing tape 804 in the method for manufacturing the semiconductor device A4.

[0099] In the fourth embodiment, a case where there is a step on the resin side surface 63 has been shown, but there may also be a step on the exposed side surface 223 of the columnar section 22. Fig. 39 shows a case where there is a step on such an exposed side surface 223. Fig. 39 shows a cross-sectional view of a semiconductor device according to such a modified example, and corresponds to Fig. 36.

[0100] In this modification, as shown in FIG. 39 , the exposed side surface 223 includes an exposed side surface first portion 223a and an exposed side surface second portion 223b. Both the exposed side surface first portion 223a and the exposed side surface second portion 223b are flat. The exposed side surface first portion 223a is disposed outward from the exposed side surface second portion 223b in a plan view. The exposed side surface first portion 223a is flush with the resin side surface 63. The exposed side surface second portion 223b is flush with the end surface 213 of the wiring layer 21. Also, as shown in FIG. 39 , the exposed side surface first portion 223a is not covered by the external electrode 3, and the exposed side surface second portion 223b is covered by the external electrode 3.

[0101] In this modification, the exposed side surface 223 is formed by shallowing the depth of the grooves 89 (see FIG. 37) in the half-cut dicing, i.e., by reducing the amount of cutting during half-cut dicing, and not completely cutting the columnar portion 822 in the z direction. As a result, when the sealing resin 6 (86) is cut later to separate the semiconductor elements 1 (81), the exposed side surface 223 including the exposed side surface first portion 223a and the exposed side surface second portion 223b is formed.

[0102] Fifth Embodiment 40 and 41 show a semiconductor device according to the fifth embodiment. The semiconductor device A5 of this embodiment differs from the semiconductor device A1 (first embodiment) in that the columnar portion 22 includes a protrusion 225.

[0103] Fig. 40 is a plan view showing the semiconductor device A5. Note that the sealing resin 6 is omitted in Fig. 40. Fig. 41 is a cross-sectional view taken along the line FF in Fig. 40.

[0104] In this embodiment, the columnar portion 22 includes a protrusion 225 as shown in Fig. 40. The protrusion 225 is a portion that protrudes from the resin abutment side surface 224 that faces the y direction in a plan view. In this embodiment, one protrusion 225 protrudes from each of the two resin abutment side surfaces 224 that face the y direction as shown in Fig. 40. The protrusion 225 has a locking surface 225a.

[0105] The locking surface 225a is a surface that protrudes from the resin abutting side surface 224. In this embodiment, the angle formed between the locking surface 225a and the resin abutting side surface 224 is a right angle. That is, the locking surface 225a is perpendicular to the resin abutting side surface 224. The locking surface 225a may be inclined with respect to the resin abutting side surface 224. In this embodiment, the locking surface 225a faces outward in the x direction in a plan view. Therefore, the locking surface 225a is parallel to the yz plane. The locking surface 225a is in contact with the sealing resin 6. In the x direction, the sealing resin 6 is interposed between the locking surface 225a and the resin side surface 63.

[0106] In the semiconductor device A5 as well, wiring is performed by plating, so that the same effect as in the first embodiment can be achieved, that is, the semiconductor device A5 can be made thinner.

[0107] According to this embodiment, the columnar portion 22 includes a protrusion 225. The protrusion 225 protrudes from the resin contact side surface 224 and has a locking surface 225a that contacts the sealing resin 6. With this configuration, even if stress is applied to the internal electrode 2 in the outward x-direction, the locking surface 225a is caught by the sealing resin 6. Therefore, the semiconductor device A5 can prevent the internal electrode 2 from coming loose in the x-direction.

[0108] Sixth Embodiment 42 shows a semiconductor device according to Embodiment 6. The semiconductor device A6 of this embodiment differs from the semiconductor device A1 (first embodiment) in that the columnar portion 22 includes a protrusion 226.

[0109] Fig. 42 is a cross-sectional view showing the semiconductor device A6, which corresponds to Fig. 4 of the first embodiment.

[0110] In this embodiment, the top surface 222 of the columnar portion 22 is a curved surface as shown in Fig. 42. Also, as shown in Fig. 42, the columnar portion 22 includes a protruding portion 226. The protruding portion 226 is a portion that protrudes from the resin-contacting side surface 224 in a plan view. The protruding portion 226 has a locking surface 226a.

[0111] The locking surface 226a is a surface that protrudes from the resin abutting side surface 224. In this embodiment, the angle formed between the locking surface 226a and the resin abutting side surface 224 is a right angle. That is, the locking surface 226a is perpendicular to the resin abutting side surface 224. The locking surface 226a may be inclined with respect to the resin abutting side surface 224. In this embodiment, the locking surface 226a faces downward in the z direction (downward in FIG. 42). Therefore, the locking surface 226a is parallel to the xy plane. The locking surface 226a is in contact with the sealing resin 6.

[0112] Fig. 43 is a diagram for explaining a method for forming the protrusion 226. Fig. 43 shows the subsequent plating layer forming step (see Fig. 16) of the manufacturing method according to the first embodiment.

[0113] In the subsequent plating layer formation step of this embodiment, similar to the first embodiment, the resist layer 805 is patterned by photolithography in areas other than the area where the plating layer 820d is to be formed. Thereafter, the plating layer 820d is deposited by electrolytic plating. At this time, if the electrolytic plating is continued until the thickness of the plating layer 820d exceeds the thickness of the patterned resist layer 805, the plating layer 820d grows along the upper surface of the resist layer 805. Thereafter, the resist layer 805 is removed, thereby forming the protrusion 226 in the columnar section 22.

[0114] In the semiconductor device A6, wiring is performed by plating, so that the same effect as in the first embodiment can be achieved, that is, the semiconductor device A6 can be made thinner.

[0115] According to this embodiment, the columnar portion 22 includes a protrusion 226. The protrusion 226 protrudes from the resin contact side surface 224 and has a locking surface 226a that contacts the sealing resin 6. With this configuration, even if stress is applied to the internal electrode 2 outward in the z direction, the locking surface 226a is caught by the sealing resin 6. Therefore, the semiconductor device A6 can prevent the internal electrode 2 from coming loose in the z direction.

[0116] In the first to sixth embodiments, two external electrodes 3 are exposed on each of the two resin side surfaces 63 facing the x direction, but the number of external electrodes 3 is not limited. Furthermore, the arrangement and shape of the internal electrodes 2 are not limited to those described above. For example, the internal electrodes 2 may be formed (wired) as shown in FIGS. 44 to 46. Each of FIGS. 44 to 46 is a plan view. In each of FIGS. 44 to 46, the conductive bonding material 5 and the sealing resin 6 are omitted, and the semiconductor element 1 is indicated by an imaginary line (a two-dot chain line). In FIGS. 45 and 46, a resistor, a capacitor, or another semiconductor element may be disposed in the region 19 indicated by the imaginary line (a two-dot chain line).

[0117] In the first to sixth embodiments, the semiconductor device is shown to have a SON package type resin package in which terminals are arranged on each of two side surfaces (two resin side surfaces 63 facing the x direction in the above examples), but the present invention is not limited to this. For example, the semiconductor device may have a QFN package type resin package in which terminals are arranged on each of four side surfaces.

[0118] In the first to sixth embodiments, the case where there is one wiring layer 21 in the z direction has been shown, but there may be multiple wiring layers 21 in the z direction. FIGS. 47 and 48 show a semiconductor device having a multilayer structure with two wiring layers 21 (a first wiring layer 21A and a second wiring layer 21B) in the z direction. FIG. 47 is a plan view showing the semiconductor device. Note that the sealing resin 6 is omitted in FIG. 47. FIG. 48 is a cross-sectional view taken along line GG in FIG. 47.

[0119] As shown in FIG. 48, the internal electrode 2 includes a first wiring layer 21A, a second wiring layer 21B, and a columnar portion 22. The first wiring layer 21A and the second wiring layer 21B are in partial contact with each other, and are otherwise insulated by an insulating film 43. The insulating film 43 is made of, for example, polyimide resin. The columnar portion 22 is formed so as to protrude from the second wiring layer 21B in the z direction. In this way, the columnar portion 22 may also be provided in a semiconductor device with a multilayer structure in which multiple wiring layers 21 are formed in the z direction.

[0120] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the method for manufacturing the semiconductor device according to the present disclosure can be freely designed and modified in various ways. [Explanation of symbols]

[0121] A1 to A6: Semiconductor device 1: Semiconductor element 11: Main surface of element 12: Back side of element 13: Electrode pad 131: First conductive part 132: Second conductive part 14: Passivation film 2: Internal electrode 21: Wiring layer 21A: 1st wiring layer 21B: 2nd wiring layer 210a: seed layer 210b: plating layer 211: Wiring layer main surface 212: Back side of wiring layer 212a: Electrode covering area 212b: insulating film covered area 213: End face 214: Protrusion 22: Columnar part 220a: seed layer 220b: plating layer 221: Proximal surface 222:Top surface 223:Exposed side 223a:Exposed side part 1 223b:Exposed side part 2 224: Resin contact side 225,226:Protrusion 225a, 226a: Locking surface 23: Filling section 3: External electrode 31: First covering part 32: Second coating part 33: Third covering part 41 to 43: insulating film 411: Main surface of insulating film 412: Insulating film backside 413: Opening 421: Through hole 5: Conductive bonding material 6: Sealing resin 61: Resin main surface 62: Resin back 63: Resin side 631:Resin side part 1 632: Resin side part 2 7: Metal layer 800: Support substrate 800a: Main surface 800b: Back 801: Temporary fixing material 802: Sputtered film 804: Dicing tape 805: Resist layer 81: Semiconductor elements 82: Internal electrode 820a: seed layer 820b: plating layer 820c: seed layer 820d: plating layer 821: Wiring layer 821b: Back side of wiring layer 821c: End face 822: Columnar part 822c: exposed side 83: External electrode 841: insulating film 841b: Back side of insulating film 85: Conductive bonding material 86: Sealing resin 861: Resin main surface 863: Resin side 89: Groove

Claims

1. a semiconductor element having a main surface and a rear surface facing opposite to each other in a thickness direction; a wiring layer electrically connected to the semiconductor element; a sealing resin that covers a portion of the wiring layer and the semiconductor element; Equipped with the wiring layer has a wiring layer main surface facing the element rear surface and electrically connected to the semiconductor element, and a wiring layer rear surface facing the opposite side to the wiring layer main surface in the thickness direction; the rear surface of the wiring layer includes a protruding portion that protrudes in the thickness direction, The protrusion has a tapered cross-sectional shape when viewed in a direction perpendicular to the thickness direction. Semiconductor device.

2. an internal electrode electrically connected to the semiconductor element; The semiconductor device according to claim 1 .

3. The internal electrode includes the wiring layer and a columnar portion. The semiconductor device according to claim 2 .

4. the columnar portion has an exposed side surface that is exposed from the sealing resin and faces a first direction perpendicular to the thickness direction; The semiconductor device according to claim 3 .

5. further comprising an external electrode exposed from the sealing resin and electrically connected to the internal electrode; The semiconductor device according to claim 4 .

6. The external electrode includes a first covering portion that covers the exposed side surface of the columnar portion. The semiconductor device according to claim 5 .

7. The semiconductor device further includes a conductive bonding material disposed between the semiconductor element and the wiring layer, the conductive bonding material electrically connecting the semiconductor element and the wiring layer.

7. The semiconductor device according to claim 1.

8. a metal coating layer interposed between a part of the columnar portion and the wiring layer; 7. The semiconductor device according to claim 3.

9. One end of the sealing resin and one end of the columnar portion are flush with each other.

7. The semiconductor device according to claim 3.

10. The columnar portion contains copper.

7. The semiconductor device according to claim 3.

11. the external electrode includes a portion that covers the protruding portion and protrudes in the thickness direction along a surface of the protruding portion.

7. The semiconductor device according to claim 5.

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