Control apparatus, control method, and decentralized processing system

Abstract

To provide a control apparatus, a control method, and a decentralized processing system for improving processing efficiency of a programmable logic circuit.SOLUTION: In a system 1, an optimization device 4 comprises a control unit configured to: read a second template of a second circuit logic for executing second processing related to first processing from a storage region when information related to the first processing executed by a first circuit logic satisfies a predetermined condition, the first circuit logic being set in a rewritable circuit area 70 included in a programmable logic circuit 7 and being realized by writing a first template in which a synthesis of a circuit design has been completed and an arrangement wiring has been determined into the circuit area 70; and set the second circuit logic for executing the second processing into the circuit area 70 by writing the read second template into the circuit area 70.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a control device, a control method, and a distributed processing system. [Background technology]

[0002] In recent years, the performance improvement of semiconductors such as CPUs (Central Processing Units) has slowed down, and the improvement in computer performance due to the high performance of semiconductors is approaching its limit.

[0003] On the other hand, with the development of AI (Artificial Intelligence) technology and IoT (Internet of Things), the amount of data to be processed is increasing, and applications run by computers are expected to perform tasks at higher speeds and with higher throughput than ever before.

[0004] One method for speeding up applications is a system that uses a domain-oriented architecture (hereinafter referred to as a "domain-oriented system"). Domain-oriented architecture is an approach that improves server performance and operability by narrowing down the application area to which it is applied and optimizing the hardware and software to suit the characteristics of that area.

[0005] Domain-oriented systems use ASICs (Application Specific Integrated Circuits), which are accelerators specialized for specific calculations in specific fields. Because ASICs are manufactured as dedicated hardware, their use is limited to specific applications. This means that it is difficult to apply domain-oriented systems in terms of design and manufacturing costs unless the application is commercially viable.

[0006] To facilitate the application of domain-oriented systems to applications, FPGAs (Field-Programmable Gate Arrays) have been attracting attention as reprogrammable ASICs. FPGAs are an example of PLDs (Programmable Logic Devices). PLDs may also be called programmable logic circuits.

[0007] An FPGA has a circuit area where circuit logic is written, and the reconfigurable function allows the circuit logic of the circuit area to be rewritten. Circuit logic is information that indicates the structure of the logic circuit that enables the FPGA to perform a specific process. Since various types of ASICs can be created by rewriting the circuit logic of the circuit area, using FPGAs in domain-oriented systems makes it possible to balance design and manufacturing costs with performance. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-014705 Summary of the Invention [Problem to be solved by the invention]

[0009] For example, in a domain-oriented system (distributed processing system) in which multiple processes are distributed and executed by one or more FPGAs, consider a case in which the loads among the multiple circuit logics that execute the processes are unbalanced, such as when there are many execution requests for process A and few execution requests for process B.

[0010] In such a case, the FPGA in which the circuit logic of process B is written may have ample processing resources, while the FPGA in which the circuit logic of process A is written may have insufficient processing resources, causing process A to stagnate (wait for processing).This decrease in the processing efficiency (operating efficiency) of the FPGA may cause processing delays in the computer that requested the execution of process A.

[0011] Therefore, it is conceivable to resolve the load imbalance by using the reconfigurable function to write the circuit logic of process A to the circuit area of ​​one or more FPGAs. However, rewriting the circuit logic of an FPGA takes time. For example, the synthesis and place and route steps in the rewriting process can take several days. This makes it difficult to change the processes to be executed by the FPGA in real time, and in some cases the load imbalance cannot be resolved.

[0012] In this way, the processing efficiency of the FPGA may decrease depending on the load of the circuit logic that executes the processing of the FPGA, which may cause processing delays in the computer that originated the execution request.

[0013] In one aspect, an object of the present invention is to improve the processing efficiency of a programmable logic circuit. [Means for solving the problem]

[0014] In one aspect, the control device may include a control unit that performs the following processing. When information regarding a first processing performed by a first circuit logic set in a rewritable circuit area included in a programmable logic circuit and realized by writing a first template, for which circuit design synthesis has been completed and placement and routing has been determined, into the circuit area satisfies a predetermined condition, the control unit may read from a storage area a second template of a second circuit logic that performs a second processing related to the first processing. The control unit may also set the second circuit logic that performs the second processing in the circuit area by writing the read second template into the circuit area. [Effects of the Invention]

[0015] In one aspect, the present invention can improve the processing efficiency of a programmable logic circuit. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a block diagram showing a configuration of a system according to a comparative example. [Figure 2] FIG. 10 is a diagram for explaining an example of a process for writing circuit logic to an FPGA. [Figure 3] 1 is a block diagram illustrating an example of the configuration of a system according to an embodiment. [Figure 4] FIG. 2 is a block diagram illustrating an example of a hardware configuration of a system according to an embodiment. [Figure 5] FIG. 1 is a block diagram showing an example of the configuration of a system spanning multiple bases. [Figure 6] FIG. 2 is a block diagram illustrating an example of the software configuration of an optimization device and a shared pool storage according to an embodiment. [Figure 7] FIG. 10 is a diagram illustrating an example of determination condition management information. [Figure 8] FIG. 10 illustrates an example of template management information. [Figure 9] 10 is a flowchart illustrating an example of the operation of a system according to an embodiment. [Figure 10] FIG. 10 is a diagram showing changes in the processing result according to the first operation example. [Figure 11] FIG. 10 is a diagram showing template management information according to a first operation example. [Figure 12] FIG. 10 is a diagram illustrating updating of template management information according to the first operation example. [Figure 13] FIG. 2 is a sequence diagram illustrating a first operation example of a system according to an embodiment. [Figure 14] FIG. 2 is a sequence diagram illustrating a first operation example of a system according to an embodiment. [Figure 15] FIG. 2 is a sequence diagram illustrating a first operation example of a system according to an embodiment. [Figure 16] FIG. 10 is a diagram showing changes in the processing result according to the second operation example. [Figure 17] FIG. 11 is a diagram showing template management information according to a second operation example. [Figure 18] FIG. 11 is a diagram illustrating updating of template management information according to the second operation example. [Figure 19] FIG. 11 is a diagram illustrating updating of template management information according to the second operation example. [Figure 20] FIG. 10 is a sequence diagram illustrating a second operation example of the system according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and are not intended to exclude various modifications or application of techniques not explicitly described below. For example, the present embodiment can be implemented with various modifications within the scope of the spirit thereof. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[0018] [A] Comparative example 1 is a block diagram showing the configuration of a system 100 according to a comparative example. The system 100 illustratively includes a plurality of cameras 110 (cameras #0 to #n-1) (n cameras in the example of FIG. 1, where n is an integer equal to or greater than 2), a host PC (Personal Computer) 120, an interface 130, and one or more FPGAs 140 (FPGA groups) (four FPGAs in the example of FIG. 1).

[0019] The host PC 120 executes AI processing used in autonomous driving or security systems, etc., using captured images captured by the multiple cameras 110. The AI ​​processing may be, for example, image recognition processing such as object detection processing. For the AI ​​processing, images that have been subjected to preprocessing (image processing) such as edge extraction processing and binarization processing on the captured image are input, rather than the captured image itself.

[0020] The pre-processing is a process that places a heavy load on the host PC 120. Therefore, a processing delay occurs when the host PC 120 executes the pre-processing. Therefore, in the system 100 according to the comparative example, the execution of the pre-processing is offloaded from the host PC 120 to the FPGA 140.

[0021] For example, the host PC 120 outputs the captured image to the FPGA 140 via a high-speed communication path connected to the interface 130 or an IO (Input / Output) port (not shown) of the FPGA 140. Then, the host PC 120 acquires the preprocessing results executed at high speed by the FPGA 140 and performs AI processing using the preprocessing results.

[0022] The FPGA 140 has a circuit area where the circuit logic can be rewritten, and executes predetermined processing using circuits set in the circuit area. Hereinafter, when distinguishing between the FPGAs 140, they will be referred to as FPGAs #0 to #3 (see FIG. 1). For example, each of the FPGAs #0 to #3 may execute the following processing.

[0023] FPGA#0: Processing A: Edge extraction processing for 4K resolution captured images FPGA#1: Process B: Edge extraction processing for FHD (Full High Definition) captured images FPGA#2: Processing C: Edge extraction processing for captured images with STD (Standard) resolution FPGA#3: Processing D: Binarization

[0024] In the example of Fig. 1, captured images are input to FPGAs #0 to #2 according to resolution. Edges extracted from the captured images by each of FPGAs #0 to #2 (processing A to C) are input to FPGA #3 and binarized by FPGA #3 (processing D). The binarized image data is output to host PC 120 as a preprocessing result.

[0025] Processes A to C are all edge extraction processes for a captured image, but they differ in the resolution (maximum resolution) that they can handle. In the example of Fig. 1, system 100 has FPGAs #0 to #2 execute the same edge extraction process for each resolution, which can easily lead to a redundant configuration.

[0026] The scale of the circuit set in the rewritable circuit area of ​​the FPGA 140 differs depending on the content of the processes A to D executed by the circuit. The circuit scale of each of the processes A to D is indicated by the size of the frame indicated by reference numeral 141 in FIG.

[0027] For example, the higher the resolution of the edge extraction processes A to C, the larger the circuit scale 141. In the example of Fig. 1, the resolutions that can be handled are processed in descending order of process A (4K), process B (FHD), and process C (STD), and the circuit scales 141 are processed A, B, and C in descending order of process. Note that process D is a process that uses pre-processing results sequentially output from processes A to C, and inputs edges based on captured images with a maximum resolution of 4K, so the circuit scale 141 shown is in line with the circuit scale of process A.

[0028] For this reason, for example, when changing the circuit of each FPGA 140 using a reconfigurable function, it is important to determine an appropriate combination of processes based on the size of the free space in the rewritable circuit area of ​​each FPGA 140 and the circuit scale 141 of each process.

[0029] Next, a description will be given of a process for rewriting (writing) the circuit logic to the FPGA 140, that is, a process for setting the circuit. FIG.

[0030] As shown in Figure 2, a developer inputs a circuit logic design into a development environment using a language such as HDL (Hardware Description Language) (process P1), and then synthesizes the design using a logic synthesis tool (process P2). At this point, the developer performs logic verification of the design (process P3), completing the design synthesis.

[0031] After completing the design synthesis, the developer implements the design to incorporate the logic circuit on the FPGA 140 (step P4).

[0032] For example, developers optimize each function to be implemented on the rewritable circuit area (step P41), and then place and route each optimized function on the circuit area (step P42). At this time, developers perform static timing analysis (step P5) and timing verification (step P7) using back annotation (step P6) to determine placement and routing.

[0033] Then, based on the determined placement and wiring, the developer creates a bitstream for writing (programming) the circuit into the circuit area (step P43).

[0034] The developer downloads the bitstream to the FPGA 140 (step P8). For example, the developer writes the bitstream to an external storage device of the FPGA 140 via an interface that complies with a standard such as JTAG (Joint Test Action Group). Step P8 may also be referred to as configuring the FPGA 140, writing the logic circuit, or the like.

[0035] The bitstream written to the external storage device is read from the external storage device when the FPGA 140 is started up or when the reconfigurable function is executed, and written to the rewritable circuit area of ​​the FPGA 140. After writing the bitstream to the circuit area, the developer performs actual device verification (step P9). This completes the circuit configuration in the FPGA 140.

[0036] For example, if a load imbalance occurs between the circuit logics that execute processes A to D in the FPGA 140, the operating efficiency of the FPGA 140 will deteriorate, which may result in a delay in the execution of AI processing by the host PC 120. In order to resolve this imbalance, it is conceivable to resolve the load imbalance by, for example, setting a circuit that executes a high-load process in a circuit area of ​​the FPGA 140 in which a circuit that executes a low-load process is set.

[0037] However, as described above, the synthesis, placement, and wiring steps (e.g., steps P2 and P42 in FIG. 2) of the rewrite process can take several days, making it difficult to change the process executed by the FPGA 140 in real time.

[0038] Therefore, in one embodiment, an example of a method for improving the processing efficiency of an FPGA will be described.

[0039] [B] Description of a system according to one embodiment FIG. 3 is a block diagram showing an example of the configuration of a system 1 according to an embodiment. The system 1 is an example of a distributed processing system or an information processing system. The system 1 includes a regional system 10. The regional system 10 is an example of an information processing system installed in each region (each location). The regional system 10 illustratively includes a plurality (n cameras in the example of FIG. 3) of cameras 2 (cameras #0 to #n-1), a host PC 3, an optimization device 4, an interface 6, and one or more (four in the example of FIG. 3) FPGAs 7 (FPGA groups).

[0040] The system 1 according to one embodiment causes the FPGA 7 to execute multiple processes that are pre-processing for AI processing. The pre-processing is an example of the first process or the second process, and may include, for example, edge extraction processing for an image, binarization processing based on the extracted edges, etc. Note that the multiple processes executed by the FPGA 7 are not limited to pre-processing for AI processing, and may include various other processes.

[0041] The camera 2 is an example of an imaging device that captures an image of a predetermined imaging area and outputs the captured image. Each of the multiple cameras 2 may output captured images with different resolutions.

[0042] The host PC 3 is an example of an information processing device or a computer, and includes an AI processing engine 30 that performs AI processing on images captured by the camera 2. The AI ​​processing engine 30 is an example of a machine learning model. The host PC 3, for example, offloads preprocessing to the FPGA 7, and performs AI processing using the AI ​​processing engine 30 based on the results of the preprocessing by the FPGA 7.

[0043] For example, when the host PC 3 acquires a captured image from the camera 2, it may transmit a request to execute pre-processing (processing request) including the acquired captured image. The execution request may be transmitted in a manner that can be acquired by the optimization device 4. The AI ​​processing may be, for example, image recognition processing such as object detection processing, and may be used in autonomous driving or security systems, etc.

[0044] The host PC 3 and the optimization device 4 may be connected to the IO port of the FPGA 7 via a communication path 1a so that they can communicate with each other. The communication path 1a may be used for transmitting a preprocessing execution request and the preprocessing results, and for writing the template 5 to the circuit area 70. For example, the host PC 3 may send an execution request to the optimization device 4 via a network or the communication path 1a. The host PC 3 may receive the preprocessing results from the FPGA 7 via the interface 6.

[0045] The FPGA 7 is an example of a PLD, and may include a rewritable circuit area 70, and executes predetermined processing using logic circuits set in the circuit area 70. Hereinafter, when distinguishing between the FPGAs 7, they will be referred to as FPGAs #0 to #3 (see FIG. 3). For example, the FPGAs #0 to #3 may execute the above-mentioned processes A to D, respectively. In FIG. 3, the circuit scale of each process is indicated by reference numeral 71.

[0046] The optimization device 4 is an example of an information processing device or a computer, and is an optimizer that improves the processing efficiency of the FPGA 7. The optimization device 4 may be provided, for example, between the host PC 3 and the FPGA 7 so as to be able to communicate with each of them.

[0047] For example, the optimization device 4 may include a logic pool 40. The logic pool 40 is an example of a storage area, and may store a plurality of templates 5 in which the synthesis of the circuit design of the circuit logic has been completed and the placement and wiring has been determined. The templates 5 are information for realizing the circuit logic by being written into the circuit area 70, and may be, for example, a bitstream.

[0048] When the optimization device 4 detects a load imbalance between circuit logics set in the rewritable circuit areas 70 provided in each of one or more FPGAs 7 that execute multiple processes, the optimization device 4 reads a first template 5 that satisfies a preset condition from the logic pool 40. The first template 5 may be, for example, a template 5 for a circuit that executes a process with a high load (as an example, a process that is stalled).

[0049] The optimization device 4 writes the read first template 5 to a first circuit area 70 that satisfies the conditions among one or more circuit areas 70. As a result, the optimization device 4 sets, in the first circuit area 70, a first circuit logic that is realized by the first template 5 and that executes a first process.

[0050] In recent years, FPGA7 has integrated various functions such as IO, networking, etc. in addition to dedicated functions. If the logic circuit to be written is prepared, only the dedicated function part of the functions installed in FPGA7 can be rewritten in a few milliseconds, which has a wide range of applications.

[0051] In one embodiment, focusing on this point, a template 5 of a circuit that can be set in the FPGA 7 is prepared in advance. This allows the optimization device 4 to set a logic circuit in the circuit area 70 in real time or nearly real time in order to eliminate the imbalance in load between the circuit logics. This makes it possible to optimize the processing to be executed by the FPGA 7, and improve the processing efficiency of the FPGA 7.

[0052] An optimization device 4 according to one embodiment reads a second template 5 of a second circuit logic that executes a second process from a logic pool 40 when the processing result of the first process executed by the first circuit logic realized by the first template 5 satisfies a detection condition. The detection condition is an example of a predetermined condition. The first process and the second process may be, for example, preprocessing, and may be referred to as a first preprocessing and a second preprocessing, respectively. The second process is a process related to the first process.

[0053] The second template 5 to be read out may be, for example, a template 5 of a circuit that executes a second process that is partially different from the first process. Alternatively, the second template 5 to be read out may be a template 5 of a circuit that executes the second process that is the same as the first process but has a larger processing load than the first process (for example, a template 5 of a logical partition size).

[0054] The optimization device 4 writes the read second template 5 into the circuit area 70, thereby setting the second circuit logic for executing the second preprocessing in the circuit area 70. Note that the first template 5 is written in the circuit area 70 before the second template 5 is written. Therefore, hereafter, the process of "writing" the second template 5 is a process of overwriting the template 5, and may be understood as a process of rewriting the template 5.

[0055] With the above-described configuration, when the optimization device 4 determines that the detection conditions are satisfied, it replaces the template 5 in the circuit area 70 without any user operation. This makes it possible to set an appropriate circuit logic in the circuit area 70, and for example, to efficiently recover the performance of preprocessing using the circuit logic or processing using the results of the preprocessing.

[0056] In other words, the optimization device 4 can set logic circuits in the circuit area 70 in real time or nearly real time to improve or maintain the performance of the processing. Therefore, in the above-mentioned configuration that can optimize the processing to be executed by the FPGA 7 and improve the processing efficiency of the FPGA 7, it is possible to suppress performance degradation of preprocessing to be executed by the FPGA 7 or processing that uses the results of the preprocessing of the FPGA 7.

[0057] [C] Hardware configuration example 4 is a block diagram showing an example of the hardware configuration of the system 1 according to an embodiment. In FIG. 4, attention is focused on the connection configuration between devices in one regional system 10 of the system 1 shown in FIG. 3 and the configuration of the optimization device 4.

[0058] As shown in FIG. 4, the camera 2 and the host PC 3, and the host PC 3 and the optimization device 4 may be connected to each other so that they can communicate with each other via a network such as a LAN (Local Area Network) or the Internet.

[0059] The interface 6 may be, for example, an interconnect conforming to standards such as PCIe (Peripheral Component Interconnect-express) or CXL (Compute Express Link). For example, the interface 6 may be an adapter (connector) compatible with PCIe or CXL. In addition to the adapter, the interface 6 may also include a PCIe switch or a CXL switch that switches communication (connection) between the host PC 3 and each of the one or more FPGAs 7.

[0060] Furthermore, as shown in FIG. 4, the host PC 3 and the FPGA 7, and the optimization device 4 and the FPGA 7 may be connected to each other so that they can communicate with each other via a high-speed communication path 1a that conforms to the standard of the IO port of the FPGA 7.

[0061] At least one of the host PC 3 and the optimization device 4 according to an embodiment may be a physical server or a virtual server (VM: Virtual Machine). Furthermore, at least one of the functions of the host PC 3 and the functions of the optimization device 4 may be realized by one computer, or by two or more computers.

[0062] The functions of the host PC 3 and the optimization device 4 according to one embodiment may both be implemented by a computer having a similar hardware (HW) configuration. The HW configurations of the host PC 3 and the optimization device 4 will be described below using the optimization device 4 as a representative example.

[0063] Figure 4 shows an example in which one computer is used as the HW resource that realizes the functions of the optimization device 4, but if multiple computers are used, each computer may have the HW configuration shown in Figure 4.

[0064] As shown in FIG. 4, the optimization device 4 may include, as a HW configuration, a processor 4a, a graphics processing unit 4b, a memory 4c, a storage unit 4d, an IF (Interface) unit 4e, an IO unit 4f, and a reading unit 4g, for example.

[0065] The processor 4a is an example of a processing unit that performs various controls and calculations. The processor 4a may be connected to each block in the optimization device 4 via a bus 4j so that they can communicate with each other. The processor 4a may be a multiprocessor including multiple processors, a multi-core processor having multiple processor cores, or a configuration having multiple multi-core processors.

[0066] The processor 4a may be, for example, an integrated circuit (IC) such as a CPU, MPU, APU, DSP, ASIC, or FPGA. Note that the processor 4a may be a combination of two or more of these integrated circuits. MPU is an abbreviation for Micro Processing Unit. APU is an abbreviation for Accelerated Processing Unit. DSP is an abbreviation for Digital Signal Processor.

[0067] The graphics processing device 4b controls screen display for an output device such as a monitor in the IO unit 4f. The graphics processing device 4b may also be configured as an accelerator that executes machine learning processing and inference processing using a machine learning model. Examples of the graphics processing device 4b include various arithmetic processing devices, such as a GPU (Graphics Processing Unit), an APU, a DSP, an ASIC, an FPGA, or other integrated circuits (ICs).

[0068] The memory 4c is an example of hardware that stores various types of data, programs, and other information. Examples of the memory 4c include a volatile memory such as a dynamic random access memory (DRAM) and / or a non-volatile memory such as a persistent memory (PM).

[0069] The storage unit 4d is an example of hardware that stores various types of data, programs, and other information. Examples of the storage unit 4d include various storage devices such as a magnetic disk device such as a hard disk drive (HDD), a semiconductor drive device such as an SSD, and a nonvolatile memory. Examples of nonvolatile memory include a flash memory, a storage class memory (SCM), and a read-only memory (ROM).

[0070] The storage unit 4d may store a program 4h (control program) that realizes all or part of the various functions of the optimization device 4.

[0071] For example, the processor 4a of the optimization device 4 can realize the function of the optimization device 4 (for example, the control unit 49 shown in Figure 6) described below by expanding the program 4h stored in the storage unit 4d into the memory 4c and executing it.

[0072] The IF unit 4e is an example of a communication IF that controls connections and communications between the host PC 3 and the optimization device 4, between the optimization device 4 and the FPGA 7, etc. For example, the IF unit 4e may include an adapter that complies with various communication standards such as Ethernet (registered trademark), InfiniBand, Millinet, PCIe, CXL, and the IO port of the FPGA 7. The adapter may support either or both of wireless and wired communication methods. The adapter may also be compliant with optical communication such as FC (Fibre Channel).

[0073] The program 4h may be downloaded to the optimization device 4 from a network (not shown) via the communication IF and stored in the storage unit 4d.

[0074] The IO unit 4f may include one or both of an input device and an output device. Examples of input devices include a keyboard, a mouse, and a touch panel. Examples of output devices include display devices such as a monitor, a projector, and a printer. The IO unit 4f may also include a touch panel or the like that combines an input device and an output device. The output device may be connected to the graphics processing device 4b.

[0075] The reading unit 4g is an example of a reader that reads data and program information recorded on the recording medium 4i. The reading unit 4g may include a connection terminal or device to which the recording medium 4i can be connected or inserted. Examples of the reading unit 4g include an adapter that complies with USB (Universal Serial Bus) or the like, a drive device that accesses a recording disk, and a card reader that accesses a flash memory such as an SD card. Note that the recording medium 4i may store a program 4h, and the reading unit 4g may read the program 4h from the recording medium 4i and store it in the memory unit 4d.

[0076] Examples of the recording medium 4i include non-transitory computer-readable recording media such as magnetic / optical disks and flash memories. Examples of magnetic / optical disks include flexible disks, CDs (Compact Discs), DVDs (Digital Versatile Discs), Blu-ray Discs, and HVDs (Holographic Versatile Discs). Examples of flash memories include semiconductor memories such as USB memories and SD cards.

[0077] The above-described hardware configuration of the optimization device 4 is an example. Therefore, the hardware in the optimization device 4 may be increased or decreased (for example, adding or deleting any block), divided, integrated in any combination, or buses may be added or deleted as needed. For example, the optimization device 4 may omit the IO unit 4f and the reading unit 4g.

[0078] The host PC 3 may also have the same hardware configuration as the optimization device 4. For example, the processor 4a of the host PC 3 can implement the functions of the host PC 3 (AI processing engine 30) by expanding a program 4h stored in the storage unit 4d into the memory 4c and executing it, and by controlling instructions to the graphics processing device 4b.

[0079] Fig. 5 is a block diagram showing an example of the configuration of a system 1 spanning multiple bases. As shown in Fig. 5, the system 1 may include a shared pool storage 8 and multiple (m in the example of Fig. 5: m is an integer equal to or greater than 2) regional systems 10. The shared pool storage 8 and the optimization device 4 of each regional system 10 may be connected to each other via the above-mentioned IF unit 4e, for example, via a network such as a LAN or the Internet, so that they can communicate with each other. The shared pool storage 8 may be accessible from each of the multiple optimization devices 4, and may be storage implemented in a cloud environment, such as cloud storage, for example.

[0080] The shared pool storage 8 is a storage area shared between multiple logical pools 40, in other words, between multiple regional systems 10 (e.g., multiple optimization devices 4), and is an example of a shared storage area. The shared pool storage 8 may store multiple templates 5. The shared pool storage 8 may include, for example, various storage devices (not shown) capable of storing multiple templates 5, as well as a processor, memory, interface, etc. (not shown).

[0081] The regional systems 10 at each base share the template 5 in the shared pool storage 8. Therefore, even when optimal operation is no longer possible using the template 5 existing in the logical pool 40 at the optimization device 4's own base, the optimization device 4 can configure the logic circuit using the template 5 in the shared pool storage 8.

[0082] The regional system 10 illustrated in FIG. 5 may be installed in each of the regions (one base) shown as region A, region B, . . . , or region C.

[0083] Each regional system 10 may have a hardware configuration exemplified in Fig. 4. For example, in order to realize edge computing, each regional system 10 may have one or more cameras 2, an interface 6, one or more FPGAs 7, as well as a host PC 3 and an optimization device 4 (optimization devices #0 to m-1).

[0084] With the above-described configuration, each regional system 10 can reduce communication delays between devices constituting the regional system 10, and therefore, relatively high-speed AI processing and its preprocessing, such as image recognition processing related to autonomous driving, can be realized by the host PC 3 and optimization device 4.

[0085] [D] Software configuration example Fig. 6 is a block diagram showing an example of the software configuration of the optimization device 4 and the shared pool storage 8 according to an embodiment. As shown in Fig. 6, the optimization device 4 may exemplarily include a memory unit 41, a communication unit 42, an information collection unit 43, a determination unit 44, a creation unit 45, a reading unit 46, a writing unit 47, and an update unit 48. The communication unit 42, the information collection unit 43, the determination unit 44, the creation unit 45, the reading unit 46, the writing unit 47, and the update unit 48 are examples of a control unit 49.

[0086] The memory unit 41 is an example of a storage area, and stores various data used by the optimization device 4. The memory unit 41 may be realized, for example, by a storage area included in one or both of the memory 4c and the storage unit 4d (see FIG. 4) of the optimization device 4.

[0087] 6, the memory unit 41 may be capable of storing, for example, a logical pool area 41a, judgment condition management information 41b, and template management information 41c. The judgment condition management information 41b is an example of information for managing judgment conditions. The template management information 41c is an example of information for managing templates 5.

[0088] The logical pool area 41a is a storage area secured as the logical pool 40 (see FIG. 3). Of the logical pool area 41a, the storage area that stores multiple templates 5 as the logical pool 40 may be realized by the storage area of ​​the storage unit 4d. Also, of the logical pool area 41a, the storage area that stores the template 5 selected from the logical pool 40 (read from the storage unit 4d) to be written to the FPGA 7 may be realized by the storage area of ​​the memory 4c.

[0089] The shared pool storage 8 may, for example, include a shared logical pool area 81 and template management information 82. The shared logical pool area 81 is a storage area secured as a logical pool in the shared pool storage 8. The template management information 82 is an example of information for managing templates 5 in the shared pool storage 8. The shared logical pool area 81 and the storage area for storing the template management information 82 may each be realized by one or both of hardware similar to the memory 4c of the optimization device 4 and hardware similar to the storage unit 4d.

[0090] The following describes the templates 5 stored in the logical pool 40. For example, assume that the host PC 3 (AI processing engine 30) collects captured images from a camera 2 used for autonomous driving or the like and performs AI processing on them.

[0091] Pre-processing is performed on the captured images to absorb differences in the performance of the multiple cameras 2 and differences in the captured images due to the imaging environment, such as day and night. The pre-processing includes one or more processing elements, such as thinning, brightness correction, projective transformation, distortion correction, edge extraction, etc., and the number and content of the processing elements vary depending on the content of the AI ​​processing.

[0092] These processes are executed according to the maximum resolution. Therefore, a processing pipeline is formed for each resolution, and processing by the FPGA 7 is performed for each processing pipeline. The processes included in the processing pipeline, in other words, the processes executed by the FPGA 7, include, for example, the following series of processes: Processing pipeline: thinning → brightness correction → distortion processing → edge extraction

[0093] The number of input images (channels) that can be processed by one processing pipeline decreases as the resolution increases. The resolutions of the captured images input to preprocessing include, in descending order, 8K (7680 x 4320), 4K (3840 x 2160), WQHD (2560 x 1440), FHD (1920 x 1080), WXGA++ (1600 x 900), and HD (1280 x 720). The numbers in parentheses for each resolution indicate the number of horizontal and vertical pixels.

[0094] In this way, the higher the resolution, the more the number of processing pipelines increases, and therefore the higher the resolution, the larger the circuit scale 71 of the logic circuit written in the circuit area 70 of the FPGA 7. To compare the circuit scale 71, Figures 3 to 5 show an example of processing pipelines (processing A to processing C) executed by FPGAs #0 to #2, where processing A is for 4K, processing B is for WQHD, and processing C is for FHD.

[0095] The logic pool 40 may store in advance a bitstream (step P43 in FIG. 2) generated upon completion of synthesis (step P2 in FIG. 2) and placement and wiring (step P42 in FIG. 2) for each of a plurality of processes including these processes A to C. In FIG. 3, templates 5 of logic circuits that execute each of processes A to G are stored in the logic pool 40.

[0096] The communication unit 42 performs various communications with the host PC 3 and the FPGA 7 using the IF unit 4e (see FIG. 4).

[0097] The information collecting unit 43 collects processing results from each of the host PC 3 and the FPGA 7 via the communication unit 42. The processing results are an example of information related to the first processing. The information related to the first processing may include one or both of an index (first information) indicating the quality of a result (inference result) obtained by inputting the result of the first processing into a machine learning model, and information (second information) related to the load of the circuit logic that executes the first processing. The information collecting unit 43 may acquire the processing results, for example, at predetermined time intervals (for example, every 5 seconds).

[0098] The first information may be, for example, a recognition rate obtained when the preprocessing result of the first process is input to a machine learning model and image recognition processing is performed. The information collection unit 43 may collect the recognition rate output from the AI ​​processing engine 30 of the host PC 3 via a network, for example.

[0099] The second information may be, for example, an operating rate, which is an example of information relating to the load of the circuit logic that executes the first process. The information collecting unit 43 may acquire the operating rate based on the operating status of the FPGA 7, for example.

[0100] An example of the operating status is the network transfer rate of the FPGA 7. For example, the information collecting unit 43 may use a system monitoring tool to acquire the network transfer rate of each FPGA 7 via the communication path 1a. Note that the information collecting unit 43 (and the determining unit 44, which will be described later) may acquire the network transfer rate by measuring the amount of information (data) sent to each FPGA 7.

[0101] Furthermore, according to a method of one embodiment, logic circuits that execute two or more types of processing may be configured in each FPGA 7. In such a case, the information collection unit 43 may acquire the network traffic for each type of processing (template 5) that runs on the FPGA 7. The network traffic for each type of processing may be, for example, the network traffic for each logic circuit that executes the processing.

[0102] For example, the information collecting unit 43 may calculate the ratio of the acquired (current) network transfer volume to the maximum network transfer volume when the FPGA 7 or each process operates with the maximum number of input videos (number of channels) as the operation rate of the FPGA 7 or each process. The maximum network transfer volume may be measured in advance, for example. In this way, by using the network transfer volume to calculate the operation rate, the information collecting unit 43 can accurately estimate the load based on the actual operation status of the logic circuit. The operation rate of the FPGA 7 or each process can be considered as an index indicating the processing volume of the FPGA 7 or each process.

[0103] Furthermore, for example, the information collecting unit 43 may acquire (receive) an execution request for preprocessing from the host PC 3. As an example, the information collecting unit 43 may acquire the execution request transmitted from the host PC 3 via the communication path 1a by the IF unit 4e (communication IF). Note that, if the host PC 3 can change the transmission mode of the execution request, it may transmit the execution request to the optimization device 4 via a network such as a LAN. In this case, the information collecting unit 43 may acquire the execution request by the IF unit 4e (communication IF) via the network.

[0104] The information collecting unit 43 may use the number of execution requests received from the host PC 3 to calculate the availability of the FPGA 7. As an example, the information collecting unit 43 may calculate, as the availability of the FPGA 7, the ratio of the number of execution requests issued to the FPGA 7 from the host PC 3 during a predetermined period to the maximum number of execution requests that the FPGA 7 can process during that period.

[0105] The determination unit 44 determines whether or not the processing result acquired by the information collection unit 43 satisfies the detection condition. If the determination unit 44 determines that the processing result satisfies the detection condition, it determines that the second template 5 should be written into the circuit area 70 into which the first circuit logic of the first preprocessing has been written.

[0106] The detection conditions may include, for example, one or both of a first condition that the recognition rate is less than a first predetermined value and a second condition that the load is equal to or greater than a second predetermined value.

[0107] For example, if the judgment unit 44 determines that the recognition rate is less than a first predetermined value based on the recognition rate of the AI ​​processing of the host PC 3, it may determine that a second template 5 that meets the read conditions in the judgment conditions described below should be set in a predetermined circuit area 70.

[0108] Furthermore, for example, if the judgment unit 44 determines that the operating rate of the first circuit logic that executes the first preprocessing is equal to or greater than a second predetermined value, it may determine that a second template 5 that meets the read conditions in the judgment conditions described below should be set in a predetermined circuit area 70.

[0109] The judgment condition is a condition according to a policy that matches the state indicated by the processing result, in other words, the state indicated by the monitoring result of the recognition rate and the operation rate. Hereinafter, the processing result may be referred to as the monitoring result.

[0110] Fig. 7 is a diagram showing an example of the judgment condition management information 41b. As shown in Fig. 6, the judgment condition management information 41b may include the items of "condition name", "judgment condition (policy)", and "details".

[0111] The "condition name" is an example of identification information for a judgment condition entry. The "judgment condition (policy)" is a variety of approaches for resolving processing imbalances, such as methods (perspectives) such as "improving recognition rate," "reducing utilization rate," and "improving efficiency." The "details" are specific conditions for achieving the judgment condition approach, and may define at least one of the following: detection conditions, information on the template 5 to be written (read conditions), and information on the FPGA 7 to which the template 5 is written (write conditions). Examples of detection conditions include low recognition rate, high utilization rate, and an imbalance state. FPGA#x shown in FIG. 7 is an FPGA 7 in which the written template 5 (circuit logic) satisfies the detection conditions. In the examples of FIGS. 3 to 5, 0≦x≦2.

[0112] The determination unit 44 may compare the processing result with the determination condition management information 41b, and if the monitoring result matches the detection condition, determine that the template 5 that matches the read condition of the entry should be written to the FPGA 7 that matches the write condition. The template 5 that matches the read condition is an example of the second template 5 of the second circuit logic that executes the second process related to the first process. Then, the determination unit 44 notifies the read unit 46 and the write unit 47 of the determination result.

[0113] An example of the judgment process by the judgment unit 44 will be described below. Assume that the recognition rate of the AI ​​process using the preprocessing results of process A executed by FPGA#0 is less than 99.95%. Process A is an example of the first process. Note that, in the above judgment conditions, the detection condition "recognition rate: less than 99.95%" is an example of the first condition.

[0114] In this case, the determination unit 44 determines, based on the entry (condition name) R1 in the determination condition management information 41b, to write to FPGA #0 a second template 5 that has the same resolution as process A (4K processing in this example) and that executes a second preprocessing. The second preprocessing may be a preprocessing that includes multiple processing elements to which at least one of the following has been applied: deleting one or more processing elements, replacing one or more processing elements, and adding one or more processing elements, among the multiple processing elements included in the first preprocessing. As a result, when a decrease in the recognition rate is detected, the template 5 is automatically rewritten. This makes it possible to efficiently suppress a decrease in the recognition rate, for example, to recover (improve) the recognition rate, without requiring a user operation to add a template 5 to the logical pool 40.

[0115] Another example of the determination process by the determination unit 44 will be described. Assume that the operation rate of FPGA #2 executing process C is 100.00%. Process C is an example of a first process. In the above determination conditions, the detection condition "operation rate: 100.00%" is an example of a second condition for determining whether the processing load of the first circuit logic according to the written first template 5 is equal to or greater than a second predetermined value (e.g., 100.00%). The predetermined value may be less than 100.00%.

[0116] In this case, the determination unit 44 determines, in accordance with the determination condition R2 in the determination condition management information 41b, to write to FPGA#2 a second template 5 that executes a second pre-processing, which has the same resolution as process C (FHD processing in this example) and includes the same processing elements as those included in process C. In this case, the determination unit 44 determines to write, as the second template 5 that executes the second pre-processing, a template 5 that has a larger logical partition size than the template 5 that executes process C and is equal to or smaller than the circuit scale 71 of FPGA#2. This allows the size of the circuit logic that executes process C (circuit scale 71) to be increased, for example, the number of processing pipelines that execute parallel processing to be increased. Therefore, the throughput of the circuit logic that executes process C in FPGA#2 can be improved, and the operating rate can be reduced.

[0117] It is also possible to consider an operation in which, depending on the processing results, a user adds a template 5 to the logical pool 40 by user operation, and the optimization device 4 writes the added template 5 to the FPGA 7. However, in this case, it is unclear whether the added template 5 alone can directly lead to optimization of the system 1. Meanwhile, the determination unit 44 according to one embodiment determines that the template 5 for which the second preprocessing is to be executed should be written to the FPGA 7, and repeats the process of selecting a template 5 that satisfies the read condition from the template management information 41c, until the processing results no longer satisfy the detection condition. This allows for more efficient setting of the optimal template 5 compared to adding a template 5 by user operation.

[0118] If there are multiple entries in the judgment condition management information 41b whose processing results match the detection condition, the judgment unit 44 may select the policy with the highest priority according to the priority of the policy. The priority (descending order) of the policy may be, for example, descending order of the entry (condition name), descending order of the strictness of the detection condition (large number of conditions, high recognition rate, low operation rate, etc.), or designated in advance by the administrator.

[0119] The determination unit 44 may be realized, for example, by a function of an application such as an optimization solver, or may be realized by a machine learning model trained by a method such as deep learning. For example, when the monitoring results are input, the machine learning model may be trained to output read processing conditions and write destination conditions according to the detection conditions.

[0120] Note that, when the system 1 (or FPGA 7) is started up, the determination unit 44 may identify the template 5 to be initially written to each FPGA 7 and notify the read unit 46 and the write unit 47. The template 5 to be initially written may be designated by an administrator or user of the system 1, or a determination condition for selecting the template 5 to be initially written may be set in the determination condition management information 41b.

[0121] Furthermore, the determining unit 44 refers to the template management information 41c and assigns the FPGA 7 to which the execution request sent from the host PC 3 is to be transferred to an appropriate FPGA 7 that processes the execution request.

[0122] 8 is a diagram showing an example of template management information 41c. As shown in Fig. 8, the template management information 41c may include the following items: "template number," "logical partition size," "FPGA number," "processing content," "processing result," and "timestamp."

[0123] The "template number" is an example of identification information for the template 5. The "logical partition size" is the area size that the logic circuit realized by the template 5 occupies in the circuit area 70 (logical partition), and is an example of the circuit scale 71. The "FPGA number" is an example of identification information for the FPGA 7.

[0124] The "processing content" is the content of the processing that is realized as a logic circuit by the circuit logic realized by template 5. For example, template #2 shown in Fig. 8 is template 5 of a logic circuit (size: 100) that realizes 4K processing.

[0125] The "processing result" is an example of information related to preprocessing. In the example of Figure 8, the "processing result" includes the "recognition rate" and "operation rate," which are elements of the detection conditions (see Figure 7). The "recognition rate" is the recognition rate of the AI ​​processing using the preprocessing result of template 5. The "operation rate" is the operation rate of the circuit logic that executes preprocessing using template 5. The "timestamp" is an example of information related to the last use of template 5, and may be set to, for example, the time when template 5 was last written to the circuit area 70 of FPGA 7.

[0126] For example, the determination unit 44 may identify, from the template management information 41c, a template 5 that implements the processing requested in the execution request transmitted from the host PC 3, and may then identify, from the template management information 41c, an FPGA 7 on which the identified template 5 runs. Then, the determination unit 44 may issue (transmit) the execution request transmitted from the host PC 3 to the identified FPGA 7 via the communication path 1a. This makes it possible to distribute the load among the types of templates 5 (logic circuits), thereby improving the processing efficiency of the system 1 as a distributed processing system.

[0127] When the same template 5 is set in multiple logical partitions within one FPGA 7 or among multiple FPGAs 7, the processing of the template 5 can be executed in each of these multiple logical partitions. When the determination unit 44 identifies multiple FPGAs 7 (logical partitions) as candidates for the destination of the acquired execution request, the determination unit 44 may determine the destination of the execution request in accordance with the processing load of the circuit logic of the FPGA 7 (logical partition).

[0128] For example, the determination unit 44 may manage a portion of the storage area of ​​the memory 4c of the optimization device 4 as a queue (buffer) that stores execution requests. The queue may be shared by all execution requests, or may be provided for each template 5 or each FPGA 7. For example, the determination unit 44 may read the execution requests stored in the queue using logic such as FIFO (First-In First-Out), and issue the execution request to an FPGA 7 (logical partition) selected from among candidate FPGAs 7 (logical partitions) to which the execution request is to be issued. The preprocessing results by the FPGA 7 are transmitted to the host PC 3 via the interface 6.

[0129] Furthermore, before selecting the second template 5, the determination unit 44 may determine whether there are any template candidates in the logic pool area 41a that have not yet been selected during the period in which the processing results continuously satisfy the detection conditions. The template candidates are candidates for templates 5 that match the read conditions and are an example of selectable templates 5 that have not been written to the circuit area 70 during the period in which the processing results continuously satisfy the detection conditions. Note that whether a template candidate has not yet been selected during the period in which the detection conditions continuously satisfy may be determined based on the "timestamp" in the template management information 41c. This allows the determination unit 44 to avoid re-reading into the FPGA 7 a template 5 that was selected during the period in which the detection conditions continuously satisfied but did not produce the expected processing results, thereby efficiently recovering the processing results.

[0130] For example, when the determination unit 44 determines that the processing result satisfies the detection condition, it may refer to the template management information 41c and determine whether or not a template candidate for the second circuit logic for executing the second preprocessing exists in the logic pool 40. When the determination unit 44 determines that the template candidate exists in the logic pool 40, it may identify the template candidate from the template management information 41c by the method described above, and identify an FPGA 7 that satisfies the write condition from the template management information 41c.

[0131] Furthermore, the determination unit 44 may determine whether or not the template candidate exists in the shared pool storage 8 by referring to the template management information 82. This determination may be made, for example, when it is determined that the template candidate does not exist in the logical pool 40. When the determination unit 44 determines that the template candidate exists in the shared pool storage 8, it may identify the template candidate to be moved to the logical pool 40 from the template management information 82 of the shared pool storage 8. The template management information 82 may include the items of "template number," "logical partition size," and "processing content." Details of these items are the same as the template number, logical partition size, and processing content of the template management information 41c shown in FIG. 8.

[0132] Furthermore, the determination unit 44 may determine whether or not a template candidate can be created by the creation unit 45, which will be described later. This determination may be made, for example, when it is determined that a template candidate does not exist in the shared pool storage 8. Examples of cases in which a template candidate cannot be created include when there are insufficient templates 5 in the logical pool 40, or when there are no templates 5 that can be created.

[0133] It should be noted that, as a method for adding a template 5 to the logic pool 40, it is conceivable to use a method in which a user adds the template 5 via the IF unit 4e (see FIG. 4), but this method is not suitable for replacing the template 5 in real time or near real time. On the other hand, according to a method according to one embodiment, the optimization device 4 can set the second circuit logic realized by a second template 5 that does not exist in the logic pool 40 without user operation. Therefore, compared to adding a template 5 by user operation, it is possible to rewrite the template 5 in a shorter time.

[0134] When there are no template candidates during a period in which the processing results continuously satisfy the detection conditions, the determination unit 44 may select a fourth template 5 selected based on information related to the first processing from among one or more second templates 5 set in the circuit area 70 during that period. For example, when there are no selectable template candidates, the determination unit 44 may select the best template 5 in the logic pool 40 based on the "processing result" in the template management information 41c. For example, the determination unit 44 may identify the template 5 that produced the best processing result during the period in which the detection conditions are satisfied as the template 5 to be written to the FPGA 7. The template 5 that produced the best processing result is an example of the fourth template. When the determination unit 44 determines that the creation unit 45 should create a template candidate, the determination unit 44 may notify the creation unit 45 to create a template candidate.

[0135] Furthermore, the determination unit 44 may determine to move the template 5 in the logical pool 40 to the shared pool storage 8 in accordance with the usage amount of the memory unit 41. The template 5 to be moved to the shared pool storage 8 is an example of a third template. For example, the determination unit 44 may refer to the timestamps in the template management information 41c and determine to move the templates 5 to the shared pool storage 8 in order from the oldest to the newest, until the usage amount of the logical pool 40 decreases to the allowable amount. Note that when the template 5 is moved to the shared pool storage 8, the determination unit 44 may add an entry for the template 5 to the template management information 82.

[0136] This prevents the inability to add new templates 5 due to tight capacity in the optimization device 4. Furthermore, the templates 5 that realize optimization of the system 1 may change over time and may differ from region to region. For example, a template 5 that was deemed optimal for optimizing processing results in a particular region may no longer be optimal at some point, resulting in an extended period of unused usage. However, such a template 5 may be suitable for optimizing processing results in other regions different from the particular region. Therefore, by moving the template 5 to the shared pool storage 8 and sharing it with the logical pool 40 of another regional system 10, it may be possible to realize optimization of processing results in the other region.

[0137] Furthermore, the judgment unit 44 may update the information 41b, 41c stored in the memory unit 41 after the writing unit 47 described later writes the template 5 to the circuit area 70, and after the updating unit 48 described later updates the template 5 in the logical pool 40.

[0138] For example, when a template 5 created by the creation unit 45 described below or a template 5 read from the shared pool storage 8 is added to the logical pool 40, the determination unit 44 may add an entry for the added template 5 to the template management information 41c. Furthermore, when a template 5 is changed or deleted from the logical pool 40, the determination unit 44 may update or delete the corresponding entry in the template management information 41c.

[0139] Furthermore, the determination unit 44 may update the template management information 41c based on the usage status of the template 5. As an example, the determination unit 44 may update the "FPGA number," "timestamp," and "processing result." The "processing result" may include the recognition rate of the AI ​​processing using the results of preprocessing with the template 5, and the operation rate of the FPGA 7 when the template 5 is used, and the determination unit 44 may update the "processing result" with, for example, the average value of the recognition rate and the average value of the operation rate within a predetermined period.

[0140] Furthermore, for example, if the "details" of the judgment condition management information 41b change due to the addition, modification, or deletion of a template 5, the judgment unit 44 may update each entry of the judgment condition management information 41b to match the change. The judgment condition management information 41b may be updated based on a judgment condition update request, which will be described later.

[0141] The creation unit 45 creates a template 5 that meets the read conditions based on the notification from the determination unit 44 that a template 5 is to be created. For example, the creation unit 45 may create (compile) a template 5 that meets the read conditions based on one or more templates 5. For example, the creation unit 45 may create a template 5 that meets the read conditions by combining multiple templates 5 included in one or both of the logical pool 40 and the shared pool storage 8. As an example, the creation unit 45 may create a template 5 that meets the read conditions by combining and recompiling multiple processing contents (processing elements) included in each of the multiple templates 5. Alternatively, the creation unit 45 may create a new template 5 by deleting at least one of the multiple processing elements included in one template 5.

[0142] In order to create a new template 5 by combining existing processing elements, the creation unit 45 may create the template 5 through design input (step P1), design synthesis (step P2), and design implementation (step P4) illustrated in Fig. 2. The creation unit 45 may store the created template 5 in the logic pool 40. In other words, the creation unit 45 may omit the execution of the processes of logic verification (step P3), static timing analysis (step P5), timing verification (step P7), and actual device verification (step P9) illustrated in Fig. 2.

[0143] When creating a template 5 using a template 5 in the shared pool storage 8, the creating unit 45 may identify the template 5 by referring to the template management information 82 and read it into the logical pool 40 or the memory 4c.

[0144] By the processing of the creation unit 45 described above, a template 5 that is effective for optimization can be added in a short time compared to adding a new template 5 to the logical pool 40 by user operation.

[0145] The creation unit 45 stores the created template 5 in the logical pool 40, and notifies the determination unit 44 that the template 5 has been created. The determination unit 44 may register information about the stored template 5 in the template management information 41c.

[0146] The reading unit 46 reads the template 5 identified by the determination unit 44 or the creation unit 45 from the logical pool 40. For example, the reading unit 46 reads the template 5 identified by the determination unit 44 from the logical pool 40 realized by a partial storage area of ​​the storage unit 4d, and writes it to the memory 4c.

[0147] Furthermore, the reading unit 46 may read the template 5 identified by the determination unit 44 from the shared pool storage 8. For example, the reading unit 46 may read the template 5 identified by the determination unit 44 from the shared pool storage 8 and write it to the logical pool 40.

[0148] Furthermore, if the determination unit 44 determines that a template 5 that has not been used for a long period of time should be moved to the shared pool storage 8, the reading unit 46 may read the template 5 identified by the determination unit 44 from the logical pool 40 and write it to the shared pool storage 8.

[0149] The writing unit 47 writes the template 5 written to the memory 4c by the reading unit 46 to the circuit area 70 of the FPGA 7 identified by the determining unit 44 via the communication path 1a. The writing unit 47 may write the template 5 to the circuit area 70, for example, by a method similar to that used for downloading a bitstream to the circuit area 70 (step P8 in FIG. 2). When the writing of the template 5 is completed, the writing unit 47 notifies the determining unit 44 of the completion.

[0150] The update unit 48 updates the templates 5 stored in the logical pool 40 based on a template update request input by a user operation. A template update request is an example of a request to register a template 5, and may include a storage request to add a new template 5, a change request to change an existing template 5, a deletion request to delete an existing template 5, etc.

[0151] For example, when the update unit 48 receives a storage request including information about a new template 5, it may store the template 5 in the logical pool 40. Furthermore, when the update unit 48 receives a change request including information about the changed template 5 and information identifying the original template 5, it may update the original template 5 in the logical pool 40 to the changed template 5. Furthermore, when the update unit 48 receives a deletion request including information identifying a template 5 stored in the logical pool 40, it may delete the template 5 from the logical pool 40. When the processing in response to the template update request is completed, the update unit 48 notifies the determination unit 44 of the completion.

[0152] For example, the update unit 48 may receive a template update request from the host PC 3 or a computer (not shown) via a network such as a LAN. Alternatively, the update unit 48 may acquire a template update request input by an administrator or user of the system 1 via the IO unit 4f or the reading unit 4g.

[0153] The template update request may also include a judgment condition update request for updating judgment conditions that change as the template 5 is updated. The judgment condition update request is an example of a condition registration request. The judgment condition update request may include information regarding changing or deleting existing conditions included in the judgment condition management information 41b, or information regarding conditions to be newly added to the judgment condition management information 41b. The judgment condition update request may be transmitted from the host PC 3 or a computer (not shown) independently of the template update request, or may be input via the IO unit 4f or the reading unit 4g.

[0154] [E] Example of operation Next, an example of the operation of the system 1 according to an embodiment will be described. Fig. 9 is a flowchart illustrating an example of the operation of the system 1 according to an embodiment. Hereinafter, an example of the above-mentioned processing by the system 1 (for example, the optimization device 4) will be described with reference to the flowchart.

[0155] 9, the determination unit 44 of the optimization device 4 determines whether the processing result obtained by the information collection unit 43 satisfies the detection condition of the determination condition management information 41b (step S1). In this case, satisfying the detection condition means that the processing result is not in the expected state, for example, when a low recognition rate or a high operation rate is confirmed.

[0156] If the determination unit 44 determines that the detection condition is not satisfied (NO in step S1), the process ends. If the determination unit 44 determines that the detection condition is satisfied (YES in step S1), the process proceeds to step S2.

[0157] The determination unit 44 references the determination condition management information 41b and the template management information 41c and determines whether or not there are any unselected template candidates in the logical pool area 41a among the templates 5 that match the read conditions (step S2). An unselected template candidate is a template 5 that has not been used during the period in which the processing result continuously satisfies the detection conditions in step S1, and the determination unit 44 determines whether or not a template is unselected based on the timestamp in the template management information 41c.

[0158] If the determination unit 44 determines that an unselected template candidate exists in the logical pool area 41a (YES in step S2), the process proceeds to step S3. The determination unit 44 references the template management information 41c to select one unselected template candidate that exists in the logical pool area 41a (logical pool 40) (step S3), notifies the reading unit 46 of the selected template candidate, and the process proceeds to step S4.

[0159] The reading unit 46 reads the template candidate selected by the determination unit 44 from the logic pool 40 into the memory 4c. The writing unit 47 writes the template candidate stored in the memory 4c into the circuit area 70 of the FPGA 7. As a result, the FPGA 7 operates according to the circuit logic realized by the written template candidate. The optimization device 4 then waits for a certain period of time (step S4), and the process proceeds to step S1.

[0160] If the determination unit 44 determines that no unselected template candidates exist in the logical pool area 41a (NO in step S2), the process proceeds to step S5. The determination unit 44 references the template management information 82 of the shared pool storage 8, and determines whether or not a template candidate that meets the read conditions exists in the shared logical pool area 81 (step S5).

[0161] If the determination unit 44 determines that a template candidate that meets the read conditions exists in the shared logical pool area 81 (YES in step S5), the process proceeds to step S6. In step S6, the determination unit 44 selects a template candidate that meets the read conditions from the shared logical pool area 81. The read unit 46 moves the selected template candidate to the logical pool area 41a. As a result, unselected template candidates are added to the logical pool area 41a. Then, the process proceeds to step S3.

[0162] If the determination unit 44 determines that there are no template candidates that match the read conditions in the shared logical pool area 81 (NO in step S5), the process proceeds to step S7. The determination unit 44 references the template management information 41c, 82 and determines whether or not a template candidate that matches the read conditions can be created (step S7).

[0163] If the determination unit 44 determines that a template candidate that matches the read conditions can be created (YES in step S7), the creation unit 45 creates a template candidate that matches the read conditions and stores the created template candidate in the logical pool area 41a (step S8). This adds an unselected template candidate to the logical pool area 41a. The process then proceeds to step S3.

[0164] If the determination unit 44 determines that it is not possible to create a template candidate that meets the read conditions (NO in step S7), the process proceeds to step S9. In step S9, the determination unit 44 selects the template 5 that has been confirmed to have the best processing result from among the templates 5 set in the circuit area 70 during the period in which the detection conditions have been continuously satisfied. For example, the determination unit 44 references the timestamp and processing result in the template management information 41c and selects the template 5 that has the best processing result during the period in which the detection conditions have been continuously satisfied. The read unit 46 stores the selected template 5 in the memory 4c. The write unit 47 sets the stored template 5 in the circuit area 70, and the process proceeds to step S10.

[0165] After the process of step S9, the determination unit 44 may consider that the detection condition that had been continuously satisfied is no longer satisfied, regardless of whether or not the distribution process of step S12 described below is executed. This marks the end of the period in which the detection condition was continuously satisfied.

[0166] In step S10, the determination unit 44 determines whether or not to increase the number of processes to be executed. The number of processes may be increased, for example, when the logical partition size of the template 5 written in step S9 is larger than the size of the circuit logic that was set before writing. If the determination unit 44 determines not to increase the number of processes to be executed (NO in step S10), the process ends.

[0167] If the determination unit 44 determines that the number of processes to be executed should be increased (YES in step S10), the determination unit 44 determines whether distributed processing is possible (step S11). For example, the determination unit 44 may determine whether distributed processing is possible based on an imbalance in the processing load (operation rate) among multiple FPGAs 7. For example, assume that a large-sized template 5 is to be written to FPGA #0 among FPGAs #0 to #2. In this case, if the operation rates of FPGAs #1 and #2 are on a downward trend, the determination unit 44 may determine that the processing of FPGA #0 should be written to the circuit area 70 of FPGA #1 or FPGA #2. The above-mentioned determination may be made based on a determination condition related to distributed processing (see, for example, condition name: R3 in FIG. 7) included in the determination condition management information 41b.

[0168] If the determination unit 44 determines that distributed processing is not possible (NO in step S11), the processing ends. A case in which distributed processing is not possible is assumed to be, for example, a case in which the processing load on all FPGAs #7 is increasing or is constant.

[0169] If the determination unit 44 determines that distributed processing is possible (YES in step S11), distributed processing is performed to distribute the processing performed by the template 5 (step S12), and the processing ends. Distributed processing is performed by setting the template 5 set in the FPGA 7 with a heavy load to the FPGA 7 with a light load.

[0170] In this way, in steps S1 to S8, the optimization device 4 repeats the process of selecting template candidates and writing them into the circuit area 70 while the processing results satisfy the detection conditions, until there are no more template candidates.

[0171] The order of execution of steps S5 and S6 and steps S7 and S8 may be reversed. Also, one or both of steps S5 and S6 and steps S7 and S8 may be omitted.

[0172] [E-1] First operation example Next, a first operation example of the system 1 according to an embodiment will be described with reference to FIGS.

[0173] Fig. 10 is a diagram showing changes in processing results according to the first operation example. The horizontal axis of the graph shown in Fig. 10 represents time, and as an example, the graph shows processing results from midnight to midnight on a certain day. The left vertical axis represents the availability of FPGA #0, and the right vertical axis represents the AI ​​recognition rate of host PC 3. The solid line graph connects the availability rates of FPGA #0 (hatched circles) obtained at predetermined time intervals, and the dotted line graph connects the AI ​​recognition rates of host PC 3 (open circles) obtained at predetermined time intervals.

[0174] FIG. 11 is a diagram showing template management information 41c according to a first operation example, and FIG. 12 is a diagram showing updates to the template management information 41c according to the first operation example. FIGS. 11 and 12 show an example of template management information 41c that focuses on 4K processing, which has the same resolution as the resolution of process A performed by FPGA #0. As an example, the determination unit 44 may obtain the template management information 41c shown in FIGS. 11 and 12 by filtering (narrowing) the "processing content" of the template management information 41c by 4K processing. It is assumed that template #2 is operating in the circuit area 70 of FPGA #0 at the start of the graph shown in FIG. 10.

[0175] 13 to 15 are sequence diagrams each illustrating a first operation example of the system 1 according to an embodiment.

[0176] 13, the information collection unit 43 of the optimization device 4 periodically collects the recognition rate of the host PC 3 and the availability rate of each FPGA 7 based on the network transfer rate of each FPGA 7. The determination unit 44 determines whether the collected information matches the detection conditions of the determination condition management information 41b (processes A1a and A1b).

[0177] In the example of Fig. 10, the information collection unit 43 collects a processing result indicating that the recognition rate is 99.90% for a certain period of time starting from midnight. The determination unit 44 determines that the result matches the detection condition of determination condition R1 in the determination condition management information 41b illustrated in Fig. 7. The determination unit 44 sets the processing result of template #2 for a predetermined period of time in the past in template management information 41c, as shown in bold in Fig. 12.

[0178] Furthermore, the determination unit 44 references the template management information 41c, identifies template #3 as a template candidate that exists in the logical pool 40 and meets the read condition of condition R1 (process A2), and notifies the reading unit 46 and writing unit 47 (process A3). Note that the determination unit 44 may use the template management information 41c illustrated in FIG. 11 to identify template #3, which has the same resolution as template #2 and is obtained by adding the processing element "histogram conversion" to template #2, as a template candidate that meets the read condition. The notification may include template #3 identified by the determination unit 44 and determination condition R1.

[0179] After receiving the notification from the determining unit 44, the reading unit 46 reads template #3 from the logical pool 40 (for example, the storage unit 4d) (process A4), and stores the read template #3 in the memory 4c.

[0180] In accordance with the write condition R1, the writing unit 47 writes template #3 stored in memory 4c to a logical partition in the circuit area 70 of FPGA #0 via communication path 1a (process A5), and notifies the determination unit 44 of the completion of the write. Thereafter, FPGA #0 executes preprocessing using the circuit logic of the written template #3 in response to an execution request from the host PC. Based on the result of writing template #3, the determination unit 44 updates the "timestamp" of template #3 in the template management information 41c to the date and time when template #3 was written, and updates the "FPGA number" to "0," as shown in bold in FIG. 12.

[0181] As illustrated in Figure 13, the information collection unit 43 continues to collect the processing results of FPGA #0 to which template #3 is set, and the judgment unit 44 judges whether the collected information matches the detection conditions of the judgment condition management information 41b based on the collected information (processes A6a and A6b).

[0182] If the recognition rate does not recover within a predetermined time after template #3 is rewritten in the circuit area 70 of FPGA #0, the determination unit 44 determines that the detection condition of condition R1 is met. The determination unit 44 updates the "processing result" of template #3 in the template management information 41c, as shown in bold in FIG.

[0183] Furthermore, the determination unit 44 references the template management information 41c and determines that a template candidate that meets the read condition of condition R1 cannot be identified in the logical pool 40 (process A7). As illustrated in FIG. 11, the only template candidate that has the same resolution as template #3 set in FPGA #0 is template #2. This is because template #2 is determined to have already been used since meeting the determination condition of condition R1 based on the timestamp.

[0184] In this case, the judgment unit 44 refers to the template management information 82 of the shared pool storage 8 via the network, identifies template #4 as a template candidate that meets the read condition of condition R1 (process A8), and notifies the read unit 46 (process A9).

[0185] After receiving the notification from the determination unit 44, the reading unit 46 reads template #4 from the shared logical pool area 81 of the shared pool storage 8 (process A10), and stores the read template #4 in the memory 4c.

[0186] The determination unit 44 refers to the template management information 41c, identifies template #4 that was newly added to the logical pool 40 in process A10 as a template candidate that meets the read condition of condition R1 (process A11), and notifies the reading unit 46 and writing unit 47 (process A12).

[0187] After receiving the notification from the determining unit 44, the reading unit 46 reads template #4 from the logical pool 40 (process A13) and stores the read template #4 in the memory 4c.

[0188] In accordance with the write condition of condition R1, the writing unit 47 writes template #4 stored in memory 4c to a logical partition in the circuit area 70 of FPGA #0 via communication path 1a (process A14), and notifies the determination unit 44 of the completion of the write. Thereafter, in response to an execution request from the host PC 3, FPGA #0 executes preprocessing using the circuit logic of the written template #4. As shown in bold in FIG. 12, the determination unit 44 adds the information about template #4 read from the shared pool storage 8 to the template management information 41c. Furthermore, based on the write result of template #4, the determination unit 44 updates the "timestamp" to the date and time when template #4 was written, and updates the "FPGA number" to "0".

[0189] 14, the information collection unit 43 continues to collect the processing results of FPGA #0 in which template #4 is set, and the determination unit 44 determines whether the detection conditions are met based on the collected information (processes A15a and A15b). If the recognition rate does not recover even after a predetermined time has passed since the template #4 was rewritten, the determination unit 44 determines that the detection condition of condition R1 is met, and updates the "processing result" for template #4 in the template management information 41c, as shown in bold in FIG.

[0190] Furthermore, the determination unit 44 references the template management information 41c and determines that no template candidates that meet the read condition of condition R1 can be identified in the logical pool 40 (Process A16). This is because the template candidates that have the same resolution as template #4 are templates #2 and #3, and it is determined based on the timestamps that they have already been used since meeting condition R1.

[0191] Furthermore, the determination unit 44 references the template management information 82, determines that a template candidate that meets the read condition of condition R1 cannot be identified in the shared storage pool 8 (process A17), and notifies the creation unit 45 of this (process A18). For example, if the shared storage pool 8 does not have a template candidate with a resolution of "4K processing," it is determined that a template candidate in the shared storage pool 8 cannot be identified.

[0192] Next, if the determination unit 44 determines that a new template candidate that meets the read condition of condition R1 can be created, the creation unit 45 creates template #5 that meets the read condition of condition R1 and stores it in the logical pool 40 (process A19). The creation unit 45 notifies the determination unit 44 that template #5 has been created.

[0193] The determination unit 44 refers to the template management information 41c, identifies template #5 that was newly added to the logical pool 40 as a template candidate that meets the read condition of condition R1 (process A20), and notifies the reading unit 46 and writing unit 47 (process A21).

[0194] After receiving the notification from the determining unit 44, the reading unit 46 reads template #5 from the logical pool 40 (process A22) and stores the read template #5 in the memory 4c.

[0195] The writing unit 47 writes the template #5 stored in the memory 4c to the logical partition in the circuit area 70 of the FPGA #0 via the communication path 1a in accordance with the write condition of the condition R1 (process A23), and notifies the determination unit 44 of the completion of the writing. After that, in response to an execution request from the host PC 3, the FPGA #0 executes preprocessing using the circuit logic realized by the written template #5.

[0196] 12, the determination unit 44 adds information about template #5 to the template management information 41c. Based on the result of writing template #5 to FPGA #0 by the writing unit 47, the determination unit 44 updates the "timestamp" of template #5 in the template management information 41c to the date and time when template #5 was written, and updates the "FPGA number" to "0".

[0197] Next, as illustrated in FIG. 14, the information collection unit 43 continues to collect the processing results by FPGA #0 to which template #5 is set, and the judgment unit 44 judges whether the detection conditions are met based on the collected information (processes A24a and A24b).

[0198] For example, in the graph of changes in processing results shown in FIG. 10, the recognition rate recovers to 100% at 7:00 a.m. In this case, the determination unit 44 determines that the detection conditions are not met based on the determination condition management information 41b. Furthermore, the determination unit 44 updates the "processing result" for template #5 in the template management information 41c, as shown in FIG. 12, and the processing ends.

[0199] On the other hand, if the recognition rate does not recover even after preprocessing is performed by FPGA #0 in which template #5 is set, the process shown in Fig. 15 is executed. Fig. 15 shows the continuation of the process when template #5 is set in FPGA #0 by the above-mentioned process, the process results are collected and judged (processes A24a and A24b), and the judgement unit 44 judges that the detection condition of condition R1 is still met.

[0200] The determination unit 44 updates the "processing result" for template #5 in the template management information 41c to, for example, 99.92%. The determination unit 44 references the template management information 41c, and determines that a template candidate that meets the read condition of condition R1 cannot be identified in the logical pool 40 (process A25).

[0201] Next, the determination unit 44 references the template management information 82 and determines that a template candidate that meets condition R1 cannot be identified in the shared pool storage 8 (processing A26). If the determination unit 44 further determines that a new template candidate cannot be created by the creation unit 45, the determination unit 44 references the template management information 41c. Based on the "processing result" and "timestamp," the determination unit 44 identifies the template candidate that achieved the best recognition rate during the period in which the processing result continuously satisfied the detection condition of condition R1 (processing A27), and notifies the reading unit 46 and writing unit 47 of this (processing A28).

[0202] The reading unit 46 reads out the template 5 identified by the determining unit 44 (process A29), and stores the read out template 5 in the memory 4c.

[0203] The writing unit 47 writes the template 5 stored in the memory 4c to the logical partition in the circuit area 70 of the FPGA#0 via the communication path 1a (process A30), and notifies the determining unit 44 of the completion of the writing.

[0204] Based on the result of writing template 5 into FPGA #0 by writing unit 47, determination unit 44 updates the "timestamp" of template 5 in template management information 41c to the date and time when template 5 was written, and processing ends.

[0205] [E-2] Second operation example Next, a second operation example of the system 1 according to an embodiment will be described with reference to FIGS.

[0206] Fig. 16 is a diagram showing changes in processing results according to the second operation example. The horizontal axis of the graph shown in Fig. 16 represents time, and as an example, the graph shows processing results from midnight to midnight on a certain day. The left vertical axis represents the availability of FPGA #2, and the right vertical axis represents the AI ​​recognition rate of host PC 3. The solid line in the graph connects the availability rates (diagonal lines) of FPGA #2 obtained at predetermined time intervals, and the dotted line graph connects the AI ​​recognition rates of host PC 3 obtained at predetermined time intervals.

[0207] FIG. 17 is a diagram showing template management information 41c according to the second operation example, and FIGS. 18 and 19 are diagrams showing updates to the template management information 41c according to the second operation example. FIGS. 17 to 19 show an example of template management information 41c focusing on template 5 having the same processing content as process C performed by FPGA #2. As an example, the determination unit 44 may obtain the template management information 41c shown in FIGS. 17 to 19 by filtering the template management information 41c by the same "processing content." At the start of the graph shown in FIG. 16, it is assumed that template #0 is operating in the circuit area 70 of FPGA #2.

[0208] FIG. 20 is a sequence diagram illustrating a second operation example of the system 1 according to an embodiment.

[0209] 20, the information collecting unit 43 of the optimization device 4 periodically collects the recognition rate of the host PC 3 and the availability rate of each FPGA 7 based on the network transfer rate of each FPGA 7. The determining unit 44 determines whether the collected information matches the detection conditions of the determination condition management information 41b (processes B1a and B1b).

[0210] In the example of Fig. 16, the operation rate has been 100.00% since around 3:00 PM. In the judgment conditions illustrated in Fig. 7, when the recognition rate is 100.00%, the detection condition of judgment condition R2 is met, and so the judgment unit 44 judges that the detection condition is met. Furthermore, as illustrated in bold in Fig. 18, the judgment unit 44 updates the "processing result" of template #0 in the template management information 41c.

[0211] The determination unit 44 identifies template #1 from the template management information 41c as a template candidate in the logical pool 40 that meets the read condition of condition R2 (process B2), and notifies the read unit 46 and write unit 47 (process B3). The determination unit 44 identifies template #1 of circuit logic that has the same processing content as template #0, is larger than the logical partition size of template #0, and is equal to or smaller than the circuit scale 71 of FPGA #2. The notification may include template #1 identified by the determination unit 44 and condition R2.

[0212] After receiving the notification from the determining unit 44, the reading unit 46 reads template #1 from the logical pool 40 (for example, the storage unit 4d) (process B4), and stores the read template #1 in the memory 4c.

[0213] The writing unit 47 writes the template #1 stored in the memory 4c to the logical partition in the circuit area 70 of the FPGA #2 via the communication path 1a in accordance with the writing condition R2 (process B5), and notifies the determination unit 44 of the completion of the writing.

[0214] Based on the result of writing template #1 to FPGA #2 by the writing unit 47, the determination unit 44 updates the "timestamp" of template #1 in the template management information 41c to the date and time when template #1 was written, as shown in Fig. 18. Furthermore, based on the result of writing template #1 to FPGA #2, the determination unit 44 updates the "FPGA number" of template #1 in the template management information 41c to "2", as shown in Fig. 18.

[0215] As illustrated in FIG. 20, the information collection unit 43 continues to collect the recognition rate and operation rate of FPGA #2 to which template #1 is set, and the judgment unit 44 judges, based on the collected information, whether or not the detection conditions of the judgment condition management information 41b are met (processes B6a and B6b).

[0216] If the availability rate falls below 100.00% (for example, 99.00%) after a predetermined time has elapsed since the template was rewritten to template #1, the determination unit 44 determines that the detection condition of condition R2 is not met. Note that the determination unit 44 updates the "processing result" of template #1 in the template management information 41c, as shown in bold in FIG. 18.

[0217] On the other hand, if the availability rate does not fall below 100.00% even after a predetermined time has elapsed since the template was rewritten to template #1, the determination unit 44 determines that the detection condition of condition R2 is met. An example of the template management information 41c that is updated in this case is shown in FIG. 19. The determination unit 44 updates the "processing result" of template #1 in the template management information 41c, as shown in bold in FIG. 19.

[0218] Next, the determination unit 44 references the template management information 41c, and determines that a template candidate that matches the read condition of condition R2 cannot be identified in the logical pool 40 (Process B7). Furthermore, the determination unit 44 references the template management information 82, and if there is no template candidate that matches the read condition of condition R2, determines that a template candidate cannot be identified in the shared pool storage 8 (Process B8).

[0219] Furthermore, the determination unit 44 determines whether the creation unit 45 can create a template candidate that complies with the read condition of condition R2. If the determination unit 44 determines that a new template candidate cannot be created, it references the template management information 41c, identifies template 5 that has the best processing results (process B9), and notifies the read unit 46 and write unit 47 (process B10). In this case, there is no difference in availability between template #0 and template #1, but template #1, which has a larger logical partition size, can be considered the best.

[0220] The reading unit 46 reads out the template #1 identified by the determining unit 44 (process B11), and stores the read out template #1 in the memory 4c.

[0221] The writing unit 47 writes the template #4 stored in the memory 4c to the logical partition in the circuit area 70 of the FPGA #2 via the communication path 1a (process B12), and notifies the determining unit 44 of the completion of the writing.

[0222] Based on the result of writing template #1 to FPGA #2 by the writing unit 47, the judgment unit 44 updates the "timestamp" of template #1 in the template management information 41c to the date and time when template #1 was written again, as shown in FIG. 19.

[0223] Next, as shown in processes B13a and B13b, it is assumed that the operation rate of the FPGA 7 matches the distribution condition (condition R3) in the judgment condition management information 41b in the judgment by the information collecting unit 43 and the judgment unit 44. In this case, the judgment unit 44 notifies the reading unit 46 and the writing unit 47 of the distribution condition R3.

[0224] The reading unit 46 reads template #1 from the logical pool 40 (for example, the storage unit 4d) in accordance with the reading condition of condition R3 (process B14), and stores the read template #1 in memory 4c.

[0225] In accordance with the write condition R3, the writing unit 47 writes the template #1 stored in the memory 4c via the communication path 1a to a logical partition in the circuit area 70 of FPGA #0 in which no other template 5 is set (process B15). Furthermore, the writing unit 47 notifies the determination unit 44 of the completion of the writing. Note that the logical partition in the circuit area 70 of FPGA #0 in which the other template 5 is set continues to operate without being affected by the writing of template #1.

[0226] With the above, the process of writing the template 5 into the FPGA 7 (the process when the detection conditions are satisfied) is completed.

[0227] [F] Other The techniques according to the above-described embodiments can be implemented with the following modifications and variations.

[0228] For example, the functional blocks 42 to 48 included in the optimization device 4 shown in Fig. 6 may be merged in any combination or may be divided. The information 41b and 41c stored in the memory unit 41 shown in Fig. 5 may be merged in any combination or may be divided.

[0229] In addition, in one embodiment, the host PC 3 and the optimization device 4 are described as separate computers, but this is not limiting. For example, the host PC 3 and the optimization device 4 may be a single computer, or at least some of the functions or information provided in the optimization device 4 may be provided in the host PC 3.

[0230] Furthermore, although the logical pool 40 is provided in the optimization device 4, this is not limited to this and the logical pool 40 may be provided in a computer or storage device different from the optimization device 4. In this case, the reading unit 46 may read the template 5 from the logical pool 40 via the IF unit 4e, and the update unit 48 may update the template 5 in the logical pool 40 via the IF unit 4e.

[0231] In addition, in the embodiment, an FPGA 7 is used as an example of a programmable logic circuit, but the present invention is not limited to this, and the method according to the embodiment can also be applied when a CPLD (Complex PLD) is used. Note that the template 5 for the CPLD may be bitstream data in which the placement and wiring (which may also be called fitting) of the circuit logic has been completed, similar to the template 5 for the FPGA 7.

[0232] Furthermore, in one embodiment, the processing in each situation has been described using examples of a low recognition rate and a high availability rate (see FIGS. 10 to 12), but the present invention is not limited to this. For example, the judgment criteria management information 41b may provide judgment criteria for determining whether the recognition rate is low and the availability rate is high. If the criteria are met, the judgment unit 44 may identify a template 5 that restores the recognition rate and reduces the availability rate from the logical pool 40 or the shared pool storage 8 as a candidate template that meets the criteria, or may have the creation unit 45 create the template.

[0233] This makes it possible to recover the recognition rate and reduce the operating rate in situations where a low recognition rate and a high operating rate occur, such as when there are a large number of objects to be processed by AI in dark conditions or when a large-scale disaster occurs at night.

[0234] Furthermore, the timing at which the determination unit 44 updates each piece of information in the template management information 41c is not limited to the timing in the above-described embodiment. For example, the "timestamp" and "FPGA number" may be updated at the same time as the "processing result."

[0235] Furthermore, in one embodiment, a process is described in which a template candidate is identified from the template management information 82 of the shared pool storage 8 when no template candidate exists in the logical pool 40, but the number of template candidates identified is not limited to one. For example, multiple template candidates that meet the read conditions may be read from the shared pool storage 8 and moved to the logical pool 40 all at once.

[0236] [G] Notes The following additional notes are provided regarding the above-described embodiments.

[0237] (Appendix 1) a first circuit logic set in a rewritable circuit area of ​​a programmable logic circuit, the first circuit logic being realized by writing a first template, the first template having a circuit design already synthesized and a layout and wiring already determined, into the circuit area, when information relating to a first process executed by the first circuit logic satisfies a predetermined condition; and a second template of a second circuit logic that executes a second process related to the first process is read from a storage area; writing the read second template into the circuit area, thereby setting the second circuit logic that executes the second process in the circuit area; A control device comprising a control unit.

[0238] (Appendix 2) the information about the first processing includes an index indicating whether a result obtained by inputting a result of the first processing into a machine learning model is good or bad; When a first condition of the predetermined conditions that the index is less than a first predetermined value is satisfied in the reading process, the control unit reads from the storage area the second template of the second circuit logic that executes the second process, the second template including a plurality of processing elements to which at least one of deletion of one or more processing elements, replacement of one or more processing elements, and addition of one or more processing elements is applied, among the plurality of processing elements included in the first process. 10. The control device of claim 1.

[0239] (Appendix 3) the information about the first process includes information about a load of the first circuit logic that executes the first process; When a second condition of the predetermined conditions, that is, the information on the load is equal to or greater than a second predetermined value, is satisfied in the reading process, the control unit reads the second template of the second circuit logic, which is larger in size than the first circuit logic, from the storage area. 10. The control device according to claim 1 or 2.

[0240] (Appendix 4) the control unit stores, from a shared storage area shared among the plurality of control devices, selectable templates that have not been written to the circuit area during a period in which the predetermined condition is continuously satisfied, into the storage area; The control device according to any one of Supplementary notes 1 to 3.

[0241] (Appendix 5) the control unit moves a third template selected based on an unused period from among the plurality of templates stored in the storage area to the shared storage area in accordance with the amount of usage of the storage area; 5. The control device according to claim 4.

[0242] (Appendix 6) the control unit creates a selectable template that has not been written in the circuit area during a period in which the predetermined condition is continuously satisfied, based on one or more templates stored in the storage area; The control device according to any one of Supplementary notes 1 to 5.

[0243] (Appendix 7) The control unit when there are no selectable templates that have not been written to the circuit area during the period in which the predetermined condition is continuously satisfied, writing a fourth template to the circuit area, selected from the second templates set in the circuit area during the period based on information related to the first process; Ending said period; The control device according to any one of Supplementary notes 1 to 6.

[0244] (Appendix 8) a first circuit logic set in a rewritable circuit area of ​​a programmable logic circuit, the first circuit logic being realized by writing a first template, the first template having a circuit design already synthesized and a layout and wiring already determined, into the circuit area, when information relating to a first process executed by the first circuit logic satisfies a predetermined condition; and a second template of a second circuit logic that executes a second process related to the first process is read from a storage area; writing the read second template into the circuit area, thereby setting the second circuit logic that executes the second process in the circuit area; A control method in which processing is performed by a computer.

[0245] (Appendix 9) the information about the first processing includes an index indicating whether a result obtained by inputting a result of the first processing into a machine learning model is good or bad; The reading process includes a process of reading, when a first condition of the predetermined conditions that the index is less than a first predetermined value is satisfied, from the storage area the second template of the second circuit logic that executes the second process, the second template including a plurality of processing elements to which at least one of deletion of one or more processing elements, replacement of one or more processing elements, and addition of one or more processing elements has been applied, among the plurality of processing elements included in the first process. 9. The control method according to claim 8.

[0246] (Appendix 10) the information about the first process includes information about a load of the first circuit logic that executes the first process; The reading process includes a process of reading, from the storage area, the second template of the second circuit logic, which is larger in size than the first circuit logic, when a second condition of the predetermined conditions, that the information on the load is equal to or greater than a second predetermined value, is satisfied. 10. The control method according to claim 8 or 9.

[0247] (Appendix 11) storing, from a shared storage area shared among the plurality of control devices, selectable templates that have not been written to the circuit area during a period in which the predetermined condition is continuously satisfied, into the storage area; The processing is executed by the computer. The control method according to any one of Supplementary notes 8 to 10.

[0248] (Appendix 12) moving a third template selected based on an unused period from among the plurality of templates stored in the storage area to the shared storage area in accordance with the amount of usage of the storage area; The processing is executed by the computer. 12. The control method of claim 11.

[0249] (Appendix 13) creating a selectable template that has not been written in the circuit area during a period in which the predetermined condition is continuously satisfied, based on one or more templates stored in the storage area; The processing is executed by the computer. The control method according to any one of Supplementary notes 8 to 12.

[0250] (Appendix 14) when there are no selectable templates that have not been written to the circuit area during the period in which the predetermined condition is continuously satisfied, writing a fourth template to the circuit area, selected from the second templates set in the circuit area during the period based on information related to the first process; Ending said period; The processing is executed by the computer. A control method according to any one of Supplementary notes 8 to 13.

[0251] (Appendix 15) a programmable logic circuit; a control device; The control device a first circuit logic set in a rewritable circuit area of ​​the programmable logic circuit, the first circuit logic being realized by writing a first template, for which circuit design synthesis has been completed and placement and wiring has been determined, into the circuit area, when information relating to a first process executed by the first circuit logic satisfies a predetermined condition; and a second template of a second circuit logic executing a second process related to the first process is read from a storage area; a control unit that writes the read second template into the circuit area to set the second circuit logic that executes the second process in the circuit area; Distributed processing system.

[0252] (Appendix 16) the information about the first processing includes an index indicating whether a result obtained by inputting a result of the first processing into a machine learning model is good or bad; When a first condition of the predetermined conditions that the index is less than a first predetermined value is satisfied in the reading process, the control unit reads from the storage area the second template of the second circuit logic that executes the second process, the second template including a plurality of processing elements to which at least one of deletion of one or more processing elements, replacement of one or more processing elements, and addition of one or more processing elements is applied, among the plurality of processing elements included in the first process. 16. The distributed processing system of claim 15.

[0253] (Appendix 17) the information about the first process includes information about a load of the first circuit logic that executes the first process; When a second condition of the predetermined conditions that the information on the load is equal to or greater than a second predetermined value is satisfied in the reading process, the control unit reads the second template of the second circuit logic, which is larger in size than the first circuit logic, from the storage area. 17. The distributed processing system according to claim 15 or 16.

[0254] (Appendix 18) A plurality of the control devices; a shared storage area shared among the plurality of control devices, the control unit stores, from the shared storage area, selectable templates that have not been written to the circuit area during a period in which the predetermined condition is continuously satisfied, in the storage area; 18. The distributed processing system according to any one of Supplementary notes 15 to 17.

[0255] (Appendix 19) the control unit moves a third template selected based on an unused period from among the plurality of templates stored in the storage area to the shared storage area in accordance with the amount of usage of the storage area; 19. The distributed processing system of claim 18.

[0256] (Appendix 20) the control unit creates a selectable template that has not been written in the circuit area during a period in which the predetermined condition is continuously satisfied, based on one or more templates stored in the storage area; 19. A distributed processing system according to any one of Supplementary notes 15 to 19. [Explanation of symbols]

[0257] 1 System 1a Communication Channel 10 Regional Systems 2 Cameras 3. Host PC 30 AI processing engines 4 Optimization Device 40 logical pools 41 Memory section 41a Logical pool area 41b Judgment condition management information 41c Template Management Information 42 Communications Department 43 Information Gathering Department 44 Judgment section 45 Creation Department 46 Reading part 47 Writing section 48 Update section 49 Control Unit 5. Templates 6 Interface 7 FPGA 70 circuit area 71 Circuit scale 8 Shared Pool Storage 81 Shared logical pool area 82 Template Management Information

Claims

1. a first circuit logic set in a rewritable circuit area of ​​a programmable logic circuit, the first circuit logic being realized by writing a first template, the synthesis of which has been completed and the placement and wiring of which has been determined, into the circuit area, when information relating to a first process executed by the first circuit logic satisfies a predetermined condition; and a second template of a second circuit logic executing a second process related to the first process is read from a storage area; writing the read second template into the circuit area, thereby setting the second circuit logic that executes the second process in the circuit area; A control device comprising a control unit.

2. the information about the first processing includes an index indicating whether a result obtained by inputting a result of the first processing into a machine learning model is good or bad; When a first condition of the predetermined conditions that the index is less than a first predetermined value is satisfied in the reading process, the control unit reads from the storage area the second template of the second circuit logic that executes the second process, the second template including a plurality of processing elements to which at least one of deletion of one or more processing elements, replacement of one or more processing elements, and addition of one or more processing elements has been applied, among a plurality of processing elements included in the first process. The control device according to claim 1 .

3. the information about the first process includes information about a load of the first circuit logic that executes the first process; In the reading process, when a second condition of the predetermined conditions that the information on the load is equal to or greater than a second predetermined value is satisfied, the control unit reads the second template of the second circuit logic, which is larger in size than the first circuit logic, from the storage area. The control device according to claim 1 or 2.

4. the control unit stores, from a shared storage area shared among the plurality of control devices, selectable templates that have not been written to the circuit area during a period in which the predetermined condition is continuously satisfied, into the storage area; The control device according to claim 1 or 2.

5. the control unit moves a third template selected based on an unused period from among a plurality of templates stored in the storage area to the shared storage area in accordance with the amount of usage of the storage area; The control device according to claim 4.

6. the control unit creates a selectable template that has not been written in the circuit area during a period in which the predetermined condition is continuously satisfied, based on one or more templates stored in the storage area; The control device according to claim 1 or 2.

7. a first circuit logic set in a rewritable circuit area of ​​a programmable logic circuit, the first circuit logic being realized by writing a first template, the synthesis of which has been completed and the placement and wiring of which has been determined, into the circuit area, when information relating to a first process executed by the first circuit logic satisfies a predetermined condition; and a second template of a second circuit logic executing a second process related to the first process is read from a storage area; writing the read second template into the circuit area, thereby setting the second circuit logic that executes the second process in the circuit area; A control method in which processing is performed by a computer.

8. a programmable logic circuit; a control device; The control device a first circuit logic set in a rewritable circuit area of ​​the programmable logic circuit, the first circuit logic being realized by writing a first template, the first template having a circuit design already synthesized and a layout and wiring already determined, into the circuit area, when information relating to a first process executed by the first circuit logic satisfies a predetermined condition; and a control unit that writes the read second template into the circuit area to set the second circuit logic that executes the second process in the circuit area; Distributed processing system.

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