Semiconductor device

Abstract

To provide a semiconductor device capable of reducing stress generated in a conductive joint material used in mounting.SOLUTION: A semiconductor device A1 includes a semiconductor element 1, and a sealing resin 2 with which the semiconductor element 1 is coated. The sealing resin 2 has a resin main surface 21 and a resin rear face 22, and a resin first side face 23A and a resin second side face 23B. The semiconductor device A1 includes: a first lead 3 having a first rear face 32, a first end face 33A and a second end face 33B; a second lead 4A which is conducted to the semiconductor element 1, and has a second rear face 42A exposed from the resin rear face 22 and a third end face 43A exposed from the resin first side face 23A; a third lead 5A which is located between the first lead 3 and the second lead 4A in a first direction x, and has a third rear face 52A exposed from the resin rear face 22, and a fourth end face 53A exposed from the resin first side face 23A; and a first connection part 6A for connecting the first lead 3 and the third lead 5A.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a semiconductor element, multiple leads, and a sealing resin. The multiple leads have a mounting surface exposed from the back surface of the sealing resin and an end surface exposed from the side surface of the sealing resin. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-87155

[0004] [overview] The mounting surfaces of the multiple leads are joined to a circuit board or the like by a conductive bonding material such as solder. If excessive stress occurs in any of these conductive bonding materials, it can cause cracks or peeling of the conductive bonding material.

[0005] The present disclosure has been devised in light of the above circumstances, and an object of the present disclosure is to provide a semiconductor device that can reduce stress generated in a conductive bonding material used for mounting.

[0006] A semiconductor device provided by the present disclosure includes a semiconductor element and a sealing resin covering the semiconductor element, the sealing resin having a resin main surface and a resin back surface facing opposite to each other in a thickness direction, a resin first side surface along a first direction intersecting the thickness direction, and a resin second side surface along a second direction intersecting the thickness direction and the first direction, and the semiconductor element includes: a first lead having a first back surface exposed from the resin back surface, a first end face exposed from the resin first side surface, and a second end face exposed from the resin second side surface; a second lead electrically connected to the semiconductor element and having a second back surface exposed from the resin back surface and a third end face exposed from the resin first side surface; a third lead located between the first lead and the second lead in the first direction, and having a third back surface exposed from the resin back surface and a fourth end face exposed from the resin first side surface; and a first connecting portion connecting the first lead and the third lead.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a partial plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a front view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a side view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. [Figure 12] FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] 15 is a cross-sectional view taken along line XV-XV in FIG. [Figure 16] FIG. 16 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. [Figure 17] 17 is a partially enlarged cross-sectional view taken along line XVII-XVII in FIG. [Figure 18] FIG. 18 is a partially enlarged cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 19] FIG. 19 is a partially enlarged cross-sectional view showing a second modification of the semiconductor device according to the first embodiment of the present disclosure. [Figure 20] FIG. 20 is a partial enlarged plan view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 21] FIG. 21 is a partially enlarged front view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. [Figure 22] FIG. 22 is a partially enlarged plan view showing the semiconductor device according to the second embodiment of the present disclosure. [Figure 23] 23 is a partially enlarged cross-sectional view taken along line XXIII-XXIII in FIG. 22. FIG. [Figure 24] FIG. 24 is a partially enlarged plan view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 25] 25 is a partially enlarged cross-sectional view taken along line XXV-XXV in FIG. [Figure 26] FIG. 26 is a partially enlarged plan view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 27] FIG. 27 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present disclosure.

[0009] [Detailed explanation] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0011] In this disclosure, unless otherwise specified, the terms "a certain object A is formed on an object B" and "a certain object A is formed on an object B" include "a certain object A is formed directly on an object B" and "a certain object A is formed on an object B with another object interposed between the objects A and B." Similarly, the terms "a certain object A is disposed on an object B" and "a certain object A is disposed on an object B" include "a certain object A is disposed directly on an object B" and "a certain object A is disposed on an object B with another object interposed between the objects A and B," unless otherwise specified. Similarly, the term "a certain object A is located on an object B" includes "a certain object A is located on an object B in contact with the object B" and "a certain object A is located on an object B with another object interposed between the objects A and B," unless otherwise specified. Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in this disclosure, "a surface A faces (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] 1 to 17 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a semiconductor element 1, a sealing resin 2, one or more first leads 3, one or more second leads 4A, one or more third leads 5A, and one or more first coupling portions 6A. The semiconductor device A1 may further include one or more fourth leads 4B and an island lead 9. The specific configuration of the semiconductor device A1 is not limited in any way, and it may be, for example, a QFN (Quad Flat No-leaded package) type semiconductor device.

[0013] FIG. 1 is a plan view showing the semiconductor device A1. FIG. 2 is a partial plan view showing the semiconductor device A1. FIG. 3 is a bottom view showing the semiconductor device A1. FIG. 4 is a front view showing the semiconductor device A1. FIG. 5 is a side view showing the semiconductor device A1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 2. FIG. 10 is a cross-sectional view taken along line XX in FIG. 2. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 2. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 2. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 2. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 2. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 2. Fig. 16 is a partially enlarged plan view showing the semiconductor device A1. Fig. 17 is a partially enlarged cross-sectional view taken along line XVII-XVII in Fig. 16. For ease of understanding, the sealing resin 2 is shown by an imaginary line (two-dot chain line) in Figs. 2 and 16.

[0014] In these figures, the thickness direction of the present disclosure is defined as thickness direction z. A direction perpendicular to thickness direction z is defined as first direction x. A direction perpendicular to thickness direction z and first direction x is defined as second direction y.

[0015] The semiconductor element 1 performs the main electrical function of the semiconductor device A1 when the semiconductor device A1 is mounted on a circuit board or the like to form part of an electrical circuit. The specific configuration of the semiconductor element 1 is not limited in any way, and may include an LSI (Large Scale Integration), an IC (Integrated Circuit), etc. The semiconductor element 1 of this embodiment has a rectangular shape when viewed in the thickness direction z, with two sides along the first direction x and two sides along the second direction y.

[0016] There are no particular limitations on the mounting form of the semiconductor element 1. In this embodiment, the semiconductor element 1 may be mounted to one or more second leads 4A and one or more fourth leads 4B by so-called flip-chip mounting.

[0017] The sealing resin 2 covers the semiconductor element 1, one or more first leads 3, one or more second leads 4A, one or more third leads 5A, and one or more portions of the first connecting portions 6A, as well as one or more fourth leads 4B and one or more portions of the island lead 9. The specific configuration of the sealing resin 2 is not limited in any way, and the constituent materials may include, for example, epoxy resin. The sealing resin 2 of this embodiment may have a resin main surface 21, a resin back surface 22, two resin first side surfaces 23A, and two resin second side surfaces 23B.

[0018] The resin main surface 21 is a surface facing one side in the thickness direction z, and in the illustrated example, is a flat rectangular surface. The resin back surface 22 is a surface facing the other side in the thickness direction z, and in the illustrated example, is a flat rectangular surface. The two resin first side surfaces 23A are surfaces extending along the first direction x and the thickness direction z. The two resin second side surfaces 23B are surfaces extending along the second direction y and the thickness direction z.

[0019] The one or more first leads 3, one or more second leads 4A, one or more third leads 5A, one or more first connecting portions 6A, one or more fourth leads 4B, and island lead 9 perform functions such as supporting the semiconductor element 1, forming a conductive path to the semiconductor element 1, and mounting the semiconductor device A1 on a circuit board. The one or more first leads 3, one or more second leads 4A, one or more third leads 5A, one or more first connecting portions 6A, one or more fourth leads 4B, and island lead 9 may contain, as a constituent material, for example, Cu (copper), Ni (nickel), Fe (iron), and alloys thereof. The one or more first leads 3, one or more second leads 4A, one or more third leads 5A, one or more first connecting portions 6A, one or more fourth leads 4B, and island lead 9 may be provided with a metal layer (not shown) formed by plating or the like at appropriate locations.

[0020] There is no limitation on the number of the one or more first leads 3. As shown in Figures 1 to 3, in this embodiment, the number of the one or more first leads 3 is plural, and in the illustrated example, it is four. As shown in Figures 4, 5, 9, 10, and 15 to 17, the first lead 3 may have a first main surface 31, a first back surface 32, a first end surface 33A, and a second end surface 33B.

[0021] The first main surface 31 faces the same side as the resin main surface 21 in the thickness direction z. The first main surface 31 may be covered with the sealing resin 2. The first back surface 32 faces the same side as the resin back surface 22 in the thickness direction z. The first back surface 32 is exposed from the resin back surface 22. The first back surface 32 may be flush with the resin back surface 22. The first back surface 32 is used as a mounting surface when mounting the semiconductor device A1 on a circuit board.

[0022] The first end surface 33A is a surface along the thickness direction z and the first direction x. The first end surface 33A may be connected to the first main surface 31 and the first back surface 32. The first end surface 33A is exposed from the resin first side surface 23A. The first end surface 33A may be flush with the resin first side surface 23A.

[0023] The second end surface 33B is a surface along the thickness direction z and the second direction y. The second end surface 33B may be connected to the first main surface 31 and the first back surface 32. The second end surface 33B may be connected to the first end surface 33A. The second end surface 33B is exposed from the resin second side surface 23B.

[0024] The number of the one or more second leads 4A is not limited in any way. As shown in FIGS. 1 to 3, in this embodiment, the number of the one or more second leads 4A is plural, and in the illustrated example, five second leads 4A are arranged on each side in the second direction y. The five second leads 4A are located between two first leads 3 in the first direction x. As shown in FIGS. 4, 8 to 12, 16, and 17, the second lead 4A may have a second main surface 41A, a second back surface 42A, a third end surface 43A, a thick portion 45A, and a thin portion 46A.

[0025] The second main surface 41A faces the same side as the resin main surface 21 in the thickness direction z. The second main surface 41A may be covered with the sealing resin 2. The second back surface 42A faces the same side as the resin back surface 22 in the thickness direction z. The second back surface 42A is exposed from the resin back surface 22. The second back surface 42A may be flush with the resin back surface 22. The second back surface 42A is used as a mounting surface when mounting the semiconductor device A1 on a circuit board.

[0026] The third end surface 43A is a surface along the thickness direction z and the first direction x. The third end surface 43A may be connected to the second main surface 41A and the second back surface 42A. The third end surface 43A is exposed from the resin first side surface 23A. The third end surface 43A may be flush with the resin first side surface 23A.

[0027] The thick portion 45A is a portion that includes at least a part of the second main surface 41 A and at least a part of the second back surface 42 A. In this embodiment, the thick portion 45A is located on the outer side of the second lead 4A in the second direction y.

[0028] The thin portion 46A is a portion that includes at least a portion of the second main surface 41A, but does not include the second back surface 42A. The thin portion 46A is covered with the sealing resin 2 from the other side in the thickness direction z. In this embodiment, the thin portion 46A extends inward in the second direction y from the thick portion 45A.

[0029] The semiconductor element 1 may be conductively joined to a portion of the second main surface 41A included in the thick portion 45A via a conductive bonding material 18. The conductive bonding material 18 may be, for example, solder.

[0030] The number of the one or more third leads 5A is not limited in any way. As shown in FIGS. 1 to 3, in this embodiment, the number of the one or more third leads 5A is plural, and in the illustrated example, it is four. The third lead 5A is located between the first lead 3 and the second lead 4A in the first direction x. As shown in FIGS. 4, 9, 10, 16, and 17, the third lead 5A may have a third main surface 51A, a third back surface 52A, and a fourth end surface 53A.

[0031] The third main surface 51A faces the same side as the resin main surface 21 in the thickness direction z. The third main surface 51A may be covered with the sealing resin 2. The third back surface 52A faces the same side as the resin back surface 22 in the thickness direction z. The third back surface 52A is exposed from the resin back surface 22. The third back surface 52A may be flush with the resin back surface 22. The third back surface 52A is used as a mounting surface when mounting the semiconductor device A1 on a circuit board.

[0032] The fourth end surface 53A is a surface along the thickness direction z and the first direction x. The fourth end surface 53A may be connected to the third main surface 51A and the third back surface 52A. The fourth end surface 53A is exposed from the resin first side surface 23A. The fourth end surface 53A may be flush with the resin first side surface 23A.

[0033] The number of the one or more first connecting portions 6A is not limited in any way. As shown in FIGS. 1 to 3, in this embodiment, the number of the one or more first connecting portions 6A is plural, and in the illustrated example, it is four. The first connecting portion 6A is located between the first lead 3 and the third lead 5A in the first direction x and connects the first lead 3 and the third lead 5A. As shown in FIGS. 9, 16, and 17, the first connecting portion 6A may have a fourth main surface 61A and a fourth back surface 62A.

[0034] The fourth main surface 61A faces the same side as the resin main surface 21 in the thickness direction z. The fourth main surface 61A may be covered with the sealing resin 2. The fourth back surface 62A faces the same side as the resin back surface 22 in the thickness direction z. The fourth back surface 62A may be located between the fourth main surface 61A and the resin back surface 22 in the thickness direction z, and may be covered with the sealing resin 2.

[0035] In the illustrated example, the first connecting portion 6A may be spaced apart in the second direction y from the resin first side surface 23A. The first connecting portion 6A may be covered with the sealing resin 2 from the outside in the second direction y.

[0036] The first lead 3, the third lead 5A and the first connecting portion 6A may be separate from the semiconductor element 1 and may be insulated from the semiconductor element 1.

[0037] As shown in FIG. 16 , the size W11 of the third lead 5A in the first direction x may be smaller than the size W01 of the second lead 4A in the first direction x. The distance D11 between the second lead 4A and the third lead 5A in the first direction x may be the same as the distance D01 between adjacent second leads 4A in the first direction x. The distance D21 between the first lead 3 and the third lead 5A in the first direction x may be smaller than the distance D11. The specific sizes of the sizes W01, W11, distance D01, distance D11, and distance D21 are not limited in any way. For example, the size W01 may be 0.15 mm or more and 0.3 mm or less. The size W11 may be 0.1 mm or more and 0.3 mm or less. The distance D01 may be 0.15 mm or more and 0.3 mm or less. The distance D11 may be 0.15 mm or more and 0.6 mm or less. The distance D21 may be equal to or greater than 0.15 mm and equal to or less than 0.6 mm.

[0038] The size L3 of the first connecting portion 6A in the second direction y may be smaller than the size L2 of the third lead 5A in the second direction y. The size L3 may be smaller than the size L1 of the first lead 3 in the second direction y. The size L2 may be larger than the size L1. The specific sizes of L1, L2, and L3 are not limited in any way. As an example of each size, the size L1 may be 0.2 mm or more and 0.4 mm or less. The size L2 may be 0.21 mm or more and 0.41 mm or less. The size L3 may be 0.1 mm or more and 0.3 mm or less.

[0039] There is no limitation on the positional relationship in the thickness direction z among the first main surface 31, the second main surface 41A, the third main surface 51A, and the fourth main surface 61A. In the illustrated example, the first main surface 31, the second main surface 41A, the third main surface 51A, and the fourth main surface 61A may be at the same position in the thickness direction z.

[0040] The number of the one or more fourth leads 4B is not limited in any way. As shown in FIGS. 1 to 3, in this embodiment, the number of the one or more fourth leads 4B is plural, and in the illustrated example, five fourth leads 4B are arranged on each side in the first direction x. The five fourth leads 4B are located between two first leads 3 in the second direction y. As shown in FIGS. 5 to 8 and 13 to 16, the fourth lead 4B may have a fifth main surface 41B, a fifth back surface 42B, a fifth end surface 43B, a thick portion 45B, and a thin portion 46B.

[0041] The fifth main surface 41B faces the same side as the resin main surface 21 in the thickness direction z. The fifth main surface 41B may be covered with the sealing resin 2. The fifth back surface 42B faces the same side as the resin back surface 22 in the thickness direction z. The fifth back surface 42B is exposed from the resin back surface 22. The fifth back surface 42B may be flush with the resin back surface 22. The fifth back surface 42B is used as a mounting surface when mounting the semiconductor device A1 on a circuit board.

[0042] The fifth end surface 43B is a surface along the thickness direction z and the second direction y. The fifth end surface 43B may be connected to the fifth main surface 41B and the fifth back surface 42B. The fifth end surface 43B is exposed from the resin second side surface 23B. The fifth end surface 43B may be flush with the resin second side surface 23B.

[0043] The thick portion 45B is a portion that includes at least a part of the fifth main surface 41 B and at least a part of the fifth back surface 42 B. In the present embodiment, the thick portion 45B is located on the outer side of the fourth lead 4B in the first direction x.

[0044] The thin portion 46B is a portion that includes at least a portion of the fifth main surface 41B, but does not include the fifth back surface 42B. The thin portion 46B is covered with the sealing resin 2 from the other side in the thickness direction z. In this embodiment, the thin portion 46B extends inward in the first direction x from the thick portion 45B.

[0045] The semiconductor element 1 may be conductively bonded to a portion of the fifth main surface 41B included in the thick portion 45B via a conductive bonding material .

[0046] As shown in FIGS. 1 to 3, the island lead 9 may be located at the center of the semiconductor device A1 as viewed in the thickness direction z. As shown in FIGS. 6, 7, 11, 12, and 16, the island lead 9 may have an island main surface 91, an island back surface 92, and two island connecting portions 93. The specific shape of the island lead 9 is not limited in any way and may be various shapes such as a rectangle, a polygon, a circle, or an ellipse as viewed in the thickness direction z. In the illustrated example, the island lead 9 is rectangular. The size of the island lead 9 is not limited in any way and may be smaller than the semiconductor element 1 as viewed in the thickness direction z in the illustrated example.

[0047] The island main surface 91 faces the same side as the resin main surface 21 in the thickness direction z. The island main surface 91 may face the semiconductor element 1. The island main surface 91 may be separated from the semiconductor element 1 via the sealing resin 2. Unlike the illustrated example, the island main surface 91 may be joined to the semiconductor element 1 by solder or the like.

[0048] The island back surface 92 faces the same side as the resin back surface 22 in the thickness direction z. The island back surface 92 is exposed from the resin back surface 22. The island back surface 92 may be flush with the resin back surface 22. The island back surface 92 is used as a mounting surface when the semiconductor device A1 is mounted on a circuit board.

[0049] The two island connecting portions 93 may be connected to the two fourth leads 4B. In the illustrated example, the island connecting portions 93 extend along the first direction x. The island connecting portions 93 may include a part of the island main surface 91 and may not include the island back surface 92. The island connecting portions 93 may be covered with the sealing resin 2 from the other side in the thickness direction z.

[0050] Next, the operation of the semiconductor device A1 will be described.

[0051] 16 and 17, when the semiconductor device A1 is mounted on the circuit board Sb, a conductive bonding material Sd such as solder may be attached to the first back surface 32 and the third back surface 52A. This reduces stress generated in the conductive bonding material Sd attached to the first back surface 32 compared to when solder is attached only to the first back surface 32 and the third back surface 52A is not present. Therefore, according to this embodiment, stress generated in the conductive bonding material Sd used for mounting can be reduced.

[0052] Furthermore, even if a crack occurs in the conductive bonding material Sd attached to the first back surface 32, the presence of the conductive bonding material Sd attached to the third back surface 52A can reduce the likelihood of the crack reaching the conductive bonding material Sd attached to the second back surface 42A. Since the fourth back surface 62A is located on one side of the resin back surface 22 in the thickness direction z and is covered with the sealing resin 2, the conductive bonding material Sd attached to the first back surface 32 and the conductive bonding material Sd attached to the third back surface 52A are separated from each other. This configuration is preferable for suppressing the propagation of a crack.

[0053] Since the first lead 3 is connected to the third lead 5A by the first connecting portion 6A, the first lead 3 is less likely to fall off from the sealing resin 2 than when the first lead 3 is provided alone, thereby improving the operational reliability of the semiconductor device A1.

[0054] Because the size W11 is smaller than the size W01, it is possible to provide the third lead 5A while preventing the size of the semiconductor device A1 from increasing. If the distance D11 is the same as the distance D01, it is possible to more reliably ensure the insulation distance between the second lead 4A and the third lead 5A. Because the distance D21 is smaller than the distance D11, it is possible to provide the first connecting portion 6A while preventing the size of the semiconductor device A1 from increasing.

[0055] Because the size L3 is smaller than the sizes L1 and L2, when the first lead 3, the first connecting portion 6A, and the third lead 5A are viewed as an integrated member in the thickness direction z, the first connecting portion 6A has a constricted shape. This results in a shape in which the sealing resin 2 flows toward the first connecting portion 6A. This is preferable for preventing the integrated member comprising the first lead 3, the first connecting portion 6A, and the third lead 5A from falling off the sealing resin 2.

[0056] 18 to 26 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified example and each embodiment can be appropriately combined with each other as long as no technical contradiction occurs.

[0057] 18 shows a first modified example of the semiconductor device A1. In the semiconductor device A11 of this modified example, the fourth back surface 62A is exposed from the resin back surface 22. The fourth back surface 62A may be flush with the first back surface 32, the third back surface 52A, and the resin back surface 22.

[0058] This modification can reduce stress generated in the conductive bonding material Sd used for mounting. As can be seen from this modification, the specific position of the fourth rear surface 62A in the thickness direction z is not limited in any way. In this modification, the conductive bonding material Sd can be integrally formed across the first rear surface 32, the fourth rear surface 62A, and the third rear surface 52A. Even with this configuration, since the size L3 of the first coupling portion 6A is smaller than the size L1 and the size L2, if a crack occurs on the first rear surface 32, it can be prevented from progressing to the third rear surface 52A.

[0059] 19 shows a second modified example of the semiconductor device A1. In the semiconductor device A12 of this modified example, the fourth main surface 61A is located between the first main surface 31 and the third main surface 51A and the first back surface 32 and the third back surface 52A in the thickness direction z.

[0060] This modification can reduce stress generated in the conductive bonding material Sd used for mounting. As can be understood from this modification, the specific position of the fourth main surface 61A in the thickness direction z is not limited in any way.

[0061] 20 and 21 show a third modified example of the semiconductor device A1. In the semiconductor device A13 of this modified example, the first coupling portion 6A can have a ninth end face 63A.

[0062] The ninth end face 63A is exposed from the first resin side face 23A. The ninth end face 63A may be flush with the first end face 33A and the fourth end face 53A. The size L3 may be smaller than the size L1 and the size L2.

[0063] This modification can reduce stress generated in the conductive bonding material Sd used for mounting. As can be seen from this modification, the first coupling portion 6A may be configured to be exposed from the resin first side surface 23A.

[0064] 22 and 23 show a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device A2 according to this embodiment can include one or more fifth leads 5B and one or more second coupling portions 6B.

[0065] The number of the one or more fifth leads 5B is not limited in any way. In this embodiment, the number of the one or more fifth leads 5B may be a plurality, for example, four. The fifth lead 5B is located between the first lead 3 and the fourth lead 4B in the second direction y. The fifth lead 5B may have a sixth main surface 51B, a sixth back surface 52B, and a sixth end surface 53B.

[0066] The sixth main surface 51B faces the same side as the resin main surface 21 in the thickness direction z. The sixth main surface 51B may be covered with the sealing resin 2. The sixth back surface 52B faces the same side as the resin back surface 22 in the thickness direction z. The sixth back surface 52B is exposed from the resin back surface 22. The sixth back surface 52B may be flush with the resin back surface 22. The sixth back surface 52B is used as a mounting surface when mounting the semiconductor device A2 on a circuit board.

[0067] The sixth edge surface 53B is a surface along the thickness direction z and the second direction y. The sixth edge surface 53B may be connected to the sixth main surface 51B and the sixth back surface 52B. The sixth edge surface 53B is exposed from the resin second side surface 23B. The sixth edge surface 53B may be flush with the resin second side surface 23B.

[0068] The number of the one or more second connecting portions 6B is not limited in any way. In this embodiment, the number of the one or more second connecting portions 6B may be plural, for example, four. The second connecting portion 6B is located between the first lead 3 and the fifth lead 5B in the second direction y and connects the first lead 3 and the fifth lead 5B. The second connecting portion 6B may have a seventh main surface 61B and a seventh back surface 62B.

[0069] The seventh main surface 61B faces the same side as the resin main surface 21 in the thickness direction z. The seventh main surface 61B may be covered with the sealing resin 2. The seventh back surface 62B faces the same side as the resin back surface 22 in the thickness direction z. The seventh back surface 62B may be located between the seventh main surface 61B and the resin back surface 22 in the thickness direction z, and may be covered with the sealing resin 2.

[0070] In the illustrated example, the second connecting portion 6B may be spaced apart from the second resin side surface 23B in the first direction x. The second connecting portion 6B may be covered with the sealing resin 2 from the outside in the first direction x.

[0071] The first lead 3, the fifth lead 5B and the second connecting portion 6B may be spaced apart from the semiconductor element 1 and may be insulated from the semiconductor element 1.

[0072] The size W12 of the fifth lead 5B in the second direction y may be smaller than the size W02 of the fourth lead 4B in the second direction y. The distance D12 in the second direction y between the fourth lead 4B and the fifth lead 5B may be the same as the distance D02 in the second direction y between adjacent fourth leads 4B. The distance D22 in the second direction y between the first lead 3 and the fifth lead 5B may be smaller than the distance D12. The specific sizes of the size W02, size W12, distance D02, distance D12, and distance D22 are not limited in any way. As an example of each size, the size W02 may be 0.15 mm or more and 0.3 mm or less. The size W12 may be 0.1 mm or more and 0.3 mm or less. The distance D02 may be 0.15 mm or more and 0.3 mm or less. The distance D12 may be 0.15 mm or more and 0.6 mm or less. The distance D22 may be equal to or greater than 0.15 mm and equal to or less than 0.6 mm.

[0073] The size L6 of the second connecting portion 6B in the first direction x may be smaller than the size L5 of the fifth lead 5B in the first direction x. The size L6 may be smaller than the size L4 of the first lead 3 in the first direction x. The size L5 may be larger than the size L4. The specific sizes of L4, L5, and L6 are not limited in any way. As an example of each size, the size L4 may be 0.2 mm or more and 0.4 mm or less. The size L5 may be 0.4 mm or more. The size L6 may be 0.1 mm or more and 0.3 mm or less.

[0074] There is no limitation on the positional relationship in the thickness direction z among the first main surface 31, the fifth main surface 41B, the sixth main surface 51B, and the seventh main surface 61B. In the illustrated example, the first main surface 31, the fifth main surface 41B, the sixth main surface 51B, and the seventh main surface 61B may be at the same position in the thickness direction z.

[0075] This embodiment can reduce stress generated in the conductive bonding material Sd used for mounting. By attaching the conductive bonding material Sd to the sixth back surface 52B, another conductive bonding material Sd is positioned on both the first direction x and the second direction y with respect to the conductive bonding material Sd attached to the first back surface 32. This can further reduce stress generated in the conductive bonding material Sd attached to the first back surface 32. Furthermore, even if a crack occurs in the conductive bonding material Sd attached to the first back surface 32, this can prevent the crack from reaching the conductive bonding material Sd attached to the fifth back surface 42B.

[0076] 24 and 25 show a semiconductor device according to a third embodiment of the present disclosure. A semiconductor device A3 of this embodiment includes one or more sixth leads 7A and one or more third coupling portions 8A.

[0077] The number of the one or more sixth leads 7A is not limited in any way. In the present embodiment, the number of the one or more sixth leads 7A may be a plurality, for example, four. The sixth lead 7A is located between the third lead 5A and the second lead 4A in the first direction x. The sixth lead 7A may have an eighth main surface 71A, an eighth back surface 72A, and a seventh end surface 73A.

[0078] The eighth main surface 71A faces the same side as the resin main surface 21 in the thickness direction z. The eighth main surface 71A may be covered with the sealing resin 2. The eighth back surface 72A faces the same side as the resin back surface 22 in the thickness direction z. The eighth back surface 72A is exposed from the resin back surface 22. The eighth back surface 72A may be flush with the resin back surface 22. The eighth back surface 72A is used as a mounting surface when mounting the semiconductor device A3 on a circuit board.

[0079] The seventh end face 73A is a surface along the thickness direction z and the first direction x. The seventh end face 73A may be connected to the eighth main surface 71A and the eighth back surface 72A. The seventh end face 73A is exposed from the resin first side surface 23A. The seventh end face 73A may be flush with the resin first side surface 23A.

[0080] The number of the one or more third connecting portions 8A is not limited in any way. In this embodiment, the number of the one or more third connecting portions 8A may be plural, for example, four. The third connecting portion 8A is located between the third lead 5A and the sixth lead 7A in the first direction x and connects the third lead 5A and the sixth lead 7A. The third connecting portion 8A may have a ninth main surface 81A and a ninth back surface 82A.

[0081] The ninth main surface 81A faces the same side as the resin main surface 21 in the thickness direction z. The ninth main surface 81A may be covered with the sealing resin 2. The ninth back surface 82A faces the same side as the resin back surface 22 in the thickness direction z. The ninth back surface 82A may be located between the ninth main surface 81A and the resin back surface 22 in the thickness direction z, and may be covered with the sealing resin 2.

[0082] In the illustrated example, the third connecting portion 8A may be spaced apart from the resin first side surface 23A in the second direction y. The third connecting portion 8A may be covered with the sealing resin 2 from the outside in the second direction y.

[0083] 24, the size W21 of the sixth lead 7A in the first direction x may be smaller than the size W01. The distance D41 between the second lead 4A and the sixth lead 7A in the first direction x may be the same as the distance D01. The distance D31 between the third lead 5A and the sixth lead 7A in the first direction x may be smaller than the distance D31. The distance D31 may be the same as the distance D21, for example.

[0084] The size in the second direction y of the third connecting portion 8A may be the same as the size in the second direction y of the first connecting portion 6A. The size in the second direction y of the sixth lead 7A may be the same as the size in the second direction y of the third lead 5A.

[0085] This embodiment can reduce stress generated in the conductive bonding material Sd used for mounting. By attaching the conductive bonding material Sd to the eighth back surface 72A, the conductive bonding material Sd attached to the third back surface 52A and the conductive bonding material Sd attached to the eighth back surface 72A are present between the conductive bonding material Sd attached to the first back surface 32 and the conductive bonding material Sd attached to the second back surface 42A. This can further reduce stress generated in the conductive bonding material Sd attached to the first back surface 32. Furthermore, even if a crack occurs in the conductive bonding material Sd attached to the first back surface 32, this can more reliably prevent the crack from reaching the conductive bonding material Sd attached to the second back surface 42A.

[0086] 26 shows a semiconductor device according to a fourth embodiment of the present disclosure. In a semiconductor device A4 of this embodiment, a third lead 5A has a thick portion 55A and a thin portion 56A.

[0087] The thick portion 55A may include at least a part of the third main surface 51A and the third back surface 52A. The thin portion 56A may include at least a part of the third main surface 51A, but may not include the third back surface 52A. The thin portion 56A may be covered with the sealing resin 2 from the other side in the thickness direction z.

[0088] The semiconductor element 1 may be conductively joined to a portion of the third main surface 51A included in the thin portion 56A via a conductive bonding material 18. This allows the first lead 3, the first connecting portion 6A, and the third lead 5A to be conductively connected to the semiconductor element 1.

[0089] This embodiment can reduce stress generated in the conductive bonding material Sd used for mounting. As can be understood from this embodiment, the first lead 3, the first connecting portion 6A, and the third lead 5A may be electrically connected to the semiconductor element 1.

[0090] 27 shows a semiconductor device according to a fifth embodiment of the present disclosure. In a semiconductor device A5 of this embodiment, a semiconductor element 1 is electrically connected to a plurality of second leads 4A and a plurality of fourth leads 4B via a plurality of connecting members 19.

[0091] The connecting member 19 may be, for example, a wire containing a metal such as Au (gold), Ag (silver), Cu (copper), Al (aluminum), or an alloy thereof. The semiconductor element 1 can be bonded to the island main surface 91 by, for example, a bonding material 17.

[0092] This embodiment can reduce stress generated in the conductive bonding material Sd used for mounting. As can be understood from this embodiment, the semiconductor device according to the present disclosure is not limited to a configuration in which the semiconductor element 1 is flip-chip mounted, but includes various mounting configurations.

[0093] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0094] [Appendix 1] A semiconductor element (1), and a sealing resin (2) that covers the semiconductor element (1), The sealing resin (2) has a resin main surface (21) and a resin back surface (22) facing opposite to each other in a thickness direction (z), a resin first side surface (23A) along a first direction (x) intersecting the thickness direction (z), and a resin second side surface (23B) along a second direction (y) intersecting the thickness direction (z) and the first direction (x), a first lead (3) having a first back surface (32) exposed from the resin back surface (22), a first end surface (33A) exposed from the resin first side surface (23A), and a second end surface (33B) exposed from the resin second side surface (23B); a second lead (4A) that is electrically connected to the semiconductor element (1) and has a second back surface (42A) exposed from the resin back surface (22) and a third end surface (43A) exposed from the resin first side surface (23A); a third lead (5A) located between the first lead (3) and the second lead (4A) in the first direction (x), and having a third back surface (52A) exposed from the resin back surface (22) and a fourth end surface (53A) exposed from the resin first side surface (23A); a first connecting portion (6A) connecting the first lead (3) and the third lead (5A); A semiconductor device (A1) comprising: [Appendix 2] The semiconductor device (A1) according to appendix 1, wherein the first lead (3), the third lead (5A), and the first connecting portion (6A) are insulated from the semiconductor element (1). [Appendix 3] The semiconductor device (A4) according to appendix 1, wherein the first lead (3), the third lead (5A), and the first connecting portion (6A) are electrically connected to the semiconductor element (1). [Appendix 4] The first lead (3) has a first main surface (31) facing the same side as the resin main surface (21), The second lead (4A) has a second main surface (41A) facing the same side as the resin main surface (21), The third lead (5A) has a third main surface (51A) facing the same side as the resin main surface (21), The semiconductor device (A1) according to any one of Appendices 1 to 3, wherein the first connecting portion (6A) has a fourth main surface (61A) facing the same side as the resin main surface (21) and a fourth back surface (62A) facing the same side as the resin back surface (22). [Appendix 5] The semiconductor device (A1) according to appendix 4, wherein the first main surface (31), the second main surface (41A), and the third main surface (51A) are at the same position in the thickness direction (z). [Appendix 6] The semiconductor device (A1) described in Appendix 5, wherein the fourth main surface (61A) is at the same position as the first main surface (31), the second main surface (41A), and the third main surface (51A) in the thickness direction (z). [Appendix 7] A semiconductor device (A12) described in Appendix 5, wherein the fourth main surface (61A) is located between the first main surface (31), the second main surface (41A), the third main surface (51A) and the resin back surface (22) in the thickness direction (z). [Appendix 8] The semiconductor device (A1) described in Appendix 6 or 7, wherein the fourth back surface (62A) is located between the fourth main surface (61A) and the resin back surface (22) in the thickness direction (z) and is covered with the sealing resin (2). [Appendix 9] The semiconductor device (A11) according to appendix 6 or 7, wherein the fourth back surface (62A) is exposed from the resin back surface (22). [Appendix 10] 10. The semiconductor device (A1) according to any one of appendixes 1 to 9, wherein the first connecting portion (6A) is spaced apart from the first resin side surface (23A). [Appendix 11] The semiconductor device (A13) according to any one of appendixes 1 to 9, wherein the first connecting portion (6A) is exposed from the first resin side surface (23A). [Appendix 12] A semiconductor device (A1) according to any one of appendices 1 to 11, wherein the size of the third lead (5A) in the first direction (x) is smaller than the size of the second lead (4A) in the first direction (x). [Appendix 13] A semiconductor device (A1) according to any one of Appendices 1 to 12, wherein the distance between the first lead (3) and the third lead (5A) in the first direction (x) is smaller than the distance between the second lead (4A) and the third lead (5A) in the first direction (x). [Appendix 14] a fourth lead (4B) that is electrically connected to the semiconductor element (1) and has a fifth back surface (42B) exposed from the resin back surface (22) and a fifth end surface (43B) exposed from the resin second side surface (23B); a fifth lead (5B) located between the first lead (3) and the fourth lead (4B) in the second direction (y), and having a sixth back surface (52B) exposed from the resin back surface (22) and a sixth end surface (53B) exposed from the resin second side surface (23B); a second connecting portion (6B) connecting the first lead (3) and the fifth lead (5B); The semiconductor device (A2) according to any one of Supplementary Notes 1 to 13, further comprising: [Appendix 15] 15. The semiconductor device (A1) according to any one of appendices 1 to 14, wherein the semiconductor element (1) is flip-chip mounted on the second lead (4A). [Appendix 16] A semiconductor device (A1) according to any one of Appendices 1 to 15, wherein the size of the first connecting portion (6A) in the second direction (y) is smaller than the size of the third lead (5A) in the second direction (y). [Appendix 17] A semiconductor device (A1) described in any one of Appendices 1 to 16, wherein the size of the first connecting portion (6A) in the second direction (y) is smaller than the size of the first lead (3) in the second direction (y). [Appendix 18] a sixth lead (7A) located between the second lead (4A) and the third lead (5A) in the first direction (x); The semiconductor device (A3) according to any one of appendices 1 to 17, further comprising a third connecting portion (8A) connecting the third lead (5A) and the sixth lead (7A). [Appendix 19] A semiconductor device (A3) described in Appendix 18, wherein the sixth lead (7A) has an eighth back surface (72A) exposed from the resin back surface (22) and a seventh end surface (73A) exposed from the resin first side surface (23A). [Appendix 20] A semiconductor device (A3) described in Appendix 19, wherein the size of the third connecting portion (8A) in the second direction (y) is smaller than the size of the third lead (5A) and the sixth lead (7A) in the second direction (y). [Explanation of symbols]

[0095] A1, A11, A12, A13, A2, A3, A4, A5: semiconductor device 1: Semiconductor element 2: Sealing resin 3: First lead 4A: 2nd lead 4B: 4th lead 5A: 3rd lead 5B: 5th lead 6A: 1st connection part 6B: 2nd connection part 7A: 6th lead 8A: 3rd connection part 9: Island Lead 17: Bonding material 18: Conductive bonding material 19: Connection member 21: Resin main surface 22: Resin back 23A: Resin first side 23B: Resin second side 31: First main surface 32: First back side 33A: 1st end surface 33B: 2nd end face 41A: Second main surface 41B: 5th main surface 42A: Second back side 42B: 5th back side 43A: 3rd end surface 43B: 5th end face 45A, 45B, 55A: Thick wall part 46A, 46B, 56A: Thin wall part 51A: 3rd principal surface 51B: 6th main surface 52A: Third back side 52B: 6th back 53A: 4th end surface 53B: 6th end face 61A: Fourth main surface 61B: 7th main surface 62A: 4th back side 62B: 7th back 63A: 9th end face 71A: 8th main surface 72A: No. 8 back side 73A: 7th end face 81A: 9th main surface 82A: 9th back 91: Island main surface 92: Back of island 93: Island connection Sb: Circuit board Sd: Conductive adhesive x :1st direction y: second direction z: thickness direction

Claims

1. A semiconductor element; a sealing resin that covers the semiconductor element, the sealing resin has a resin main surface and a resin back surface facing opposite to each other in a thickness direction, a resin first side surface extending along a first direction intersecting the thickness direction, and a resin second side surface extending along a second direction intersecting the thickness direction and the first direction; a first lead having a first rear surface exposed from the resin rear surface, a first end surface exposed from the resin first side surface, and a second end surface exposed from the resin second side surface; a second lead electrically connected to the semiconductor element and having a second rear surface exposed from the rear surface of the resin and a third end surface exposed from the first side surface of the resin; a third lead located between the first lead and the second lead in the first direction, the third lead having a third rear surface exposed from the resin rear surface and a fourth end surface exposed from the resin first side surface; a first connecting portion connecting the first lead and the third lead; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the first lead, the third lead, and the first coupling portion are insulated from the semiconductor element.

3. The semiconductor device according to claim 1 , wherein the first lead, the third lead, and the first coupling portion are electrically connected to the semiconductor element.

4. the first lead has a first main surface facing the same side as the resin main surface; the second lead has a second main surface facing the same side as the resin main surface; the third lead has a third main surface facing the same side as the resin main surface, The semiconductor device according to claim 1 , wherein said first coupling portion has a fourth main surface facing the same side as said resin main surface and a fourth back surface facing the same side as said resin back surface.

5. The semiconductor device according to claim 4 , wherein said first main surface, said second main surface, and said third main surface are at the same position in said thickness direction.

6. The semiconductor device according to claim 5 , wherein said fourth main surface is at the same position as said first main surface, said second main surface, and said third main surface in said thickness direction.

7. The semiconductor device according to claim 5 , wherein the fourth main surface is located between the first main surface, the second main surface, the third main surface and the resin rear surface in the thickness direction.

8. The semiconductor device according to claim 6 , wherein said fourth rear surface is located between said fourth main surface and said resin rear surface in said thickness direction and is covered with said sealing resin.

9. The semiconductor device according to claim 6 , wherein said fourth rear surface is exposed from said resin rear surface.

10. The semiconductor device according to claim 1 , wherein the first connecting portion is spaced apart from the first side surface of the resin.

11. The semiconductor device according to claim 1 , wherein the first connecting portion is exposed from the first side surface of the resin.

12. 2. The semiconductor device according to claim 1, wherein the size of said third lead in said first direction is smaller than the size of said second lead in said first direction.

13. 2. The semiconductor device according to claim 1, wherein the distance between said first lead and said third lead in said first direction is smaller than the distance between said second lead and said third lead in said first direction.

14. a fourth lead that is electrically connected to the semiconductor element and has a fifth rear surface exposed from the resin rear surface and a fifth end surface exposed from the resin second side surface; a fifth lead located between the first lead and the fourth lead in the second direction, the fifth lead having a sixth rear surface exposed from the resin rear surface and a sixth end surface exposed from the resin second side surface; a second connecting portion connecting the first lead and the fifth lead; The semiconductor device according to claim 1 , further comprising:

15. 15. The semiconductor device according to claim 1, wherein the semiconductor element is flip-chip mounted on the second lead.

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