Semiconductor device and method for manufacturing semiconductor device

Abstract

To improve heat dissipation efficiency.SOLUTION: A semiconductor device comprises an insulating base material, an electronic component, a metal plate, a sealing resin, a wiring layer, and a metal layer. The insulating base material includes an adhesive layer on one surface. The electronic component is fixed to one surface of the insulating base material via the adhesive layer. The metal plate is arranged so as to sandwich the electronic component between the metal plate and one surface of the insulating base material. The sealing resin is filled between the insulating base material and the metal plate and covers the electronic component. The wiring layer is formed on the other surface of the insulating base material and is connected to the electronic component via a veer penetrating the insulating base material and the adhesive layer. The metal layer is made of the same metal material as the wiring layer and covers a surface of the metal plate opposite to a surface covered by the sealing resin.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices have been known in which electronic components, such as semiconductor elements, are disposed on one surface of an insulating substrate via an adhesive layer, and a wiring layer is formed on the other surface of the insulating substrate. In such semiconductor devices, the wiring layer is connected to the electronic components through vias that penetrate the insulating substrate and the adhesive layer. In this way, the wiring layer is connected to the electronic components through the vias, so that heat generated by the electronic components is dissipated to the outside through the wiring layer and the vias.

[0003] Furthermore, in order to increase the number of heat dissipation paths from the electronic components, a metal plate acting as a heat sink is sometimes disposed so as to sandwich the electronic components between the insulating substrate and the electronic components, and the electronic components are joined to this metal plate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-198607 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in a semiconductor device in which electronic components are bonded to a metal plate, there is a problem in that it is difficult to sufficiently dissipate the heat generated by the electronic components. That is, because the metal plate bonded to the electronic components is relatively thin, the heat generated by the electronic components is conducted in the thickness direction of the metal plate and dissipated to the outside. However, compared to the heat conduction in the thickness direction of the metal plate, the heat diffusion in the surface direction of the metal plate (direction perpendicular to the thickness direction) is not sufficient, and the heat dissipation efficiency is not very high. Therefore, when the heat generated by the electronic components is relatively large, it is difficult to sufficiently dissipate the heat from the electronic components.

[0006] The disclosed technology has been made in view of the above, and aims to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve heat dissipation efficiency. [Means for solving the problem]

[0007] In one aspect, the semiconductor device disclosed herein comprises an insulating substrate, an electronic component, a metal plate, a sealing resin, a wiring layer, and a metal layer. The insulating substrate has an adhesive layer on one surface. The electronic component is fixed to one surface of the insulating substrate via the adhesive layer. The metal plate is disposed on one surface of the insulating substrate, sandwiching the electronic component between the insulating substrate and the metal plate. The sealing resin is filled between the insulating substrate and the metal plate and covers the electronic component. The wiring layer is formed on the other surface of the insulating substrate and is connected to the electronic component through vias that penetrate the insulating substrate and the adhesive layer. The metal layer is made of the same metal material as the wiring layer and covers the surface of the metal plate opposite to the surface covered by the sealing resin. [Effects of the Invention]

[0008] According to one aspect of the semiconductor device disclosed in the present application, it is possible to achieve an effect of improving heat dissipation efficiency. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing the configuration of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a flowchart showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a diagram showing a specific example of an insulating substrate. [Figure 4] FIG. 4 is a diagram showing a specific example of the adhesive layer forming step. [Figure 5] FIG. 5 is a diagram showing a specific example of a via hole forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of the electronic component fixing step. [Figure 7]FIG. 7 is a diagram showing a specific example of the seed layer forming step. [Figure 8] FIG. 8 is a diagram showing a specific example of the outer periphery cutting step. [Figure 9] FIG. 9 is a diagram showing a specific example of the joining step. [Figure 10] FIG. 10 is a diagram showing a specific example of the resin sealing step. [Figure 11] FIG. 11 is a diagram showing a specific example of an electrolytic copper plating process. [Figure 12] FIG. 12 is a diagram showing a specific example of the wiring layer forming step. [Figure 13] FIG. 13 is a diagram showing a specific example of the surface treatment layer forming step. [Figure 14] FIG. 14 is a diagram illustrating the mounting of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device and a method for manufacturing a semiconductor device disclosed in the present application will be described in detail with reference to the accompanying drawings. However, the disclosed technology is not limited to these embodiments.

[0011] FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to an embodiment. FIG. 1 shows a schematic cross section of the semiconductor device 100. In the following description, the surface of the semiconductor device 100 that is closest to the mounting substrate when the semiconductor device 100 is mounted on the mounting substrate will be referred to as the "bottom surface," and the surface that is farther from the mounting substrate will be referred to as the "top surface," and the up-down direction will be defined accordingly. However, the semiconductor device 100 may be manufactured and used, for example, upside down, or in any orientation.

[0012] 1 includes an insulating base material 110 and a metal plate 130, and includes a sealing resin 140 that covers an electronic component 120 sandwiched between a lower surface 110b (an example of one surface) of the insulating base material 110 and the metal plate 130. The semiconductor device 100 also includes a wiring layer 150 formed on an upper surface 110a of the insulating base material 110 that is exposed from the sealing resin 140, and an electrolytic copper plating layer 160 (an example of a metal layer) that covers a lower surface 130b of the metal plate 130 that is exposed from the sealing resin 140.

[0013] The insulating substrate 110 is a film-like member and has an adhesive layer 111 on its lower surface 110b. The insulating substrate 110 can be made of an insulating resin such as a polyimide resin, a polyethylene resin, or an epoxy resin. The insulating substrate 110 can have a thickness of, for example, about 25 μm to 200 μm. The adhesive layer 111 can be made of a thermosetting resin such as an epoxy resin, a polyimide resin, or a silicone resin. The adhesive layer 111 can have a thickness of, for example, about 10 μm to 60 μm. The insulating substrate 110 and the adhesive layer 111 have through-holes 112 formed therein, which penetrate the insulating substrate 110 and the adhesive layer 111 in the thickness direction, at positions that do not overlap the wiring layer 150.

[0014] The electronic component 120 is an electronic component in which electronic circuits having various functions are integrated on a semiconductor. The electronic component 120 is fixed to the lower surface 110b of the insulating base material 110 via an adhesive layer 111.

[0015] The electronic component 120 may be a semiconductor element using, for example, silicon (Si) or silicon carbide (SiC). Alternatively, the electronic component 120 may be a semiconductor element using gallium nitride (GaN) or gallium arsenide (GaAs). For example, the electronic component 120 may be a semiconductor element as an active element (for example, a silicon chip such as a CPU), an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, or the like.

[0016] The metal plate 130 is disposed on the lower surface 110b of the insulating base material 110, sandwiching the electronic component 120 between the metal plate 130 and the lower surface 110b of the insulating base material 110. The metal plate 130 is joined to the electronic component 120 fixed to the lower surface 110b of the insulating base material 110. The metal plate 130 absorbs heat generated by the electronic component 120 and dissipates the heat to the outside via the electrolytic copper plating layer 160. The material of the metal plate 130 can be, for example, copper or a copper alloy. The thickness of the metal plate 130 can be, for example, about 100 μm to 2000 μm.

[0017] Metal plate 130 is bonded to electronic component 120 on top surface 130a. Recess 131 may be formed on top surface 130a of metal plate 130 at a position corresponding to electronic component 120. In this case, electronic component 120 is housed in recess 131 and bonded to the bottom surface of recess 131 via conductive bonding material 121 such as solder paste.

[0018] Forming recess 131 in upper surface 130a of metal plate 130 restricts excessive spreading of conductive bonding material 121. Furthermore, electronic component 120 to be fixed to lower surface 110b of insulating base material 110 is housed and bonded in recess 131 of metal plate 130, thereby narrowing the gap between metal plate 130 and insulating base material 110 and reducing the thickness of semiconductor device 100. Note that, as conductive bonding material 121, silver (Ag) paste may be used in addition to solder paste.

[0019] The sealing resin 140 is an insulating resin such as a thermosetting epoxy resin, and is filled between the insulating substrate 110 and the metal plate 130 to cover the electronic component 120. The sealing resin 140 also extends to the side surfaces of the insulating substrate 110 to cover the side surfaces of the insulating substrate 110. Covering the side surfaces of the insulating substrate 110 with the sealing resin 140 suppresses moisture penetration from the side surfaces of the insulating substrate 110, thereby suppressing damage to the electronic component 120 due to moisture absorption by the insulating substrate 110. A portion of the sealing resin 140 also fills through holes 112 that penetrate the insulating substrate 110 and the adhesive layer 111. Filling a portion of the sealing resin 140 into the through holes 112 improves adhesion between the sealing resin 140 and the insulating substrate 110 and the adhesive layer 111 due to an anchor effect.

[0020] The wiring layer 150 is formed on the upper surface 110a of the insulating base material 110. The wiring layer 150 is electrically connected to the electronic component 120 by vias 151 that penetrate the insulating base material 110 and the adhesive layer 111. The wiring layer 150 and the vias 151 are formed by electrolytic copper plating using, for example, copper or a copper alloy. The thickness of the wiring layer 150 (the thickness of the portion excluding the vias 151) can be, for example, about 25 μm to 300 μm.

[0021] The upper surface and part of the side surface of the wiring layer 150 are exposed from the sealing resin 140. By exposing the upper surface and part of the side surface of the wiring layer 150 from the sealing resin 140, heat generated from the electronic component 120 is conducted to the wiring layer 150 through the vias 151, and is efficiently dissipated from the upper surface and part of the side surface of the wiring layer 150.

[0022] A surface treatment layer 171 (an example of a first surface treatment layer) is formed on the upper surface of the wiring layer 150 that is exposed from the sealing resin 140. The surface treatment layer 171 is a plating layer in which a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer are laminated in this order. The surface treatment layer 171 can be formed by, for example, electrolytic plating or electroless plating. As the surface treatment layer 171, a Ni / Au layer or an Au layer may be used instead of the Ni / Pd / Au layer. By forming the surface treatment layer 171 on the upper surface of the wiring layer 150, the wettability of the solder to the upper surface of the wiring layer 150 is improved.

[0023] The electrolytic copper plating layer 160 covers the lower surface 130b of the metal plate 130 that is exposed from the sealing resin 140. The electrolytic copper plating layer 160 is formed using the same metal material as the wiring layer 150 and the vias 151, that is, copper or a copper alloy. The electrolytic copper plating layer 160 is formed, for example, at the same time as the electrolytic copper plating layer that becomes the wiring layer 150 and the vias 151 are formed by electrolytic copper plating. The thickness of the electrolytic copper plating layer 160 can be, for example, approximately 25 μm to 300 μm.

[0024] In the embodiment, the electrolytic copper plating layer 160 covers the lower surface 130b of the metal plate 130, thereby effectively increasing the thickness of the metal plate 130 by the thickness of the electrolytic copper plating layer 160. This promotes heat conduction in the thickness direction of the metal plate 130 as well as heat diffusion in the surface direction of the metal plate 130 (the direction perpendicular to the thickness direction). As a result, the heat dissipation efficiency of the semiconductor device 100 can be improved.

[0025] A surface treatment layer 172 (an example of a second surface treatment layer) is formed on the lower surface of the electrolytic copper plating layer 160. The surface treatment layer 172 is a plating layer made of the same metal material as the surface treatment layer 171, and like the surface treatment layer 171, is a plating layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order. The surface treatment layer 172 is formed simultaneously with the formation of the surface treatment layer 171 by, for example, electrolytic plating or electroless plating. As the surface treatment layer 172, a Ni / Au layer or an Au layer may be used instead of the Ni / Pd / Au layer. Forming the surface treatment layer 172 on the lower surface of the electrolytic copper plating layer 160 improves the wettability of solder to the lower surface of the electrolytic copper plating layer 160.

[0026] Next, a method for manufacturing the semiconductor device 100 configured as described above will be described using a specific example with reference to Fig. 2. Fig. 2 is a flowchart showing the method for manufacturing the semiconductor device 100 according to the embodiment.

[0027] First, insulating base material 110 is prepared (step S101). Specifically, as shown in FIG. 3, a rectangular support frame 210 is fixed to the lower surface 110b of insulating base material 110. FIG. 3 is a diagram showing a specific example of the insulating base material. As the material of insulating base material 110, for example, insulating resin such as polyimide resin, polyethylene resin, or epoxy resin can be used.

[0028] Next, an adhesive layer 111 is formed on the lower surface 110b of the insulating base material 110 (step S102). Specifically, as shown in FIG. 4, for example, the semi-cured adhesive layer 111 is formed on the lower surface 110b of the insulating base material 110 by, for example, spin coating in the area surrounded by the support frame 210. FIG. 4 is a diagram showing a specific example of the adhesive layer formation step. The adhesive layer 111 can be made of a thermosetting resin such as an epoxy resin, a polyimide resin, or a silicone resin.

[0029] Next, via holes are formed in the insulating base material 110 and the adhesive layer 111 (step S103). Specifically, in the region where the wiring layer 150 (see FIG. 1) is to be formed, a via hole 211 is formed, penetrating the insulating base material 110 and the adhesive layer 111 in the thickness direction, as shown in FIG. 5, for example. At this time, a through hole 112 is formed adjacent to the via hole 211, penetrating the insulating base material 110 and the adhesive layer 111 in the thickness direction, at a position that does not overlap with the wiring layer 150. FIG. 5 is a diagram showing a specific example of the via hole forming step. The via hole 211 and the through hole 112 have a tapered shape whose diameter decreases with increasing distance from the upper surface 110a of the insulating base material 110. The via hole 211 and the through hole 112 can be formed by, for example, laser processing or punching.

[0030] Next, the electronic component 120 is fixed to the lower surface 110b of the insulating base material 110 at the position of the via hole 211 via the adhesive layer 111 (step S104). Specifically, for example, as shown in Fig. 6, the electronic component 120 is bonded to the lower surface 110b of the insulating base material 110 via the adhesive layer 111, and electrodes (not shown) of the electronic component 120 are exposed at the bottom of the via hole 211. Once the electronic component 120 is bonded to the lower surface 110b of the insulating base material 110 via the adhesive layer 111, the adhesive layer 111 is thermally cured. Fig. 6 is a diagram showing a specific example of the electronic component fixing step.

[0031] Once the electronic component 120 is fixed, a seed layer is formed on the upper surface 110a of the insulating base material 110 (step S105). Specifically, as shown in FIG. 7, for example, a seed layer 212 is formed to continuously cover the upper surface 110a of the insulating base material 110, the inner surfaces of the via holes 211, and the electrodes (not shown) of the electronic component 120 exposed at the bottoms of the via holes 211. At this time, the seed layer 212 is also formed inside the through holes 112. FIG. 7 is a diagram showing a specific example of the seed layer formation step. The seed layer 212 is formed by, for example, sputtering or electroless plating. The seed layer 212 can be made of, for example, copper (Cu). The seed layer 212 can have a thickness of, for example, about 10 nm to 1000 nm.

[0032] If necessary, an adhesion layer may be formed under the seed layer 212. The adhesion layer is formed by sputtering or electroless plating. Titanium (Ti) or the like can be used as the material for the adhesion layer. By forming the adhesion layer under the seed layer 212, the adhesion of the seed layer 212 to the upper surface 110a of the insulating base material 110 is improved. The thickness of the adhesion layer can be, for example, about 10 nm to 500 nm.

[0033] After the seed layer 212 is formed, the outer peripheries of the insulating base material 110 and the adhesive layer 111 are cut by dicing (step S106). Specifically, the outer peripheries of the insulating base material 110 and the adhesive layer 111 are cut by, for example, a dicer or slicer along a cutting line A (see FIG. 7) that passes inside the support frame 210. As a result, the support frame 210 is separated from the insulating base material 110 and the adhesive layer 111, as shown in FIG. 8, for example. FIG. 8 is a diagram showing a specific example of the outer periphery cutting step.

[0034] Once the support frame 210 is separated, the electronic component 120 fixed to the lower surface 110b of the insulating base material 110 is bonded to the metal plate 130 (step S107). Specifically, first, a metal plate 130 having a recess 131 formed on an upper surface 130a is prepared. Then, the electronic component 120 is accommodated in the recess 131 of the metal plate 130 and bonded to the bottom surface of the recess 131 via a conductive bonding material 121 such as solder paste. As a result, an intermediate structure is formed in which the electronic component 120 is sandwiched between the insulating base material 110 and the metal plate 130, as shown in FIG. 9, for example. FIG. 9 is a diagram showing a specific example of the bonding process.

[0035] The intermediate structure is resin-sealed by, for example, transfer molding (step S108). That is, the intermediate structure is placed in a mold, and uncured sealing resin 140 is poured into the mold. Then, the sealing resin 140 is heated to a predetermined temperature and cured. In addition to transfer molding, other methods of resin sealing may be used, such as compression molding and injection molding. By resin-sealing the intermediate structure, as shown in FIG. 10, the sealing resin 140 fills the space between the insulating substrate 110 and the metal plate 130, thereby sealing the electronic component 120. The sealing resin 140 also extends to the side surfaces of the insulating substrate 110, sealing the side surfaces of the insulating substrate 110. A portion of the sealing resin 140 also fills through holes 112 penetrating the insulating substrate 110 and the adhesive layer 111. FIG. 10 illustrates a specific example of the resin-sealing step.

[0036] Once the intermediate structure is resin-sealed, electrolytic copper plating is applied to the upper surface 110a of the insulating base material 110 exposed from the sealing resin 140 and the lower surface 130b of the metal plate 130 exposed from the sealing resin 140 (step S109). That is, a resist layer is formed on the side surface of the metal plate 130, and power is supplied from the seed layer 212 and the metal plate 130, thereby applying electrolytic copper plating to the entire surface of the intermediate structure. At this time, because the lower surface 130b of the metal plate 130 is not covered with the resist layer, electrolytic copper is deposited not only on the upper surface 110a and via holes 211 of the insulating base material 110, but also on the lower surface 130b of the metal plate 130.

[0037] That is, as shown in Fig. 11, for example, an electrolytic copper-plated layer 150A (an example of a metal layer on the other surface of an insulating substrate) is formed on the upper surface 110a of the insulating substrate 110, and the via holes 211 are filled with electrolytic copper to form vias 151. Simultaneously with the formation of the electrolytic copper-plated layer 150A and the vias 151, an electrolytic copper-plated layer 160 is formed on the lower surface 130b of the metal plate 130. Therefore, the lower surface 130b of the metal plate 130 is covered with the electrolytic copper-plated layer 160. Fig. 11 is a diagram showing a specific example of the electrolytic copper plating process. After the electrolytic copper plating, the resist layer covering the side surface of the metal plate 130 is removed.

[0038] Then, the wiring layer 150 having the desired wiring pattern is formed from the electrolytic copper-plated layer 150A (step S110). The wiring layer 150 is formed from the electrolytic copper-plated layer 150A by, for example, a subtractive method. That is, a resist layer is formed on the upper surface of the electrolytic copper-plated layer 150A to cover the portion to be left as the wiring pattern. Then, the exposed electrolytic copper-plated layer 150A that is not covered by the resist layer is removed by etching, thereby forming the wiring layer 150 having the desired wiring pattern and connecting to the electronic component 120 through the via 151, as shown in FIG. 12, for example. FIG. 12 is a diagram showing a specific example of the wiring layer formation step. The upper surface and part of the side surface of the wiring layer 150 are exposed from the sealing resin 140. After the wiring layer 150 is formed, the resist layer is removed, and the portion of the seed layer 212 not covered by the wiring layer 150 is removed by flash etching using the wiring layer 150 as a mask. The seed layer 212 in contact with the wiring layer 150 and the via 151 and the seed layer 212 located inside the through hole 112 remain even after flash etching, but are not shown in FIG.

[0039] When the seed layer 212 is removed, grooves are formed on the outer peripheries of the metal plate 130 and the electrolytic copper plated layer 160. That is, a resist layer having openings at positions where the grooves are to be formed is formed on the lower surface of the electrolytic copper plated layer 160. Then, the outer peripheries of the metal plate 130 and the electrolytic copper plated layer 160 corresponding to the openings in the resist layer are removed by half etching, thereby forming a pair of grooves 213 on the outer peripheries of the metal plate 130 and the electrolytic copper plated layer 160. Each groove 213 has a tapered shape whose width decreases in the depth direction.

[0040] Next, a surface treatment layer 171 that covers the upper surface of the wiring layer 150 and a surface treatment layer 172 that covers the lower surface of the electrolytic copper plating layer 160 are formed by, for example, electroless plating (step S111).

[0041] Through the steps up to this point, a structure having a structure equivalent to semiconductor device 100 is obtained, for example, as shown in FIG. 13. FIG. 13 is a diagram showing a specific example of the surface treatment layer forming step. Thereafter, the outer periphery of the structure shown in FIG. 13 is cut off by dicing (step S112). Specifically, the outer periphery of electrolytic copper plating layer 160, metal plate 130, and sealing resin 140 is cut along cutting line B along the tapered inner surface of groove 213 using, for example, a dicer or slicer, thereby obtaining semiconductor device 100.

[0042] At this time, the outer peripheries of the electrolytic copper plating layer 160, the metal plate 130, and the sealing resin 140 are cut along the tapered inner side surfaces of the grooves 213, so that the side surfaces of the electrolytic copper plating layer 160, the metal plate 130, and the sealing resin 140 have tapered sides in a side view. Therefore, the metal plate 130 has a tapered shape in which the width of the lower surface 130b exposed from the sealing resin 140 is smaller than the width of the upper surface 130a covered by the sealing resin 140. This reduces the size of the bottom surface of the semiconductor device 100, and when the semiconductor device 100 is mounted on a mounting substrate, the pads of the mounting substrate and the bottom surface of the semiconductor device 100 can be aligned with high precision.

[0043] The outer peripheral cutting step of step S112 may be omitted if necessary, in which case the side surfaces of the electrolytic copper plating layer 160, the metal plate 130, and the sealing resin 140 will be linear in side view.

[0044] The semiconductor device 100 obtained by cutting can be mounted on a mounting board. Specifically, the semiconductor device 100 can be mounted on a mounting board using the metal plate 130 and the electrolytic copper plating layer 160 as terminals. Figure 14 is a diagram illustrating the mounting of the semiconductor device 100.

[0045] 14, pads 310 are formed on the wiring layer on the upper surface of mounting substrate 300, and pads 310 are exposed from openings in solder resist layer 320. When mounting semiconductor device 100 on mounting substrate 300, electrolytic copper plating layer 160 on the bottom surface of semiconductor device 100 is aligned with pads 310 on mounting substrate 300. Then, electrolytic copper plating layer 160 and pads 310 are joined by solder 330. At this time, because metal plate 130 has a tapered shape, the size of electrolytic copper plating layer 160 below metal plate 130 is reduced, allowing for accurate alignment of electrolytic copper plating layer 160 and pads 310.

[0046] 14 , heat generated by electronic component 120 is conducted to electrolytic copper-plated layer 160 via metal plate 130, and is then dissipated from electrolytic copper-plated layer 160 via solder 330 and pad 310. That is, in addition to the conduction of heat in the thickness direction of metal plate 130, electrolytic copper-plated layer 160 can promote the diffusion of heat in the surface direction of metal plate 130 (the direction perpendicular to the thickness direction), and as a result, the heat dissipation efficiency of semiconductor device 100 can be improved.

[0047] As described above, the semiconductor device according to the embodiment (for example, semiconductor device 100) includes an insulating substrate (for example, insulating substrate 110), an electronic component (for example, electronic component 120), a metal plate (for example, metal plate 130), a sealing resin (for example, sealing resin 140), a wiring layer (for example, wiring layer 150), and a metal layer (for example, electrolytic copper plating layer 160). The insulating substrate includes an adhesive layer (for example, adhesive layer 111) on one surface (for example, bottom surface 110b). The electronic component is fixed to one surface of the insulating substrate via the adhesive layer. The metal plate is disposed on one surface of the insulating substrate, sandwiching the electronic component between the metal plate and the one surface of the insulating substrate. The sealing resin is filled between the insulating substrate and the metal plate and covers the electronic component. The wiring layer is formed on the other surface of the insulating substrate (for example, top surface 110a) and is connected to the electronic component through a via (for example, via 151) that penetrates the insulating substrate and the adhesive layer. The metal layer is made of the same metal material as the wiring layer and covers the surface (for example, the lower surface 130b) opposite to the surface (for example, the upper surface 130a) of the metal plate that is covered with the sealing resin, thereby improving heat dissipation efficiency. [Explanation of symbols]

[0048] 100 Semiconductor device 110 Insulating substrate 110a top surface 110b Bottom side 111 Adhesive layer 112 Through hole 120 Electronic Components 121 Conductive bonding material 130 Metal plate 130a top side 130b Bottom side 131 recess 140 Sealing resin 150 wiring layer 151 Beer 160 Electrolytic copper plating layer 171, 172 Surface treatment layer

Claims

1. an insulating substrate having an adhesive layer on one surface; an electronic component fixed to one surface of the insulating substrate via the adhesive layer; a metal plate disposed on one surface of the insulating base material, with the electronic component sandwiched between the metal plate and the one surface of the insulating base material; a sealing resin filled between the insulating base material and the metal plate to cover the electronic components; a wiring layer formed on the other surface of the insulating base material and connected to the electronic component through a via that penetrates the insulating base material and the adhesive layer; a metal layer made of the same metal material as the wiring layer and the vias, covering the surface of the metal plate opposite to the surface covered by the sealing resin; A semiconductor device comprising:

2. The wiring layer is A portion of the top surface and side surfaces is exposed from the sealing resin.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. a first surface treatment layer that covers the upper surface of the wiring layer that is exposed from the sealing resin; a second surface treatment layer made of the same metal material as the first surface treatment layer and covering the surface of the metal layer opposite to the surface that contacts the metal plate; 3. The semiconductor device according to claim 2, further comprising:

4. The insulating substrate is a side surface connected to the one surface and the other surface and covered with the sealing resin; 2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

5. The metal plate is The surface has a tapered shape in which the width of the surface opposite to the surface covered with the sealing resin is smaller than the width of the surface covered with the sealing resin.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

6. The metal plate is a recessed portion is formed in a position corresponding to the electronic component on the surface covered with the sealing resin; The electronic component is The recess is accommodated in the recess and bonded to the bottom surface of the recess.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

7. The insulating substrate and the adhesive layer are a through-hole penetrating the insulating base material and the adhesive layer in a thickness direction at a position not overlapping the wiring layer; A portion of the sealing resin is The through-hole is filled 2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

8. An adhesive layer is formed on one surface of the insulating substrate; forming a via hole penetrating the insulating base material and the adhesive layer; an electronic component is fixed to one surface of the insulating substrate at the position of the via hole via the adhesive layer; a metal plate is disposed so as to sandwich the electronic component between the metal plate and one surface of the insulating base material, and the electronic component is bonded to the metal plate; a sealing resin is filled between the insulating base material and the metal plate to cover the electronic component; forming a metal layer on the other surface of the insulating base material by plating a metal material, and forming a via hole in the via hole to connect the metal layer to the electronic component; simultaneously with the formation of the metal layer and the via, a metal layer made of the metal material is formed to cover a surface of the metal plate opposite to a surface that is in contact with the sealing resin; A wiring layer is formed by etching from the metal layer on the other surface of the insulating base material, the wiring layer being connected to the electronic component through the via.

1. A method for manufacturing a semiconductor device, comprising the steps of:

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