Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing peeling of a sealing resin due to thermal load.SOLUTION: A semiconductor device A10 comprises a semiconductor chip 10; a die pad 20 (support part) including a support surface 2010 facing the semiconductor chip 10 in a thickness direction z of the semiconductor chip 10 and supporting the semiconductor chip 10; a bonding layer 30 interposed between the semiconductor chip 10 and the support surface 2010 and bonding the semiconductor chip 10 to the die pad 20; and a sealing member 50 covering the semiconductor chip 10 and the bonding layer 30. The sealing member 50 includes a covering part 50A positioned on the support surface 2010 and a sealing part 50B formed on the covering part 50A. The covering part 50A covers four corners (four corner parts 30b) of the bonding layer 30 when viewed in the thickness direction z. A plastic strain region of the covering part 50A is larger than a plastic strain region of the sealing part 50B.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a conventional semiconductor device. The semiconductor device described in Patent Document 1 includes a semiconductor element, a lead frame, solder, wire, and a sealing resin. In this semiconductor device, the semiconductor element is, for example, a diode chip or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) chip. The lead frame mounts the semiconductor element and is electrically connected to the semiconductor element via solder and wire. The solder and wire are conductive members for electrically connecting the lead frame and the semiconductor element. The solder is interposed between the semiconductor element and the lead frame, connecting them electrically. The wire is joined to the semiconductor element and the lead frame, connecting them electrically. The sealing resin covers a portion of the lead frame, the semiconductor element, the solder, and the wire. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-5165

[0004] [overview] A semiconductor device is subjected to thermal loads, for example, due to reflow when mounted on a circuit board of an electronic device or due to heat generated by a semiconductor element during operation. This thermal load causes thermal stress to concentrate at the joint between the solder and the lead frame. This concentration of thermal stress can cause peeling of the sealing resin at the interface between the joint and the sealing resin. If a thermal load is then applied again when the sealing resin has peeled off, cracks may occur, for example, in the solder serving as a conductive member. These can cause malfunctions of the semiconductor device.

[0005] The present disclosure has been made in view of the above circumstances, and has an object to provide a semiconductor device that can suppress peeling of the sealing resin due to thermal load.

[0006] The semiconductor device provided by the present disclosure comprises a semiconductor chip, a support portion having a support surface facing the semiconductor chip in the thickness direction of the semiconductor chip and supporting the semiconductor chip, a bonding layer interposed between the semiconductor chip and the support surface and bonding the semiconductor chip to the support portion, and a sealing member covering the semiconductor chip and the bonding layer, the sealing member including a covering portion located on the support surface and a sealing portion formed on the covering portion, the covering portion covering four corners of the bonding layer when viewed in the thickness direction, and the plastic strain range of the covering portion being larger than the plastic strain range of the sealing portion.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a plan view of FIG. 2, in which the sealing portion of the sealing member is indicated by an imaginary line (two-dot chain line). [Figure 4] FIG. 4 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a front view showing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9]FIG. 9 is a partially enlarged view of a part of FIG. [Figure 10] FIG. 10 is a partially enlarged view of a part of FIG. [Figure 11] FIG. 11 shows a characteristic curve showing the relationship between stress and strain for a certain material. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to a modified example of the first embodiment, and corresponds to the cross section of FIG. [Figure 13] FIG. 13 is a plan view showing the semiconductor device according to the second embodiment, in which the sealing portion of the sealing member is indicated by an imaginary line (two-dot chain line). [Figure 14] FIG. 14 is a partially enlarged view of a part of FIG. [Figure 15] FIG. 15 is an enlarged cross-sectional view of a main part showing the semiconductor device according to the second embodiment, and corresponds to the cross section of FIG. [Figure 16] FIG. 16 is a plan view showing a semiconductor device according to a first modified example of the second embodiment, in which the sealing portion of the sealing member is indicated by an imaginary line (two-dot chain line). [Figure 17] FIG. 17 is a partially enlarged view of a part of FIG. [Figure 18] FIG. 18 is an enlarged cross-sectional view of a main part showing a semiconductor device according to a first modified example of the second embodiment, and corresponds to the cross section of FIG. [Figure 19] FIG. 19 is an enlarged cross-sectional view of a main part showing a semiconductor device according to another configuration example of the first modified example of the second embodiment, and corresponds to the cross section of FIG. [Figure 20] FIG. 20 is an enlarged plan view of a main part showing a semiconductor device according to a second modification of the second embodiment, and corresponds to FIG. [Figure 21] FIG. 21 is an enlarged cross-sectional view of a main part showing a semiconductor device according to a second modification of the second embodiment, and corresponds to the cross section of FIG. [Figure 22] FIG. 22 is a plan view showing the semiconductor device according to the third embodiment, in which the sealing portion of the sealing member is indicated by an imaginary line (two-dot chain line). [Figure 23]FIG. 23 is a partially enlarged view of a part of FIG. [Figure 24] 24 is an enlarged cross-sectional view of a main part taken along line XXIV-XXIV in FIG. [Figure 25] FIG. 25 is a cross-sectional view showing a semiconductor device according to another configuration example of the present disclosure.

[0009] [Detailed explanation] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant explanations will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an object) B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an object) B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an object) B" includes "a certain object A is in contact with a certain object B and is located on (an object) B" and "a certain object A is located on (an object) B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "object A overlaps object B when viewed from a certain direction" includes "object A overlaps the entirety of object B" and "object A overlaps part of object B." Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is primarily made of material C." Furthermore, unless otherwise specified, "a certain surface A faces in direction B (one side or the other)" does not necessarily mean that surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted relative to direction B. Furthermore, unless otherwise specified, "a certain surface A is perpendicular to surface B" does not necessarily mean that surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted relative to surface B.

[0011] First Embodiment 1 to 10 show a semiconductor device A10 according to a first embodiment. The semiconductor device A10 includes a semiconductor chip 10, a die pad 20, leads 21, 22, and 23, a bonding layer 30, two connecting members 41 and 42, and a sealing member 50. In an example different from this configuration, the semiconductor device A10 may include two or more semiconductor chips 10, four or more leads, or three or more connecting members. In the illustrated example, the package format of the semiconductor device A10 is a TO (Transistor Outline) type. The package format of the semiconductor device A10 is not limited to the TO type, and various package formats can be applied, such as, for example, SOP (Small Outline Package) type, SOJ (Small Outline J-leaded package) type, SON (Small Outline Non-leaded package) type, QFP (Quad Flat Package) type, QFJ (Quad Flat J-leaded package) type, QFN (Quad Flat Non-leaded package) type, and BGA (Ball Grid Array) type. The semiconductor device A10 is used in a power conversion circuit such as an inverter, but the use example of the semiconductor device A10 is not limited to a power conversion circuit.

[0012] For ease of explanation, reference will be made to the thickness direction z, first direction x, and second direction y, which are perpendicular to each other. The thickness direction z corresponds to the thickness direction of the semiconductor device A10. The thickness direction of the semiconductor device A10 coincides with the thickness direction of the semiconductor chip 10. Furthermore, "plan view" refers to the view in the thickness direction z. The first direction x is perpendicular to the thickness direction z. The second direction y is perpendicular to the thickness direction z and the first direction x. Note that one side of the thickness direction z is sometimes referred to as "upper," and the other side of the thickness direction z is sometimes referred to as "lower." Note that terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0013] The semiconductor chip 10 is a component that is the core of the semiconductor device A10. The semiconductor chip 10 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Alternatively, the semiconductor chip 10 may be a field-effect transistor, such as a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor), or a bipolar transistor, such as an IGBT (Insulated Gate Bipolar Transistor). Alternatively, the semiconductor chip 10 may be a discrete semiconductor, such as a diode, a transformer, an inductor, or a resistor, instead of a transistor, or an integrated circuit (IC) such as an LSI (Large Scale Integration). In the description of the semiconductor device A10, the semiconductor chip 10 is an n-channel, vertically structured MOSFET.

[0014] The semiconductor chips 10 include a compound semiconductor substrate. The composition of this compound semiconductor substrate includes, for example, silicon (Si), a wide bandgap semiconductor with a wider bandgap than Si, or an ultra-wide bandgap semiconductor with an even wider bandgap than the wide bandgap semiconductor. Wide bandgap semiconductors include, but are not limited to, silicon carbide (SiC) and gallium nitride (GaN). Ultra-wide bandgap semiconductors include, but are not limited to, gallium oxide (Ga2O3), diamond, and aluminum nitride (AlN).

[0015] As shown in FIGS. 9 and 10 , the semiconductor chip 10 has a chip main surface 10a, a chip back surface 10b, and multiple chip side surfaces 10c. The chip main surface 10a and the chip back surface 10b are spaced apart in the thickness direction z. The chip main surface 10a faces upward in the thickness direction z, and the chip back surface 10b faces downward in the thickness direction z. The chip back surface 10b faces the die pad 20. In the illustrated example, the semiconductor chip 10 is rectangular in plan view. In this example, the chip main surface 10a and the chip back surface 10b are each rectangular in plan view. Note that the planar shape of the semiconductor chip 10 is not limited to a rectangle. Each of the multiple chip side surfaces 10c is located between the chip main surface 10a and the chip back surface 10b in the thickness direction z and is connected to them. Each of the multiple chip side surfaces 10c faces in a direction perpendicular to the thickness direction z. In an example where the semiconductor chip 10 has a rectangular shape in a plan view, the semiconductor chip 10 has four chip side surfaces 10c. Two of the four chip side surfaces 10c are spaced apart in a first direction x and face opposite each other in the first direction x, and the other two of the four chip side surfaces 10c are spaced apart in a second direction y and face opposite each other in the second direction y.

[0016] 3 and 9, the semiconductor chip 10 has a back surface electrode 11 and two main surface electrodes 12 and 13. The back surface electrode 11 is disposed on the chip back surface 10b and exposed at the chip back surface 10b. The two main surface electrodes 12 and 13 are disposed on the chip main surface 10a and exposed at the chip main surface 10a. As shown in FIG. 9, the back surface electrode 11 faces the die pad 20 (a support surface 2010 described below) in the thickness direction z. In the illustrated example, the area occupied by the main surface electrode 12 on the chip main surface 10a is larger than the area occupied by the main surface electrode 13 on the chip main surface 10a, but this is not limiting.

[0017] The semiconductor chip 10 switches between an ON state and an OFF state in response to a drive signal (e.g., a gate voltage) input to the principal surface electrode 13. In the ON state, the back surface electrode 11 and the principal surface electrode 12 are electrically connected, and in the OFF state, the back surface electrode 11 and the principal surface electrode 12 are electrically disconnected. In the semiconductor chip 10, a current flows from the back surface electrode 11 to the principal surface electrode 12 in response to a drive signal input to the principal surface electrode 13. In an example in which the semiconductor chip 10 is a MOSFET, the back surface electrode 11 is a drain electrode, the principal surface electrode 12 is a source electrode, and the principal surface electrode 13 is a gate electrode. The semiconductor chip 10 may, for example, have an additional principal surface electrode on the chip principal surface 10a. This additional principal surface electrode has the same potential as the principal surface electrode 12 and is, for example, a source sense electrode.

[0018] As shown in FIGS. 3 and 6 to 8, the semiconductor chip 10 is mounted on the die pad 20. In the semiconductor device A10, the die pad 20 is a support that supports the semiconductor chip 10. The die pad 20, together with the leads 21, 22, and 23, are obtained from the same lead frame. The lead frame is made of copper (Cu) or a copper alloy. Therefore, the composition of each of the die pad 20, the leads 21, the leads 22, and the leads 23 includes copper.

[0019] As shown in FIGS. 6 to 8 , the die pad 20 has a main surface 201 and a back surface 202. The main surface 201 faces the side facing the semiconductor chip 10 in the thickness direction z. The main surface 201 is covered with a sealing member 50 except for a portion thereof. The back surface 202 faces the opposite side to the main surface 201 in the thickness direction z. The back surface 202 is plated with, for example, tin (Sn). The back surface 202 is exposed from the sealing member 50.

[0020] As shown in FIGS. 3, 4, and 6 to 8, the die pad 20 has a first portion 20A and a second portion 20B connected to the first portion 20A. When viewed in the thickness direction z, the second portion 20B is located on one side of the first portion 20A in the first direction x (the side opposite to the leads 21 to 23). The second portion 20B is covered with a sealing member 50. The first portion 20A includes a back surface 202. The second portion 20B is provided with a through portion 203. The through portion 203 penetrates the second portion 20B in the thickness direction z. The through portion 203 has a circular shape when viewed in the thickness direction z. In the semiconductor device A10, a first dimension t1 in the thickness direction z of the first portion 20A is greater than a second dimension t2 in the thickness direction z of the second portion 20B. In the semiconductor device A10, the dimension of the second portion 20B in the first direction x is larger than the dimension of the back surface 202 in the first direction x.

[0021] The main surface 201 has a support surface 2010. The support surface 2010 faces the semiconductor chip 10 in the thickness direction z. The semiconductor chip 10 is mounted on the support surface 2010. The support surface 2010 corresponds to the main surface 201 of the first part 20A. As shown in FIGS. 9 and 10 , the support surface 2010 has a contact region 2011 that contacts the bonding layer 30 and a non-contact region 2012 that does not contact the bonding layer 30. In a plan view, the non-contact region 2012 surrounds the abutment region 2011.

[0022] 3 and 8, the lead 21 includes a portion extending in the first direction x and is connected to the die pad 20. As a result, the lead 21 is electrically connected to the back electrode 11 of the semiconductor chip 10. Therefore, the lead 21 corresponds to the drain terminal of the semiconductor device A10. The lead 21 is located on the opposite side of the first portion 20A from the second portion 20B of the die pad 20 in the first direction x.

[0023] 3 and 8, the lead 21 includes a covering portion 211 and an exposed portion 212. The covering portion 211 is connected to the first portion 20A of the die pad 20 and is covered by the sealing member 50. When viewed in the second direction y, the covering portion 211 is bent. The exposed portion 212 is connected to the covering portion 211 and is exposed from the sealing member 50. The exposed portion 212 protrudes from the sealing member 50 on the side opposite to the side on which the die pad 20 is located in the first direction x. The surface of the exposed portion 212 is plated with, for example, tin.

[0024] As shown in FIGS. 3 and 6, the lead 22 is located away from the die pad 20. The lead 22 extends in the first direction x. In the semiconductor device A10, the lead 22 is a wiring portion located away from the die pad 20. The lead 22 is electrically connected to the main surface electrode 12 of the semiconductor chip 10 via the connection member 41. Therefore, the lead 22 corresponds to the source terminal of the semiconductor device A10. The lead 22 is located adjacent to the lead 21 in the second direction y.

[0025] 3 and 6, the lead 22 has a covering portion 221, an exposed portion 222, and a bonding surface 223. The covering portion 221 is covered by the sealing member 50. The exposed portion 222 is connected to the covering portion 221 and is exposed from the sealing member 50. The exposed portion 222 protrudes from the sealing member 50 on the side opposite to the side on which the die pad 20 is located in the first direction x. The surface of the exposed portion 222 is plated with, for example, tin. The bonding surface 223 faces the same side as the main surface 201 (support surface 2010) of the die pad 20 in the thickness direction z. The bonding surface 223 is included as part of the covering portion 221. The bonding surface 223 is located on the side on which the semiconductor chip 10 is located relative to the main surface 201 (support surface 2010) in the thickness direction z.

[0026] As shown in FIGS. 3 and 7, the lead 23 is located away from the die pad 20. The lead 23 extends in the first direction x. In the semiconductor device A10, the lead 23 is a wiring portion that is located away from the die pad 20. The lead 23 is electrically connected to the main surface electrode 13 of the semiconductor chip 10. Therefore, the lead 23 corresponds to the gate terminal of the semiconductor device A10. The lead 23 is located on the opposite side of the lead 22 from the lead 21 in the second direction y.

[0027] As shown in FIGS. 3 and 7 , the lead 23 has a covering portion 231, an exposed portion 232, and a bonding surface 233. The covering portion 231 is covered by the sealing member 50. The exposed portion 232 is connected to the covering portion 231 and is exposed from the sealing member 50. The exposed portion 232 protrudes from the sealing member 50 on the side opposite to the side on which the die pad 20 is located in the first direction x. The surface of the exposed portion 232 is plated with, for example, tin. The bonding surface 233 faces the same side as the main surface 201 (support surface 2010) of the die pad 20 in the thickness direction z. The bonding surface 233 is included as part of the covering portion 231. In the thickness direction z, the position of the bonding surface 233 is the same as the position of the bonding surface 223 of the lead 22.

[0028] 3, the leads 21, 22, and 23 are arranged along the second direction y. As shown in Fig. 5, the exposed portion 212 of the lead 21, the exposed portion 222 of the lead 22, and the exposed portion 232 of the lead 23 all have the same height h from the bottom surface 52 of the sealing member 50, which will be described later.

[0029] As shown in FIGS. 6 to 10 , the bonding layer 30 bonds the die pad 20 and the semiconductor chip 10. As shown in FIG. 9 , the back electrode 11 of the semiconductor chip 10 is conductively bonded to the support surface 2010 of the die pad 20 via the bonding layer 30. This allows electrical continuity between the back electrode 11 and the die pad 20. The bonding layer 30 is, for example, solder. Alternatively, the bonding layer 30 may be a sintered metal. Alternatively, the bonding layer 30 may be a metal layer formed when the semiconductor chip 10 and the die pad 20 are bonded by solid-state diffusion bonding using an insert metal. In the illustrated example, the entire bonding layer 30 is located between the semiconductor chip 10 and the die pad 20 in the thickness direction z. Unlike this example, a portion of the bonding layer 30 may be configured to cover each chip side surface 10c of the semiconductor chip 10.

[0030] As shown in FIG. 9 , the bonding layer 30 has a first surface 31, a second surface 32, and a third surface 33. The first surface 31 faces upward in the thickness direction z and faces the semiconductor chip 10. The first surface 31 contacts the semiconductor chip 10. The second surface 32 faces downward in the thickness direction z and faces the die pad 20. The second surface 32 contacts the die pad 20. In a plan view, the area of ​​the second surface 32 is larger than the area of ​​the first surface 31. The third surface 33 faces upward in the thickness direction z and connects to the first surface 31 and the second surface 32. The third surface 33 contacts the sealing member 50 (in the semiconductor device A10, the covering portion 50A described below). In this embodiment, the third surface 33 is inclined with respect to each of the first surface 31 and the second surface 32. The third surface 33 is inclined from the side connected to the first surface 31 toward the side connected to the second surface 32 so that the area of ​​the cross section perpendicular to the thickness direction z increases.

[0031] 10, the bonding layer 30 has, for example, a rectangular shape in a plan view. In this example, the peripheral edge 30a of the bonding layer 30 has a shape in a plan view. Furthermore, in a plan view, the bonding layer 30 has four corners 30b. The four corners 30b correspond to the four corners of the bonding layer 30 in a plan view. Each of the four corners 30b may be curved in a plan view.

[0032] The two connection members 41, 42 each electrically connect two parts spaced apart from each other. In this embodiment, the two connection members 41, 42 are each bonding wires. Unlike this example, the two connection members 41, 42 may each be a metal plate (metal clip) or a ribbon-type bonding wire (ribbon wire). The composition of each of the two connection members 41, 42 includes gold (Au). The composition of each of the two connection members 41, 42 may also include copper or aluminum. In the illustrated example, the thickness (wire diameter) of the connection member 41 is larger than the thickness (wire diameter) of the connection member 42.

[0033] As shown in FIGS. 3 and 6 , the connection member 41 is conductively bonded to the principal surface electrode 12 of the semiconductor chip 10 and the bonding surface 223 of the lead 22. This electrically connects the lead 22 to the principal surface electrode 12. As shown in FIG. 6 , the connection member 41 has two bonding portions 411 and 412 and an intermediate portion 413. The bonding portion 411 is located at one end of the connection member 41 and is bonded to the principal surface electrode 12. The bonding portion 412 is located at the other end of the connection member 41 and is bonded to the bonding surface 223. The intermediate portion 413 is interposed between the two bonding portions 411 and 412 and is connected to them. In an example in which the connection member 41 is a bonding wire, the intermediate portion 413 is a loop portion.

[0034] 3 and 7, the connection member 42 is electrically connected to the principal surface electrode 13 of the semiconductor chip 10 and the bonding surface 233 of the lead 23. This electrically connects the lead 23 to the principal surface electrode 13. As shown in FIG. 7, the connection member 42 has two bonding portions 421 and 422 and an intermediate portion 423. The bonding portion 421 is located at one end of the connection member 42 and is bonded to the principal surface electrode 13. The bonding portion 422 is located at the other end of the connection member 42 and is bonded to the bonding surface 233. The intermediate portion 423 is interposed between the two bonding portions 421 and 422 and is connected to the two bonding portions 421 and 422. In an example in which the connection member 42 is a bonding wire, the intermediate portion 423 is a loop portion.

[0035] As shown in FIGS. 3, 6, and 7, the sealing member 50 covers the semiconductor chip 10 and the bonding layer 30. As shown in FIGS. 6 to 8, the sealing member 50 covers a portion of each of the die pad 20, the leads 21, the leads 22, and the leads 23. The sealing member 50 covers the two connection members 41 and 42. The sealing member 50 has electrical insulation properties. The sealing member 50 has a top surface 51, a bottom surface 52, two side surfaces 53, and two side surfaces 54.

[0036] The top surface 51 and the bottom surface 52 are spaced apart in the thickness direction z. As shown in FIGS. 6 to 8, the top surface 51 faces the same side as the support surface 2010 of the die pad 20 in the thickness direction z. As shown in FIGS. 6 to 8, the bottom surface 52 faces the opposite side to the top surface 51 in the thickness direction z. The back surface 202 of the first portion 20A of the die pad 20 is exposed from the bottom surface 52.

[0037] As shown in FIGS. 2 and 4, the two side surfaces 53 are spaced apart from each other in the first direction x. Each of the two side surfaces 53 is connected to the top surface 51 and the bottom surface 52. The exposed portion 212 of the lead 21, the exposed portion 222 of the lead 22, and the exposed portion 232 of the lead 23 each protrude from one of the two side surfaces 53 in the first direction x. As shown in FIGS. 2 and 4, the two side surfaces 54 are spaced apart from each other in the second direction y. Each of the two side surfaces 54 is connected to the top surface 51 and the bottom surface 52.

[0038] 1 and 2, the sealing member 50 has two openings 55. As shown in FIG. 2, the two openings 55 are spaced apart from each other in the second direction y. Each of the two openings 55 is recessed inward into the sealing member 50 from both the top surface 51 and one of the two side surfaces 54. A portion of the main surface 201 of the second portion 20B of the die pad 20 is exposed from each of the two openings 55.

[0039] 2, 4, and 8, the sealing member 50 has an attachment portion 56. The attachment portion 56 penetrates in the thickness direction z from the top surface 51 to the bottom surface 52. As shown in FIG. 3, in plan view, the attachment portion 56 is surrounded by the through portion 203 of the second part 20B of the die pad 20. That is, in plan view, the attachment portion 56 is contained within the through portion 203.

[0040] 2 and 8, sealing member 50 has an inner circumferential surface 561 that is connected to top surface 51 and bottom surface 52 and that defines mounting portion 56. Mounting portion 56 includes a first hole edge 56A that is the boundary between inner circumferential surface 561 and top surface 51, and a second hole edge 56B that is the boundary between inner circumferential surface 561 and bottom surface 52. As shown in FIGS. 2 and 4, in a plan view, first hole edge 56A surrounds second hole edge 56B.

[0041] 6 to 8, a second dimension t2 in the thickness direction z of the second portion 20B of the die pad 20 and a third dimension t3 in the thickness direction z of the portion of the sealing member 50 extending from the bottom surface 52 to the second portion 20B are different from each other. The second dimension t2 is greater than the third dimension t3.

[0042] As shown in FIGS. 6 to 9, the sealing member 50 includes a covering portion 50A and a sealing portion 50B. The covering portion 50A and the sealing portion 50B each include, for example, an insulating resin. The insulating resin is not limited to, but may be, for example, an epoxy resin. Furthermore, the insulating resin (e.g., epoxy resin) of the sealing portion 50B contains a silica filler, while the insulating resin (e.g., epoxy resin) of the covering portion 50A does not contain a silica filler. For example, the silica filler content of the sealing portion 50B is 80% or more and 90% or less. The covering portion 50A may be made of rubber instead of a silica filler-free resin.

[0043] The covering portion 50A is located above the support surface 2010 in the thickness direction z. In this embodiment, the covering portion 50A covers the non-contact region 2012 of the support surface 2010, the third surface 33 of the bonding layer 30, and the semiconductor chip 10. In particular, the covering portion 50A covers the entire main surface 201 of the second portion 20B. Note that, unless otherwise specified, "covering the entire surface" in this disclosure is not limited to strictly covering the entire surface, and may include portions that are not completely covered due to manufacturing precision, etc. For example, in the example shown in FIGS. 3 and 7, a portion of the main surface 201 slightly inward from the periphery of the opening 55 in a plan view is not covered by the covering portion 50A. Furthermore, the covering portion 50A covers the entire bonding layer 30. As shown in FIG. 10, the covering portion 50A covers the entire periphery 30a of the bonding layer 30. Therefore, covering portion 50A covers the four corners (four corner portions 30b) of bonding layer 30 in a plan view. Also, covering portion 50A covers a part of bonding portion 411 of connecting member 41 and a part of bonding portion 421 of connecting member 42, as shown in FIGS.

[0044] The sealing portion 50B is located above the covering portion 50A in the thickness direction z. The sealing portion 50B covers the die pad 20 (excluding the back surface 202), a portion of each of the leads 21 to 23 (each of the covering portions 211, 221, 231), the two connecting members 41 and 42, the semiconductor chip 10, and the bonding layer 30. The thickness of the sealing portion 50B is greater than the thickness of the covering portion 50A.

[0045] The methods for forming the covering portion 50A and the sealing portion 50B are not limited in any way, but for example, the covering portion 50A is formed by compression molding, and the sealing portion 50B is formed by transfer molding. Unlike this example, the covering portion 50A may be formed by other molding methods, potting, or coating. Also, unlike this example, the sealing portion 50B may be formed by other molding methods. The covering portion 50A is formed before the sealing portion 50B. Also, the covering portion 50A is formed after the two connecting members 41, 42 are joined.

[0046] The thickness t50A (dimension in the thickness direction z) of the covering portion 50A shown in FIG. 9 and the thickness t50 from the main surface 201 to the top surface 51 of the sealing member 50 shown in FIG. 9 are, for example, 1:40, but this ratio is not limited to any particular value. In this embodiment, the thickness t50A of the covering portion 50A is, for example, 0.1 mm or more and 0.2 mm or less, and the thickness t50 from the main surface 201 to the top surface 51 of the sealing member 50 is, for example, approximately 4 mm. The thickness t50A of the covering portion 50A and the thickness t50 are not limited to the above example. The thickness t50A of the covering portion 50A (dimension in the thickness direction z) is, for example, approximately the same as the thickness of the bonding layer 30 (dimension in the thickness direction z).

[0047] In semiconductor device A10, the plastic strain range of covering portion 50A is larger than the plastic strain range of sealing portion 50B. The values ​​of the plastic strain ranges of covering portion 50A and sealing portion 50B are not limited as long as they satisfy the above-mentioned relationship. For example, when the internal temperature of covering portion 50A is 100°C or higher, the plastic strain range of covering portion 50A is 5% or higher. The plastic strain range of sealing portion 50B is approximately 0%, regardless of the internal temperature of sealing portion 50B.

[0048] The plastic strain region will now be explained with reference to Figure 11. Figure 11 shows a characteristic curve illustrating the relationship between stress and strain for a material. When stress is applied to a material, strain occurs in the material. However, up to the yield point, when the stress is removed, the strain becomes zero due to the material's elasticity. On the other hand, once the yield point is passed, strain remains even when the stress is removed. When the applied stress increases the magnitude of strain up to the breaking point, the material breaks. In this characteristic curve, the elastic region extends from the base point to the yield point, and the plastic region extends from the yield point to the breaking point. The plastic strain region is the percentage of the plastic region in the total range (from the base point to the breaking point) of the elastic and plastic regions combined. The characteristic curve shown in Figure 11 is an example; the elastic region, plastic region, yield point, and breaking point vary depending on the material, temperature, and other factors.

[0049] Furthermore, the difference (absolute value) between the thermal expansion coefficient of the sealing portion 50B and the linear expansion coefficient of the die pad 20 is smaller than the difference (absolute value) between the thermal expansion coefficient of the covering portion 50A and the thermal expansion coefficient of the die pad 20. For example, in an example where the die pad 20 is made of copper, the thermal expansion coefficient (linear expansion coefficient) of the die pad 20 is 2 ppm or more and 25 ppm or less, the thermal expansion coefficient (linear expansion coefficient) of the covering portion 50A is 30 ppm or more and 250 ppm or less, and the thermal expansion coefficient (linear expansion coefficient) of the sealing portion 50B is, for example, 5 ppm or more and 20 ppm or less.

[0050] Next, the effects of the semiconductor device A10 will be described.

[0051] In the semiconductor device A10, the sealing member 50 includes a covering portion 50A and a sealing portion 50B. The covering portion 50A is located on a support surface 2010 that supports the semiconductor chip 10. The sealing portion 50B is formed on the covering portion 50A. The plastic strain range of the covering portion 50A is larger than the plastic strain range of the sealing portion 50B. As can be seen from FIG. 11 , a larger plastic strain range increases the amount of strain that the material can sustain before fracture. In other words, a larger plastic strain range increases the likelihood of strain, but also increases the material's resistance to fracture. Therefore, by making the plastic strain range of the covering portion 50A larger than the plastic strain range of the sealing portion 50B, the sealing member 50A has a higher fracture resistance than the sealing portion 50B. Therefore, the semiconductor device A10 can suppress peeling of the sealing member 50 due to thermal load (thermal stress).

[0052] In the semiconductor device A10, the sealing portion 50B contains a silica filler in an insulating resin (e.g., epoxy resin), while the covering portion 50A does not contain a silica filler in an insulating resin (e.g., epoxy resin). Research by the present inventors has revealed that the plastic strain range varies depending on the content (content) of the silica filler in the insulating resin (e.g., epoxy resin). Specifically, the plastic strain range decreases when the content (content) of the silica filler in the insulating resin (e.g., epoxy resin) is high, while the plastic strain range increases when the content (content) of the silica filler in the insulating resin (e.g., epoxy resin) is low. Therefore, in the semiconductor device A10, as described above, the insulating resin (e.g., epoxy resin) for the covering portion 50A does not contain a silica filler, while the insulating resin (e.g., epoxy resin) for the sealing portion 50B contains a silica filler. As a result, in the semiconductor device A10, the plastic strain range of the covering portion 50A can be made larger than the plastic strain range of the sealing portion 50B.

[0053] In the semiconductor device A10, the plastic strain range of the covering 50A is 5% or more when the internal temperature of the covering 50A is 100°C or higher. This configuration ensures appropriate fracture resistance of the covering 50A. For example, research by the present inventors has revealed that the stress at the yield point and the strain from the yield point to the fracture point vary depending on the internal temperature of the insulating resin (e.g., epoxy resin). Specifically, when the internal temperature of the insulating resin (e.g., epoxy resin) is low, the stress at the yield point is high and the strain from the yield point to the fracture point is small. On the other hand, when the internal temperature of the insulating resin (e.g., epoxy resin) is high, the stress at the yield point is low and the strain from the yield point to the fracture point is large. Therefore, when the internal temperature is lower than 100°C, the stress at the yield point is large, ensuring appropriate stress resistance. This prevents the covering 50A from exceeding the yield point due to the thermal load (thermal stress), allowing the semiconductor device A10 to reduce breakage of the covering 50A and prevent peeling of the covering 50A. On the other hand, if the internal temperature is 100°C or higher, the amount of strain from the yield point to the breaking point increases, ensuring an appropriate amount of strain. This allows the covering 50A to continue to strain even after exceeding the yield point due to the thermal load (thermal stress), preventing it from exceeding the breaking point, allowing the semiconductor device A10 to reduce breakage of the covering 50A and prevent peeling of the covering 50A.

[0054] In the semiconductor device A10, the difference (absolute value) between the thermal expansion coefficient of the sealing portion 50B and the linear expansion coefficient of the die pad 20 is smaller than the difference (absolute value) between the thermal expansion coefficient of the covering portion 50A and the thermal expansion coefficient of the die pad 20. This configuration reduces warpage of the die pad 20 in response to temperature changes in the semiconductor device A10, making it possible to maintain the shape of the semiconductor device A10. In particular, the thermal expansion coefficient of the sealing portion 50B is, for example, 5 ppm or more and 20 ppm or less. This configuration is preferable in terms of reducing warpage in response to temperature changes and maintaining the shape of the semiconductor device A10 in a configuration in which the die pad 20 (support portion) contains copper.

[0055] In the semiconductor device A10, the covering portion 50A covers the four corners (four corner portions 30b) of the bonding layer 30 when viewed in the thickness direction z. The aforementioned thermal load is greatest at the four corners of the bonding layer 30. Therefore, peeling of the sealing member 50 can occur from the four corners of the bonding layer 30. Therefore, in the semiconductor device A10, peeling of the sealing member 50 can be suppressed by covering at least the four corners of the bonding layer 30 with the covering portion 50A.

[0056] In the semiconductor device A10, the covering portion 50A covers the periphery 30a of the bonding layer 30 when viewed in the thickness direction z. The aforementioned thermal load is greatest at the periphery 30a of the bonding layer 30, next to the four corners of the bonding layer 30. Therefore, peeling of the sealing member 50 may occur from the periphery 30a of the bonding layer 30, next to the four corners of the bonding layer 30. Therefore, in the semiconductor device A10, the covering portion 50A covers at least the periphery 30a of the bonding layer 30, thereby enhancing the effect of suppressing peeling of the sealing member 50.

[0057] In the semiconductor device A10, the covering portion 50A covers the entire third surface 33 of the bonding layer 30. Peeling of the sealing member 50 can occur at the interface between the bonding layer 30 and the sealing member 50. Therefore, in the semiconductor device A10, the entire third surface 33 of the bonding layer 30 is covered with the covering portion 50A, which further enhances the effect of suppressing peeling of the sealing member 50.

[0058] In the semiconductor device A10, the covering portion 50A covers the entire non-contact region 2012. Peeling of the sealing member 50 can occur at the interface between the sealing member 50 and the die pad 20, after it occurs at the interface between the sealing member 50 and the bonding layer 30. Therefore, in the semiconductor device A10, the effect of suppressing peeling of the sealing member 50 can be further enhanced by covering the entire non-contact region 2012 with the covering portion 50A.

[0059] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0060] 12 shows a semiconductor device A11 according to a modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the range in which the covering portion 50A is formed. In the semiconductor device A10, a portion of the die pad 20 is exposed from each opening 55 of the sealing member 50, but in the semiconductor device A11, this exposed portion is covered with the covering portion 50A.

[0061] The semiconductor device A11 configured as described above also achieves the same effects as the semiconductor device A10. Furthermore, in the semiconductor device A11, the die pad 20 is not exposed in each opening 55 of the sealing member 50. This makes it possible for the semiconductor device A11 to suppress unintentional short circuits more effectively than the semiconductor device A10.

[0062] In the first embodiment, the covering portion 50A covers the entire main surface 201 of the die pad 20 (the main surface 201 of the first portion 20A and the main surface 201 of the second portion 20B). However, unlike this example, the main surface 201 of the second portion 20B does not need to be covered by the covering portion 50A (it may be in contact with the sealing portion 50B). The semiconductor chip 10 is bonded to the first portion 20A, and the lower surface (rear surface 202) of the first portion 20A is exposed from the sealing member 50. In this configuration, heat from the semiconductor chip 10 is released from the lower surface (rear surface 202) of the first portion 20A, and heat transfer to the second portion 20B is reduced. In other words, the thermal load on the sealing member 50 is reduced in the second portion 20B, thereby reducing peeling of the sealing member 50. From this perspective, the covering portion 50A does not need to cover the main surface 201 of the second portion 20B. In this case, the area where the covering portion 50A is formed can be reduced, which is preferable in terms of suppressing the warpage deformation of the die pad 20 described above.

[0063] Second Embodiment 13 to 15 show a semiconductor device A20 according to the second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respect: the covering portion 50A does not cover the chip main surface 10a of the semiconductor chip 10.

[0064] In the semiconductor device A20, the covering portion 50A has an opening 501A. The opening 501A penetrates in the thickness direction z from the upper surface (the surface facing upward in the thickness direction z) of the covering portion 50A to the lower surface (the surface facing downward in the thickness direction z) of the covering portion 50A. In the semiconductor device A20, the opening 501A is formed along each chip side surface 10c of the semiconductor chip 10, and a portion (a portion on the lower side in the thickness direction z) of each chip side surface 10c is covered by the covering portion 50A. The semiconductor chip 10 (chip main surface 10a) is exposed from the opening 501A. In this way, since the chip main surface 10a of the semiconductor chip 10 is exposed from the covering portion 50A, in the semiconductor device A20, it is possible to connect two connecting members 41 and 42 after forming the covering portion 50A. In the semiconductor device A20, the covering portion 50A covers the entire non-contact region 2012 of the support surface 2010, similarly to the semiconductor device A10.

[0065] In the semiconductor device A20, similar to the semiconductor device A10, the sealing member 50 includes a covering portion 50A and a sealing portion 50B, and the plastic strain range of the covering portion 50A is larger than the plastic strain range of the sealing portion 50B. Therefore, similar to the semiconductor device A10, the semiconductor device A20 can suppress peeling of the sealing member 50 due to thermal load. In addition, the semiconductor device A20 has a common configuration with the semiconductor device A10, and therefore achieves the same effects as the semiconductor device A10.

[0066] 16 to 18 show a semiconductor device A21 according to a first modified example of the second embodiment. The semiconductor device A21 differs from the semiconductor device A20 in the following respect: a part of the third surface 33 of the bonding layer 30 is exposed in the opening 501A.

[0067] In the semiconductor device A21, the periphery (multiple chip side surfaces 10c) of the semiconductor chip 10 is enclosed in the opening 501A in plan view, so that a part of the third surface 33 (a part closer to the semiconductor chip 10) is exposed from the covering portion 50A.

[0068] The semiconductor device A21 configured as described above also achieves the same effects as the semiconductor device A20. As can be seen from the semiconductor device A21, in the semiconductor device of the present disclosure, the covering portion 50A may or may not be in contact with the semiconductor chip 10. However, in terms of reducing the contact area between the sealing portion 50B and the bonding layer 30, the semiconductor device A20 is preferable to the semiconductor device A21.

[0069] In the semiconductor device A21, as shown in Figure 18, an example is shown in which the thickness of the covering portion 50A gradually changes along the third surface 33, but unlike this example, as shown in Figure 19, the thickness of the covering portion 50A may be uniform.

[0070] 20 and 21 show a semiconductor device A22 according to a second modified example of the second embodiment. The semiconductor device A22 differs from the semiconductor device A21 in the following respect: the covering portion 50A is formed in a ring shape in a plan view.

[0071] In the semiconductor device A22, the covering portion 50A overlaps the entire periphery of the peripheral edge 30a in a plan view. In a plan view, the outer peripheral edge of the covering portion 50A is located outward from the peripheral edge 30a of the bonding layer 30. In the illustrated example, the peripheral edge 30a is rectangular, so the covering portion 50A is rectangular-annular. Note that the shape of the covering portion 50A is not limited to a rectangular annular shape, and it may be a circular annular shape, an elliptical annular shape, or a polygonal annular shape, as long as it overlaps the entire periphery of the peripheral edge 30a in a plan view. In the semiconductor device A22, the opening 501A corresponds to the inner peripheral edge of the covering portion 50A. In other words, in a plan view, in the semiconductor device A22, in which the peripheral edge (multiple chip side surfaces 10c) of the semiconductor chip 10 is enclosed in the opening 501A as in the semiconductor device A21, the semiconductor chip 10 is located inside the inner peripheral edge of the covering portion 50A. In the example shown in FIG. 21, the thickness of the covering portion 50A on the third surface 33 gradually changes, similar to FIG. 18, but unlike this example, it may be uniform, similar to FIG.

[0072] The semiconductor device A22 configured as described above also has the same effects as the semiconductor device A20. As can be seen from the semiconductor device A22, in the semiconductor device of the present disclosure, the covering portion 50A is not limited to covering the entire non-contact region 2012 of the main surface 201.

[0073] Third Embodiment 22 to 24 show a semiconductor device A30 according to the third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following respect: the covering portion 50A is divided into a plurality of portions.

[0074] In the semiconductor device A30, the covering portion 50A includes a plurality of separating portions 500A. Each separating portion 500A individually covers one of the four corners (four corner portions 30b) of the bonding layer 30 in a plan view.

[0075] In the semiconductor device A30, similar to the semiconductor device A10, the sealing member 50 includes a covering portion 50A and a sealing portion 50B, and the plastic strain range of the covering portion 50A is larger than the plastic strain range of the sealing portion 50B. Therefore, similar to the semiconductor device A10, the semiconductor device A30 can suppress peeling of the sealing member 50 due to thermal load. In addition, the semiconductor device A30 has a common configuration with the other semiconductor devices A10 and A20, and therefore achieves the same effects as the semiconductor devices A10 and A20.

[0076] In a configuration different from the first to third embodiments (including their modifications), the semiconductor device of the present disclosure may include an insulating substrate and a wiring pattern. Fig. 25 shows a semiconductor device according to such a modification. The semiconductor device shown in Fig. 25 includes an insulating substrate 25, a wiring pattern 26, a plurality of through-hole wires 271, and a plurality of external electrodes 272.

[0077] The insulating substrate 25 supports the semiconductor chip 10. For example, an insulating semiconductor substrate, a ceramic substrate, or an insulating resin substrate can be used as the insulating substrate 25. The sealing member 50 is formed on the insulating substrate 25.

[0078] The wiring pattern 26 is formed on the upper surface (surface facing upward in the thickness direction z) of the insulating substrate 25. The wiring pattern 26 contains, for example, Cu or a Cu alloy, but may contain other metals. The wiring pattern 26 includes a conductor portion 261 as a support portion and a plurality of conductor portions 262 as wiring portions. The semiconductor chip 10 is bonded to the conductor portion 261 via the bonding layer 30. A plurality of connection members 40 are individually bonded to the plurality of conductor portions 262. The plurality of connection members 40 are bonding wires.

[0079] Each of the plurality of through wires 271 penetrates the insulating substrate 25 in the thickness direction z. The plurality of through wires 271 are individually connected to the plurality of conductor portions 262. Each of the through wires 271 contains, for example, Cu or a Cu alloy, but may also contain other metals.

[0080] The plurality of external electrodes 272 are individually connected to the plurality of through wires 271. The plurality of external electrodes 272 cover the lower surfaces (surfaces facing downward in the thickness direction z) of the plurality of through wires 271. The plurality of external electrodes 272 may each be formed of a single metal layer, a laminate of multiple metal layers, or a bonding bump such as solder.

[0081] In a configuration different from the first to third embodiments (including their variations), the covering portion 50A may contain a silica filler in the insulating resin (e.g., epoxy resin). However, in this example, the content (content rate) of the silica filler in the covering portion 50A is lower than the content (content rate) of the silica filler in the sealing portion 50B. As described above, when the content of the silica filler in the insulating resin (e.g., epoxy resin) is low, the plastic strain range can be increased. Therefore, even in this configuration, the plastic strain range of the covering portion 50A can be made larger than the plastic strain range of the sealing portion 50B.

[0082] The first to third embodiments (including their modifications) are not limited to the above examples as long as the plastic strain range of the covering portion 50A is larger than the plastic strain range of the sealing portion 50B. For example, the plastic strain range of the covering portion 50A and the plastic strain range of the sealing portion 50B may be configured to satisfy the above relationship by changing the insulating resin of each of the covering portion 50A and the sealing portion 50B or by changing the filler material of each of the covering portion 50A and the sealing portion 50B.

[0083] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. For example, the semiconductor device according to the present disclosure includes the following embodiments. Note that, although examples of each component in the following embodiments are indicated in parentheses using the symbols in the above-described embodiment (including modified examples), the present disclosure is not limited to these. Appendix 1. A semiconductor chip (10); a support portion (die pad 20) having a support surface (2010) facing the semiconductor chip (10) in the thickness direction (z) of the semiconductor chip (10), and supporting the semiconductor chip (10); a bonding layer (30) interposed between the semiconductor chip (10) and the support surface (2010) and bonding the semiconductor chip (10) to the support portion (die pad 20); a sealing portion (50B) material (50) that covers the semiconductor chip (10) and the bonding layer (30); Equipped with the sealing portion (50B) member (50) includes a covering portion (50A) positioned on the support surface (2010) and a sealing portion (50B) formed on the covering portion (50A), the covering portion (50A) covers four corners of the bonding layer (30) when viewed in the thickness direction (z), The semiconductor device (A10, A11, A20 to A22, A30) has a plastic strain range of the covering portion (50A) larger than a plastic strain range of the sealing portion (50B). Appendix 2. The semiconductor device (A10, A11, A20 to A22, A30) according to Appendix 1, wherein the plastic strain range of the covering portion (50A) when the internal temperature of the covering portion (50A) is 100° C. or higher is 5% or higher. Appendix 3. The semiconductor device (A10, A11, A20 to A22, A30) according to Supplementary Note 1 or 2, wherein each of the sealing portion (50B) and the covering portion (50A) contains an epoxy resin. Appendix 4. The sealing portion (50B) contains a silica filler, The semiconductor device (A10, A11, A20 to A22, A30) according to Appendix 3, wherein the covering portion (50A) does not contain a silica filler. Appendix 5. The semiconductor device (A10, A11, A20 to A22, A30) according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the thermal expansion coefficient of the sealing portion (50B) is 5 ppm or more and 20 ppm or less. Appendix 6. The semiconductor device (A10, A11, A20-A22) according to any one of Supplementary Note 1 to Supplementary Note 5, wherein the covering portion (50A) covers the periphery of the bonding layer (30) when viewed in the thickness direction (z). Appendix 7. The bonding layer (30) has a first surface (31) in contact with the semiconductor chip (10), a second surface (32) in contact with the support portion (die pad 20), and a third surface (33) connected to the first surface (31) and the second surface (32); The semiconductor device (A10, A11, A20 to A22, A30) according to Supplementary Note 6, wherein the covering portion (50A) covers the third surface (33). Appendix 8. The support surface (2010) includes a non-contact region (2012) that is not in contact with the bonding layer (30), The semiconductor device (A10, A11, A20, A21) according to any one of Supplementary Note 1 to Supplementary Note 7, wherein the covering portion (50A) covers the entire non-contact region (2012). Appendix 9. The semiconductor device (A10, A11) according to any one of Supplementary Note 1 to Supplementary Note 8, wherein the covering portion (50A) covers the semiconductor chip (10). Appendix 10. The semiconductor device (A20 to A22, A30) according to any one of Supplementary Note 1 to Supplementary Note 8, wherein the semiconductor chip (10) is exposed from the covering portion (50A). Appendix 11. The covering portion (50A) is formed in an annular shape when viewed in the thickness direction (z), The semiconductor device (A22) according to appendix 10, wherein the semiconductor chip (10) is located inside an inner peripheral edge (opening 501A) of the covering portion (50A). Appendix 12. The semiconductor device (A10, A11, A20 to A22, A30) according to any one of Supplementary Note 1 to Supplementary Note 11, wherein the support portion (die pad 20) is a die pad (20) made of metal. Appendix 13. The semiconductor device (A10, A11, A20 to A22, A30) according to Appendix 12, wherein the die pad (20) contains copper. Appendix 14. a wiring portion (leads 22, 23) spaced apart from the support portion (die pad 20); and further comprising connection members (41, 42) that electrically connect the wiring portion (leads 22, 23) and the semiconductor chip (10), The semiconductor chip (10) has a chip main surface (10a) facing in the same direction as the support surface (2010) in the thickness direction (z), and main surface electrodes (12, 13) arranged on the chip main surface (10a); 14. The semiconductor device according to claim 1, wherein the connection members (41, 42) are joined to the main surface electrodes (12, 13). [Explanation of symbols]

[0084] A10, A11, A20, A21, A22, A30: Semiconductor device 10: Semiconductor chip 10a: Main surface of chip 10b: Back side of chip 10c: Chip side 11: Back electrode 12: Main surface electrode 13: Main surface electrode 20: Die pad 20A: Part 1 20B: Part 2 201: Main surface 2010 :Support surface 2011: Contact area 2012: Non-contact area 202: Back side 203: Penetration 21, 22, 23: Lead 211, 221, 231: Covering part 212,222,232:Exposed part 223,233:Joint surface 25: Insulating substrate 26: Wiring pattern 261, 262: Conductor 271: Through wiring 272: External electrode 30: Bonding layer 30a: Periphery 30b: corner 31: 1st page 32: 2nd side 33:Third side 40, 41, 42: connecting members 411,412,421,422: Joint 413,423: Middle section 50: Sealing member 50A: Covered part 500A: Separation section 501A:Aperture 50B: Sealing part 561: Inner surface 51:Top surface 52: Bottom 53,54: Side 55 :Aperture 56: Mounting part 56A: 1st hole edge 56B: 2nd hole edge

Claims

1. A semiconductor chip; a support portion having a support surface facing the semiconductor chip in a thickness direction of the semiconductor chip and supporting the semiconductor chip; a bonding layer interposed between the semiconductor chip and the support surface and bonding the semiconductor chip to the support portion; a sealing member that covers the semiconductor chip and the bonding layer; Equipped with the sealing member includes a covering portion located on the support surface and a sealing portion formed on the covering portion; the covering portion covers four corners of the bonding layer when viewed in the thickness direction, A semiconductor device, wherein the plastic strain range of the covering portion is larger than the plastic strain range of the sealing portion.

2. 2. The semiconductor device according to claim 1, wherein the plastic strain range of the covering portion is 5% or more when the internal temperature of the covering portion is 100° C. or more.

3. The semiconductor device according to claim 1 , wherein each of said sealing portion and said covering portion contains an epoxy resin.

4. the sealing portion contains a silica filler, The semiconductor device according to claim 3 , wherein the covering portion does not contain a silica filler.

5. 5. The semiconductor device according to claim 1, wherein the sealing portion has a coefficient of thermal expansion of 5 ppm or more and 20 ppm or less.

6. 5. The semiconductor device according to claim 1, wherein the covering portion covers a periphery of the bonding layer when viewed in the thickness direction.

7. the bonding layer has a first surface in contact with the semiconductor chip, a second surface in contact with the support portion, and a third surface connected to the first surface and the second surface; The semiconductor device according to claim 6 , wherein the covering portion covers the third surface.

8. the support surface includes a non-contact region that is not in contact with the bonding layer, 5. The semiconductor device according to claim 1, wherein the covering portion covers the entire non-contact region.

9. 5. The semiconductor device according to claim 1, wherein the covering portion covers the semiconductor chip.

10. 5. The semiconductor device according to claim 1, wherein the semiconductor chip is exposed from the covering portion.

11. The covering portion is formed in an annular shape when viewed in the thickness direction, The semiconductor device according to claim 10 , wherein the semiconductor chip is located inside an inner periphery of the covering portion.

12. 5. The semiconductor device according to claim 1, wherein the support portion is a die pad made of metal.

13. The semiconductor device according to claim 12 , wherein the die pad comprises copper.

14. a wiring portion spaced apart from the support portion; a connection member that electrically connects the wiring portion and the semiconductor chip, the semiconductor chip has a chip main surface facing the same direction as the support surface in the thickness direction, and a main surface electrode disposed on the chip main surface; 5. The semiconductor device according to claim 1, wherein the connecting member is bonded to the main surface electrode.

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