Real-time clock device

Abstract

To realize time synchronization with a simple system configuration.SOLUTION: A real-time clock device 20 having a first mode and a second mode includes: an input terminal TPRF to which a reference pulse signal PRF of a time is input; an output terminal TPSY that outputs a synchronization pulse signal PSY of the time; an oscillation circuit 60 that outputs an oscillation clock signal CK; a clock count circuit 70 that generates information on an internal time on the basis of the oscillation clock signal CK; and a processing circuit 40 that performs time correction of the internal time on the basis of the reference pulse signal PRF input from the input terminal TPRF and causes the output terminal TPSY to output the synchronization pulse signal PSY generated based on the information on the internal time in the first mode, and performs the time correction of the internal time on the basis of the reference pulse signal PRF input from the input terminal TPRF in the second mode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a real-time clock device and the like. [Background technology]

[0002] There are known real-time clock devices that generate time information by measuring time based on an oscillating clock signal. For example, Patent Document 1 discloses a method for correcting subsecond time by reading data from a subsecond counter at a timing corresponding to a reference pulse signal, measuring the error in the measured time data, and performing distributed logical speed-up / speed-down with a subsecond counter. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-189037 Summary of the Invention [Problem to be solved by the invention]

[0004] When building a system using multiple real-time clock devices, there is a problem that if time information is input from outside the system to each real-time clock device to synchronize the time, the system becomes complicated. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a real-time clock device having a first mode and a second mode, including an input terminal to which a time reference pulse signal is input, an output terminal to which a time synchronization pulse signal is output, an oscillation circuit to output an oscillation clock signal, a timekeeping counting circuit to generate internal time information based on the oscillation clock signal, and a processing circuit that, in the first mode, corrects the internal time based on the reference pulse signal input from the input terminal and outputs the synchronization pulse signal generated based on the internal time information from the output terminal, and, in the second mode, corrects the internal time based on the reference pulse signal input from the input terminal. [Brief explanation of the drawings]

[0006] [Figure 1] 2 shows an example of the configuration of a real-time clock device according to the present embodiment. [Figure 2] 1 shows an example of a system configuration according to the present embodiment. [Figure 3] 2 shows a detailed configuration example of the real-time clock device of the present embodiment. [Figure 4] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 5] 4 is a flowchart illustrating the operation of the present embodiment. [Figure 6] FIG. 3 is an explanatory diagram of time correction control according to the present embodiment. [Figure 7] FIG. 3 is an explanatory diagram of time correction control according to the present embodiment. [Figure 8] FIG. 10 is an explanatory diagram of a problem in the method of the comparative example. [Figure 9] FIG. 3 is an explanatory diagram of a frequency correction and time correction method according to the present embodiment. [Figure 10] FIG. 3 is an explanatory diagram of input and output signals according to the embodiment. [Figure 11] 1 shows a detailed example of the configuration of a real-time clock device that achieves frequency correction. [Figure 12] FIG. 4 is a signal waveform diagram illustrating the operation of the present embodiment. [Figure 13] 4 is a flowchart illustrating the operation of the present embodiment. [Figure 14]4 is a flowchart illustrating the operation of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the content of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential components.

[0008] 1. Real-time clock device FIG. 1 shows an example of the configuration of a real-time clock device 20 according to this embodiment. The real-time clock device 20 is, for example, a device that generates time information by measuring time based on an oscillation clock signal CK, such as a real-time clock module. The real-time clock device 20 in FIG. 1 includes a processing circuit 40, an oscillation circuit 60, a timekeeping count circuit 70, an input terminal TPRF for a reference pulse signal PRF, and an output terminal TPSY for a synchronization pulse signal PSY. Note that the configuration of the real-time clock device 20 is not limited to that shown in FIG. 1, and various modifications are possible, such as omitting some of the components, adding other components, or replacing some components with other components.

[0009] The input terminal TPRF is a terminal to which a time reference pulse signal PRF is input. The input terminal TPRF is, for example, an input terminal for external connection provided on the package of the real-time clock device 20. The reference pulse signal PRF is a time reference signal. For example, the edge timing of the reference pulse signal PRF serves as the reference timing for the time, e.g., the timing indicating the hour. As an example, the reference pulse signal PRF may be a 1PPS (Pulse Per Second) signal, which is a timing standard signal in GPS (GNSS) or the like. In this embodiment, a reference signal such as 1PPS output from an external GPS module may be used as the reference pulse signal PRF, but this is not limiting. For example, instead of a signal output every second like 1PPS, a signal output every 10 seconds, which is greater than 1 second, may also be used. Furthermore, when time information is transmitted to synchronize the time of multiple communication devices connected via a network, a synchronization signal for the time information may be used as the reference pulse signal PRF. For example, a signal generated by time synchronization using NTP (Network Time Protocol) or PTP (Precision Time Protocol) may be used as the reference pulse signal PRF.

[0010] The output terminal TPSY is a terminal from which a time synchronization pulse signal PSY is output. The output terminal TPSY is, for example, an output terminal for external connection provided on the package of the real-time clock device 20. The synchronization pulse signal PSY is a signal that serves as a reference pulse signal for another real-time clock device outside the real-time clock device 20. For example, the synchronization pulse signal PSY is a signal for time synchronization between the real-time clock device 20 and another real-time clock device. For example, the edge timing of the synchronization pulse signal PSY corresponds to the edge timing of the reference pulse signal PRF. For example, when the voltage level of the reference pulse signal PRF changes at its edge timing, the voltage level of the synchronization pulse signal PSY also changes. However, it is not necessary for the voltage level of the synchronization pulse signal PSY to always change at the edge timing of the reference pulse signal PRF. For example, the voltage level of the synchronization pulse signal PSY may change every n edge timings (n is an integer greater than or equal to 2) of the reference pulse signal PRF. For example, if the reference pulse signal PRF is a pulse signal whose voltage level changes every second, the synchronization pulse signal PSY may be a pulse signal whose voltage level changes every 10 seconds, every minute, or every hour.

[0011] The oscillator circuit 60 is a circuit that outputs an oscillation clock signal CK. For example, the oscillator circuit 60 generates an oscillation signal through oscillation operation and outputs the oscillation clock signal CK based on the oscillation signal. For example, the oscillator circuit 60 generates an oscillation signal with a frequency controlled by a frequency control signal from the processing circuit 40 and outputs the oscillation clock signal CK based on this oscillation signal. As an example, the oscillator circuit 60 generates a sine-wave oscillation signal by driving an oscillator such as a quartz oscillator with a drive circuit to oscillate it, and then waveform-shapes the generated oscillation signal with a waveform shaping circuit to output a square-wave oscillation clock signal CK. The oscillation clock signal CK is a clock signal with a frequency of, for example, 32.768 kHz. Note that the frequency of the oscillation clock signal CK is not limited to this and may be a frequency such as 32 kHz. The real-time clock device 20 may also have a clock output terminal that outputs the oscillation clock signal CK. Note that the oscillation operation of the oscillator circuit 60 is not limited to using such an oscillator and various modifications are possible.

[0012] The processing circuit 40 is a circuit that performs various arithmetic processing and control processing in the real-time clock device 20. The processing circuit 40 can be realized, for example, by a logic circuit, and more specifically, by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and routed using a gate array or the like.

[0013] The time count circuit 70 generates internal time information based on the oscillation clock signal CK from the oscillation circuit 60. For example, the time count circuit 70 performs time counting based on a frequency-divided clock signal obtained by dividing the oscillation clock signal CK using, for example, a frequency divider circuit, and generates time information indicating, for example, the current time through this time counting process. For example, a frequency-divided clock signal with a frequency of, for example, 1 Hz or 1 kHz is generated by dividing the oscillation clock signal CK using the frequency divider circuit, and time information is generated through time counting based on this frequency-divided clock signal. The time information, which is timekeeping data, can include data indicating seconds, minutes, hours, days, months, and years. For example, the time count circuit 70 has counters for counting seconds, minutes, hours, days, months, and years, and generates time information through the counting process of these counters. The generated time information is output to the outside, for example, via an interface circuit. Internal time information corresponding to the time information is also output from the time count circuit 70 to the processing circuit 40.

[0014] The real-time clock device 20 of this embodiment has a first mode and a second mode. For example, when the control mode is set to the first mode, the real-time clock device 20 operates in the first mode, and when the control mode is set to the second mode, the real-time clock device 20 operates in the second mode. The first mode is, for example, the master mode, and the second mode is, for example, the slave mode. The master is the real-time clock device that outputs the synchronization pulse signal PSY, and the slave is the real-time clock device that receives the synchronization pulse signal PSY as the reference pulse signal PRF.

[0015] In the first mode, the processing circuit 40 corrects the internal time based on the reference pulse signal PRF input from the input terminal TPRF, and outputs a synchronization pulse signal PSY generated based on the internal time information from the output terminal TPSY. In the second mode, the processing circuit 40 corrects the internal time based on the reference pulse signal PRF input from the input terminal TPRF. Time correction is a process that updates the internal time of the real-time clock device 20 to the correct time. For example, the edge timing of the reference pulse signal PRF is set to the hour, and the processing circuit 40 uses this reference pulse signal PRF to perform time correction, updating the internal time information so that the internal time is on the hour.

[0016] For example, when the control mode is set to the first mode, which is the master mode, the processing circuit 40 corrects the internal time based on the reference pulse signal PRF input from the input terminal TPRF and outputs a synchronization pulse signal PSY from the output terminal TPSY based on the information of the internal time thus corrected. For example, the timekeeping counting circuit 70 includes counters for, for example, seconds, minutes, hours, days, weeks, months, and years. The processing circuit 40 generates a synchronization pulse signal PSY based on the timing signals of these counters and outputs it from the output terminal TPSY. For example, the processing circuit 40 may generate a synchronization pulse signal PSY that becomes active every time a second counter is incremented. Alternatively, the processing circuit 40 may generate a synchronization pulse signal PSY that becomes active every time a minute, hour, day, week, month, or year counter is incremented. Alternatively, the processing circuit 40 may generate a synchronization pulse signal PSY by combining timing signals from multiple counters, such as second, minute, hour, day, week, month, and year counters.

[0017] On the other hand, when the control mode is set to the second mode, which is slave mode, processing circuit 40 performs time correction of the internal time based on the reference pulse signal PRF input from input terminal TPRF. For example, a synchronization pulse signal PSY output by another real-time clock device set to first mode is input from input terminal TPRF as the reference pulse signal PRF. Processing circuit 40 then performs time correction to update the internal time to the correct time based on the reference pulse signal PRF, which is the synchronization pulse signal PSY from this other real-time clock device.

[0018] For example, FIG. 2 shows an example system configuration of this embodiment. In FIG. 2, time source 15 outputs a reference pulse signal PRF. Time source 15 is, for example, a GPS (GNSS) module or the like, but it may also be a time source based on NTP or PTP. In FIG. 2, real-time clock device 20A is set to the first mode and serves as the master, while real-time clock devices 20B and 20C are set to the second mode and serve as slaves. Therefore, master real-time clock device 20A receives the reference pulse signal PRF from time source 15 at its input terminal TPRF. Based on this reference pulse signal PRF, it corrects its internal time and outputs a synchronization pulse signal PSY from its output terminal TPSY. Slave real-time clock devices 20B and 20C receive the synchronization pulse signal PSY from master real-time clock device 20A at their input terminals TPRF. They perform time correction using the synchronization pulse signal PSY from the master as the reference pulse signal PRF. In this way, the master real-time clock device 20A can maintain the accurate internal time by correcting the internal time based on the reference pulse signal PRF from the time source 15. The slave real-time clock devices 20B and 20C can maintain the accurate internal time by correcting the internal time using the synchronization pulse signal PSY from the master real-time clock device 20A as the reference pulse signal PRF.

[0019] As described above, the real-time clock device 20 of this embodiment includes an input terminal TPRF to which a time reference pulse signal PRF is input, an output terminal TPSY to which a time synchronization pulse signal PSY is output, an oscillation circuit 60 to which an oscillation clock signal CK is output, a timekeeping count circuit 70 to which internal time information is generated based on the oscillation clock signal CK, and a processing circuit 40. In the first mode, the processing circuit 40 corrects the internal time based on the reference pulse signal PRF input from the input terminal TPRF and outputs the synchronization pulse signal PSY generated based on the internal time information from the output terminal TPSY. In the second mode, the processing circuit 40 corrects the internal time based on the reference pulse signal PRF input from the input terminal TPRF. In this manner, in the first mode, the internal time can be corrected based on the reference pulse signal PRF input from the input terminal TPRF, and the synchronization pulse signal PSY can be output from the output terminal TPSY to enable time synchronization with other real-time clock devices. In other words, the real-time clock device 20 itself functions as a master and supplies the synchronization pulse signal PSY to other real-time clock devices, enabling time synchronization. In the second mode, the internal time can be corrected using the synchronization pulse signal PSY output by another real-time clock device as the reference pulse signal PRF. Therefore, in a system with multiple real-time clock devices such as the one shown in Figure 2, time synchronization can be achieved without complicating the system, reducing the power consumption and cost of the terminal device.

[0020] For example, in a real-time clock device 20 module, internal time deviations occur due to various factors, such as oscillator aging and frequency-temperature characteristics. Maintaining accurate time requires time input from an external time source as needed. However, using a GPS module or network communications such as NTP or PTP as a time source for all real-time clock devices complicates the configuration and increases costs and current consumption. Furthermore, appropriately inputting time information from an external source requires activating a processing unit such as a CPU, which writes the time information, thereby increasing system current consumption. Furthermore, in a time correction method in which a first digital electronic clock (the correcting device) outputs a time synchronization signal and a second digital electronic clock (the receiving device) detects that signal and corrects the time, the master and slave cannot be swapped, meaning that an abnormality on the master side prevents the time correction of the entire network. Furthermore, in a method in which the master and slave transmit pulse signals to start and stop processing for time synchronization, the same clock signal must be supplied, and the time information is not shared, making it impossible to capture the time information as a log. Furthermore, in time correction methods using packet communications such as NTP and PTP, packet loss can adversely affect the accuracy of the time correction.

[0021] In this regard, the real-time clock device 20 of this embodiment synchronizes time using pulse signals such as the reference pulse signal PRF and the synchronization pulse signal PSY. This enables time synchronization without using a processing device such as a CPU to input time information, thereby reducing power consumption. Furthermore, time synchronization with low current consumption can be achieved by extending the output interval of the synchronization pulse signal PSY. Even if the synchronization pulse signal PSY is lost, the timing of the missing pulse signal is not corrected, which has the advantage of not significantly affecting the accuracy of time synchronization. Another advantage is that the master and slave time sources can be switched, allowing for countermeasures to be taken if an abnormality occurs on the master side by switching between the master and slave sides.

[0022] 2. Detailed configuration example Fig. 3 shows a detailed configuration example of the real-time clock device 20 of this embodiment. The real-time clock device 20 of Fig. 3 is provided with an interface circuit 30 in addition to a processing circuit 40, an oscillation circuit 60, and a time counting circuit 70. Fig. 3 also shows detailed configuration examples of the processing circuit 40 and the time counting circuit 70. Note that the configurations of the real-time clock device 20, the processing circuit 40, and the time counting circuit 70 are not limited to those shown in Fig. 3, and various modifications are possible, such as omitting some of the components, adding other components, or replacing some of the components with other components.

[0023] In FIG. 3 , the oscillator circuit 60 generates an oscillation signal by oscillating the resonator 10 and outputs an oscillation clock signal CK. The resonator 10 is an element that generates mechanical vibrations in response to an electrical signal. The resonator 10 can be realized by a resonator element such as a quartz crystal resonator element. For example, the resonator 10 can be realized by a quartz crystal resonator element that vibrates in a thickness-shear mode, such as an AT-cut or SC-cut cut angle, a tuning-fork type quartz crystal resonator element, or a double-ended tuning-fork type quartz crystal resonator element. Note that the resonator 10 of this embodiment can also be realized by various resonators, such as a resonator element other than a thickness-shear type, tuning-fork type, or double-ended tuning-fork type, or a piezoelectric resonator element formed from a material other than quartz. For example, the resonator 10 can be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) resonator, which is a silicon resonator formed using a silicon substrate.

[0024] For example, the real-time clock device 20 in FIG. 3 includes an integrated circuit device including an interface circuit 30, a processing circuit 40, an oscillation circuit 60, a timekeeping counting circuit 70, etc., and a resonator 10 housed in a package 5. The integrated circuit device is a circuit device called an IC (Integrated Circuit). For example, the integrated circuit device is an IC manufactured by a semiconductor process, and is a semiconductor chip with circuit elements formed on a semiconductor substrate. The resonator 10 is electrically connected to the integrated circuit device. For example, the resonator 10 and the integrated circuit device are electrically connected using internal wiring, bonding wires, metal bumps, or the like of the package 5 that houses the resonator 10 and the integrated circuit device. Note that a variation is also possible in which the resonator 10 is not built into the real-time clock device 20, but is instead provided externally.

[0025] The interface circuit 30 is a circuit for communicating with an external processing device. For example, the interface circuit 30 communicates with the external processing device based on a given communication standard. For example, the interface circuit 30 performs serial communication using I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface). In the case of serial communication, the real-time clock device 20 has communication terminals such as a serial clock input terminal and a serial data input / output terminal. In FIG. 3, timestamp information TMS, which is time information, is input to the interface circuit 30. For example, the timestamp information TMS is input to the interface circuit 30 as serial data. The interface circuit 30 also outputs time information TMQ, which indicates the current time kept by the real-time clock device 20.

[0026] The oscillator circuit 60 can be realized, for example, by a drive circuit for oscillation electrically connected to one end and the other end of the vibrator 10, and passive elements such as capacitors and resistors. The drive circuit can be realized, for example, by a bipolar transistor or a CMOS inverter circuit. The drive circuit is the core circuit of the oscillator circuit 60, and the drive circuit drives the vibrator 10 with voltage or current, causing the vibrator 10 to oscillate. Various types of oscillator circuits can be used as the oscillator circuit 60, for example, inverter type, Pierce type, Colpitts type, or Hartley type.

[0027] The oscillator circuit 60 may also include a variable capacitance circuit (not shown). The variable capacitance circuit may include, for example, a capacitor array having multiple capacitors and a switch array having multiple switches. Each of the multiple capacitors and each of the multiple switches are connected in series between a node at one end or the other end of the vibrator 10 and, for example, a ground node. The capacitance values ​​of the multiple capacitors in the capacitor array are binary-weighted. The multiple switches in the switch array are turned on and off based on frequency control data, which is a frequency control signal SFC from the processing circuit 40. This controls the capacitance value of the variable capacitance circuit, thereby adjusting the oscillation frequency of the oscillator circuit 60. Alternatively, the variable capacitance circuit may be implemented using a variable capacitance element, such as a varactor. In this case, a frequency control voltage is input to the oscillator circuit 60 as the frequency control signal SFC from the processing circuit 40. This frequency control voltage adjusts the capacitance of the variable capacitance element, thereby adjusting the oscillation frequency of the oscillator circuit 60. In this embodiment, a temperature compensation circuit may be provided that performs temperature compensation based on a temperature detection signal from a temperature sensor. In this case, temperature compensation of the oscillation frequency is performed by adjusting the capacitance of the variable capacitance circuit based on the temperature compensation result of the temperature compensation circuit. Note that the connection in this embodiment is an electrical connection. An electrical connection is a connection that allows the transmission of an electrical signal, and is a connection that allows the transmission of information by an electrical signal. The electrical connection may be a connection via a passive element or the like.

[0028] In FIG. 3, the time count circuit 70 includes a time counter 72 and a divider circuit 78. The divider circuit 78 divides the oscillation clock signal CK from the oscillation circuit 60 to generate a divided clock signal CKD. For example, the divider circuit 78 includes a divide-by counter that operates based on the oscillation clock signal CK and generates the divided clock signal CKD. The divided clock signal CKD is a clock signal with a frequency of, for example, 1 Hz. The divider circuit 78 may include a first divider circuit that divides the oscillation clock signal CK by a first division ratio and a second divider circuit that divides the first divided clock signal from the first divider circuit by a second division ratio to output the divided clock signal CKD, which is a second divided clock signal. The first division ratio is, for example, 32, and the frequency of the first divided clock signal is, for example, 1.024 kHz. The second division ratio is, for example, 1024, which results in the divided clock signal CKD being output from the divider circuit 78 at 1 Hz. The frequency of the divided clock signal CKD may be, for example, 1 KHz. The clock output terminal of the real-time clock device 20 may be configured to selectively output the oscillation clock signal CK, the first divided clock signal, or the divided clock signal CKD, which is the second divided clock signal.

[0029] The time counter 72 performs time counting based on the divided clock signal CKD from the frequency divider circuit 78, generating internal time TM information. For example, the time counter 72 has counters for seconds, minutes, hours, days, months, and years, and generates internal time TM information through counting by these counters. This internal time TM information is stored in the internal time register 56 of the processing circuit 40 and output to the outside via the interface circuit 30 as time information TMQ indicating the current time. For example, the time counter 72 includes a first counter 73 and a second counter 74. The first counter 73 counts hours, minutes, and seconds, and the second counter 74 counts fractions of a second. Details of the first counter 73 and second counter 74 will be described later.

[0030] 3, the processing circuit 40 includes a synchronization pulse signal generation unit 54 and an internal time register 56. The internal time register 56 stores information about the internal time TM from the timing count circuit 70. This information about the internal time TM is output to the outside via the interface circuit 30 as time information TMQ.

[0031] The synchronization pulse signal generator 54 generates a synchronization pulse signal PSY. The generated synchronization pulse signal PSY is output to the outside via the output terminal TPSY. For example, the synchronization pulse signal generator 54 generates the synchronization pulse signal PSY based on a clock signal MST from the clock count circuit 70. The clock signal MST is a signal indicating the count-up of a counter, such as a second, minute, or hour counter, provided in the clock count circuit 70. For example, the synchronization pulse signal generator 54 generates a synchronization pulse signal PSY that becomes active when the counter counts up. For example, by generating a synchronization pulse signal PSY that becomes active when the second counter counts up, a synchronization pulse signal PSY that becomes active every second can be generated. Similarly, by generating a synchronization pulse signal PSY that becomes active when the minute and hour counters count up, synchronization pulse signals PSY that become active every minute and every hour can be generated. Furthermore, if the timekeeping count circuit 70 has counters for seconds, minutes, hours, days, weeks, months, years, etc., the synchronization pulse signal generating unit 54 may generate the synchronization pulse signal PSY based on a signal combining count-up signals from these counters. This makes it possible to generate synchronization pulse signals PSY in various modes, such as every 10 seconds, every 20 seconds, every 1 minute 30 seconds, every 10 minutes, every 15 minutes, every 1 hour 20 minutes, every 2 hours, or every 12 hours.

[0032] The synchronization pulse signal generator 54 also receives mode setting and output interval setting information. This mode setting and output interval setting information is input and set, for example, from an external processing device via the interface circuit 30. The mode setting information is information for setting a control mode, such as a first mode or a second mode. For example, when the first mode is set using the mode setting information, the real-time clock device 20 operates in the first mode, which is a master mode. When the second mode is set using the mode setting information, the real-time clock device 20 operates in the second mode, which is a slave mode. The output interval setting information is information for setting the output interval of the synchronization pulse signal PSY. For example, when an output interval of one second is set, a synchronization pulse signal PSY that becomes active every second is generated. Similarly, when output intervals of one minute and one hour are set, a synchronization pulse signal PSY that becomes active every minute and every hour is generated, respectively. Note that the output interval setting is not limited to one second, one minute, one hour, etc.; by combining multiple count-up signals as described above, synchronization pulse signals PSY with various output intervals can be generated.

[0033] FIG. 4 is a signal waveform diagram illustrating the operation of the real-time clock device 20 of FIG. 3. As shown at D1 in FIG. 4, the master side time is first adjusted. For example, if the real-time clock device 20 is set to the first mode and configured as the master side, the initial time adjustment is performed, for example, using the timestamp information TMS. That is, when the timestamp information TMS inputs a time of [12:00:00], the time of [12:00:00] is set as the internal time of the master side real-time clock device 20. Then, as shown at D2, the input of the reference pulse signal PRF begins. For example, time correction is performed at the input timing of the reference pulse signal PRF, as shown at D3 and D4. The input timing, which is the edge timing of the reference pulse signal PRF, is on the hour, and time correction is performed at the input timing of this reference pulse signal PRF on the hour. For example, time correction is performed to reset fractional seconds to zero. Specifically, time correction is performed to reset the fractional seconds counter of the timekeeping count circuit 70.

[0034] After this time adjustment on the master side, the slave side is adjusted as indicated by D5. For example, the master side real-time clock device 20 set to the first mode generates and outputs a synchronization pulse signal PSY as indicated by D6, and this synchronization pulse signal PSY is input to the slave side real-time clock device 20 set to the second mode. The slave side real-time clock device 20 then performs time correction using this synchronization pulse signal PSY as a reference pulse signal. For example, at the timing when the synchronization pulse signal PSY is input, time correction is performed to reset fractional seconds to 0. Specifically, time correction is performed to reset fractional seconds of the timer count circuit 70. At this time, the master side real-time clock device 20 performs time correction based on the reference pulse signal PRF, as indicated by D10, D11, and D12.

[0035] In this way, as shown in FIG. 2, the reference pulse signal PRF from the time source 15 only needs to be input to the master real-time clock device 20 (20A), and does not need to be input to the slave real-time clock devices 20 (20B, 20C). This simplifies the system configuration, resulting in lower costs and lower power consumption. For example, by providing one real-time clock device as the master and multiple real-time clock devices as slaves, the system configuration can be significantly simplified. For example, in the system shown in FIG. 2, a real-time clock device 20 is provided for each of multiple electronic devices (terminal devices). The real-time clock device 20 provided in the first electronic device is set to the first mode and becomes the master, while the real-time clock devices 20 provided in the second to Nth electronic devices are set to the second mode and become slaves. The first electronic device inputs the reference pulse signal PRF from its time source to the real-time clock device 20. On the other hand, the second to Nth electronic devices do not need to have a time source, or do not need to input the reference pulse signal PRF from the time source to the real-time clock device 20. This will enable the system to be simplified, made smaller, and consume less power.

[0036] Furthermore, while FIG. 4 shows the input interval of the reference pulse signal PRF and the output interval of the synchronization pulse signal PSY as being the same, in this embodiment, the output interval of the synchronization pulse signal PSY can be set longer than the input interval of the reference pulse signal PRF. For example, when the input interval of the reference pulse signal PRF is one second, the output interval of the synchronization pulse signal PSY can be set to a longer interval, such as 10 seconds, one minute, or one hour. Increasing the output interval of the synchronization pulse signal PSY in this way increases the generation interval of the synchronization pulse signal PSY on the master side and also increases the interval of time correction based on the synchronization pulse signal PSY on the slave side. Therefore, power consumption can be reduced compared to when the same input interval of the reference pulse signal PRF is input to all real-time clock devices 20.

[0037] FIG. 5 is a flowchart illustrating the operation of the real-time clock device 20 of this embodiment. When the power is turned on and the master-side real-time clock device 20 starts up, the time of the master-side real-time clock device 20 is set (steps S61 and S62). For example, as shown at D1 in FIG. 4, the time is adjusted based on the timestamp information TMS. Then, the control mode of the real-time clock device 20 and the output interval of the synchronization pulse signal PSY are set (step S63). For example, information on the control mode setting and output interval setting is input from an external processing device via the interface circuit 30, whereby the control mode of the real-time clock device 20 and the output interval of the synchronization pulse signal PSY are set. Then, input of the reference pulse signal PRF begins as shown at D2 in FIG. 4, time correction is performed as shown at D3 and D4, and the synchronization pulse signal PSY is output as shown at D6 (steps S64 and S65).

[0038] Next, the slave real-time clock device 20 is started, the time is set, and the control mode of the real-time clock device 20 is set (steps S71, S72, S73). When the synchronization pulse signal PSY is input as shown at D6 in Fig. 4, the synchronization pulse signal PSY is used to perform time correction in the slave real-time clock device 20 (steps S74, S75).

[0039] As described above, in this embodiment, the processing circuit 40 sets the output interval of the synchronization pulse signal PSY in the first mode. For example, as shown in step S63 of FIG. 5 , the processing circuit 40 of the master real-time clock device 20 set to the first mode sets the output interval of the synchronization pulse signal PSY. For example, the processing circuit 40 sets the output interval of the synchronization pulse signal PSY to an interval longer than the input interval of the reference pulse signal PRF. The processing circuit 40 then outputs the synchronization pulse signal PSY from the output terminal TPSY at the set output interval. In this way, the real-time clock device 20 can output the synchronization pulse signal PSY at an output interval different from the input interval of the reference pulse signal PRF, thereby achieving time synchronization with other real-time clock devices. For example, by lengthening the output interval of the synchronization pulse signal PSY, it is possible to achieve low power consumption. For example, by lengthening the generation interval of the synchronization pulse signal PSY by the synchronization pulse signal generator 54 or by lengthening the interval of time correction based on the synchronization pulse signal PSY in the slave real-time clock device 20, low power consumption can be achieved.

[0040] 3, the real-time clock device 20 includes an interface circuit 30 to which output interval setting information is input, and a processing circuit 40 sets the output interval of the synchronization pulse signal PSY based on the output interval setting information input via the interface circuit 30. The output interval setting information is received by the interface circuit 30 via a data line such as a serial communication line, and the received output interval setting information is input to the processing circuit 40 and written, for example, to a register provided in the processing circuit 40. A synchronization pulse signal generator 54 in the processing circuit 40 then generates a synchronization pulse signal PSY at an output interval set by the output interval setting information. In this manner, the output interval of the synchronization pulse signal PSY can be set by a processing device external to the real-time clock device 20, and time synchronization can be achieved among multiple real-time clock devices using the synchronization pulse signal PSY generated at the set output interval.

[0041] The real-time clock device 20 also includes an interface circuit 30 to which mode setting information is input. The processing circuit 40 sets the control mode of the real-time clock device 20 to either the first mode or the second mode based on the mode setting information input via the interface circuit 30. The mode setting information is received by the interface circuit 30 via a data line, such as a serial communication line, and the received mode setting information is input to the processing circuit 40 and written to, for example, a register provided in the processing circuit 40. The processing circuit 40 then sets the control mode of the real-time clock device 20 to either the first mode or the second mode based on the mode setting information. For example, when the control mode is set to the first mode, the processing circuit 40 corrects the internal time based on the reference pulse signal PRF input from the input terminal TPRF and outputs a synchronization pulse signal PSY generated based on the internal time information from the output terminal TPSY. On the other hand, when the control mode is set to the second mode, the processing circuit 40 corrects the internal time using the synchronization pulse signal PSY input from the input terminal TPRF as the reference pulse signal PRF. In this way, the control mode of the real-time clock device 20 can be set by an external processing device or the like, and the real-time clock device 20 can be operated in the set control mode. For example, the control mode can be set to the first mode to operate the real-time clock device 20 as a master, or the control mode can be set to the second mode to operate the real-time clock device 20 as a slave.

[0042] The real-time clock device 20 also includes an interface circuit 30 to which timestamp information TMS is input. The processing circuit 40 then sets the internal time information based on the timestamp information TMS input via the interface circuit 30, and then outputs a synchronization pulse signal PSY from the output terminal TPSY. For example, as shown at D1 in FIG. 4 , the timestamp information TMS is input via the interface circuit 30, and the internal time of the master-side real-time clock device 20 is adjusted. For example, in FIG. 4 , the internal time of the master-side real-time clock device 20 is set to [12:00:00], as indicated by the timestamp information TMS. After the internal time is set based on this timestamp information TMS, the synchronization pulse signal PSY is output from the master-side real-time clock device 20 to the slave-side real-time clock device 20, as shown at D6. Specifically, in FIG. 4 , the internal time of the master-side real-time clock device 20 is corrected based on the reference pulse signal PRF, and then the synchronization pulse signal PSY is output. In this way, after the internal time of the real-time clock device 20 set to the first mode has been set to the appropriate time using the timestamp information TMS, a synchronization pulse signal PSY based on this internal time information can be output to the real-time clock device 20 set to the second mode. Therefore, the synchronization pulse signal PSY based on more accurate internal time information makes it possible to achieve time synchronization between the real-time clock device 20 set to the first mode and the real-time clock device 20 set to the second mode.

[0043] The time counting circuit 70 also generates time information, which is at least one of second, minute, hour, day, week, month, and year, as internal time information. The processing circuit 40 then generates a synchronization pulse signal PSY based on the time information thus generated. For example, the time counting circuit 70 includes a time counter 72 having counters for at least one of second, minute, hour, day, week, month, and year, and time information based on the output of the time counter 72 is input to the processing circuit 40. For example, as shown in FIG. 3 , a time signal MST from the time counter 72 is input to the processing circuit 40 as internal time information, and the processing circuit 40 generates a synchronization pulse signal PSY based on the time signal MST. In this manner, the internal time information generated by the time counting circuit 70 is used to generate the synchronization pulse signal PSY, enabling time synchronization with other real-time clock devices set to the second mode. For example, it is possible to generate a synchronization pulse signal PSY that becomes active in any of the time units of seconds, minutes, hours, days, weeks, months, or years, thereby achieving time synchronization with other real-time clock devices in any of the time units of seconds, minutes, hours, days, weeks, months, or years.

[0044] Next, the time correction of this embodiment will be described in detail. Figures 6 and 7 are explanatory diagrams of the time correction control of this embodiment. For example, as shown in Figure 3, the timing count circuit 70 is provided with a first counter 73 that counts hours, minutes, and seconds, and a second counter 74 that counts fractions of a second. For example, the first counter 73 is provided with counters that count hours, minutes, and seconds, and the second counter 74 is provided with a counter that counts milliseconds.

[0045] 6, the internal time of the real-time clock device 20 is ahead of the hour of [12:00:00] indicated by the reference pulse signal PRF. That is, the first counter 73, which counts hours, minutes, and seconds, indicates [12:00:00], but the second counter 74, which counts milliseconds less than seconds, has a count value of, for example, 2, so the internal time is ahead by, for example, 2 milliseconds. If it is determined that the internal time is ahead of the time corresponding to the reference pulse signal PRF in this way, the count value of the second counter 74 is reset (cleared) to, for example, 0 during time correction, as shown in FIG.

[0046] On the other hand, in FIG. 7 , the internal time of the real-time clock device 20 is delayed relative to the hour, 12:00:00, indicated by the reference pulse signal PRF. Specifically, the first counter 73, which counts hours, minutes, and seconds, indicates 11:59:59, while the second counter 74, which counts milliseconds less than seconds, has a count value of 998, indicating that the internal time is delayed by, for example, 2 milliseconds. If it is determined that the internal time is delayed relative to the time corresponding to the reference pulse signal PRF, the time correction involves resetting the count value of the second counter 74 to, for example, 0, and adding a value corresponding to one second to the count value of the first counter 73, as shown in FIG. 7 . For example, the count value of the second counter of the first counter 73 is incremented by, for example, 1. This allows time correction to be performed, in which the count values ​​of the first counter 73 and the second counter 74 are set to the count value corresponding to the hour, regardless of whether the internal time is advanced or delayed at the time the reference pulse signal PRF is input. That is, if the internal time is fast, the count value of the second counter 74 that counts fractional seconds is reset and the count value of the first counter 73 that counts hours, minutes, and seconds is left unchanged, as shown in Figure 6. If the internal time is slow, the count value of the second counter 74 that counts fractional seconds is reset and the count value of the first counter 73 that counts hours, minutes, and seconds is increased by +1 second, as shown in Figure 7, so that the count value can be set to the count value that corresponds to the hour.

[0047] As described above, the timekeeping counting circuit 70 includes a first counter 73 that counts hours, minutes, and seconds, and a second counter 74 that counts fractional seconds. For example, the first counter 73 is configured with counters that count hours, minutes, and seconds, and the second counter 74 is configured with a counter that counts fractional seconds, such as a millisecond counter. As described with reference to FIG. 6, if the internal time is ahead of the time corresponding to the reference pulse signal PRF, the processing circuit 40 resets the count value of the second counter 74 during time correction. For example, the processing circuit 40 resets the count value of the millisecond counter. On the other hand, as described with reference to FIG. 7, if the internal time is behind the time corresponding to the reference pulse signal PRF, the processing circuit 40 adds a value corresponding to one second to the count value of the first counter 73 and resets the count value of the second counter 74 during time correction. For example, the processing circuit 40 increments the count value of the second counter of the first counter 73 by one, and resets the count value of the millisecond counter of the second counter 74. In this way, whether the internal time is ahead or behind at the time the reference pulse signal PRF is input, time correction can be performed to set the count values ​​of the first counter 73 and the second counter 74 to the count values ​​corresponding to the hour.

[0048] 3. Frequency Compensation The real-time clock device 20 of this embodiment not only corrects the internal time as described above, but also corrects the frequency of the oscillation clock signal CK. The method of this embodiment for performing such processing will be described in detail below.

[0049] For example, in this embodiment, if the processing circuit 40 determines that a time discrepancy has occurred in the internal time when the reference pulse signal PRF is input, it performs frequency correction of the oscillation clock signal CK and time correction of the internal time based on the amount of time discrepancy and the time interval of the time discrepancy. For example, the processing circuit 40 monitors the internal time of the real-time clock device 20 at each timing when the reference pulse signal PRF is input and determines whether a time discrepancy has occurred in the internal time. For example, the processing circuit 40 determines whether a time discrepancy has occurred in the internal time based on internal time information generated by the timing processing of the timing counting circuit 70. For example, if the internal time generated by the timing counting circuit 70 is strictly accurate, the internal time at each input timing of the reference pulse signal PRF will coincide with the hour, and no time discrepancy will occur. However, if a situation occurs, such as a change in the frequency of the oscillation clock signal CK due to aging, a time discrepancy will occur in which the internal time deviates from the hour. When the processing circuit 40 determines that such a time deviation of the internal time has occurred, it corrects the frequency of the oscillation clock signal CK based on the amount of time deviation and the time interval of the time deviation. The amount of time deviation represents the amount of time deviation of the internal time, such as the time error of the internal time. The time interval of the time deviation represents the length of the period during which the time deviation of that amount has occurred. When the processing circuit 40 determines that a time deviation of the internal time has occurred, it corrects the internal time. For example, the processing circuit 40 outputs a signal to the timing count circuit 70 instructing it to perform time correction of the internal time, and the timing count circuit 70 then performs a process of correcting (updating) the internal time to the correct time.

[0050] In this way, if a time deviation occurs in the internal time of real time clock device 20, the internal time is corrected and the frequency of oscillation clock signal CK used for timing the internal time is also corrected. As a result, even if a deviation occurs in the oscillation frequency of oscillation circuit 60 due to aging, for example, it is possible to realize a real time clock device 20 that can suppress errors in the time count caused by this deviation in oscillation frequency and provide highly accurate time information. Note that the frequency correction of oscillation clock signal CK and the internal time correction do not need to be performed at the same time; for example, after frequency correction has been performed, the internal time correction may be performed when the next reference pulse signal PRF is input.

[0051] For example, Figure 8 is an explanatory diagram of the problems with the method of the comparative example of this embodiment. In Figure 8, the frequency error corresponding to the oscillation frequency accuracy increases over time due to aging, etc., and this frequency error causes a deviation in the internal time. Correction is then performed to eliminate the deviation in the internal time caused by this frequency error. In this case, because the frequency error increases over time, the deviation in the internal time also increases, requiring frequent correction of the internal time.

[0052] For example, in a conventional single-package real-time clock (RTC) module, the frequency offset increases over time due to aging of the internal oscillator, which causes the time deviation to accelerate. In order to maintain highly accurate time information when the time deviation is large, frequent corrections must be made to update the time information, as shown in Figure 8, making it difficult to provide highly accurate time.

[0053] On the other hand, to achieve highly accurate timekeeping, it is also possible to consider a method of correcting the logical speed and speed of the timekeeping count. However, since logical speed and speed does not adjust the frequency, when a clock signal is output from the real-time clock module, the clock accuracy remains poor.

[0054] It is also possible to consider an oscillator that has the function of detecting the error from the expected frequency based on the reference pulse signal of the GPS module, which is a GPS receiver, and performing frequency correction based on the detection results, but this oscillator does not perform time correction using the reference pulse signal.

[0055] Another method to achieve an accurate timekeeping clock is to use a processing unit such as an MCU to adjust the frequency of the clock generation circuit, rather than using a single-package real-time clock module. However, this method results in a larger device and consumes more power than a single-package real-time module. Another problem is that frequency adjustment is performed only by time comparison, so frequency adjustment can only be performed to the time resolution of the timestamp.

[0056] In this regard, the present embodiment provides an input terminal TPRF for a reference pulse signal PRF for correcting both the time and frequency. The input terminal TPRF determines whether a time discrepancy has occurred in the internal time at the input timing of the reference pulse signal PRF. If a time discrepancy is determined to have occurred, the frequency of the oscillation clock signal CK and the internal time are corrected. For example, the internal time of the real-time clock device 20 is corrected based on the reference pulse signal PRF, and the frequency is corrected based on the discrepancy between the time indicated by the reference pulse signal PRF and the internal time of the real-time clock device 20. This corrects both the time and the frequency using only the reference pulse signal PRF. As shown in FIG. 9, this allows for time correction to update the internal time to the correct time, while also performing frequency correction to reduce the frequency error to zero. This makes it possible to provide a real-time clock device 20 that can provide accurate time information and maintain time accuracy. Furthermore, in this embodiment, as shown in FIG. 10, the frequency of the oscillation clock signal CK and the internal time are corrected by inputting the reference pulse signal PRF to the real-time clock device 20. Therefore, the real-time clock device 20, which is a single-package real-time clock module, can incorporate an internal time correction function and an oscillation frequency adjustment correction function, making it possible to provide highly accurate time information with a small size and low power consumption.

[0057] 11 shows a detailed configuration example of a real-time clock device 20 for performing time correction of the internal time and frequency correction of the oscillation clock signal CK. In FIG. 11, a processing circuit 40 includes a time lag calculation unit 42, a time interval timing unit 46, a frequency offset calculation unit 50, a frequency adjustment circuit 52, a synchronization pulse signal generation unit 54, and an internal time register 56.

[0058] The time deviation calculation unit 42 calculates the time deviation of the internal time TM based on the internal time TM at the timing when the reference pulse signal PRF is input. The timing when the reference pulse signal PRF is input is, for example, the edge timing of the reference pulse signal PRF. For example, the time deviation calculation unit 42 determines whether a time deviation has occurred by performing a comparison process based on the value of the internal time TM at a first input timing of the reference pulse signal PRF and the value of the internal time TM at a second input timing of the reference pulse signal PRF after the first input timing. If the time deviation calculation unit 42 determines that a time deviation has occurred, it outputs the time deviation amount TE to the frequency offset calculation unit 50.

[0059] The time interval measuring unit 46 measures the time interval TI during which the time lag occurs and outputs the measured time interval TI to the frequency offset calculation unit 50. For example, the time interval measuring unit 46 measures the time interval from when the time correction is performed until the next time it is determined that a time lag has occurred as the time lag interval TI. For example, the time interval measuring unit 46 measures the time interval from when it is determined that there is no time lag in the internal time TM until when it is determined that a time lag has occurred in the internal time TM as the time lag interval TI. For example, assume that there is no time lag in the internal time TM at the ith input timing of the reference pulse signal PRF, and that it is determined that a time lag has occurred at the jth input timing of the reference pulse signal PRF (i, j are integers such that j > i). In this case, the period from the ith input timing to the jth input timing is measured as the time interval TI. For example, the time counter circuit 70 outputs a count pulse CP that becomes active at each input timing of the reference pulse signal PRF. The time interval measuring unit 46 measures the time interval TI by counting the number of count pulses CP. For example, if it is determined that there is no time lag at the ith input timing but that a time lag occurs at the jth input timing, the time interval measuring unit 46 measures the time interval TI of the time lag by counting the number of count pulses CP from the ith input timing to the jth input timing.

[0060] The frequency offset calculation unit 50 then performs a calculation to estimate the frequency offset FOF based on the time offset amount TE from the time offset calculation unit 42 and the time interval TI of the time offset from the time interval measurement unit 46. For example, the frequency offset calculation unit 50 calculates the frequency offset as FOF = TE / TI. The frequency adjustment circuit 52 then adjusts the frequency of the oscillation circuit 60 based on the frequency offset FOF. For example, the frequency adjustment circuit 52 performs frequency correction so as to cancel out the estimated frequency offset FOF. For example, the frequency adjustment circuit 52 generates a frequency control signal SFC that increases or decreases the frequency of the oscillation clock signal CK by the calculated frequency offset FOF and outputs it to the oscillation circuit 60. The oscillation circuit 60 then outputs the oscillation clock signal CK having an oscillation frequency corresponding to the frequency offset FOF. For example, the frequency control signal SFC based on the frequency offset FOF controls the capacitance of the variable capacitance circuit of the oscillation circuit 60, thereby generating an oscillation clock signal CK having an oscillation frequency corresponding to the frequency offset FOF.

[0061] Figure 12 is a signal waveform diagram illustrating the operation of real-time clock device 20 of Figure 11. In the initial time adjustment shown at A1 in Figure 12, the time is adjusted using timestamp information TMS. For example, if the time of [12:00:00] is input using timestamp information TMS, then the time of [12:00:00] is set as the internal time of real-time clock device 20, as shown at A2. Then, after the initial time adjustment, the time correction valid flag is set to, for example, 1, as shown at A3, and time correction is enabled.

[0062] Then, as shown at A4, input of the reference pulse signal PRF begins, and, for example, at the first input timing of the reference pulse signal PRF, time correction is executed as shown at A5. The input timing, which is the edge timing of the reference pulse signal PRF, is on the hour, and time correction is executed at the input timing of this reference pulse signal PRF on the hour. For example, time correction is executed to reset the sub-second counter of the timing count circuit 70. Then, when time correction is executed, increment processing of the time interval count for each input timing of the reference pulse signal PRF begins as shown at A6, and the time correction flag is cleared (reset), for example, to 0 as shown at A7.

[0063] After the initial time adjustment and time correction, a subsecond time comparison is performed at the input timing of the reference pulse signal PRF, as shown in A8, to detect a time discrepancy. For example, by detecting whether the last digit (1 ms) of the subsecond 000 has changed from 0 to 1, it is determined whether a time discrepancy has occurred. Then, at A9, a subsecond time comparison of the internal time detects a subsecond discrepancy. Specifically, as shown in A9, a 1 ms discrepancy in the internal time at the input timing of the reference pulse signal PRF is detected. That is, since the input timing of the reference pulse signal PRF is on the hour, the subsecond time should be 000, but since it is 001 in A9, it is determined that a subsecond discrepancy has occurred. Note that in this embodiment, the time discrepancy accuracy is assumed to be 1 ms. For example, by providing a millisecond counter as the time counter 72, an accuracy of 1 ms can be achieved. However, the time discrepancy accuracy may be smaller or larger than 1 ms.

[0064] When it is determined that a time deviation has occurred in the internal time, frequency correction of the oscillation clock signal CK is performed, as indicated by A10. Specifically, the frequency offset FOF = TE / TI = time deviation amount / time interval is calculated, and frequency correction of the oscillation clock signal CK is performed based on the calculated frequency offset FOF. For example, as indicated by A9, the time deviation amount TE is 1 ms. Also, as indicated by A11, the time count value is incremented from 0 to 1000, so the time interval TI of the time deviation is 1000 s (1000 counts x 1 second). Therefore, as indicated by A12, the frequency offset FOF = 1 ms / 1000 s = 1 ppm is calculated, and frequency correction of the oscillation clock signal CK is performed based on this frequency offset FOF. Then, as indicated by A13, the time correction valid flag is set to 1. As a result, time correction is performed when the next reference pulse signal PRF is input, as indicated by A14. Specifically, as indicated by A15, the fractional seconds of the internal time are reset to 000. For example, the millisecond counter is reset. Once the time correction is performed in this manner, the time correction valid flag is cleared to 0 as shown at A16.

[0065] Figures 13 and 14 are flowcharts illustrating the operation of the real-time clock device 20 described in Figures 11 and 12. When power is applied and the real-time clock device 20 starts up, the time count circuit 70 begins counting (steps S1 and S2). As shown at A1 and A2 in Figure 12, the initial time is adjusted using the timestamp information TMS, and as shown at A3, the time correction valid flag is set, enabling time correction (steps S3 and S4). Then, as shown at A4 in Figure 12, input of the reference pulse signal PRF begins, and the time count circuit 70 begins counting (steps S5 and S6).

[0066] As shown in Fig. 14, when the reference pulse signal PRF is input during the execution period of the time count, it is determined whether or not time correction is valid (steps S11 and S12). That is, it is determined whether or not the time correction valid flag is set, as shown at A3 in Fig. 12. If time correction is valid, time correction is executed, as shown at A5 in Fig. 12 (step S13). When time correction is executed, the time interval count is reset to 0, as shown at A6, and the increment process of the time interval count from 0 begins. At the same time, the time correction flag is cleared to 0, as shown at A7, and time correction is invalidated (steps S14 and S15).

[0067] On the other hand, if the time correction flag is cleared to 0 and time correction is disabled, the internal time is held at the edge timing of the reference pulse signal PRF (step S16). Then, the subsecond value of the internal time held last time is compared with the subsecond value of the internal time held this time (step S17). If the subsecond value held last time and the subsecond value held this time differ, and a subsecond shift is detected as shown at A9 in FIG. 12, a frequency offset FOF is calculated from the difference between the subsecond values ​​and the time interval (steps S18 and S19). That is, the frequency offset FOF is calculated based on the time shift amount TE, which is the difference between the subsecond values, and the time interval TI calculated based on the time interval count. Then, frequency correction is performed based on the calculated frequency offset FOF (step S20), as shown at A10. Then, the time correction valid flag is set as shown at A13, time correction is enabled, and the input process of the reference pulse signal PRF ends (steps S21 and S22).

[0068] Then, when the reference pulse signal PRF is next input, time correction is enabled, so step S12 after step S11 in Fig. 14 becomes "YES" and time correction is executed (step S13), as shown at A14 in Fig. 12. Then, the time interval count is reset and starts from 0, and the time correction enabled flag is cleared as shown at A16, disabling time correction (steps S14 and S15).

[0069] As described above, in this embodiment, when the processing circuit 40 determines that a time deviation has occurred in the internal time when the reference pulse signal PRF is input, it performs frequency correction of the oscillation clock signal CK and time correction of the internal time based on the amount of time deviation and the time interval of the time deviation. For example, in FIG. 12 , when the processing circuit 40 determines that a time deviation has occurred as indicated by A9, it performs frequency correction of the oscillation clock signal CK as indicated by A10 and time correction as indicated by A14. The frequency correction of the oscillation clock signal CK is performed based on the amount of time deviation TE indicated by A9 in FIG. 12 and the time interval TI of the time deviation measured, for example, by time interval counting, at A6 and A11. For example, a frequency offset is calculated based on the amount of time deviation TE and the time interval TI of the time deviation, and the oscillation frequency of the oscillation circuit 60 is adjusted based on this frequency offset, thereby performing frequency correction of the oscillation clock signal CK.

[0070] As described above, in this embodiment, an input terminal TPRF for the reference pulse signal PRF is provided. A determination is made as to whether a time discrepancy has occurred in the internal time at the timing of input of the reference pulse signal PRF to this input terminal TPRF. If a time discrepancy is determined to have occurred, frequency correction of the oscillation clock signal CK and time correction of the internal time are performed. This results in time correction to update the internal time to the correct time and frequency correction to bring the frequency error closer to zero. That is, the RTC's internal frequency offset is estimated and corrected based on the time information within the RTC at the timing the reference pulse signal PRF is input. This suppresses timekeeping count errors caused by offset deviations in the oscillation frequency due to aging, enabling the provision of highly accurate time. Therefore, a real-time clock device 20 can be provided that can provide accurate time information and maintain time accuracy. For example, by incorporating a correction function into a single-package RTC module, highly accurate time can be provided with a small size and low power consumption.

[0071] As described above, the real-time clock device of this embodiment, which has a first mode and a second mode, includes an input terminal to which a time reference pulse signal is input and an output terminal to which a time synchronization pulse signal is output. The real-time clock device also includes an oscillation circuit that outputs an oscillation clock signal, a timekeeping counting circuit that generates internal time information based on the oscillation clock signal, and a processing circuit. In the first mode, the processing circuit corrects the internal time based on the reference pulse signal input from the input terminal and outputs a synchronization pulse signal generated based on the internal time information from the output terminal, and in the second mode, corrects the internal time based on the reference pulse signal input from the input terminal.

[0072] According to this embodiment, in the first mode, the internal time can be corrected based on a reference pulse signal input from the input terminal, and a synchronization pulse signal can be output from the output terminal, enabling time synchronization with other real-time clock devices. In the second mode, the internal time can be corrected using a synchronization pulse signal output from another real-time clock device as a reference pulse signal. Therefore, in a system having multiple real-time clock devices, time synchronization can be achieved with a simple system configuration.

[0073] In this embodiment, the processing circuit may set the output interval of the synchronization pulse signal in the first mode.

[0074] In this way, the synchronization pulse signal can be output at an output interval different from the input interval of the reference pulse signal, thereby enabling time synchronization with other real-time clock devices.

[0075] Furthermore, this embodiment may include an interface circuit to which output interval setting information is input, and the processing circuit may set the output interval based on the output interval setting information.

[0076] In this way, the output interval of the synchronization pulse signal can be set by an external processing device or the like, and time synchronization can be achieved among multiple real-time clock devices using the synchronization pulse signal generated at the set output interval.

[0077] This embodiment may also include an interface circuit to which mode setting information is input, and the processing circuit may set the control mode of the real-time clock device to the first mode or the second mode based on the mode setting information.

[0078] In this way, the control mode of the real time clock device can be set by an external processing device or the like, and the real time clock device can be operated in the set control mode.

[0079] This embodiment may also include an interface circuit to which timestamp information is input, and the processing circuit may output a synchronization pulse signal from the output terminal after setting the internal time information based on the timestamp information.

[0080] In this way, after the internal time of the real-time clock device has been set to the correct time based on the timestamp information, it becomes possible to output a synchronization pulse signal based on this internal time information.

[0081] In this embodiment, the timing counting circuit generates time information, which is at least one of second, minute, hour, day, week, month, and year, as internal time information, and the processing circuit may generate a synchronization pulse signal based on the time information.

[0082] In this way, the time information of the internal time generated by the time count circuit is used to generate a synchronization pulse signal, making it possible to achieve time synchronization with other real-time clock devices.

[0083] In this embodiment, the timekeeping counting circuit may include a first counter that counts hours, minutes, and seconds, and a second counter that counts fractions of a second. If the internal time is ahead of the time corresponding to the reference pulse signal, the processing circuit may reset the count value of the second counter during time correction. If the internal time is behind the time corresponding to the reference pulse signal, the processing circuit may add a value corresponding to one second to the count value of the first counter and reset the count value of the second counter during time correction.

[0084] In this way, whether the internal time is ahead or behind at the time the reference pulse signal is input, time correction can be performed to set the count values ​​of the first counter and the second counter to the count values ​​corresponding to the hour.

[0085] In addition, in this embodiment, if the processing circuit determines that a time deviation has occurred in the internal time when the reference pulse signal is input, it may perform frequency correction of the oscillation clock signal based on the amount of time deviation and the time interval of the time deviation, and time correction of the internal time.

[0086] In this way, time correction is performed to update the internal time to the accurate time, and frequency correction is performed to bring the frequency error closer to zero, making it possible to provide a real-time clock device that can provide accurate time information and maintain time precision.

[0087] Although the present embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configuration and operation of the real-time clock device are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0088] 5...package, 10...oscillator, 15...time source, 20, 20A, 20C...real-time clock device, 30...interface circuit, 40...processing circuit, 42...time lag calculation unit, 46...time interval timing unit, 50...frequency offset calculation unit, 52...frequency adjustment circuit, 54...synchronization pulse signal generation unit, 56...internal time register, 60...oscillator circuit, 70...time count circuit, 72...time counter, 73...first counter, 74...second counter, 78...divider circuit, CK...oscillation clock signal, CKD...divided clock signal, CP...count pulse, FOF...frequency offset, MST...time signal, PRF...reference pulse signal, PSY...synchronization pulse signal, SFC...frequency control signal, TE...time lag amount, TI...time interval, TM...internal time, TMQ...time information, TMS...time stamp information, TPRF...input terminal, TPSY...output terminal

Claims

1. 1. A real time clock device having a first mode and a second mode, an input terminal to which a time reference pulse signal is input; an output terminal for outputting a time synchronization pulse signal; an oscillation circuit that outputs an oscillation clock signal; a time count circuit that generates information about an internal time based on the oscillation clock signal; a processing circuit that, in the first mode, corrects the internal time based on the reference pulse signal input from the input terminal and outputs the synchronization pulse signal generated based on information about the internal time from the output terminal, and, in the second mode, corrects the internal time based on the reference pulse signal input from the input terminal; 1. A real-time clock device comprising:

2. 2. The real-time clock device according to claim 1, The processing circuitry In the first mode, the real-time clock device sets an output interval of the synchronization pulse signal.

3. 3. The real-time clock device according to claim 2, an interface circuit to which output interval setting information is input; The real-time clock device is characterized in that the processing circuit sets the output interval based on the output interval setting information.

4. 2. The real-time clock device according to claim 1, an interface circuit to which mode setting information is input; The processing circuitry A real-time clock device, characterized in that the control mode of the real-time clock device is set to the first mode or the second mode based on the mode setting information.

5. 2. The real-time clock device according to claim 1, an interface circuit into which time stamp information is input; The processing circuitry a synchronization pulse signal output from the output terminal after the internal time information is set based on the time stamp information;

6. 2. The real-time clock device according to claim 1, The time count circuit generating time information that is at least one of second, minute, hour, day, week, month, and year information as the internal time information; The processing circuitry A real-time clock device that generates the synchronization pulse signal based on the time information.

7. 2. The real-time clock device according to claim 1, The time count circuit a first counter that counts hours, minutes, and seconds; a second counter that counts fractional seconds; Including, The processing circuitry If the internal time is ahead of the time corresponding to the reference pulse signal, resetting the count value of the second counter in the time correction; A real-time clock device characterized in that, when the internal time is behind the time corresponding to the reference pulse signal, in the time correction, a value corresponding to one second is added to the count value of the first counter and the count value of the second counter is reset.

8. 2. The real-time clock device according to claim 1, The processing circuitry A real-time clock device characterized by, when it is determined that a time deviation has occurred in the internal time when the reference pulse signal is input, performing frequency correction of the oscillating clock signal based on the amount of time deviation and the time interval of the time deviation, and performing time correction of the internal time.

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