Photoelectric conversion device, and apparatus

Abstract

To implement an improvement of a resolution of an avalanche photodiode.SOLUTION: A photoelectric conversion device comprises a semiconductor layer including an avalanche photodiode and having a first face and the second face. The avalanche photodiode includes: a first semiconductor region of a first conductivity type which is provided at a first depth position; a second semiconductor region of a second conductivity type which is closer to the second face than the first semiconductor region; a third semiconductor region of the first conductivity type which is closer to the second face than the second semiconductor region, in contact with a contact plug to which a first voltage is applied, and provided to a second depth position; a region which is a semiconductor region of the second conductivity type which is in contact with a contact plug to which a second voltage is applied, and provided to a third depth position; and a fourth semiconductor region of the first conductivity type which is provided between the region and the third semiconductor region. The photoelectric conversion device comprises a dielectric which is located in a portion overlapping the fourth semiconductor region and includes at least a portion extending beyond the third depth position.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and equipment. [Background technology]

[0002] In recent years, photoelectric conversion devices using avalanche photodiodes with avalanche multiplication have been proposed.

[0003] Patent Document 1 describes a configuration including a plurality of pixels each including an avalanche photodiode, and a high reverse bias voltage is applied to each of the avalanche photodiodes in the plurality of pixels. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-64086 [Patent Document 2] Japanese Patent Publication No. 2022-55214 Summary of the Invention [Problem to be solved by the invention]

[0005] In a pixel including the avalanche photodiode described in Patent Document 1, if the pixel area is reduced to improve resolution, the distance between the anode region and cathode region of the avalanche photodiode becomes shorter, which poses a problem of increasing leakage current between the anode region and the cathode region. [Means for solving the problem]

[0006] The technology disclosed herein provides an avalanche photodiode that performs avalanche multiplication operation in response to a first voltage and a second voltage applied thereto, and also includes a semiconductor layer having a first surface to which light is incident and a second surface opposed to the first surface, wherein the avalanche photodiode includes a first semiconductor region of a first conductivity type provided in the semiconductor layer at a first depth position as viewed from the second surface, a second semiconductor region of a second conductivity type located closer to the second surface than the first semiconductor region, and a second semiconductor region of a second conductivity type located closer to the second surface than the second semiconductor region, in contact with a contact plug to which the first voltage is applied, and having a depth from the second surface of a third semiconductor region of the first conductivity type provided to a third depth position, a region that is the semiconductor region of the second conductivity type and that is in contact with a contact plug to which the second voltage is applied and that is provided to a third depth position from the second surface, and a fourth semiconductor region of the first conductivity type provided between the region and the third semiconductor region, and the fourth semiconductor region is located in a portion that overlaps with at least the fourth semiconductor region in a planar view relative to the second surface and has at least a portion that extends from the second surface into the semiconductor layer, and the portion extends from the second surface beyond the third depth position. [Effects of the Invention]

[0007] The techniques of the present disclosure can reduce leakage current between the anode and cathode regions of an avalanche photodiode. [Brief explanation of the drawings]

[0008] [Figure 1] Overall view of the photoelectric conversion device [Figure 2] Overall view of the sensor board [Figure 3] Overall view of the circuit board [Figure 4] Diagram showing pixel circuit [Figure 5] Pixel circuit driving diagram [Figure 6] Cross-sectional view of a photoelectric conversion device (first embodiment) [Figure 7]1 is a plan view of a photoelectric conversion device (first embodiment); [Figure 8] Photoelectric conversion device manufacturing process diagram (first embodiment) [Figure 9] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 10] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 11] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 12] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 13] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 14] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 15] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 16] 1 is a plan view of a photoelectric conversion device according to a second embodiment; [Figure 17] Cross-sectional view of a photoelectric conversion device (third embodiment) [Figure 18] 10 is a plan view of a photoelectric conversion device (third embodiment); [Figure 19] Manufacturing process diagram of a photoelectric conversion device (third embodiment) [Figure 20] Cross-sectional view of a photoelectric conversion device (fourth embodiment) [Figure 21] 10 is a plan view of a photoelectric conversion device (fourth embodiment); [Figure 22] 10 is a cross-sectional view of a photoelectric conversion device (fifth embodiment); [Figure 23] 10 is a cross-sectional view of a photoelectric conversion device (sixth embodiment); [Figure 24] 10 is a cross-sectional view of a photoelectric conversion device (seventh embodiment); [Figure 25] 10 is a plan view of a photoelectric conversion device (eighth embodiment); [Figure 26] 10 is a plan view of a photoelectric conversion device (eighth embodiment); [Figure 27] Cross-sectional view of a photoelectric conversion device (ninth embodiment) [Figure 28] 10 is a plan view of a photoelectric conversion device (ninth embodiment); [Figure 29] 10 is a plan view of a photoelectric conversion device (ninth embodiment); [Figure 30] Cross-sectional view of a photoelectric conversion device (tenth embodiment) [Figure 31] 10. Plan view of a photoelectric conversion device (tenth embodiment). [Figure 32] Cross-sectional view of a photoelectric conversion device (tenth embodiment) [Figure 33] Cross-sectional view of a photoelectric conversion device (tenth embodiment) [Figure 34] Cross-sectional view of a photoelectric conversion device (tenth embodiment) [Figure 35] Cross-sectional view of a photoelectric conversion device (eleventh embodiment) [Figure 36] 11. Plan view of a photoelectric conversion device (eleventh embodiment). [Figure 37] FIG. 1 is a diagram showing impurity concentrations in semiconductor regions of a photoelectric conversion device (first embodiment); [Figure 38] Equipment configuration diagram [Figure 39] Equipment configuration diagram DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment will be described below with reference to the drawings.

[0010] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the embodiments are not limited to image pickup devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measurement device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometry device (a device that measures the amount of incident light) can be used.

[0011] Furthermore, the conductivity types of the semiconductor regions and wells and the dopants to be implanted described in the following embodiments are merely examples and are not limited to the conductivity types and dopants described in the embodiments. The conductivity types and dopants described in the embodiments can be changed as appropriate, and the potentials of the semiconductor regions and wells will be changed as appropriate in accordance with this change.

[0012] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors can be changed as appropriate.

[0013] For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate can be reversed relative to the description in the examples in accordance with a change in the conductivity type. Furthermore, the conductivity types of the semiconductor regions described in the examples below are merely examples and are not limited to the conductivity types described in the examples. The conductivity types described in the examples can be changed as appropriate, and the potential of the semiconductor region can be changed accordingly. Furthermore, although impurity concentrations may be described in the following embodiments, these impurity concentrations will be described as effective impurity concentrations unless otherwise specified. In other words, in a semiconductor region where donors and acceptors coexist, the impurity concentration will be described based on the effective characteristics of the semiconductor region as the impurity concentration corresponding to the difference between the donors and acceptors.

[0014] First Embodiment FIG. 1 is a diagram showing the configuration of a stacked-type photoelectric conversion device 100 according to an embodiment of the present invention. The photoelectric conversion device 100 is a structure in which two substrates, a sensor substrate 11 (one substrate) and a circuit substrate 21 (the other substrate), are stacked. The sensor substrate 11 and the circuit substrate 21 are electrically connected to form the photoelectric conversion device 100. The sensor substrate 11 has a first semiconductor layer having a photoelectric conversion element 102 (described later) and a first wiring structure. The circuit substrate 21 has a second semiconductor layer having circuits such as a signal processing unit 103 (described later) and a second wiring structure. The photoelectric conversion device 100 is configured by stacking the second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer in this order. The photoelectric conversion device described in each embodiment is a back-illuminated photoelectric conversion device in which light is incident from a first surface and a circuit substrate is disposed on a second surface.

[0015] In the following description, the sensor substrate 11 and the circuit substrate 21 are described as diced chips, but are not limited to chips. For example, each substrate may be a wafer. Furthermore, each substrate may be stacked in the wafer state and then diced, or may be chipped and then stacked and bonded.

[0016] The sensor substrate 11 has a pixel region 12 arranged thereon, and the circuit substrate 21 has a circuit region 22 arranged thereon for processing signals detected in the pixel region 12 .

[0017] 2 is a diagram showing an example of the arrangement of the sensor substrate 11. Pixels 101, each having a photoelectric conversion element 102 including an avalanche photodiode (hereinafter, referred to as APD), are arranged in a two-dimensional array in plan view to form a pixel region 12.

[0018] The pixel 101 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image. In other words, the pixel 101 may be a pixel for measuring the time and amount of light that arrives.

[0019] 3 is a configuration diagram of the circuit board 21. It has a signal processing unit 103 that processes the charges photoelectrically converted by the photoelectric conversion element 102 in FIG. 2, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110.

[0020] The photoelectric conversion element 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 are electrically connected via connection wiring provided for each pixel.

[0021] The vertical scanning circuit unit 110 receives a control pulse supplied from the control pulse generating unit 115 and supplies the control pulse to each pixel. The vertical scanning circuit unit 110 uses logic circuits such as a shift register and an address decoder.

[0022] The signal output from the photoelectric conversion element 102 of the pixel is processed by the signal processing unit 103. The signal processing unit 103 is provided with a counter, a memory, etc., and the memory holds digital values.

[0023] The horizontal scanning circuit unit 111 inputs a control pulse to the signal processing unit 103 to sequentially select each column in order to read out the signal from the memory of each pixel in which the digital signal is held.

[0024] A signal is output to the signal line 113 from the signal processing unit 103 of the pixel selected by the vertical scanning circuit unit 110 for the selected column.

[0025] The signal output to the signal line 113 is output via an output circuit 114 to a recording unit or a signal processing unit outside the photoelectric conversion device 100 .

[0026] In Figure 2, the photoelectric conversion elements in the pixel region may be arranged one-dimensionally. The effects of the present invention can be obtained even with just one pixel, and the case of one pixel is also included in the present disclosure. The function of the signal processing unit does not necessarily need to be provided for each photoelectric conversion element; for example, one signal processing unit may be shared by multiple photoelectric conversion elements, and signal processing may be performed sequentially.

[0027] 2 and 3, a plurality of signal processing units 103 are arranged in a region overlapping the pixel region 12 in a plan view. A vertical scanning circuit unit 110, a horizontal scanning circuit unit 111, column circuits 112, output circuits 114, and a control pulse generating unit 115 are arranged so as to overlap between an edge of the sensor substrate 11 and an edge of the pixel region 12 in a plan view. In other words, the sensor substrate 11 has the pixel region 12 and a non-pixel region arranged around the pixel region 12, and the vertical scanning circuit unit 110, the horizontal scanning circuit unit 111, the column circuits 112, the output circuits 114, and the control pulse generating unit 115 are arranged in a region overlapping the non-pixel region in a plan view.

[0028] FIG. 4 is an example of a block diagram including the equivalent circuits of FIGS.

[0029] In FIG. 2, the photoelectric conversion element 102 having the APD 201 is provided on a sensor substrate 11, and the other members are provided on a circuit board 21.

[0030] The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A voltage VL (second voltage) is supplied to the anode of the APD 201. A voltage VH (first voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage is supplied to the anode and cathode so that the APD 201 performs avalanche multiplication. With this voltage supplied, charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0031] When a reverse bias voltage is supplied, there are two modes: a Geiger mode in which the device operates with a potential difference between the anode and cathode greater than the breakdown voltage, and a linear mode in which the device operates with a potential difference between the anode and cathode close to or less than the breakdown voltage.

[0032] An APD operated in Geiger mode is called a SPAD. For example, the voltage VL (second voltage) is −30 V and the voltage VH (first voltage) is 1 V. The APD 201 may be operated in either linear mode or Geiger mode. A SPAD is preferable because the potential difference is larger than that of a linear mode APD, resulting in a more pronounced effect in terms of withstand voltage.

[0033] The quench element 202 is connected to a power supply that supplies voltage VH and the APD 201. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD 201 and suppressing avalanche multiplication (quench operation). The quench element 202 also functions to return the voltage supplied to the APD 201 to voltage VH by passing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0034] The signal processing unit 103 has a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. In this specification, the signal processing unit 103 may have any one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212.

[0035] The waveform shaping unit 210 shapes the potential change at the cathode of the APD 201 obtained when photons are detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 210. While an example using one inverter as the waveform shaping unit 210 is shown in FIG. 4, a circuit in which multiple inverters are connected in series, or another circuit having a waveform shaping effect, may also be used.

[0036] The counter circuit 211 counts the pulse signals output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via a drive line 213, the signal held in the counter circuit 211 is reset.

[0037] A control pulse pSEL is supplied to the selection circuit 212 from the vertical scanning circuit unit 110 in Fig. 3 via a drive line 214 (not shown in Fig. 3) in Fig. 4, and switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0038] The electrical connection may be switched by disposing a switch such as a transistor between the quench element 202 and the APD 201 or between the photoelectric conversion element 102 and the signal processing unit 103. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion element 102 may be electrically switched using a switch such as a transistor.

[0039] In this embodiment, a configuration using the counter circuit 211 has been described. However, instead of the counter circuit 211, the photoelectric conversion device 100 may be configured to acquire pulse detection timing using a time-to-digital converter (hereinafter referred to as TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 210 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line. The TDC acquires, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 210 into a relative time based on the control pulse pREF.

[0040] FIG. 5 is a diagram showing a schematic diagram of the relationship between the operation of an APD and an output signal.

[0041] Fig. 5(a) is a diagram illustrating the APD 201, quench element 202, and waveform shaping unit 210 of Fig. 4. Here, the input side of the waveform shaping unit 210 is referred to as node A, and the output side is referred to as node B. Fig. 5(b) shows the waveform change at node A in Fig. 5(a), and Fig. 5(c) shows the waveform change at node B in Fig. 5(a).

[0042] Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5(a). When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops. As the voltage drop increases and the potential difference applied to the APD 201 decreases, avalanche multiplication in the APD 201 stops, as shown at time t2, and the voltage level at node A drops no more than a certain value. After that, between time t2 and time t3, a current flows through node A from voltage VL to compensate for the voltage drop, and at time t3, node A settles to its original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by the waveform shaping unit 210 and output as a signal at node B.

[0043] The arrangement of the signal lines 113, the column circuits 112, and the output circuits 114 is not limited to that shown in Fig. 3. For example, the signal lines 113 may be arranged to extend in the row direction, and the column circuits 112 may be arranged at the ends of the signal lines 113.

[0044] The photoelectric conversion devices of the respective embodiments will be described below.

[0045] 6 is a cross-sectional view showing the structure of the APD of this embodiment. This cross-sectional view shows APDs 201 for two pixels. The two APDs 201 have the same structure. For convenience of illustration, the same reference numerals are assigned to parts of the configuration of the two APDs 201, but the configuration is provided in both of the two APDs 201.

[0046] The semiconductor substrate 301 has a first surface F1, which is the surface onto which light is incident, and a second surface F2 corresponding to the first surface F1. An interconnect layer 303 is provided on the upper side of the second surface F2 (opposite the surface onto which light is incident). The sensor substrate 11 shown in FIG. 1 is configured from the semiconductor substrate 301, including the semiconductor layer 302 and the interconnect layer 303.

[0047] The semiconductor substrate 301 is an N-type semiconductor layer that contains donors as a whole.

[0048] The APD 201 has an N-type semiconductor region 311 (third semiconductor region), a P-type semiconductor region 312 (second semiconductor region), a P-type semiconductor region 313, an N-type semiconductor region 314 (first semiconductor region), an N-type semiconductor region 316 (fourth semiconductor region), and an N-type semiconductor region 317. The semiconductor region 316 may have the same donor concentration as the semiconductor layer 302, or may have an increased donor impurity concentration through ion implantation. The impurity concentrations of the semiconductor regions 311, 314, 316, and 317, which are N-type semiconductor regions, satisfy the following relationship: 311>317>314>316. The semiconductor region 311 has a cathode contact 331. A first voltage (positive voltage) is supplied to the cathode contact 331 from an interconnect 333 via a contact plug.

[0049] The APD 201 includes a region that functions as inter-pixel isolation and as a region for applying a second voltage. In this embodiment, this region is a P-type semiconductor region. The semiconductor region 315 and the semiconductor region 319, which are provided at multiple depths, are all P-type semiconductor regions. The impurity concentrations of the semiconductor regions 312, 313, 315, and 319, which are P-type semiconductor regions, are such that the semiconductor region 319 has the highest impurity concentration. The semiconductor region 319 is a region that contacts an anode contact 334. A second voltage (negative voltage) is supplied to the anode contact 334 from the wiring 332 via a contact plug. For example, the second voltage is about −30 V.

[0050] 37 shows the relationship between the impurity concentration (effective impurity concentration) of the acceptor at the position of the line L1 shown in FIG. 6 and the depth from the second face F2. The peak concentration of the semiconductor region 319 is approximately 6×10^19 (in this specification, ^ indicates a power) / cm 3 The impurity concentration at the depth D3 is approximately 4×10^17 / cm 3 Thus, in the region at depth position D3, which is the end of the semiconductor region 319 on the first face F1 side, the concentration is about 10 squared lower than the peak concentration. Note that this concentration difference relationship is not essential, and typically, the concentration at depth position D3 is 1 / 1000 to 1 / 50 of the peak concentration. In this embodiment, depth position D3 is approximately 0.6 μm from the second face F2. This depth position is not limited to this, and typically, depth position D3 is within a range of 0.4 to 1.5 μm from the second face F2. Although an example is shown in which the multiple-stage P-type semiconductor region 315 is provided at each of four depth stages, the present invention is not limited to this example. A greater number of P-type semiconductor regions 315 may be provided, or a smaller number of P-type semiconductor regions 315 may be provided.

[0051] The semiconductor region 312 is supplied with a second voltage from the semiconductor region 315. Therefore, a voltage exceeding the avalanche breakdown voltage is applied to the PN junction formed between the semiconductor region 317 and the semiconductor region 312. A part of the semiconductor region 317, which is located between the semiconductor region 311 and the semiconductor region 312, is an N-type semiconductor region (fifth semiconductor region). This realizes avalanche multiplication. This PN junction becomes the avalanche multiplication region APDR. This avalanche multiplication occurs when electrons (seed electrons) generated in the semiconductor region 316 or the semiconductor region 314 pass through the avalanche multiplication region APDR. Therefore, far more electrons than the seed electrons generated in the semiconductor region 316 or the semiconductor region 314 are transported to the semiconductor region 311.

[0052] The APD 201 further includes a P-type semiconductor region 313. This semiconductor region 313 serves to reduce the entry into the semiconductor region 316 of dark current components that are generated mainly due to defects on the surface of the semiconductor layer F1.

[0053] The first surface F1 has a pinning film (fixed charge film) 321 on the incident surface side. The pinning film 321 is a film having a negative fixed charge. This pinning film 321 generates a positive charge in a region inside the semiconductor layer 302 near the first surface F1. As a result, together with the P-type semiconductor region 313, it plays a role in reducing the entry of dark current components, which are mainly caused by defects on the surface of the semiconductor layer F1, into the semiconductor region 316. The pinning film is typically an aluminum oxide film, but may also be a film containing at least one of aluminum oxide and tantalum oxide. When a laminated film of an aluminum oxide film and a tantalum oxide film is used, it is preferable to laminate the aluminum oxide film and the tantalum oxide film in this order from the side closest to the first surface F1.

[0054] A planarization film 322 is formed on the pinning film 321. The planarization film 322 may be a film including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or may be configured as a stacked film of multiple films. A microlens 323 is provided on the planarization film 322. The microlens 323 focuses light and directs it to the APD 201. The optical layer 380 includes the pinning film 321, the planarization layer 322, and the microlens 323. A color filter may be further provided between the microlens 323 and the planarization layer 322. Color information can be acquired by providing color filters of different colors for multiple pixels. A film with a different function may also be provided between the pinning film 321 and the planarization film 322. For example, an anti-reflection film may be provided to further enhance the sensitivity of the APD 201.

[0055] The semiconductor layer 302 has a dielectric 344. This dielectric 344 can be formed by a LOCOS (LOCal Oxidation of Silicon) process, an STI (Shallow Trench Isolation) process, or the like. Here, a structure formed by the STI process is shown. The dielectric 344 typically contains silicon oxide. Whether formed by the LOCOS process or the STI process, the dielectric 344 has a portion extending into the semiconductor layer 302. In the LOCOS process or the STI process, the dielectric 344 may contain a silicon compound. The silicon compound typically includes a silicon oxide film or a silicon oxynitride film. The dielectric 344 may also contain a void. The void may contain a gas or a vacuum. The dielectric 344 extends to a position deeper than the depth D3 at which the semiconductor region 319 is provided, as viewed from the second face F2. The depth D3 can also be considered to be the position at which the semiconductor region 316 is disposed. Therefore, the dielectric 344 has a portion provided at the depth position where the semiconductor region 316 is disposed. It can also be said that the depth position D3 is the depth position where the semiconductor region 317 is disposed. Therefore, the dielectric 344 has a portion provided at the depth position where the semiconductor region 317 is disposed.

[0056] The semiconductor regions described so far will be summarized. In this embodiment, N type is the first conductivity type and P type is the second conductivity type. The first semiconductor region of the first conductivity type provided at a first depth from the first face F1 is semiconductor region 314. The second semiconductor region of the second conductivity type located closer to the second face than the first semiconductor region is semiconductor region 312. The third semiconductor region of the first conductivity type located closer to the second face than the second semiconductor region is semiconductor region 311 and to which a first voltage is applied is semiconductor region 319. The fourth semiconductor region of the first conductivity type provided between this region and the third semiconductor region is at least one of the portion of semiconductor region 316 at the depth where semiconductor region 319 is provided and semiconductor region 317. The dielectric located at least in a portion overlapping with the fourth semiconductor region in a plan view with respect to second face F2 and having at least a portion extending from the second face into the semiconductor layer is dielectric 344. Moreover, the dielectric 344 extends to a position deeper than the depth position D3 at which the semiconductor region 319 is provided, as viewed from the second face F2. The dielectric 344 has a portion provided at the depth position at which the semiconductor region 316 is provided. The dielectric 344 also has a portion provided at the depth position at which the semiconductor region 317 is provided. From another perspective, the end of the dielectric 344 on the first face F1 side is located at a position deeper than the depth position D3 at which the semiconductor region 319 is provided, as viewed from the second face F2. A portion of the dielectric 344 is located at the depth position at which the semiconductor region 316 is provided. A portion of the dielectric 344 is located at the depth position at which the semiconductor region 317 is provided.

[0057] Returning to FIG. 6 , in FIG. 6 , avalanche multiplication is limited to the avalanche multiplication region APDR, thereby suppressing noise and achieving stable avalanche multiplication. However, when the area of ​​the APD 201 is reduced in plan view relative to the second surface F2 in order to improve the resolution of the photoelectric conversion device, the distance between the semiconductor region 311 with the highest impurity concentration among the N-type semiconductor regions and the semiconductor region 319 with the highest impurity concentration among the P-type semiconductor regions becomes shorter. This causes a tunneling current or avalanche multiplication between the semiconductor regions 311 and 319, resulting in increased noise. In contrast, in this embodiment, the provision of the dielectric 344 separates the PN junction between the semiconductor regions 311 and 319, thereby suppressing the occurrence of tunneling current or avalanche multiplication. This makes it possible to limit avalanche multiplication to the avalanche multiplication region APDR, thereby improving the resolution of the photoelectric conversion device and suppressing noise and achieving stable avalanche multiplication. Furthermore, when viewed from the second face F2, the dielectric 344 extends to a position deeper than the depth position D3 at which the semiconductor region 319 is disposed. This makes it possible to reduce leakage current between the anode region and the cathode region even if the semiconductor region 319, which is the anode region, and the semiconductor region 311, which is the cathode region, are brought closer together due to miniaturization of the pixel structure.

[0058] Fig. 7 is a plan view of the structure shown in Fig. 6, viewed from the second surface F2. In Fig. 7, the same components as those shown in Fig. 6 are assigned the same reference numerals as those in Fig. 6. Fig. 7 also shows APDs 201 of four pixels arranged in two rows and two columns. Fig. 6 is also a cross-sectional view taken along the line A1-A2 shown in Fig. 7.

[0059] 7, dielectric 344 is provided in a square ring shape so as to surround semiconductor region 319. This shape makes it possible to separate the PN junction occurring between semiconductor region 311 and semiconductor region 319. Furthermore, semiconductor region 312 is arranged so as to overlap semiconductor region 316 shown in Fig. 7. Typically, the portion where semiconductor region 316 is arranged and the portion where semiconductor region 312 is arranged coincide with each other in a plan view from second face F2.

[0060] Next, a method for manufacturing the photoelectric conversion device of this embodiment described with reference to FIGS. 6 and 7 will be described.

[0061] FIG. 8 is a diagram showing some steps in the method for manufacturing the photoelectric conversion device of this embodiment.

[0062] As shown in FIG. 8(a), a silicon wafer having an N-type semiconductor layer 302 into which donors are introduced entirely is prepared.

[0063] 8(b), after forming a mask pattern MP1 by photolithography, the trench portion 344T is formed by reactive ion etching such as dry etching. The trench portion 344T is formed in the location where the dielectric 344 is to be provided.

[0064] As shown in FIG. 8(c), after removing the mask pattern MP1, silicon dioxide (SiO2) is deposited inside the trench portion 344T by CVD (Chemical Vapor Deposition). Then, excess silicon dioxide is removed by CMP (Chemical Mechanical Polishing) to form the dielectric 344. Here, the dielectric 344 is formed before the formation of the other semiconductor regions 311-315, 317, and 319. This allows for sufficient annealing after the formation of the dielectric 344. If the dielectric 344 were formed after the formation of the semiconductor regions 311-315, 317, and 319, annealing would cause impurities in each semiconductor region to diffuse, making it difficult to fabricate a device with an appropriate concentration distribution. In this embodiment, the dielectric 344 is formed prior to the formation of the other semiconductor regions, allowing for sufficient annealing. This reduces dark current due to defects in the semiconductor layer 302 that are likely to occur when the dielectric 344 is formed.

[0065] 8(d), the semiconductor regions 311 to 315, 317, and 319 are formed by ion implantation. In this case, it is preferable to first form the silicon oxide film 341 and then perform ion implantation for the semiconductor regions 311 to 315, 317, and 319. By using this method, damage to the semiconductor layer 302 caused by ion implantation can be reduced.

[0066] 8(e), after forming a silicon nitride film 342, a wiring layer 303 is formed, which includes a cathode contact 333, an anode contact 334, wiring 331, wiring 332, and a planarization layer 322. Through this process, a semiconductor substrate 301A is formed before being made into a stacked sensor (structure).

[0067] After this step, the semiconductor substrate 301A (one substrate) is bonded to the circuit substrate 21 (the other substrate) shown in FIG. 1 to form a stacked sensor. Various bonding methods can be used for this bonding. For example, a silicon oxide film is formed on the bonding surfaces of the semiconductor substrate 301A and the circuit substrate 21. A recess is formed in a portion of the silicon oxide film of each of the semiconductor substrate 301A and the circuit substrate 21, and a conductive member is embedded in the recess. The conductive member is electrically connected to the underlying wiring layer through a via plug. A metal material such as copper, aluminum, or tungsten is used for this conductive member. The conductive members of the semiconductor substrate 301A and the circuit substrate 12 are bonded. Furthermore, the silicon oxide films on the bonding surfaces of the semiconductor substrate 301A and the circuit substrate 21 are bonded. In other words, a bond between the silicon oxide films and a bond between the conductive members are formed on the bonding surfaces. This is also called a hybrid bonding. This bonding achieves bonding and electrical connection between the semiconductor substrate 301A and the circuit substrate 21.

[0068] FIG. 8(f) shows the process for the semiconductor substrate 301A after bonding. Unlike FIG. 8(e), FIG. 8(f) depicts the first surface F1 on the upper side and the second surface F2 on the lower side. The process of FIG. 8(f) includes a process for thinning the semiconductor layer 302. Typically, the semiconductor layer 302 is adjusted to a thickness of 1 to 10 μm. To improve sensitivity to long-wavelength light such as infrared light, the semiconductor layer 302 may be thicker (e.g., 10 to 100 μm). As shown in FIG. 8(f), a pinning film 321 is formed by ALD (atomic layer deposition) on the first surface F1, which is the incident surface of the semiconductor substrate 301A after bonding. Thereafter, a planarization layer 322 and a microlens 323 are formed, thereby manufacturing the photoelectric conversion device having the structure shown in FIG. 6.

[0069] In this embodiment, as described above, the dielectric 344 extends to a position deeper than the depth position D3 at which the semiconductor region 319 is provided, as viewed from the second face F2. The dielectric 344 also has a portion provided at the depth position at which the semiconductor region 316 is provided. The dielectric 344 also has a portion provided at the depth position at which the semiconductor region 317 is provided. This makes it possible to reduce leakage current between the semiconductor region 319 serving as the anode region and the semiconductor region 311 serving as the cathode region, even if the semiconductor region 319 serving as the anode region and the semiconductor region 311 serving as the cathode region are brought closer together due to miniaturization of the pixel structure.

[0070] Furthermore, by providing the dielectric 344, incident light can be reflected by the dielectric 344 and guided to the semiconductor region 314. This can improve the sensitivity of the avalanche photodiode APD.

[0071] Second Embodiment The present embodiment will be described focusing on the differences from the first embodiment. The present embodiment is a modified example of the arrangement of the dielectric 344.

[0072] 9 is a plan view seen from the second face F2, showing one of the modified examples of the arrangement of the dielectric 344. In this arrangement, the dielectric 344 is provided in a circular ring shape. Note that the shape of this circular ring is not limited to a perfect circle. In other words, it may be an ellipse.

[0073] FIG. 10 is a plan view seen from the second surface F2, showing the arrangement of the dielectric 344, which is one of the modified examples. In this arrangement, the dielectric 344 is provided in a quadrilateral shape. This quadrilateral has four corners. The angles of this quadrilateral are not limited to 90 degrees. In other words, the quadrilateral may be a parallelogram or a rhombus. The shape shown in FIG. 10 is a rhombus.

[0074] 11 is a plan view of a modified example of the arrangement of the dielectric 344, viewed from the second surface F2. In this configuration, the sides of the quadrangle are separated. The dielectric 344 is not continuous across multiple APDs 201, but is provided within one APD 201. In this configuration as well, the PN junction occurring between the semiconductor region 311 and the semiconductor region 319 can be separated.

[0075] 12 is a plan view seen from the second face F2, showing the arrangement of the dielectric 344, which is one of the modified examples. In this embodiment, the circular ring is divided. The dielectric 344 is not continuous across multiple APDs 201, but is provided inside one APD 201.

[0076] 13 is a plan view seen from the second face F2, showing one of the modified examples, illustrating the arrangement of the dielectric 344. In this embodiment, the diamond-shaped ring is divided, and the dielectric 344 is not continuous across multiple APDs 201, but is provided inside one APD 201.

[0077] 14 is a plan view seen from the second face F2, showing one of the modified examples, illustrating the arrangement of dielectric 344. In this embodiment, quadrilateral ring-shaped dielectric 344 is provided on the outer periphery of a quadrangle with cathode contact 331 at the center.

[0078] 15 is a plan view seen from the second face F2, showing one of the modified examples, illustrating the arrangement of dielectric 344. In this embodiment, circular ring-shaped dielectric 344 is provided on the circumference of a circle centered on cathode contact 331.

[0079] 16 is a plan view seen from the second face F2, showing one modification of the arrangement of the dielectric 344. In this embodiment, the semiconductor region 319 and the anode contact 334 are provided only at some corners of one APD 201, and the dielectric 344 is provided so as to surround the semiconductor region 319. Also, in the embodiments shown in FIGS. 9 to 13, the semiconductor region 319 and the anode contact 334 may be provided only at some of the four corners of one APD 201, as shown in FIG.

[0080] In each example of this embodiment, the same effects as those described in the first embodiment can be obtained. That is, it is possible to reduce the leakage current between the semiconductor region 319, which is the anode region, and the semiconductor region 311, which is the cathode region. Furthermore, as in the first embodiment, by providing the dielectric 344, it is possible to reflect incident light by the dielectric 344 and guide it to the semiconductor region 314. This makes it possible to improve the sensitivity of the avalanche photodiode APD.

[0081] Third Embodiment The present embodiment will be described, focusing on the differences from the first embodiment.

[0082] 17 is a cross-sectional view of the photoelectric conversion device of this embodiment. In this embodiment, a P-type semiconductor region 350 is formed at the boundary surface between the dielectric 344 and the N-type semiconductor region 302.

[0083] The impurity concentrations of semiconductor regions 312, 319, and 350, which are P-type semiconductor regions, have the relationship 319>312>350. Because the dielectric 344 and semiconductor region 302 are made of different materials, dangling bonds occur at the boundary surface, and dark current is generated by the capture and release of electrons by these dangling bonds. However, by forming P-type semiconductor region 350, the dark current can be canceled out by the holes present in semiconductor region 350.

[0084] Fig. 18 is a plan view of this embodiment as seen from the second surface F2. The cross-sectional view of Fig. 17 is a cross-sectional view taken along line A1-A2 in Fig. 18. As seen from the semiconductor region 319, semiconductor regions 350 are formed on the outer and inner peripheries of the dielectric 344. This structure makes it possible to cancel out dark currents generated at the boundary between the dielectric 344 and the semiconductor region 302.

[0085] Next, a method for manufacturing the photoelectric conversion device of this embodiment described with reference to FIGS. 17 and 18 will be described.

[0086] FIG. 19 is a diagram showing some steps in the method for manufacturing the photoelectric conversion device of this embodiment.

[0087] As shown in FIG. 19(a), a silicon wafer having an N-type semiconductor layer 302 (epitaxial layer) into which donors are entirely introduced is prepared.

[0088] 19(b), the semiconductor regions 311 to 315, 317, and 319 are formed by ion implantation. In this case, it is preferable to first form the silicon oxide film 341 and then perform ion implantation for the semiconductor regions 311 to 315, 317, and 319. By using this method, damage to the semiconductor layer 302 caused by ion implantation can be reduced.

[0089] 19(c), after forming a mask pattern MP1 by photolithography, the trench portion 344T is formed by reactive ion etching such as dry etching. The trench portion 344T is formed in the location where the dielectric 344 is to be provided.

[0090] 19(d), a semiconductor region 350 is formed on the inner surface of the trench portion 344T by plasma doping. By using this method, damage to the trench portion 344T can be reduced.

[0091] As shown in FIG. 19(e), after removing the mask pattern MP1, silicon oxide (SiO2) is deposited in the trench portion 344T by CVD (short for Chemical Vapor Deposition). Then, excess silicon oxide is removed by CMP (short for Chemical Mechanical Polishing) to form the dielectric 344. Here, the dielectric 344 is formed after the other semiconductor regions 311-315, 317, and 319 are formed. For this reason, it is difficult to perform a sufficient annealing process after forming the dielectric 344, but the semiconductor region 350 can reduce dark current.

[0092] Thereafter, as shown in FIGS. 19(f) to (g), the same steps as in the first embodiment are carried out to manufacture a photoelectric conversion device having the structure shown in FIG.

[0093] <Fourth embodiment> This embodiment will be described, focusing on the differences from the third embodiment.

[0094] 20 is a cross-sectional view of the photoelectric conversion device of this embodiment. In this embodiment, a dielectric 344 is provided in contact with a semiconductor region 319. The impurity concentrations of the semiconductor regions 319 and 350, which are P-type semiconductor regions, satisfy the relationship 319>350, which can enhance the effect of reducing dark current.

[0095] Fig. 21 is a plan view of this embodiment as seen from the second face F2. The cross-sectional view of Fig. 20 is a cross-sectional view taken along line A1-A2 in Fig. 21. When viewed from the semiconductor region 319, the semiconductor region 350 is formed on the outer periphery of the dielectric 344, and the inner periphery is in contact with the semiconductor region 319. In this embodiment, the dielectric 344 has a quadrilateral ring shape, but as another embodiment, it may be a modified example of the second embodiment.

[0096] Fifth Embodiment In this embodiment, a modified example of the depth from the second face F2 of the dielectric 344 of the first embodiment will be described. The layout of the dielectric 344 in plan view with respect to the first face F1 can be the same as that of each of the embodiments described in the first to fourth embodiments.

[0097] FIG. 22 is a cross-sectional view showing the depth of the dielectric 344 from the second surface F2, which is one of the modified examples. The end of the dielectric 344 on the first surface F1 side extends to the depth where the semiconductor region 312 is disposed, as viewed from the second surface F2. The semiconductor region 312 is disposed from a fourth depth D1 to a fifth depth D2, as viewed from the second surface F2. The end of the dielectric 344 on the first surface F1 side is deeper than the fourth depth D1 and shallower than the fifth depth D2, as viewed from the second surface F2. From another perspective, the end of the dielectric 344 on the first surface F1 side is shallower than the fourth depth D1 and deeper than the fifth depth D2, as viewed from the first surface F1. With this configuration, the dielectric 344 is positioned deeper inside the semiconductor layer 302 than the dielectric 344 of the first embodiment. This makes it easier to separate the PN junction occurring between the semiconductor region 311 and the semiconductor region 319. This makes it possible to further reduce the leakage current between the semiconductor region 319, which is the anode region, and the semiconductor region 311, which is the cathode region.

[0098] Sixth Embodiment FIG. 23 shows another modified example of the fifth embodiment. In this embodiment, the layout of the dielectric 344 in plan view relative to the first surface F1 can be any of the embodiments described in the first to fourth embodiments, excluding those shown in FIGS. 14 and 15. This is a cross-sectional view showing the depth of the dielectric 344 from the second surface F2. The depth of the dielectric 344 passes through the semiconductor region 312 and extends to the semiconductor region 316. In this embodiment, the end of the dielectric 344 on the first surface F1 side can also be said to extend beyond the depth position D2 at which the semiconductor region 312 is disposed, as viewed from the second surface F2. The semiconductor region 312 is disposed from a fourth depth position to a fifth depth position as viewed from the second surface F2, similar to the embodiment shown in FIG. 22. The end of the dielectric 344 on the first surface F1 side is located deeper (shallower) than the fourth depth position D1 and the fifth depth position D2 as viewed from the second surface F2 (as viewed from the first surface F1). 22, the dielectric 344 is positioned deeper inside the semiconductor layer 302. This makes it easier to separate the PN junction occurring in the semiconductor region 311 and the semiconductor region 319. This makes it possible to further reduce the leakage current between the semiconductor region 319, which is the anode region, and the semiconductor region 311, which is the cathode region.

[0099] 23, the dielectric 344 penetrates the semiconductor region 312. However, in this embodiment, the second voltage can be supplied from the semiconductor region 319 to the avalanche multiplication region APDR via the semiconductor region 315 or the portion where the dielectric 344 is divided.

[0100] In these embodiments, the PN junction occurring between the semiconductor region 311 and the semiconductor region 319 can be separated. Therefore, in each example of this embodiment, the same effects as those described in the first embodiment can be obtained. That is, the leakage current between the semiconductor region 319, which is the anode region, and the semiconductor region 311, which is the cathode region, can be reduced. Furthermore, as in the first embodiment, by providing the dielectric 344, incident light can be reflected by the dielectric 344 and guided to the semiconductor region 314. This can improve the sensitivity of the avalanche photodiode APD.

[0101] Seventh Embodiment In this embodiment, a configuration in which the present disclosure is applied to the configuration disclosed in Patent Document 2 will be described. The following description will focus on the differences from the first embodiment.

[0102] 24 is a cross-sectional view of the photoelectric conversion device of this embodiment, taken along the same line A1-A2 as in the first embodiment.

[0103] An N-type semiconductor region 1814 is provided within a P-type semiconductor region 1816. Photoelectric conversion occurs mainly in the N-type semiconductor region 1814. The N-type semiconductor region 1820 has a higher impurity concentration (effective donor concentration) than the semiconductor region 1814. The APD 201 includes a P-type semiconductor region 1812 and an N-type semiconductor region 1811. A cathode contact 331 is connected to the N-type semiconductor region 1811. In the anode portion, an anode electrode 1834 (metal member) is embedded in a groove provided within the semiconductor layer 302. A silicon oxide film 1841 is formed to surround the outer periphery of the anode electrode 1834. The anode electrode 1834 is in contact with the P-type semiconductor region 1819. A light-shielding portion 1850 is provided on the first face F1 side to provide light shielding between the multiple APDs 201. An insulating film 1815 is provided to surround the light-shielding portion 1850. The insulating film 1815 may include a pinning film 321 .

[0104] Charges generated by photoelectric conversion move from semiconductor region 1814 to semiconductor region 1820 and reach semiconductor region 1812. A voltage applied to P-type semiconductor region 1819 is supplied to semiconductor region 1812 via P-type semiconductor region 1816. Therefore, avalanche multiplication occurs at the PN junction between semiconductor region 1812 and semiconductor region 1811.

[0105] In this embodiment, a P-type semiconductor region 1819 corresponds to a region to which a second voltage different from the first voltage applied to the semiconductor region 1811 is applied.

[0106] In this embodiment, the dielectric 344 is provided between the semiconductor region 1819 and the semiconductor region 1811. The dielectric 344 extends from the second face F2 to a position deeper than the semiconductor region 1819. The end of the dielectric 344 on the first face F1 side is located deeper than the depth position D4 at which the semiconductor region 1819 is disposed, as viewed from the second face F2. This configuration also allows the PN junction generated between the semiconductor region 1819 and the semiconductor region 1811 to be separated, thereby reducing leakage current. As in the first embodiment, the provision of the dielectric 344 allows incident light to be reflected by the dielectric 344 and guided to the semiconductor region 1814. This improves the sensitivity of the avalanche photodiode APD.

[0107] Eighth Embodiment In this embodiment, a modification of the arrangement of the dielectric 344 in the first embodiment will be described.

[0108] 25 is a plan view seen from the second surface F2, showing an arrangement of dielectrics 344K, which is one of the modified examples. In this arrangement, the dielectrics 344K are provided in a lattice pattern. In this figure, the lattice-patterned dielectrics 344K are provided inside one APD 201. As another example, the lattice-patterned dielectrics 344K may be formed continuously across the multiple APDs 201, without being separated between them.

[0109] 26 is a plan view seen from the second face F2, showing the arrangement of the dielectric 344L, which is another modified example. In this arrangement, the circular dielectric 344L is provided on the circumference of a circle centered on the cathode contact 334.

[0110] In these configurations, incident light can be reflected and suitably guided to the semiconductor region 314, and the sensitivity of the APD 201 can be improved.

[0111] Ninth Embodiment The present embodiment will be described, focusing on the differences from the first embodiment.

[0112] 27, in this embodiment, the wiring 333 is arranged so as to overlap the dielectric 344 in a plan view. With this configuration, light reflected by the dielectric 344 enters the semiconductor layer 302 via the wiring 333.

[0113] Furthermore, in this embodiment, the dielectric 344 may be arranged in a rectangular shape so as to surround the semiconductor region 317, or may be the example shown in FIG. 28. The dielectric 344 is provided between the semiconductor regions 317 of two APDs 201 adjacent to each other in the row direction. The dielectric 344 is also provided between the semiconductor regions 317 of two APDs 201 adjacent to each other in the column direction. On the other hand, the dielectric 344 is not provided at a position where the diagonal of the APD 201 passes, and the semiconductor region 316 is provided at that depth. Even with this configuration, the effect of improving the sensitivity of the APD can be obtained.

[0114] 29, another dielectric 345 may be provided inside a rectangular dielectric 344. Alternatively, as shown in FIG. 28, the dielectrics 344, 345 may not be provided at the position of a line passing through the diagonal of the APD 201, and the semiconductor region 316 may be provided at that depth. The dielectric 345 may be located so as to overlap the semiconductor region 317 in a planar view. That is, a configuration may be possible in which the dielectric 344 is located so as to overlap the semiconductor region 316 between the semiconductor region 317 and the semiconductor region 319 in a planar view, and the dielectric 345 is located so as to overlap the semiconductor region 317.

[0115] The depth positions of the end portions of the dielectrics 344 and 345 on the first surface F1 side may be appropriately combined with those of other embodiments. That is, the depth positions of the dielectrics 344 and 345 on the first surface F1 side may be deeper than the depth position D2 when viewed from the second surface F2. The depth positions of the dielectrics 344 and 345 on the first surface F1 side may be different from each other. For example, the depth position of the end portion of the dielectric 344 on the first surface F1 side may be between the depth positions D1 and D3, and the depth position of the end portion of the dielectric 345 on the first surface F1 side may be between the depth positions D2 and D3. It is sufficient that the depth position of the end portion of at least one of the dielectrics 344 and 345 on the first surface F1 side is deeper than the depth position D3 when viewed from the second surface F2.

[0116] This embodiment can also provide the same effects as those of the first embodiment. The wiring 333 extends to a position where it overlaps with the dielectric 344 in a plan view, thereby improving the sensitivity of the APD 201.

[0117] Tenth Embodiment This embodiment will be described, focusing on the differences from the ninth embodiment.

[0118] FIG. 30 is a cross-sectional view of the APD of this embodiment. The APD of this embodiment has a trench portion 880 extending from the first face F1 toward the second face F2. The trench portion 880 has a deep trench isolation (DTI) structure. The trench portion 880 may be filled with a silicon compound or may contain a void. The void may contain air, or the inside of the void may be a vacuum. Alternatively, a metal may be embedded inside the trench portion 880. Embedding a metal can improve the light-shielding performance of the trench portion 880 and reduce crosstalk from one APD to another APD. This crosstalk occurs when avalanche light generated in one APD enters the other APD. The trench portion 880 can suppress the avalanche light from entering the other APD. The trench portion 880 is provided inside the semiconductor region 315, which is the sixth semiconductor region. The semiconductor region 315 is a semiconductor region provided between a plurality of APDs. Furthermore, a trench portion 828 (a modified example of the dielectric 344) is provided inside the semiconductor region 319. In this embodiment, the trench portion 828 further has a portion disposed inside the semiconductor region 315. The end portion of the trench portion 828 on the first surface F1 side is located at a depth position between depth positions D1 and D2 as viewed from the second surface F2. This is not a limitation, and the end portion of the trench portion 828 on the first surface F1 side may have a portion extending to a position deeper than depth position D3 as viewed from the second surface F2, or may be located at a depth position deeper than depth position D2.

[0119] FIG. 31 is a plan view of the APD shown in FIG. 30, viewed from the second surface F2. FIG. 30 is a cross-sectional view taken along the line A1-A2 in FIG. 31. Trench portion 828 is disposed so as to surround semiconductor region 316 in plan view. Trench portion 880 is also provided so as to surround trench portion 828. This configuration improves the sensitivity of the APD by reflecting incident light by trench portions 880 and 828. It also reduces crosstalk between multiple APDs.

[0120] In this embodiment, the trench portion 880 penetrates the semiconductor layer 302, but as shown in Fig. 32, the trench portion 880 may extend from the first face F1 to a depth partway through the semiconductor layer 302. In this configuration, the end of the trench portion 880 on the second face F2 side contacts a semiconductor region inside the semiconductor layer 302. With this configuration, the distance between two adjacent trench portions 828 can be narrower than in the configuration shown in Fig. 30, which makes it easier to miniaturize pixels.

[0121] 33, a trench portion 830 (a variation of the dielectric 344) extending from the second surface F2 may be connected to the trench portion 880 inside the semiconductor layer 302. In this configuration, the width of the trench portion 830 can be made wider than the width of the trench portion 880. This can further facilitate reflection of incident light by the trench portion 830. Alternatively, a metal may be embedded inside the trench portion 830. In this case, the reflection of incident light can be further enhanced compared to when the trench portion 830 is filled with at least one of a silicon compound and air. Furthermore, tapering the trench portion 830 can further enhance the reflection of incident light. The end of the trench portion 830 on the first surface F1 side is located deeper than the depth position D2 when viewed from the second surface F2. However, this is not limited to this configuration, and it is sufficient if the trench portion 830 has a portion extending deeper than the depth position D3.

[0122] 34, the trench portion 878 extending from the first surface F1 may have a tapered portion. In this configuration, the tapered portion of the trench portion 878 is first formed as an STI structure. Then, a DTI structure is formed from the bottom surface of the STI structure toward the inside of the semiconductor layer 302. The inside of the trench portion 878 may be filled with at least one of a silicon compound and air, or may be filled with metal, or may be a vacuum. This structure makes it easier to guide incident light into the APD, thereby improving sensitivity.

[0123] Eleventh Embodiment The present embodiment will be described, focusing on the differences from the first embodiment.

[0124] 35 is a cross-sectional view of the APD of this embodiment. The trench portion 822 corresponds to the dielectric 344 in the above-described embodiment. In this embodiment, a diffractive structure 850 (formed of a dielectric) is provided on the first face F1, which is the incident face of the APD. This diffractive structure 850 can be formed as an STI structure or a DTI structure.

[0125] The diffractive structure 850 can lengthen the optical path length from when the incident light enters the APD until it is photoelectrically converted, thereby improving the sensitivity to light in the long wavelength band (especially near-infrared light).

[0126] 36 is a plan view of the first surface F1 of the APD of this embodiment. The diffractive structure 850 is provided in a lattice pattern on the first surface F1. The lattice-shaped diffractive structure 850 is disposed so as to overlap with the semiconductor region 314 in plan view.

[0127] In this way, the APD of this embodiment has a dielectric on each of the first surface F1 and the second surface F2, which makes it possible to further improve sensitivity to near-infrared light.

[0128] It should be noted that this embodiment can be applied in combination with other embodiments.

[0129] In these embodiments, the intervals between the dielectrics provided on the first surface F1 are narrower than the intervals between the dielectrics provided on the second surface F2, which allows the diffractive structure 850 to more suitably diffract incident light.

[0130] In each embodiment, the dielectric 344 and a modified example of the dielectric 344 have been described. The depth positions of the ends of the dielectric 344 and the modified examples on the first surface F1 side can be modified to the depth positions shown in other embodiments, as well as the configurations of the respective embodiments. That is, the depth positions of the ends of the dielectric 344 and the modified examples on the first surface F1 side, as viewed from the second surface F2, may be deeper than the depth position D3 at which the semiconductor region 319 is disposed. This configuration can reduce leakage currents in the anode and cathode regions. Furthermore, the depth positions of the ends of the dielectric 344 and the modified examples on the first surface F1 side, as viewed from the second surface F2, may be between the depth positions D1 and D2 at which the semiconductor region 312 is disposed. In this case, leakage currents can be further reduced. Furthermore, the depth positions of the ends of the dielectric 344 and the modified examples on the first surface F1 side, as viewed from the second surface F2, may be deeper than the depth position D2 at which the semiconductor region 312 is disposed. In this case, the leakage current can be further reduced.

[0131] <Twelfth embodiment> This embodiment can be applied to any of the above-described embodiments. FIG. 38(a) is a schematic diagram illustrating a device 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device (imaging device) of each of the above-described embodiments can be used as the semiconductor device 930. The device 9191 including the semiconductor device 930 will be described in detail. As described above, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910, in addition to the semiconductor device 910 having the semiconductor layer 10. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0132] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a memory device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0133] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0134] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0135] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0136] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0137] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0138] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0139] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIG.

[0140] FIG. 38(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (image capture device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0141] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820 (control unit), which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0142] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 38(c) shows a photoelectric conversion system for capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0143] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0144] <Thirteenth embodiment> A photoelectric conversion system, which is an example of the device of this embodiment, will be described with reference to Fig. 39. Fig. 39 is a block diagram showing an example of the configuration of a range image sensor, which is the photoelectric conversion system of this embodiment.

[0145] 39, the range image sensor 401 is configured to include an optical system 407, a photoelectric conversion device 408, an image processing circuit 404, a monitor 405, and a memory 406. The photoelectric conversion devices of each of the above-described embodiments can be applied to the photoelectric conversion device 408. The range image sensor 401 can obtain a range image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected from a light source device 409 toward the subject and reflected from the surface of the subject.

[0146] The optical system 407 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photoelectric conversion device 408, forming an image on the light receiving surface (sensor section) of the photoelectric conversion device 408.

[0147] The photoelectric conversion device 408 is the photoelectric conversion device of each of the above-described embodiments, and a distance signal indicating a distance determined from a light reception signal output from the photoelectric conversion device 408 is supplied to the image processing circuit 404.

[0148] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 408. The distance image (image data) obtained by this image processing is then supplied to a monitor 405 for display, or supplied to a memory 406 for storage (recording).

[0149] In the range image sensor 401 configured in this way, by applying the above-described photoelectric conversion device, it is possible to obtain, for example, a more accurate range image as the pixel characteristics improve.

[0150] [Modified embodiment] The present disclosure is not limited to the above-described embodiment, and various modifications are possible.

[0151] For example, an example in which part of the configuration of any one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present disclosure.

[0152] Furthermore, the devices shown in the seventh and eighth embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and the devices and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 38 and 39.

[0153] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features.

[0154] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0155] The contents disclosed in this specification have the following configuration.

[0156] (Configuration 1) an avalanche photodiode that performs an avalanche multiplication operation in response to a first voltage and a second voltage applied thereto, and a semiconductor layer having a first surface onto which light is incident and a second surface opposite to the first surface; The avalanche photodiode is a first semiconductor region of a first conductivity type provided in the semiconductor layer at a first depth position as viewed from the second surface; a second semiconductor region of a second conductivity type located closer to the second surface than the first semiconductor region; a third semiconductor region of the first conductivity type located closer to the second surface than the second semiconductor region, in contact with a contact plug to which the first voltage is applied, and provided to a second depth position from the second surface; a region that is the semiconductor region of the second conductivity type and that is in contact with the contact plug to which the second voltage is applied and that is provided up to a third depth position in terms of depth from the second surface; a fourth semiconductor region of the first conductivity type provided between the region and the third semiconductor region, a dielectric located at a portion overlapping at least the fourth semiconductor region in a plan view with respect to the second surface and having at least a portion extending from the second surface into the semiconductor layer; The portion extends from the second surface beyond the third depth. A photoelectric conversion device characterized by:

[0157] (Configuration 2) 2. The photoelectric conversion device according to configuration 1, wherein the end of the dielectric member on the first surface side is located deeper from the second surface than the region.

[0158] (Configuration 3) the second semiconductor region is provided from a fourth depth position as viewed from the second surface to a fifth depth position that is deeper than the fourth depth position, 3. The photoelectric conversion device according to configuration 2, wherein the end portion is located at a depth position between the fourth depth position and the fifth depth position.

[0159] (Configuration 4) the second semiconductor region is provided from a fourth depth position as viewed from the second surface to a fifth depth position that is deeper than the fourth depth position, The photoelectric conversion device according to configuration 2, wherein the end portion is located at a position deeper than the fifth depth position when viewed from the second surface.

[0160] (Configuration 5) a fifth semiconductor region of the first conductivity type between the second semiconductor region and the third semiconductor region; 5. The photoelectric conversion device according to any one of configurations 1 to 4, wherein a dielectric other than the dielectric is disposed at a position overlapping at least the fourth semiconductor region in the plan view.

[0161] (Configuration 6) 6. The photoelectric conversion device according to any one of configurations 1 to 5, wherein the dielectric is disposed at a position overlapping the region in the plan view.

[0162] (Configuration 7) 7. The photoelectric conversion device according to any one of configurations 1 to 6, further comprising a sixth semiconductor region of the second conductivity type along the inner side surface of the trench in the dielectric.

[0163] (Configuration 8) 8. The photoelectric conversion device according to configuration 7, wherein the sixth semiconductor region has an impurity concentration lower than the impurity concentration of the second semiconductor region.

[0164] (Configuration 9) 9. The photoelectric conversion device according to any one of configurations 1 to 8, further comprising a metal member embedded inside the semiconductor layer, the second voltage being applied to the region from the metal member.

[0165] (Configuration 10) 10. The photoelectric conversion device according to any one of configurations 1 to 9, wherein the first voltage is a positive voltage and the second voltage is a negative voltage.

[0166] (Configuration 11) 11. The photoelectric conversion device according to any one of configurations 1 to 10, wherein the first conductivity type is N-type and the second conductivity type is P-type.

[0167] (Configuration 12) a structure in which a plurality of substrates are stacked, one of the plurality of substrates includes a wiring layer and the semiconductor layer, and the second surface is located between the first surface and the wiring layer; 12. The photoelectric conversion device according to any one of configurations 1 to 11, wherein the other substrate of the plurality of substrates and the one substrate are stacked.

[0168] (Configuration 13) The photoelectric conversion device according to any one of configurations 1 to 12, a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

[0169] (Configuration 14) A moving object including the photoelectric conversion device according to any one of configurations 1 to 12, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

[0170] (Configuration 15) An apparatus including the photoelectric conversion device according to any one of configurations 1 to 12, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. [Explanation of symbols]

[0171] 301 Semiconductor substrate 302 Semiconductor layer 311, 314, 316, 317 First conductivity type semiconductor regions 312, 313, 315, 319, 350 second conductivity type semiconductor region 344 Dielectric

Claims

1. an avalanche photodiode that performs an avalanche multiplication operation in response to a first voltage and a second voltage applied thereto, and a semiconductor layer having a first surface onto which light is incident and a second surface opposite to the first surface; The avalanche photodiode is a first semiconductor region of a first conductivity type provided at a first depth position as viewed from the second surface in the semiconductor layer; a second semiconductor region of a second conductivity type located closer to the second surface than the first semiconductor region; a third semiconductor region of the first conductivity type located closer to the second surface than the second semiconductor region, in contact with a contact plug to which the first voltage is applied, and provided to a second depth position from the second surface; a region that is the second conductivity type semiconductor region and that is in contact with the contact plug to which the second voltage is applied and that is provided up to a third depth position in terms of depth from the second surface; a fourth semiconductor region of the first conductivity type provided between the region and the third semiconductor region, a dielectric located at a portion overlapping at least the fourth semiconductor region in a plan view with respect to the second surface and having at least a portion extending from the second surface into the semiconductor layer; The portion extends from the second surface beyond the third depth. A photoelectric conversion device characterized by:

2. 2. The photoelectric conversion device according to claim 1, wherein an end of the dielectric member on the side of the first surface is located deeper from the second surface than the region.

3. the second semiconductor region is provided from a fourth depth position as viewed from the second surface to a fifth depth position that is deeper than the fourth depth position, 3. The photoelectric conversion device according to claim 2, wherein the end portion is located at a depth position between the fourth depth position and the fifth depth position.

4. the second semiconductor region is provided from a fourth depth position as viewed from the second surface to a fifth depth position that is deeper than the fourth depth position, 3. The photoelectric conversion device according to claim 2, wherein the end portion is located at a position deeper than the fifth depth position when viewed from the second surface.

5. a fifth semiconductor region of the first conductivity type between the second semiconductor region and the third semiconductor region; 2 . The photoelectric conversion device according to claim 1 , further comprising a dielectric body other than the dielectric body, the dielectric body being disposed at a position overlapping at least the fourth semiconductor region in the plan view.

6. The photoelectric conversion device according to claim 1 , wherein the dielectric is disposed at a position overlapping the region in the plan view.

7. 2. The photoelectric conversion device according to claim 1, further comprising a sixth semiconductor region of the second conductivity type along an inner side surface of the trench in the dielectric.

8. 8. The photoelectric conversion device according to claim 7, wherein the sixth semiconductor region has an impurity concentration lower than the impurity concentration of the second semiconductor region.

9. 2. The photoelectric conversion device according to claim 1, further comprising a metal member embedded in the semiconductor layer, the second voltage being applied to the region from the metal member.

10. 2. The photoelectric conversion device according to claim 1, wherein the first voltage is a positive voltage and the second voltage is a negative voltage.

11. 11. The photoelectric conversion device according to claim 10, wherein the first conductivity type is N-type and the second conductivity type is P-type.

12. a structure in which a plurality of substrates are stacked, one of the plurality of substrates includes a wiring layer and the semiconductor layer, and the second surface is located between the first surface and the wiring layer; 2. The photoelectric conversion device according to claim 1, wherein the one substrate is stacked on the other substrate of the plurality of substrates.

13. The photoelectric conversion device according to any one of claims 1 to 12, a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

14. A moving object equipped with the photoelectric conversion device according to any one of claims 1 to 12, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

15. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 12, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

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